Pileus Git - ~andy/linux/blob - drivers/staging/dwc2/hcd.c

   1 /*
   2  * hcd.c - DesignWare HS OTG Controller host-mode routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the core HCD code, and implements the Linux hc_driver
  39  * API
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/delay.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 /**
  58  * dwc2_dump_channel_info() - Prints the state of a host channel
  59  *
  60  * @hsotg: Programming view of DWC_otg controller
  61  * @chan:  Pointer to the channel to dump
  62  *
  63  * Must be called with interrupt disabled and spinlock held
  64  *
  65  * NOTE: This function will be removed once the peripheral controller code
  66  * is integrated and the driver is stable
  67  */
  68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
  69                                    struct dwc2_host_chan *chan)
  70 {
  71 #ifdef VERBOSE_DEBUG
  72         int num_channels = hsotg->core_params->host_channels;
  73         struct dwc2_qh *qh;
  74         u32 hcchar;
  75         u32 hcsplt;
  76         u32 hctsiz;
  77         u32 hc_dma;
  78         int i;
  79
  80         if (chan == NULL)
  81                 return;
  82
  83         hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
  84         hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
  85         hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
  86         hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
  87
  88         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
  89         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
  90                 hcchar, hcsplt);
  91         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
  92                 hctsiz, hc_dma);
  93         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
  94                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
  95         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
  96         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
  97         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
  98         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
  99         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 100         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 101         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 102                 (unsigned long)chan->xfer_dma);
 103         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 104         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 105         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 106         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 107                             qh_list_entry)
 108                 dev_dbg(hsotg->dev, "    %p\n", qh);
 109         dev_dbg(hsotg->dev, "  NP active sched:\n");
 110         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 111                             qh_list_entry)
 112                 dev_dbg(hsotg->dev, "    %p\n", qh);
 113         dev_dbg(hsotg->dev, "  Channels:\n");
 114         for (i = 0; i < num_channels; i++) {
 115                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 116
 117                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 118         }
 119 #endif /* VERBOSE_DEBUG */
 120 }
 121
 122 /*
 123  * Processes all the URBs in a single list of QHs. Completes them with
 124  * -ETIMEDOUT and frees the QTD.
 125  *
 126  * Must be called with interrupt disabled and spinlock held
 127  */
 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
 129                                       struct list_head *qh_list)
 130 {
 131         struct dwc2_qh *qh, *qh_tmp;
 132         struct dwc2_qtd *qtd, *qtd_tmp;
 133
 134         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 135                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 136                                          qtd_list_entry) {
 137                         dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
 138                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 139                 }
 140         }
 141 }
 142
 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
 144                               struct list_head *qh_list)
 145 {
 146         struct dwc2_qtd *qtd, *qtd_tmp;
 147         struct dwc2_qh *qh, *qh_tmp;
 148         unsigned long flags;
 149
 150         if (!qh_list->next)
 151                 /* The list hasn't been initialized yet */
 152                 return;
 153
 154         spin_lock_irqsave(&hsotg->lock, flags);
 155
 156         /* Ensure there are no QTDs or URBs left */
 157         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
 158
 159         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 160                 dwc2_hcd_qh_unlink(hsotg, qh);
 161
 162                 /* Free each QTD in the QH's QTD list */
 163                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 164                                          qtd_list_entry)
 165                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 166
 167                 spin_unlock_irqrestore(&hsotg->lock, flags);
 168                 dwc2_hcd_qh_free(hsotg, qh);
 169                 spin_lock_irqsave(&hsotg->lock, flags);
 170         }
 171
 172         spin_unlock_irqrestore(&hsotg->lock, flags);
 173 }
 174
 175 /*
 176  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
 177  * and periodic schedules. The QTD associated with each URB is removed from
 178  * the schedule and freed. This function may be called when a disconnect is
 179  * detected or when the HCD is being stopped.
 180  *
 181  * Must be called with interrupt disabled and spinlock held
 182  */
 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
 184 {
 185         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
 186         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
 187         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
 188         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
 189         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
 190         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
 191 }
 192
 193 /**
 194  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
 195  *
 196  * @hsotg: Pointer to struct dwc2_hsotg
 197  */
 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
 199 {
 200         u32 hprt0;
 201
 202         if (hsotg->op_state == OTG_STATE_B_HOST) {
 203                 /*
 204                  * Reset the port. During a HNP mode switch the reset
 205                  * needs to occur within 1ms and have a duration of at
 206                  * least 50ms.
 207                  */
 208                 hprt0 = dwc2_read_hprt0(hsotg);
 209                 hprt0 |= HPRT0_RST;
 210                 writel(hprt0, hsotg->regs + HPRT0);
 211         }
 212
 213         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
 214                            msecs_to_jiffies(50));
 215 }
 216
 217 /* Must be called with interrupt disabled and spinlock held */
 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
 219 {
 220         int num_channels = hsotg->core_params->host_channels;
 221         struct dwc2_host_chan *channel;
 222         u32 hcchar;
 223         int i;
 224
 225         if (hsotg->core_params->dma_enable <= 0) {
 226                 /* Flush out any channel requests in slave mode */
 227                 for (i = 0; i < num_channels; i++) {
 228                         channel = hsotg->hc_ptr_array[i];
 229                         if (!list_empty(&channel->hc_list_entry))
 230                                 continue;
 231                         hcchar = readl(hsotg->regs + HCCHAR(i));
 232                         if (hcchar & HCCHAR_CHENA) {
 233                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
 234                                 hcchar |= HCCHAR_CHDIS;
 235                                 writel(hcchar, hsotg->regs + HCCHAR(i));
 236                         }
 237                 }
 238         }
 239
 240         for (i = 0; i < num_channels; i++) {
 241                 channel = hsotg->hc_ptr_array[i];
 242                 if (!list_empty(&channel->hc_list_entry))
 243                         continue;
 244                 hcchar = readl(hsotg->regs + HCCHAR(i));
 245                 if (hcchar & HCCHAR_CHENA) {
 246                         /* Halt the channel */
 247                         hcchar |= HCCHAR_CHDIS;
 248                         writel(hcchar, hsotg->regs + HCCHAR(i));
 249                 }
 250
 251                 dwc2_hc_cleanup(hsotg, channel);
 252                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
 253                 /*
 254                  * Added for Descriptor DMA to prevent channel double cleanup in
 255                  * release_channel_ddma(), which is called from ep_disable when
 256                  * device disconnects
 257                  */
 258                 channel->qh = NULL;
 259         }
 260 }
 261
 262 /**
 263  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
 264  *
 265  * @hsotg: Pointer to struct dwc2_hsotg
 266  *
 267  * Must be called with interrupt disabled and spinlock held
 268  */
 269 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
 270 {
 271         u32 intr;
 272
 273         /* Set status flags for the hub driver */
 274         hsotg->flags.b.port_connect_status_change = 1;
 275         hsotg->flags.b.port_connect_status = 0;
 276
 277         /*
 278          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 279          * interrupt mask and status bits and disabling subsequent host
 280          * channel interrupts.
 281          */
 282         intr = readl(hsotg->regs + GINTMSK);
 283         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
 284         writel(intr, hsotg->regs + GINTMSK);
 285         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
 286         writel(intr, hsotg->regs + GINTSTS);
 287
 288         /*
 289          * Turn off the vbus power only if the core has transitioned to device
 290          * mode. If still in host mode, need to keep power on to detect a
 291          * reconnection.
 292          */
 293         if (dwc2_is_device_mode(hsotg)) {
 294                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
 295                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
 296                         writel(0, hsotg->regs + HPRT0);
 297                 }
 298
 299                 dwc2_disable_host_interrupts(hsotg);
 300         }
 301
 302         /* Respond with an error status to all URBs in the schedule */
 303         dwc2_kill_all_urbs(hsotg);
 304
 305         if (dwc2_is_host_mode(hsotg))
 306                 /* Clean up any host channels that were in use */
 307                 dwc2_hcd_cleanup_channels(hsotg);
 308
 309         dwc2_host_disconnect(hsotg);
 310 }
 311
 312 /**
 313  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
 314  *
 315  * @hsotg: Pointer to struct dwc2_hsotg
 316  */
 317 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
 318 {
 319         if (hsotg->lx_state == DWC2_L2)
 320                 hsotg->flags.b.port_suspend_change = 1;
 321         else
 322                 hsotg->flags.b.port_l1_change = 1;
 323 }
 324
 325 /**
 326  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
 327  *
 328  * @hsotg: Pointer to struct dwc2_hsotg
 329  *
 330  * Must be called with interrupt disabled and spinlock held
 331  */
 332 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
 333 {
 334         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
 335
 336         /*
 337          * The root hub should be disconnected before this function is called.
 338          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 339          * and the QH lists (via ..._hcd_endpoint_disable).
 340          */
 341
 342         /* Turn off all host-specific interrupts */
 343         dwc2_disable_host_interrupts(hsotg);
 344
 345         /* Turn off the vbus power */
 346         dev_dbg(hsotg->dev, "PortPower off\n");
 347         writel(0, hsotg->regs + HPRT0);
 348 }
 349
 350 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
 351                                 struct dwc2_hcd_urb *urb, void **ep_handle,
 352                                 gfp_t mem_flags)
 353 {
 354         struct dwc2_qtd *qtd;
 355         unsigned long flags;
 356         u32 intr_mask;
 357         int retval;
 358
 359         if (!hsotg->flags.b.port_connect_status) {
 360                 /* No longer connected */
 361                 dev_err(hsotg->dev, "Not connected\n");
 362                 return -ENODEV;
 363         }
 364
 365         qtd = kzalloc(sizeof(*qtd), mem_flags);
 366         if (!qtd)
 367                 return -ENOMEM;
 368
 369         dwc2_hcd_qtd_init(qtd, urb);
 370         retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
 371                                   mem_flags);
 372         if (retval < 0) {
 373                 dev_err(hsotg->dev,
 374                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
 375                         retval);
 376                 kfree(qtd);
 377                 return retval;
 378         }
 379
 380         intr_mask = readl(hsotg->regs + GINTMSK);
 381         if (!(intr_mask & GINTSTS_SOF) && retval == 0) {
 382                 enum dwc2_transaction_type tr_type;
 383
 384                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
 385                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
 386                         /*
 387                          * Do not schedule SG transactions until qtd has
 388                          * URB_GIVEBACK_ASAP set
 389                          */
 390                         return 0;
 391
 392                 spin_lock_irqsave(&hsotg->lock, flags);
 393                 tr_type = dwc2_hcd_select_transactions(hsotg);
 394                 if (tr_type != DWC2_TRANSACTION_NONE)
 395                         dwc2_hcd_queue_transactions(hsotg, tr_type);
 396                 spin_unlock_irqrestore(&hsotg->lock, flags);
 397         }
 398
 399         return retval;
 400 }
 401
 402 /* Must be called with interrupt disabled and spinlock held */
 403 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
 404                                 struct dwc2_hcd_urb *urb)
 405 {
 406         struct dwc2_qh *qh;
 407         struct dwc2_qtd *urb_qtd;
 408
 409         urb_qtd = urb->qtd;
 410         if (!urb_qtd) {
 411                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
 412                 return -EINVAL;
 413         }
 414
 415         qh = urb_qtd->qh;
 416         if (!qh) {
 417                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
 418                 return -EINVAL;
 419         }
 420
 421         urb->priv = NULL;
 422
 423         if (urb_qtd->in_process && qh->channel) {
 424                 dwc2_dump_channel_info(hsotg, qh->channel);
 425
 426                 /* The QTD is in process (it has been assigned to a channel) */
 427                 if (hsotg->flags.b.port_connect_status)
 428                         /*
 429                          * If still connected (i.e. in host mode), halt the
 430                          * channel so it can be used for other transfers. If
 431                          * no longer connected, the host registers can't be
 432                          * written to halt the channel since the core is in
 433                          * device mode.
 434                          */
 435                         dwc2_hc_halt(hsotg, qh->channel,
 436                                      DWC2_HC_XFER_URB_DEQUEUE);
 437         }
 438
 439         /*
 440          * Free the QTD and clean up the associated QH. Leave the QH in the
 441          * schedule if it has any remaining QTDs.
 442          */
 443         if (hsotg->core_params->dma_desc_enable <= 0) {
 444                 u8 in_process = urb_qtd->in_process;
 445
 446                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 447                 if (in_process) {
 448                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
 449                         qh->channel = NULL;
 450                 } else if (list_empty(&qh->qtd_list)) {
 451                         dwc2_hcd_qh_unlink(hsotg, qh);
 452                 }
 453         } else {
 454                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 455         }
 456
 457         return 0;
 458 }
 459
 460 /* Must NOT be called with interrupt disabled or spinlock held */
 461 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
 462                                      struct usb_host_endpoint *ep, int retry)
 463 {
 464         struct dwc2_qtd *qtd, *qtd_tmp;
 465         struct dwc2_qh *qh;
 466         unsigned long flags;
 467         int rc;
 468
 469         spin_lock_irqsave(&hsotg->lock, flags);
 470
 471         qh = ep->hcpriv;
 472         if (!qh) {
 473                 rc = -EINVAL;
 474                 goto err;
 475         }
 476
 477         while (!list_empty(&qh->qtd_list) && retry--) {
 478                 if (retry == 0) {
 479                         dev_err(hsotg->dev,
 480                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
 481                         rc = -EBUSY;
 482                         goto err;
 483                 }
 484
 485                 spin_unlock_irqrestore(&hsotg->lock, flags);
 486                 usleep_range(20000, 40000);
 487                 spin_lock_irqsave(&hsotg->lock, flags);
 488                 qh = ep->hcpriv;
 489                 if (!qh) {
 490                         rc = -EINVAL;
 491                         goto err;
 492                 }
 493         }
 494
 495         dwc2_hcd_qh_unlink(hsotg, qh);
 496
 497         /* Free each QTD in the QH's QTD list */
 498         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
 499                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 500
 501         ep->hcpriv = NULL;
 502         spin_unlock_irqrestore(&hsotg->lock, flags);
 503         dwc2_hcd_qh_free(hsotg, qh);
 504
 505         return 0;
 506
 507 err:
 508         ep->hcpriv = NULL;
 509         spin_unlock_irqrestore(&hsotg->lock, flags);
 510
 511         return rc;
 512 }
 513
 514 /* Must be called with interrupt disabled and spinlock held */
 515 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
 516                                    struct usb_host_endpoint *ep)
 517 {
 518         struct dwc2_qh *qh = ep->hcpriv;
 519
 520         if (!qh)
 521                 return -EINVAL;
 522
 523         qh->data_toggle = DWC2_HC_PID_DATA0;
 524
 525         return 0;
 526 }
 527
 528 /*
 529  * Initializes dynamic portions of the DWC_otg HCD state
 530  *
 531  * Must be called with interrupt disabled and spinlock held
 532  */
 533 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
 534 {
 535         struct dwc2_host_chan *chan, *chan_tmp;
 536         int num_channels;
 537         int i;
 538
 539         hsotg->flags.d32 = 0;
 540
 541         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
 542         hsotg->non_periodic_channels = 0;
 543         hsotg->periodic_channels = 0;
 544
 545         /*
 546          * Put all channels in the free channel list and clean up channel
 547          * states
 548          */
 549         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
 550                                  hc_list_entry)
 551                 list_del_init(&chan->hc_list_entry);
 552
 553         num_channels = hsotg->core_params->host_channels;
 554         for (i = 0; i < num_channels; i++) {
 555                 chan = hsotg->hc_ptr_array[i];
 556                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 557                 dwc2_hc_cleanup(hsotg, chan);
 558         }
 559
 560         /* Initialize the DWC core for host mode operation */
 561         dwc2_core_host_init(hsotg);
 562 }
 563
 564 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
 565                                struct dwc2_host_chan *chan,
 566                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
 567 {
 568         int hub_addr, hub_port;
 569
 570         chan->do_split = 1;
 571         chan->xact_pos = qtd->isoc_split_pos;
 572         chan->complete_split = qtd->complete_split;
 573         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
 574         chan->hub_addr = (u8)hub_addr;
 575         chan->hub_port = (u8)hub_port;
 576 }
 577
 578 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
 579                                struct dwc2_host_chan *chan,
 580                                struct dwc2_qtd *qtd, void *bufptr)
 581 {
 582         struct dwc2_hcd_urb *urb = qtd->urb;
 583         struct dwc2_hcd_iso_packet_desc *frame_desc;
 584
 585         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
 586         case USB_ENDPOINT_XFER_CONTROL:
 587                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
 588
 589                 switch (qtd->control_phase) {
 590                 case DWC2_CONTROL_SETUP:
 591                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
 592                         chan->do_ping = 0;
 593                         chan->ep_is_in = 0;
 594                         chan->data_pid_start = DWC2_HC_PID_SETUP;
 595                         if (hsotg->core_params->dma_enable > 0)
 596                                 chan->xfer_dma = urb->setup_dma;
 597                         else
 598                                 chan->xfer_buf = urb->setup_packet;
 599                         chan->xfer_len = 8;
 600                         bufptr = NULL;
 601                         break;
 602
 603                 case DWC2_CONTROL_DATA:
 604                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
 605                         chan->data_pid_start = qtd->data_toggle;
 606                         break;
 607
 608                 case DWC2_CONTROL_STATUS:
 609                         /*
 610                          * Direction is opposite of data direction or IN if no
 611                          * data
 612                          */
 613                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
 614                         if (urb->length == 0)
 615                                 chan->ep_is_in = 1;
 616                         else
 617                                 chan->ep_is_in =
 618                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
 619                         if (chan->ep_is_in)
 620                                 chan->do_ping = 0;
 621                         chan->data_pid_start = DWC2_HC_PID_DATA1;
 622                         chan->xfer_len = 0;
 623                         if (hsotg->core_params->dma_enable > 0)
 624                                 chan->xfer_dma = hsotg->status_buf_dma;
 625                         else
 626                                 chan->xfer_buf = hsotg->status_buf;
 627                         bufptr = NULL;
 628                         break;
 629                 }
 630                 break;
 631
 632         case USB_ENDPOINT_XFER_BULK:
 633                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
 634                 break;
 635
 636         case USB_ENDPOINT_XFER_INT:
 637                 chan->ep_type = USB_ENDPOINT_XFER_INT;
 638                 break;
 639
 640         case USB_ENDPOINT_XFER_ISOC:
 641                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
 642                 if (hsotg->core_params->dma_desc_enable > 0)
 643                         break;
 644
 645                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 646                 frame_desc->status = 0;
 647
 648                 if (hsotg->core_params->dma_enable > 0) {
 649                         chan->xfer_dma = urb->dma;
 650                         chan->xfer_dma += frame_desc->offset +
 651                                         qtd->isoc_split_offset;
 652                 } else {
 653                         chan->xfer_buf = urb->buf;
 654                         chan->xfer_buf += frame_desc->offset +
 655                                         qtd->isoc_split_offset;
 656                 }
 657
 658                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
 659
 660                 /* For non-dword aligned buffers */
 661                 if (hsotg->core_params->dma_enable > 0 &&
 662                     (chan->xfer_dma & 0x3))
 663                         bufptr = (u8 *)urb->buf + frame_desc->offset +
 664                                         qtd->isoc_split_offset;
 665                 else
 666                         bufptr = NULL;
 667
 668                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
 669                         if (chan->xfer_len <= 188)
 670                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
 671                         else
 672                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
 673                 }
 674                 break;
 675         }
 676
 677         return bufptr;
 678 }
 679
 680 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 681                                    struct dwc2_host_chan *chan, void *bufptr)
 682 {
 683         u32 buf_size;
 684
 685         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
 686                 buf_size = hsotg->core_params->max_transfer_size;
 687         else
 688                 buf_size = 4096;
 689
 690         if (!qh->dw_align_buf) {
 691                 qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size,
 692                                                       &qh->dw_align_buf_dma,
 693                                                       GFP_ATOMIC);
 694                 if (!qh->dw_align_buf)
 695                         return -ENOMEM;
 696         }
 697
 698         if (!chan->ep_is_in && chan->xfer_len) {
 699                 dma_sync_single_for_cpu(hsotg->dev, chan->xfer_dma, buf_size,
 700                                         DMA_TO_DEVICE);
 701                 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len);
 702                 dma_sync_single_for_device(hsotg->dev, chan->xfer_dma, buf_size,
 703                                            DMA_TO_DEVICE);
 704         }
 705
 706         chan->align_buf = qh->dw_align_buf_dma;
 707         return 0;
 708 }
 709
 710 /**
 711  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
 712  * channel and initializes the host channel to perform the transactions. The
 713  * host channel is removed from the free list.
 714  *
 715  * @hsotg: The HCD state structure
 716  * @qh:    Transactions from the first QTD for this QH are selected and assigned
 717  *         to a free host channel
 718  */
 719 static void dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg,
 720                                     struct dwc2_qh *qh)
 721 {
 722         struct dwc2_host_chan *chan;
 723         struct dwc2_hcd_urb *urb;
 724         struct dwc2_qtd *qtd;
 725         void *bufptr = NULL;
 726
 727         if (dbg_qh(qh))
 728                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
 729
 730         if (list_empty(&qh->qtd_list)) {
 731                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
 732                 return;
 733         }
 734
 735         if (list_empty(&hsotg->free_hc_list)) {
 736                 dev_dbg(hsotg->dev, "No free channel to assign\n");
 737                 return;
 738         }
 739
 740         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
 741                                 hc_list_entry);
 742
 743         /* Remove the host channel from the free list */
 744         list_del_init(&chan->hc_list_entry);
 745
 746         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 747         urb = qtd->urb;
 748         qh->channel = chan;
 749         qtd->in_process = 1;
 750
 751         /*
 752          * Use usb_pipedevice to determine device address. This address is
 753          * 0 before the SET_ADDRESS command and the correct address afterward.
 754          */
 755         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
 756         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
 757         chan->speed = qh->dev_speed;
 758         chan->max_packet = dwc2_max_packet(qh->maxp);
 759
 760         chan->xfer_started = 0;
 761         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
 762         chan->error_state = (qtd->error_count > 0);
 763         chan->halt_on_queue = 0;
 764         chan->halt_pending = 0;
 765         chan->requests = 0;
 766
 767         /*
 768          * The following values may be modified in the transfer type section
 769          * below. The xfer_len value may be reduced when the transfer is
 770          * started to accommodate the max widths of the XferSize and PktCnt
 771          * fields in the HCTSIZn register.
 772          */
 773
 774         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
 775         if (chan->ep_is_in)
 776                 chan->do_ping = 0;
 777         else
 778                 chan->do_ping = qh->ping_state;
 779
 780         chan->data_pid_start = qh->data_toggle;
 781         chan->multi_count = 1;
 782
 783         if (hsotg->core_params->dma_enable > 0) {
 784                 chan->xfer_dma = urb->dma + urb->actual_length;
 785
 786                 /* For non-dword aligned case */
 787                 if (hsotg->core_params->dma_desc_enable <= 0 &&
 788                     (chan->xfer_dma & 0x3))
 789                         bufptr = (u8 *)urb->buf + urb->actual_length;
 790         } else {
 791                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
 792         }
 793
 794         chan->xfer_len = urb->length - urb->actual_length;
 795         chan->xfer_count = 0;
 796
 797         /* Set the split attributes if required */
 798         if (qh->do_split)
 799                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
 800         else
 801                 chan->do_split = 0;
 802
 803         /* Set the transfer attributes */
 804         bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
 805
 806         /* Non DWORD-aligned buffer case */
 807         if (bufptr) {
 808                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
 809                 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) {
 810                         dev_err(hsotg->dev,
 811                                 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
 812                                 __func__);
 813                         /* Add channel back to free list */
 814                         chan->align_buf = 0;
 815                         chan->multi_count = 0;
 816                         list_add_tail(&chan->hc_list_entry,
 817                                       &hsotg->free_hc_list);
 818                         qtd->in_process = 0;
 819                         qh->channel = NULL;
 820                         return;
 821                 }
 822         } else {
 823                 chan->align_buf = 0;
 824         }
 825
 826         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 827             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 828                 /*
 829                  * This value may be modified when the transfer is started
 830                  * to reflect the actual transfer length
 831                  */
 832                 chan->multi_count = dwc2_hb_mult(qh->maxp);
 833
 834         if (hsotg->core_params->dma_desc_enable > 0)
 835                 chan->desc_list_addr = qh->desc_list_dma;
 836
 837         dwc2_hc_init(hsotg, chan);
 838         chan->qh = qh;
 839 }
 840
 841 /**
 842  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
 843  * schedule and assigns them to available host channels. Called from the HCD
 844  * interrupt handler functions.
 845  *
 846  * @hsotg: The HCD state structure
 847  *
 848  * Return: The types of new transactions that were assigned to host channels
 849  */
 850 enum dwc2_transaction_type dwc2_hcd_select_transactions(
 851                 struct dwc2_hsotg *hsotg)
 852 {
 853         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
 854         struct list_head *qh_ptr;
 855         struct dwc2_qh *qh;
 856         int num_channels;
 857
 858 #ifdef DWC2_DEBUG_SOF
 859         dev_vdbg(hsotg->dev, "  Select Transactions\n");
 860 #endif
 861
 862         /* Process entries in the periodic ready list */
 863         qh_ptr = hsotg->periodic_sched_ready.next;
 864         while (qh_ptr != &hsotg->periodic_sched_ready) {
 865                 if (list_empty(&hsotg->free_hc_list))
 866                         break;
 867                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 868                 dwc2_assign_and_init_hc(hsotg, qh);
 869
 870                 /*
 871                  * Move the QH from the periodic ready schedule to the
 872                  * periodic assigned schedule
 873                  */
 874                 qh_ptr = qh_ptr->next;
 875                 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
 876                 ret_val = DWC2_TRANSACTION_PERIODIC;
 877         }
 878
 879         /*
 880          * Process entries in the inactive portion of the non-periodic
 881          * schedule. Some free host channels may not be used if they are
 882          * reserved for periodic transfers.
 883          */
 884         num_channels = hsotg->core_params->host_channels;
 885         qh_ptr = hsotg->non_periodic_sched_inactive.next;
 886         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
 887                 if (hsotg->non_periodic_channels >= num_channels -
 888                                                 hsotg->periodic_channels)
 889                         break;
 890                 if (list_empty(&hsotg->free_hc_list))
 891                         break;
 892                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 893                 dwc2_assign_and_init_hc(hsotg, qh);
 894
 895                 /*
 896                  * Move the QH from the non-periodic inactive schedule to the
 897                  * non-periodic active schedule
 898                  */
 899                 qh_ptr = qh_ptr->next;
 900                 list_move(&qh->qh_list_entry,
 901                           &hsotg->non_periodic_sched_active);
 902
 903                 if (ret_val == DWC2_TRANSACTION_NONE)
 904                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
 905                 else
 906                         ret_val = DWC2_TRANSACTION_ALL;
 907
 908                 hsotg->non_periodic_channels++;
 909         }
 910
 911         return ret_val;
 912 }
 913
 914 /**
 915  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
 916  * a host channel associated with either a periodic or non-periodic transfer
 917  *
 918  * @hsotg: The HCD state structure
 919  * @chan:  Host channel descriptor associated with either a periodic or
 920  *         non-periodic transfer
 921  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
 922  *                     for periodic transfers or the non-periodic Tx FIFO
 923  *                     for non-periodic transfers
 924  *
 925  * Return: 1 if a request is queued and more requests may be needed to
 926  * complete the transfer, 0 if no more requests are required for this
 927  * transfer, -1 if there is insufficient space in the Tx FIFO
 928  *
 929  * This function assumes that there is space available in the appropriate
 930  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
 931  * it checks whether space is available in the appropriate Tx FIFO.
 932  *
 933  * Must be called with interrupt disabled and spinlock held
 934  */
 935 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
 936                                   struct dwc2_host_chan *chan,
 937                                   u16 fifo_dwords_avail)
 938 {
 939         int retval = 0;
 940
 941         if (hsotg->core_params->dma_enable > 0) {
 942                 if (hsotg->core_params->dma_desc_enable > 0) {
 943                         if (!chan->xfer_started ||
 944                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
 945                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
 946                                 chan->qh->ping_state = 0;
 947                         }
 948                 } else if (!chan->xfer_started) {
 949                         dwc2_hc_start_transfer(hsotg, chan);
 950                         chan->qh->ping_state = 0;
 951                 }
 952         } else if (chan->halt_pending) {
 953                 /* Don't queue a request if the channel has been halted */
 954         } else if (chan->halt_on_queue) {
 955                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
 956         } else if (chan->do_ping) {
 957                 if (!chan->xfer_started)
 958                         dwc2_hc_start_transfer(hsotg, chan);
 959         } else if (!chan->ep_is_in ||
 960                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
 961                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
 962                         if (!chan->xfer_started) {
 963                                 dwc2_hc_start_transfer(hsotg, chan);
 964                                 retval = 1;
 965                         } else {
 966                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
 967                         }
 968                 } else {
 969                         retval = -1;
 970                 }
 971         } else {
 972                 if (!chan->xfer_started) {
 973                         dwc2_hc_start_transfer(hsotg, chan);
 974                         retval = 1;
 975                 } else {
 976                         retval = dwc2_hc_continue_transfer(hsotg, chan);
 977                 }
 978         }
 979
 980         return retval;
 981 }
 982
 983 /*
 984  * Processes periodic channels for the next frame and queues transactions for
 985  * these channels to the DWC_otg controller. After queueing transactions, the
 986  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
 987  * to queue as Periodic Tx FIFO or request queue space becomes available.
 988  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
 989  *
 990  * Must be called with interrupt disabled and spinlock held
 991  */
 992 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
 993 {
 994         struct list_head *qh_ptr;
 995         struct dwc2_qh *qh;
 996         u32 tx_status;
 997         u32 fspcavail;
 998         u32 gintmsk;
 999         int status;
1000         int no_queue_space = 0;
1001         int no_fifo_space = 0;
1002         u32 qspcavail;
1003
1004         if (dbg_perio())
1005                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1006
1007         tx_status = readl(hsotg->regs + HPTXSTS);
1008         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1009                     TXSTS_QSPCAVAIL_SHIFT;
1010         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1011                     TXSTS_FSPCAVAIL_SHIFT;
1012
1013         if (dbg_perio()) {
1014                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
1015                          qspcavail);
1016                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
1017                          fspcavail);
1018         }
1019
1020         qh_ptr = hsotg->periodic_sched_assigned.next;
1021         while (qh_ptr != &hsotg->periodic_sched_assigned) {
1022                 tx_status = readl(hsotg->regs + HPTXSTS);
1023                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1024                             TXSTS_QSPCAVAIL_SHIFT;
1025                 if (qspcavail == 0) {
1026                         no_queue_space = 1;
1027                         break;
1028                 }
1029
1030                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1031                 if (!qh->channel) {
1032                         qh_ptr = qh_ptr->next;
1033                         continue;
1034                 }
1035
1036                 /* Make sure EP's TT buffer is clean before queueing qtds */
1037                 if (qh->tt_buffer_dirty) {
1038                         qh_ptr = qh_ptr->next;
1039                         continue;
1040                 }
1041
1042                 /*
1043                  * Set a flag if we're queuing high-bandwidth in slave mode.
1044                  * The flag prevents any halts to get into the request queue in
1045                  * the middle of multiple high-bandwidth packets getting queued.
1046                  */
1047                 if (hsotg->core_params->dma_enable <= 0 &&
1048                                 qh->channel->multi_count > 1)
1049                         hsotg->queuing_high_bandwidth = 1;
1050
1051                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1052                             TXSTS_FSPCAVAIL_SHIFT;
1053                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1054                 if (status < 0) {
1055                         no_fifo_space = 1;
1056                         break;
1057                 }
1058
1059                 /*
1060                  * In Slave mode, stay on the current transfer until there is
1061                  * nothing more to do or the high-bandwidth request count is
1062                  * reached. In DMA mode, only need to queue one request. The
1063                  * controller automatically handles multiple packets for
1064                  * high-bandwidth transfers.
1065                  */
1066                 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1067                     qh->channel->requests == qh->channel->multi_count) {
1068                         qh_ptr = qh_ptr->next;
1069                         /*
1070                          * Move the QH from the periodic assigned schedule to
1071                          * the periodic queued schedule
1072                          */
1073                         list_move(&qh->qh_list_entry,
1074                                   &hsotg->periodic_sched_queued);
1075
1076                         /* done queuing high bandwidth */
1077                         hsotg->queuing_high_bandwidth = 0;
1078                 }
1079         }
1080
1081         if (hsotg->core_params->dma_enable <= 0) {
1082                 tx_status = readl(hsotg->regs + HPTXSTS);
1083                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1084                             TXSTS_QSPCAVAIL_SHIFT;
1085                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1086                             TXSTS_FSPCAVAIL_SHIFT;
1087                 if (dbg_perio()) {
1088                         dev_vdbg(hsotg->dev,
1089                                  "  P Tx Req Queue Space Avail (after queue): %d\n",
1090                                  qspcavail);
1091                         dev_vdbg(hsotg->dev,
1092                                  "  P Tx FIFO Space Avail (after queue): %d\n",
1093                                  fspcavail);
1094                 }
1095
1096                 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1097                     no_queue_space || no_fifo_space) {
1098                         /*
1099                          * May need to queue more transactions as the request
1100                          * queue or Tx FIFO empties. Enable the periodic Tx
1101                          * FIFO empty interrupt. (Always use the half-empty
1102                          * level to ensure that new requests are loaded as
1103                          * soon as possible.)
1104                          */
1105                         gintmsk = readl(hsotg->regs + GINTMSK);
1106                         gintmsk |= GINTSTS_PTXFEMP;
1107                         writel(gintmsk, hsotg->regs + GINTMSK);
1108                 } else {
1109                         /*
1110                          * Disable the Tx FIFO empty interrupt since there are
1111                          * no more transactions that need to be queued right
1112                          * now. This function is called from interrupt
1113                          * handlers to queue more transactions as transfer
1114                          * states change.
1115                          */
1116                         gintmsk = readl(hsotg->regs + GINTMSK);
1117                         gintmsk &= ~GINTSTS_PTXFEMP;
1118                         writel(gintmsk, hsotg->regs + GINTMSK);
1119                 }
1120         }
1121 }
1122
1123 /*
1124  * Processes active non-periodic channels and queues transactions for these
1125  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1126  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1127  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1128  * FIFO Empty interrupt is disabled.
1129  *
1130  * Must be called with interrupt disabled and spinlock held
1131  */
1132 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1133 {
1134         struct list_head *orig_qh_ptr;
1135         struct dwc2_qh *qh;
1136         u32 tx_status;
1137         u32 qspcavail;
1138         u32 fspcavail;
1139         u32 gintmsk;
1140         int status;
1141         int no_queue_space = 0;
1142         int no_fifo_space = 0;
1143         int more_to_do = 0;
1144
1145         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1146
1147         tx_status = readl(hsotg->regs + GNPTXSTS);
1148         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1149                     TXSTS_QSPCAVAIL_SHIFT;
1150         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1151                     TXSTS_FSPCAVAIL_SHIFT;
1152         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
1153                  qspcavail);
1154         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
1155                  fspcavail);
1156
1157         /*
1158          * Keep track of the starting point. Skip over the start-of-list
1159          * entry.
1160          */
1161         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1162                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1163         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1164
1165         /*
1166          * Process once through the active list or until no more space is
1167          * available in the request queue or the Tx FIFO
1168          */
1169         do {
1170                 tx_status = readl(hsotg->regs + GNPTXSTS);
1171                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1172                             TXSTS_QSPCAVAIL_SHIFT;
1173                 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1174                         no_queue_space = 1;
1175                         break;
1176                 }
1177
1178                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1179                                 qh_list_entry);
1180                 if (!qh->channel)
1181                         goto next;
1182
1183                 /* Make sure EP's TT buffer is clean before queueing qtds */
1184                 if (qh->tt_buffer_dirty)
1185                         goto next;
1186
1187                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1188                             TXSTS_FSPCAVAIL_SHIFT;
1189                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1190
1191                 if (status > 0) {
1192                         more_to_do = 1;
1193                 } else if (status < 0) {
1194                         no_fifo_space = 1;
1195                         break;
1196                 }
1197 next:
1198                 /* Advance to next QH, skipping start-of-list entry */
1199                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1200                 if (hsotg->non_periodic_qh_ptr ==
1201                                 &hsotg->non_periodic_sched_active)
1202                         hsotg->non_periodic_qh_ptr =
1203                                         hsotg->non_periodic_qh_ptr->next;
1204         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1205
1206         if (hsotg->core_params->dma_enable <= 0) {
1207                 tx_status = readl(hsotg->regs + GNPTXSTS);
1208                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1209                             TXSTS_QSPCAVAIL_SHIFT;
1210                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1211                             TXSTS_FSPCAVAIL_SHIFT;
1212                 dev_vdbg(hsotg->dev,
1213                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
1214                          qspcavail);
1215                 dev_vdbg(hsotg->dev,
1216                          "  NP Tx FIFO Space Avail (after queue): %d\n",
1217                          fspcavail);
1218
1219                 if (more_to_do || no_queue_space || no_fifo_space) {
1220                         /*
1221                          * May need to queue more transactions as the request
1222                          * queue or Tx FIFO empties. Enable the non-periodic
1223                          * Tx FIFO empty interrupt. (Always use the half-empty
1224                          * level to ensure that new requests are loaded as
1225                          * soon as possible.)
1226                          */
1227                         gintmsk = readl(hsotg->regs + GINTMSK);
1228                         gintmsk |= GINTSTS_NPTXFEMP;
1229                         writel(gintmsk, hsotg->regs + GINTMSK);
1230                 } else {
1231                         /*
1232                          * Disable the Tx FIFO empty interrupt since there are
1233                          * no more transactions that need to be queued right
1234                          * now. This function is called from interrupt
1235                          * handlers to queue more transactions as transfer
1236                          * states change.
1237                          */
1238                         gintmsk = readl(hsotg->regs + GINTMSK);
1239                         gintmsk &= ~GINTSTS_NPTXFEMP;
1240                         writel(gintmsk, hsotg->regs + GINTMSK);
1241                 }
1242         }
1243 }
1244
1245 /**
1246  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1247  * and queues transactions for these channels to the DWC_otg controller. Called
1248  * from the HCD interrupt handler functions.
1249  *
1250  * @hsotg:   The HCD state structure
1251  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1252  *           or both)
1253  *
1254  * Must be called with interrupt disabled and spinlock held
1255  */
1256 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1257                                  enum dwc2_transaction_type tr_type)
1258 {
1259 #ifdef DWC2_DEBUG_SOF
1260         dev_vdbg(hsotg->dev, "Queue Transactions\n");
1261 #endif
1262         /* Process host channels associated with periodic transfers */
1263         if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1264              tr_type == DWC2_TRANSACTION_ALL) &&
1265             !list_empty(&hsotg->periodic_sched_assigned))
1266                 dwc2_process_periodic_channels(hsotg);
1267
1268         /* Process host channels associated with non-periodic transfers */
1269         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1270             tr_type == DWC2_TRANSACTION_ALL) {
1271                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1272                         dwc2_process_non_periodic_channels(hsotg);
1273                 } else {
1274                         /*
1275                          * Ensure NP Tx FIFO empty interrupt is disabled when
1276                          * there are no non-periodic transfers to process
1277                          */
1278                         u32 gintmsk = readl(hsotg->regs + GINTMSK);
1279
1280                         gintmsk &= ~GINTSTS_NPTXFEMP;
1281                         writel(gintmsk, hsotg->regs + GINTMSK);
1282                 }
1283         }
1284 }
1285
1286 static void dwc2_conn_id_status_change(struct work_struct *work)
1287 {
1288         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1289                                                 wf_otg);
1290         u32 count = 0;
1291         u32 gotgctl;
1292
1293         dev_dbg(hsotg->dev, "%s()\n", __func__);
1294
1295         gotgctl = readl(hsotg->regs + GOTGCTL);
1296         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1297         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1298                 !!(gotgctl & GOTGCTL_CONID_B));
1299
1300         /* B-Device connector (Device Mode) */
1301         if (gotgctl & GOTGCTL_CONID_B) {
1302                 /* Wait for switch to device mode */
1303                 dev_dbg(hsotg->dev, "connId B\n");
1304                 while (!dwc2_is_device_mode(hsotg)) {
1305                         dev_info(hsotg->dev,
1306                                  "Waiting for Peripheral Mode, Mode=%s\n",
1307                                  dwc2_is_host_mode(hsotg) ? "Host" :
1308                                  "Peripheral");
1309                         usleep_range(20000, 40000);
1310                         if (++count > 250)
1311                                 break;
1312                 }
1313                 if (count > 250)
1314                         dev_err(hsotg->dev,
1315                                 "Connection id status change timed out\n");
1316                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1317                 dwc2_core_init(hsotg, false, -1);
1318                 dwc2_enable_global_interrupts(hsotg);
1319         } else {
1320                 /* A-Device connector (Host Mode) */
1321                 dev_dbg(hsotg->dev, "connId A\n");
1322                 while (!dwc2_is_host_mode(hsotg)) {
1323                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1324                                  dwc2_is_host_mode(hsotg) ?
1325                                  "Host" : "Peripheral");
1326                         usleep_range(20000, 40000);
1327                         if (++count > 250)
1328                                 break;
1329                 }
1330                 if (count > 250)
1331                         dev_err(hsotg->dev,
1332                                 "Connection id status change timed out\n");
1333                 hsotg->op_state = OTG_STATE_A_HOST;
1334
1335                 /* Initialize the Core for Host mode */
1336                 dwc2_core_init(hsotg, false, -1);
1337                 dwc2_enable_global_interrupts(hsotg);
1338                 dwc2_hcd_start(hsotg);
1339         }
1340 }
1341
1342 static void dwc2_wakeup_detected(unsigned long data)
1343 {
1344         struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1345         u32 hprt0;
1346
1347         dev_dbg(hsotg->dev, "%s()\n", __func__);
1348
1349         /*
1350          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1351          * so that OPT tests pass with all PHYs.)
1352          */
1353         hprt0 = dwc2_read_hprt0(hsotg);
1354         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1355         hprt0 &= ~HPRT0_RES;
1356         writel(hprt0, hsotg->regs + HPRT0);
1357         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1358                 readl(hsotg->regs + HPRT0));
1359
1360         dwc2_hcd_rem_wakeup(hsotg);
1361
1362         /* Change to L0 state */
1363         hsotg->lx_state = DWC2_L0;
1364 }
1365
1366 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1367 {
1368         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1369
1370         return hcd->self.b_hnp_enable;
1371 }
1372
1373 /* Must NOT be called with interrupt disabled or spinlock held */
1374 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1375 {
1376         unsigned long flags;
1377         u32 hprt0;
1378         u32 pcgctl;
1379         u32 gotgctl;
1380
1381         dev_dbg(hsotg->dev, "%s()\n", __func__);
1382
1383         spin_lock_irqsave(&hsotg->lock, flags);
1384
1385         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1386                 gotgctl = readl(hsotg->regs + GOTGCTL);
1387                 gotgctl |= GOTGCTL_HSTSETHNPEN;
1388                 writel(gotgctl, hsotg->regs + GOTGCTL);
1389                 hsotg->op_state = OTG_STATE_A_SUSPEND;
1390         }
1391
1392         hprt0 = dwc2_read_hprt0(hsotg);
1393         hprt0 |= HPRT0_SUSP;
1394         writel(hprt0, hsotg->regs + HPRT0);
1395
1396         /* Update lx_state */
1397         hsotg->lx_state = DWC2_L2;
1398
1399         /* Suspend the Phy Clock */
1400         pcgctl = readl(hsotg->regs + PCGCTL);
1401         pcgctl |= PCGCTL_STOPPCLK;
1402         writel(pcgctl, hsotg->regs + PCGCTL);
1403         udelay(10);
1404
1405         /* For HNP the bus must be suspended for at least 200ms */
1406         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1407                 pcgctl = readl(hsotg->regs + PCGCTL);
1408                 pcgctl &= ~PCGCTL_STOPPCLK;
1409                 writel(pcgctl, hsotg->regs + PCGCTL);
1410
1411                 spin_unlock_irqrestore(&hsotg->lock, flags);
1412
1413                 usleep_range(200000, 250000);
1414         } else {
1415                 spin_unlock_irqrestore(&hsotg->lock, flags);
1416         }
1417 }
1418
1419 /* Handles hub class-specific requests */
1420 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1421                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
1422 {
1423         struct usb_hub_descriptor *hub_desc;
1424         int retval = 0;
1425         u32 hprt0;
1426         u32 port_status;
1427         u32 speed;
1428         u32 pcgctl;
1429
1430         switch (typereq) {
1431         case ClearHubFeature:
1432                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1433
1434                 switch (wvalue) {
1435                 case C_HUB_LOCAL_POWER:
1436                 case C_HUB_OVER_CURRENT:
1437                         /* Nothing required here */
1438                         break;
1439
1440                 default:
1441                         retval = -EINVAL;
1442                         dev_err(hsotg->dev,
1443                                 "ClearHubFeature request %1xh unknown\n",
1444                                 wvalue);
1445                 }
1446                 break;
1447
1448         case ClearPortFeature:
1449                 if (wvalue != USB_PORT_FEAT_L1)
1450                         if (!windex || windex > 1)
1451                                 goto error;
1452                 switch (wvalue) {
1453                 case USB_PORT_FEAT_ENABLE:
1454                         dev_dbg(hsotg->dev,
1455                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1456                         hprt0 = dwc2_read_hprt0(hsotg);
1457                         hprt0 |= HPRT0_ENA;
1458                         writel(hprt0, hsotg->regs + HPRT0);
1459                         break;
1460
1461                 case USB_PORT_FEAT_SUSPEND:
1462                         dev_dbg(hsotg->dev,
1463                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1464                         writel(0, hsotg->regs + PCGCTL);
1465                         usleep_range(20000, 40000);
1466
1467                         hprt0 = dwc2_read_hprt0(hsotg);
1468                         hprt0 |= HPRT0_RES;
1469                         writel(hprt0, hsotg->regs + HPRT0);
1470                         hprt0 &= ~HPRT0_SUSP;
1471                         usleep_range(100000, 150000);
1472
1473                         hprt0 &= ~HPRT0_RES;
1474                         writel(hprt0, hsotg->regs + HPRT0);
1475                         break;
1476
1477                 case USB_PORT_FEAT_POWER:
1478                         dev_dbg(hsotg->dev,
1479                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1480                         hprt0 = dwc2_read_hprt0(hsotg);
1481                         hprt0 &= ~HPRT0_PWR;
1482                         writel(hprt0, hsotg->regs + HPRT0);
1483                         break;
1484
1485                 case USB_PORT_FEAT_INDICATOR:
1486                         dev_dbg(hsotg->dev,
1487                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1488                         /* Port indicator not supported */
1489                         break;
1490
1491                 case USB_PORT_FEAT_C_CONNECTION:
1492                         /*
1493                          * Clears driver's internal Connect Status Change flag
1494                          */
1495                         dev_dbg(hsotg->dev,
1496                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1497                         hsotg->flags.b.port_connect_status_change = 0;
1498                         break;
1499
1500                 case USB_PORT_FEAT_C_RESET:
1501                         /* Clears driver's internal Port Reset Change flag */
1502                         dev_dbg(hsotg->dev,
1503                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1504                         hsotg->flags.b.port_reset_change = 0;
1505                         break;
1506
1507                 case USB_PORT_FEAT_C_ENABLE:
1508                         /*
1509                          * Clears the driver's internal Port Enable/Disable
1510                          * Change flag
1511                          */
1512                         dev_dbg(hsotg->dev,
1513                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1514                         hsotg->flags.b.port_enable_change = 0;
1515                         break;
1516
1517                 case USB_PORT_FEAT_C_SUSPEND:
1518                         /*
1519                          * Clears the driver's internal Port Suspend Change
1520                          * flag, which is set when resume signaling on the host
1521                          * port is complete
1522                          */
1523                         dev_dbg(hsotg->dev,
1524                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1525                         hsotg->flags.b.port_suspend_change = 0;
1526                         break;
1527
1528                 case USB_PORT_FEAT_C_PORT_L1:
1529                         dev_dbg(hsotg->dev,
1530                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1531                         hsotg->flags.b.port_l1_change = 0;
1532                         break;
1533
1534                 case USB_PORT_FEAT_C_OVER_CURRENT:
1535                         dev_dbg(hsotg->dev,
1536                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1537                         hsotg->flags.b.port_over_current_change = 0;
1538                         break;
1539
1540                 default:
1541                         retval = -EINVAL;
1542                         dev_err(hsotg->dev,
1543                                 "ClearPortFeature request %1xh unknown or unsupported\n",
1544                                 wvalue);
1545                 }
1546                 break;
1547
1548         case GetHubDescriptor:
1549                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1550                 hub_desc = (struct usb_hub_descriptor *)buf;
1551                 hub_desc->bDescLength = 9;
1552                 hub_desc->bDescriptorType = 0x29;
1553                 hub_desc->bNbrPorts = 1;
1554                 hub_desc->wHubCharacteristics = cpu_to_le16(0x08);
1555                 hub_desc->bPwrOn2PwrGood = 1;
1556                 hub_desc->bHubContrCurrent = 0;
1557                 hub_desc->u.hs.DeviceRemovable[0] = 0;
1558                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1559                 break;
1560
1561         case GetHubStatus:
1562                 dev_dbg(hsotg->dev, "GetHubStatus\n");
1563                 memset(buf, 0, 4);
1564                 break;
1565
1566         case GetPortStatus:
1567                 dev_vdbg(hsotg->dev,
1568                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1569                          hsotg->flags.d32);
1570                 if (!windex || windex > 1)
1571                         goto error;
1572
1573                 port_status = 0;
1574                 if (hsotg->flags.b.port_connect_status_change)
1575                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1576                 if (hsotg->flags.b.port_enable_change)
1577                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
1578                 if (hsotg->flags.b.port_suspend_change)
1579                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1580                 if (hsotg->flags.b.port_l1_change)
1581                         port_status |= USB_PORT_STAT_C_L1 << 16;
1582                 if (hsotg->flags.b.port_reset_change)
1583                         port_status |= USB_PORT_STAT_C_RESET << 16;
1584                 if (hsotg->flags.b.port_over_current_change) {
1585                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
1586                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1587                 }
1588
1589                 if (!hsotg->flags.b.port_connect_status) {
1590                         /*
1591                          * The port is disconnected, which means the core is
1592                          * either in device mode or it soon will be. Just
1593                          * return 0's for the remainder of the port status
1594                          * since the port register can't be read if the core
1595                          * is in device mode.
1596                          */
1597                         *(__le32 *)buf = cpu_to_le32(port_status);
1598                         break;
1599                 }
1600
1601                 hprt0 = readl(hsotg->regs + HPRT0);
1602                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
1603
1604                 if (hprt0 & HPRT0_CONNSTS)
1605                         port_status |= USB_PORT_STAT_CONNECTION;
1606                 if (hprt0 & HPRT0_ENA)
1607                         port_status |= USB_PORT_STAT_ENABLE;
1608                 if (hprt0 & HPRT0_SUSP)
1609                         port_status |= USB_PORT_STAT_SUSPEND;
1610                 if (hprt0 & HPRT0_OVRCURRACT)
1611                         port_status |= USB_PORT_STAT_OVERCURRENT;
1612                 if (hprt0 & HPRT0_RST)
1613                         port_status |= USB_PORT_STAT_RESET;
1614                 if (hprt0 & HPRT0_PWR)
1615                         port_status |= USB_PORT_STAT_POWER;
1616
1617                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1618                 if (speed == HPRT0_SPD_HIGH_SPEED)
1619                         port_status |= USB_PORT_STAT_HIGH_SPEED;
1620                 else if (speed == HPRT0_SPD_LOW_SPEED)
1621                         port_status |= USB_PORT_STAT_LOW_SPEED;
1622
1623                 if (hprt0 & HPRT0_TSTCTL_MASK)
1624                         port_status |= USB_PORT_STAT_TEST;
1625                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1626
1627                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1628                 *(__le32 *)buf = cpu_to_le32(port_status);
1629                 break;
1630
1631         case SetHubFeature:
1632                 dev_dbg(hsotg->dev, "SetHubFeature\n");
1633                 /* No HUB features supported */
1634                 break;
1635
1636         case SetPortFeature:
1637                 dev_dbg(hsotg->dev, "SetPortFeature\n");
1638                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1639                         goto error;
1640
1641                 if (!hsotg->flags.b.port_connect_status) {
1642                         /*
1643                          * The port is disconnected, which means the core is
1644                          * either in device mode or it soon will be. Just
1645                          * return without doing anything since the port
1646                          * register can't be written if the core is in device
1647                          * mode.
1648                          */
1649                         break;
1650                 }
1651
1652                 switch (wvalue) {
1653                 case USB_PORT_FEAT_SUSPEND:
1654                         dev_dbg(hsotg->dev,
1655                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1656                         if (windex != hsotg->otg_port)
1657                                 goto error;
1658                         dwc2_port_suspend(hsotg, windex);
1659                         break;
1660
1661                 case USB_PORT_FEAT_POWER:
1662                         dev_dbg(hsotg->dev,
1663                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1664                         hprt0 = dwc2_read_hprt0(hsotg);
1665                         hprt0 |= HPRT0_PWR;
1666                         writel(hprt0, hsotg->regs + HPRT0);
1667                         break;
1668
1669                 case USB_PORT_FEAT_RESET:
1670                         hprt0 = dwc2_read_hprt0(hsotg);
1671                         dev_dbg(hsotg->dev,
1672                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1673                         pcgctl = readl(hsotg->regs + PCGCTL);
1674                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1675                         writel(pcgctl, hsotg->regs + PCGCTL);
1676                         /* ??? Original driver does this */
1677                         writel(0, hsotg->regs + PCGCTL);
1678
1679                         hprt0 = dwc2_read_hprt0(hsotg);
1680                         /* Clear suspend bit if resetting from suspend state */
1681                         hprt0 &= ~HPRT0_SUSP;
1682
1683                         /*
1684                          * When B-Host the Port reset bit is set in the Start
1685                          * HCD Callback function, so that the reset is started
1686                          * within 1ms of the HNP success interrupt
1687                          */
1688                         if (!dwc2_hcd_is_b_host(hsotg)) {
1689                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
1690                                 dev_dbg(hsotg->dev,
1691                                         "In host mode, hprt0=%08x\n", hprt0);
1692                                 writel(hprt0, hsotg->regs + HPRT0);
1693                         }
1694
1695                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1696                         usleep_range(50000, 70000);
1697                         hprt0 &= ~HPRT0_RST;
1698                         writel(hprt0, hsotg->regs + HPRT0);
1699                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
1700                         break;
1701
1702                 case USB_PORT_FEAT_INDICATOR:
1703                         dev_dbg(hsotg->dev,
1704                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1705                         /* Not supported */
1706                         break;
1707
1708                 default:
1709                         retval = -EINVAL;
1710                         dev_err(hsotg->dev,
1711                                 "SetPortFeature %1xh unknown or unsupported\n",
1712                                 wvalue);
1713                         break;
1714                 }
1715                 break;
1716
1717         default:
1718 error:
1719                 retval = -EINVAL;
1720                 dev_dbg(hsotg->dev,
1721                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1722                         typereq, windex, wvalue);
1723                 break;
1724         }
1725
1726         return retval;
1727 }
1728
1729 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1730 {
1731         int retval;
1732
1733         if (port != 1)
1734                 return -EINVAL;
1735
1736         retval = (hsotg->flags.b.port_connect_status_change ||
1737                   hsotg->flags.b.port_reset_change ||
1738                   hsotg->flags.b.port_enable_change ||
1739                   hsotg->flags.b.port_suspend_change ||
1740                   hsotg->flags.b.port_over_current_change);
1741
1742         if (retval) {
1743                 dev_dbg(hsotg->dev,
1744                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1745                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
1746                         hsotg->flags.b.port_connect_status_change);
1747                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
1748                         hsotg->flags.b.port_reset_change);
1749                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
1750                         hsotg->flags.b.port_enable_change);
1751                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
1752                         hsotg->flags.b.port_suspend_change);
1753                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
1754                         hsotg->flags.b.port_over_current_change);
1755         }
1756
1757         return retval;
1758 }
1759
1760 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1761 {
1762         u32 hfnum = readl(hsotg->regs + HFNUM);
1763
1764 #ifdef DWC2_DEBUG_SOF
1765         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1766                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1767 #endif
1768         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1769 }
1770
1771 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1772 {
1773         return (hsotg->op_state == OTG_STATE_B_HOST);
1774 }
1775
1776 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1777                                                int iso_desc_count,
1778                                                gfp_t mem_flags)
1779 {
1780         struct dwc2_hcd_urb *urb;
1781         u32 size = sizeof(*urb) + iso_desc_count *
1782                    sizeof(struct dwc2_hcd_iso_packet_desc);
1783
1784         urb = kzalloc(size, mem_flags);
1785         if (urb)
1786                 urb->packet_count = iso_desc_count;
1787         return urb;
1788 }
1789
1790 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1791                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
1792                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1793 {
1794         if (dbg_perio() ||
1795             ep_type == USB_ENDPOINT_XFER_BULK ||
1796             ep_type == USB_ENDPOINT_XFER_CONTROL)
1797                 dev_vdbg(hsotg->dev,
1798                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1799                          dev_addr, ep_num, ep_dir, ep_type, mps);
1800         urb->pipe_info.dev_addr = dev_addr;
1801         urb->pipe_info.ep_num = ep_num;
1802         urb->pipe_info.pipe_type = ep_type;
1803         urb->pipe_info.pipe_dir = ep_dir;
1804         urb->pipe_info.mps = mps;
1805 }
1806
1807 /*
1808  * NOTE: This function will be removed once the peripheral controller code
1809  * is integrated and the driver is stable
1810  */
1811 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1812 {
1813 #ifdef DEBUG
1814         struct dwc2_host_chan *chan;
1815         struct dwc2_hcd_urb *urb;
1816         struct dwc2_qtd *qtd;
1817         int num_channels;
1818         u32 np_tx_status;
1819         u32 p_tx_status;
1820         int i;
1821
1822         num_channels = hsotg->core_params->host_channels;
1823         dev_dbg(hsotg->dev, "\n");
1824         dev_dbg(hsotg->dev,
1825                 "************************************************************\n");
1826         dev_dbg(hsotg->dev, "HCD State:\n");
1827         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
1828
1829         for (i = 0; i < num_channels; i++) {
1830                 chan = hsotg->hc_ptr_array[i];
1831                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
1832                 dev_dbg(hsotg->dev,
1833                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1834                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
1835                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
1836                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
1837                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
1838                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
1839                         chan->data_pid_start);
1840                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
1841                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
1842                         chan->xfer_started);
1843                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
1844                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
1845                         (unsigned long)chan->xfer_dma);
1846                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
1847                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
1848                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
1849                         chan->halt_on_queue);
1850                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
1851                         chan->halt_pending);
1852                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
1853                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
1854                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
1855                         chan->complete_split);
1856                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
1857                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
1858                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
1859                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
1860                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
1861
1862                 if (chan->xfer_started) {
1863                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1864
1865                         hfnum = readl(hsotg->regs + HFNUM);
1866                         hcchar = readl(hsotg->regs + HCCHAR(i));
1867                         hctsiz = readl(hsotg->regs + HCTSIZ(i));
1868                         hcint = readl(hsotg->regs + HCINT(i));
1869                         hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1870                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
1871                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
1872                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
1873                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
1874                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
1875                 }
1876
1877                 if (!(chan->xfer_started && chan->qh))
1878                         continue;
1879
1880                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1881                         if (!qtd->in_process)
1882                                 break;
1883                         urb = qtd->urb;
1884                         dev_dbg(hsotg->dev, "    URB Info:\n");
1885                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
1886                                 qtd, urb);
1887                         if (urb) {
1888                                 dev_dbg(hsotg->dev,
1889                                         "      Dev: %d, EP: %d %s\n",
1890                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
1891                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
1892                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1893                                         "IN" : "OUT");
1894                                 dev_dbg(hsotg->dev,
1895                                         "      Max packet size: %d\n",
1896                                         dwc2_hcd_get_mps(&urb->pipe_info));
1897                                 dev_dbg(hsotg->dev,
1898                                         "      transfer_buffer: %p\n",
1899                                         urb->buf);
1900                                 dev_dbg(hsotg->dev,
1901                                         "      transfer_dma: %08lx\n",
1902                                         (unsigned long)urb->dma);
1903                                 dev_dbg(hsotg->dev,
1904                                         "      transfer_buffer_length: %d\n",
1905                                         urb->length);
1906                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
1907                                         urb->actual_length);
1908                         }
1909                 }
1910         }
1911
1912         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
1913                 hsotg->non_periodic_channels);
1914         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
1915                 hsotg->periodic_channels);
1916         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
1917         np_tx_status = readl(hsotg->regs + GNPTXSTS);
1918         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
1919                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1920         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
1921                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
1922         p_tx_status = readl(hsotg->regs + HPTXSTS);
1923         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
1924                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1925         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
1926                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
1927         dwc2_hcd_dump_frrem(hsotg);
1928         dwc2_dump_global_registers(hsotg);
1929         dwc2_dump_host_registers(hsotg);
1930         dev_dbg(hsotg->dev,
1931                 "************************************************************\n");
1932         dev_dbg(hsotg->dev, "\n");
1933 #endif
1934 }
1935
1936 /*
1937  * NOTE: This function will be removed once the peripheral controller code
1938  * is integrated and the driver is stable
1939  */
1940 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
1941 {
1942 #ifdef DWC2_DUMP_FRREM
1943         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
1944         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1945                 hsotg->frrem_samples, hsotg->frrem_accum,
1946                 hsotg->frrem_samples > 0 ?
1947                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
1948         dev_dbg(hsotg->dev, "\n");
1949         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
1950         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1951                 hsotg->hfnum_7_samples,
1952                 hsotg->hfnum_7_frrem_accum,
1953                 hsotg->hfnum_7_samples > 0 ?
1954                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
1955         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
1956         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1957                 hsotg->hfnum_0_samples,
1958                 hsotg->hfnum_0_frrem_accum,
1959                 hsotg->hfnum_0_samples > 0 ?
1960                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
1961         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
1962         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1963                 hsotg->hfnum_other_samples,
1964                 hsotg->hfnum_other_frrem_accum,
1965                 hsotg->hfnum_other_samples > 0 ?
1966                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
1967                 0);
1968         dev_dbg(hsotg->dev, "\n");
1969         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
1970         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1971                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
1972                 hsotg->hfnum_7_samples_a > 0 ?
1973                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
1974         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
1975         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1976                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
1977                 hsotg->hfnum_0_samples_a > 0 ?
1978                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
1979         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
1980         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1981                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
1982                 hsotg->hfnum_other_samples_a > 0 ?
1983                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
1984                 : 0);
1985         dev_dbg(hsotg->dev, "\n");
1986         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
1987         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1988                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
1989                 hsotg->hfnum_7_samples_b > 0 ?
1990                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
1991         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
1992         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1993                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
1994                 (hsotg->hfnum_0_samples_b > 0) ?
1995                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
1996         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
1997         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1998                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
1999                 (hsotg->hfnum_other_samples_b > 0) ?
2000                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2001                 : 0);
2002 #endif
2003 }
2004
2005 struct wrapper_priv_data {
2006         struct dwc2_hsotg *hsotg;
2007 };
2008
2009 /* Gets the dwc2_hsotg from a usb_hcd */
2010 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2011 {
2012         struct wrapper_priv_data *p;
2013
2014         p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2015         return p->hsotg;
2016 }
2017
2018 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2019
2020 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2021 {
2022         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2023
2024         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2025         _dwc2_hcd_start(hcd);
2026 }
2027
2028 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2029 {
2030         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2031
2032         hcd->self.is_b_host = 0;
2033 }
2034
2035 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2036                         int *hub_port)
2037 {
2038         struct urb *urb = context;
2039
2040         if (urb->dev->tt)
2041                 *hub_addr = urb->dev->tt->hub->devnum;
2042         else
2043                 *hub_addr = 0;
2044         *hub_port = urb->dev->ttport;
2045 }
2046
2047 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2048 {
2049         struct urb *urb = context;
2050
2051         return urb->dev->speed;
2052 }
2053
2054 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2055                                         struct urb *urb)
2056 {
2057         struct usb_bus *bus = hcd_to_bus(hcd);
2058
2059         if (urb->interval)
2060                 bus->bandwidth_allocated += bw / urb->interval;
2061         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2062                 bus->bandwidth_isoc_reqs++;
2063         else
2064                 bus->bandwidth_int_reqs++;
2065 }
2066
2067 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2068                                     struct urb *urb)
2069 {
2070         struct usb_bus *bus = hcd_to_bus(hcd);
2071
2072         if (urb->interval)
2073                 bus->bandwidth_allocated -= bw / urb->interval;
2074         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2075                 bus->bandwidth_isoc_reqs--;
2076         else
2077                 bus->bandwidth_int_reqs--;
2078 }
2079
2080 /*
2081  * Sets the final status of an URB and returns it to the upper layer. Any
2082  * required cleanup of the URB is performed.
2083  *
2084  * Must be called with interrupt disabled and spinlock held
2085  */
2086 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2087                         int status)
2088 {
2089         struct urb *urb;
2090         int i;
2091
2092         if (!qtd) {
2093                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2094                 return;
2095         }
2096
2097         if (!qtd->urb) {
2098                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2099                 return;
2100         }
2101
2102         urb = qtd->urb->priv;
2103         if (!urb) {
2104                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2105                 return;
2106         }
2107
2108         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2109
2110         if (dbg_urb(urb))
2111                 dev_vdbg(hsotg->dev,
2112                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2113                          __func__, urb, usb_pipedevice(urb->pipe),
2114                          usb_pipeendpoint(urb->pipe),
2115                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2116                          urb->actual_length);
2117
2118         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2119                 for (i = 0; i < urb->number_of_packets; i++)
2120                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2121                                  i, urb->iso_frame_desc[i].status);
2122         }
2123
2124         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2125                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2126                 for (i = 0; i < urb->number_of_packets; ++i) {
2127                         urb->iso_frame_desc[i].actual_length =
2128                                 dwc2_hcd_urb_get_iso_desc_actual_length(
2129                                                 qtd->urb, i);
2130                         urb->iso_frame_desc[i].status =
2131                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2132                 }
2133         }
2134
2135         urb->status = status;
2136         if (!status) {
2137                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2138                     urb->actual_length < urb->transfer_buffer_length)
2139                         urb->status = -EREMOTEIO;
2140         }
2141
2142         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2143             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2144                 struct usb_host_endpoint *ep = urb->ep;
2145
2146                 if (ep)
2147                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2148                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2149                                         urb);
2150         }
2151
2152         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2153         urb->hcpriv = NULL;
2154         kfree(qtd->urb);
2155         qtd->urb = NULL;
2156
2157         spin_unlock(&hsotg->lock);
2158         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2159         spin_lock(&hsotg->lock);
2160 }
2161
2162 /*
2163  * Work queue function for starting the HCD when A-Cable is connected
2164  */
2165 static void dwc2_hcd_start_func(struct work_struct *work)
2166 {
2167         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2168                                                 start_work.work);
2169
2170         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2171         dwc2_host_start(hsotg);
2172 }
2173
2174 /*
2175  * Reset work queue function
2176  */
2177 static void dwc2_hcd_reset_func(struct work_struct *work)
2178 {
2179         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2180                                                 reset_work.work);
2181         u32 hprt0;
2182
2183         dev_dbg(hsotg->dev, "USB RESET function called\n");
2184         hprt0 = dwc2_read_hprt0(hsotg);
2185         hprt0 &= ~HPRT0_RST;
2186         writel(hprt0, hsotg->regs + HPRT0);
2187         hsotg->flags.b.port_reset_change = 1;
2188 }
2189
2190 /*
2191  * =========================================================================
2192  *  Linux HC Driver Functions
2193  * =========================================================================
2194  */
2195
2196 /*
2197  * Initializes the DWC_otg controller and its root hub and prepares it for host
2198  * mode operation. Activates the root port. Returns 0 on success and a negative
2199  * error code on failure.
2200  */
2201 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2202 {
2203         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2204         struct usb_bus *bus = hcd_to_bus(hcd);
2205         unsigned long flags;
2206
2207         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2208
2209         spin_lock_irqsave(&hsotg->lock, flags);
2210
2211         hcd->state = HC_STATE_RUNNING;
2212
2213         if (dwc2_is_device_mode(hsotg)) {
2214                 spin_unlock_irqrestore(&hsotg->lock, flags);
2215                 return 0;       /* why 0 ?? */
2216         }
2217
2218         dwc2_hcd_reinit(hsotg);
2219
2220         /* Initialize and connect root hub if one is not already attached */
2221         if (bus->root_hub) {
2222                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2223                 /* Inform the HUB driver to resume */
2224                 usb_hcd_resume_root_hub(hcd);
2225         }
2226
2227         spin_unlock_irqrestore(&hsotg->lock, flags);
2228         return 0;
2229 }
2230
2231 /*
2232  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2233  * stopped.
2234  */
2235 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2236 {
2237         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2238         unsigned long flags;
2239
2240         spin_lock_irqsave(&hsotg->lock, flags);
2241         dwc2_hcd_stop(hsotg);
2242         spin_unlock_irqrestore(&hsotg->lock, flags);
2243
2244         usleep_range(1000, 3000);
2245 }
2246
2247 /* Returns the current frame number */
2248 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2249 {
2250         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2251
2252         return dwc2_hcd_get_frame_number(hsotg);
2253 }
2254
2255 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2256                                char *fn_name)
2257 {
2258 #ifdef VERBOSE_DEBUG
2259         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2260         char *pipetype;
2261         char *speed;
2262
2263         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2264         dev_vdbg(hsotg->dev, "  Device address: %d\n",
2265                  usb_pipedevice(urb->pipe));
2266         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
2267                  usb_pipeendpoint(urb->pipe),
2268                  usb_pipein(urb->pipe) ? "IN" : "OUT");
2269
2270         switch (usb_pipetype(urb->pipe)) {
2271         case PIPE_CONTROL:
2272                 pipetype = "CONTROL";
2273                 break;
2274         case PIPE_BULK:
2275                 pipetype = "BULK";
2276                 break;
2277         case PIPE_INTERRUPT:
2278                 pipetype = "INTERRUPT";
2279                 break;
2280         case PIPE_ISOCHRONOUS:
2281                 pipetype = "ISOCHRONOUS";
2282                 break;
2283         default:
2284                 pipetype = "UNKNOWN";
2285                 break;
2286         }
2287
2288         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
2289                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2290                  "IN" : "OUT");
2291
2292         switch (urb->dev->speed) {
2293         case USB_SPEED_HIGH:
2294                 speed = "HIGH";
2295                 break;
2296         case USB_SPEED_FULL:
2297                 speed = "FULL";
2298                 break;
2299         case USB_SPEED_LOW:
2300                 speed = "LOW";
2301                 break;
2302         default:
2303                 speed = "UNKNOWN";
2304                 break;
2305         }
2306
2307         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
2308         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
2309                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2310         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
2311                  urb->transfer_buffer_length);
2312         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
2313                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2314         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
2315                  urb->setup_packet, (unsigned long)urb->setup_dma);
2316         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
2317
2318         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2319                 int i;
2320
2321                 for (i = 0; i < urb->number_of_packets; i++) {
2322                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
2323                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
2324                                  urb->iso_frame_desc[i].offset,
2325                                  urb->iso_frame_desc[i].length);
2326                 }
2327         }
2328 #endif
2329 }
2330
2331 /*
2332  * Starts processing a USB transfer request specified by a USB Request Block
2333  * (URB). mem_flags indicates the type of memory allocation to use while
2334  * processing this URB.
2335  */
2336 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2337                                  gfp_t mem_flags)
2338 {
2339         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2340         struct usb_host_endpoint *ep = urb->ep;
2341         struct dwc2_hcd_urb *dwc2_urb;
2342         int i;
2343         int retval;
2344         int alloc_bandwidth = 0;
2345         u8 ep_type = 0;
2346         u32 tflags = 0;
2347         void *buf;
2348         unsigned long flags;
2349
2350         if (dbg_urb(urb)) {
2351                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2352                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2353         }
2354
2355         if (ep == NULL)
2356                 return -EINVAL;
2357
2358         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2359             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2360                 spin_lock_irqsave(&hsotg->lock, flags);
2361                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2362                         alloc_bandwidth = 1;
2363                 spin_unlock_irqrestore(&hsotg->lock, flags);
2364         }
2365
2366         switch (usb_pipetype(urb->pipe)) {
2367         case PIPE_CONTROL:
2368                 ep_type = USB_ENDPOINT_XFER_CONTROL;
2369                 break;
2370         case PIPE_ISOCHRONOUS:
2371                 ep_type = USB_ENDPOINT_XFER_ISOC;
2372                 break;
2373         case PIPE_BULK:
2374                 ep_type = USB_ENDPOINT_XFER_BULK;
2375                 break;
2376         case PIPE_INTERRUPT:
2377                 ep_type = USB_ENDPOINT_XFER_INT;
2378                 break;
2379         default:
2380                 dev_warn(hsotg->dev, "Wrong ep type\n");
2381         }
2382
2383         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2384                                       mem_flags);
2385         if (!dwc2_urb)
2386                 return -ENOMEM;
2387
2388         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2389                                   usb_pipeendpoint(urb->pipe), ep_type,
2390                                   usb_pipein(urb->pipe),
2391                                   usb_maxpacket(urb->dev, urb->pipe,
2392                                                 !(usb_pipein(urb->pipe))));
2393
2394         buf = urb->transfer_buffer;
2395
2396         if (hcd->self.uses_dma) {
2397                 if (!buf && (urb->transfer_dma & 3)) {
2398                         dev_err(hsotg->dev,
2399                                 "%s: unaligned transfer with no transfer_buffer",
2400                                 __func__);
2401                         retval = -EINVAL;
2402                         goto fail1;
2403                 }
2404         }
2405
2406         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2407                 tflags |= URB_GIVEBACK_ASAP;
2408         if (urb->transfer_flags & URB_ZERO_PACKET)
2409                 tflags |= URB_SEND_ZERO_PACKET;
2410
2411         dwc2_urb->priv = urb;
2412         dwc2_urb->buf = buf;
2413         dwc2_urb->dma = urb->transfer_dma;
2414         dwc2_urb->length = urb->transfer_buffer_length;
2415         dwc2_urb->setup_packet = urb->setup_packet;
2416         dwc2_urb->setup_dma = urb->setup_dma;
2417         dwc2_urb->flags = tflags;
2418         dwc2_urb->interval = urb->interval;
2419         dwc2_urb->status = -EINPROGRESS;
2420
2421         for (i = 0; i < urb->number_of_packets; ++i)
2422                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2423                                                  urb->iso_frame_desc[i].offset,
2424                                                  urb->iso_frame_desc[i].length);
2425
2426         urb->hcpriv = dwc2_urb;
2427
2428         spin_lock_irqsave(&hsotg->lock, flags);
2429         retval = usb_hcd_link_urb_to_ep(hcd, urb);
2430         spin_unlock_irqrestore(&hsotg->lock, flags);
2431         if (retval)
2432                 goto fail1;
2433
2434         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags);
2435         if (retval)
2436                 goto fail2;
2437
2438         if (alloc_bandwidth) {
2439                 spin_lock_irqsave(&hsotg->lock, flags);
2440                 dwc2_allocate_bus_bandwidth(hcd,
2441                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2442                                 urb);
2443                 spin_unlock_irqrestore(&hsotg->lock, flags);
2444         }
2445
2446         return 0;
2447
2448 fail2:
2449         spin_lock_irqsave(&hsotg->lock, flags);
2450         dwc2_urb->priv = NULL;
2451         usb_hcd_unlink_urb_from_ep(hcd, urb);
2452         spin_unlock_irqrestore(&hsotg->lock, flags);
2453 fail1:
2454         urb->hcpriv = NULL;
2455         kfree(dwc2_urb);
2456
2457         return retval;
2458 }
2459
2460 /*
2461  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2462  */
2463 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2464                                  int status)
2465 {
2466         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2467         int rc;
2468         unsigned long flags;
2469
2470         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2471         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2472
2473         spin_lock_irqsave(&hsotg->lock, flags);
2474
2475         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2476         if (rc)
2477                 goto out;
2478
2479         if (!urb->hcpriv) {
2480                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2481                 goto out;
2482         }
2483
2484         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2485
2486         usb_hcd_unlink_urb_from_ep(hcd, urb);
2487
2488         kfree(urb->hcpriv);
2489         urb->hcpriv = NULL;
2490
2491         /* Higher layer software sets URB status */
2492         spin_unlock(&hsotg->lock);
2493         usb_hcd_giveback_urb(hcd, urb, status);
2494         spin_lock(&hsotg->lock);
2495
2496         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2497         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
2498 out:
2499         spin_unlock_irqrestore(&hsotg->lock, flags);
2500
2501         return rc;
2502 }
2503
2504 /*
2505  * Frees resources in the DWC_otg controller related to a given endpoint. Also
2506  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2507  * must already be dequeued.
2508  */
2509 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2510                                        struct usb_host_endpoint *ep)
2511 {
2512         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2513
2514         dev_dbg(hsotg->dev,
2515                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2516                 ep->desc.bEndpointAddress, ep->hcpriv);
2517         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2518 }
2519
2520 /*
2521  * Resets endpoint specific parameter values, in current version used to reset
2522  * the data toggle (as a WA). This function can be called from usb_clear_halt
2523  * routine.
2524  */
2525 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2526                                      struct usb_host_endpoint *ep)
2527 {
2528         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2529         int is_control = usb_endpoint_xfer_control(&ep->desc);
2530         int is_out = usb_endpoint_dir_out(&ep->desc);
2531         int epnum = usb_endpoint_num(&ep->desc);
2532         struct usb_device *udev;
2533         unsigned long flags;
2534
2535         dev_dbg(hsotg->dev,
2536                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2537                 ep->desc.bEndpointAddress);
2538
2539         udev = to_usb_device(hsotg->dev);
2540
2541         spin_lock_irqsave(&hsotg->lock, flags);
2542
2543         usb_settoggle(udev, epnum, is_out, 0);
2544         if (is_control)
2545                 usb_settoggle(udev, epnum, !is_out, 0);
2546         dwc2_hcd_endpoint_reset(hsotg, ep);
2547
2548         spin_unlock_irqrestore(&hsotg->lock, flags);
2549 }
2550
2551 /*
2552  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2553  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2554  * interrupt.
2555  *
2556  * This function is called by the USB core when an interrupt occurs
2557  */
2558 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2559 {
2560         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2561
2562         return dwc2_handle_hcd_intr(hsotg);
2563 }
2564
2565 /*
2566  * Creates Status Change bitmap for the root hub and root port. The bitmap is
2567  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2568  * is the status change indicator for the single root port. Returns 1 if either
2569  * change indicator is 1, otherwise returns 0.
2570  */
2571 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2572 {
2573         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2574
2575         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2576         return buf[0] != 0;
2577 }
2578
2579 /* Handles hub class-specific requests */
2580 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2581                                  u16 windex, char *buf, u16 wlength)
2582 {
2583         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2584                                           wvalue, windex, buf, wlength);
2585         return retval;
2586 }
2587
2588 /* Handles hub TT buffer clear completions */
2589 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2590                                                struct usb_host_endpoint *ep)
2591 {
2592         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2593         struct dwc2_qh *qh;
2594         unsigned long flags;
2595
2596         qh = ep->hcpriv;
2597         if (!qh)
2598                 return;
2599
2600         spin_lock_irqsave(&hsotg->lock, flags);
2601         qh->tt_buffer_dirty = 0;
2602
2603         if (hsotg->flags.b.port_connect_status)
2604                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2605
2606         spin_unlock_irqrestore(&hsotg->lock, flags);
2607 }
2608
2609 static struct hc_driver dwc2_hc_driver = {
2610         .description = "dwc2_hsotg",
2611         .product_desc = "DWC OTG Controller",
2612         .hcd_priv_size = sizeof(struct wrapper_priv_data),
2613
2614         .irq = _dwc2_hcd_irq,
2615         .flags = HCD_MEMORY | HCD_USB2,
2616
2617         .start = _dwc2_hcd_start,
2618         .stop = _dwc2_hcd_stop,
2619         .urb_enqueue = _dwc2_hcd_urb_enqueue,
2620         .urb_dequeue = _dwc2_hcd_urb_dequeue,
2621         .endpoint_disable = _dwc2_hcd_endpoint_disable,
2622         .endpoint_reset = _dwc2_hcd_endpoint_reset,
2623         .get_frame_number = _dwc2_hcd_get_frame_number,
2624
2625         .hub_status_data = _dwc2_hcd_hub_status_data,
2626         .hub_control = _dwc2_hcd_hub_control,
2627         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2628 };
2629
2630 /*
2631  * Frees secondary storage associated with the dwc2_hsotg structure contained
2632  * in the struct usb_hcd field
2633  */
2634 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2635 {
2636         u32 ahbcfg;
2637         u32 dctl;
2638         int i;
2639
2640         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2641
2642         /* Free memory for QH/QTD lists */
2643         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2644         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2645         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2646         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2647         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2648         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2649
2650         /* Free memory for the host channels */
2651         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2652                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2653
2654                 if (chan != NULL) {
2655                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2656                                 i, chan);
2657                         hsotg->hc_ptr_array[i] = NULL;
2658                         kfree(chan);
2659                 }
2660         }
2661
2662         if (hsotg->core_params->dma_enable > 0) {
2663                 if (hsotg->status_buf) {
2664                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2665                                           hsotg->status_buf,
2666                                           hsotg->status_buf_dma);
2667                         hsotg->status_buf = NULL;
2668                 }
2669         } else {
2670                 kfree(hsotg->status_buf);
2671                 hsotg->status_buf = NULL;
2672         }
2673
2674         ahbcfg = readl(hsotg->regs + GAHBCFG);
2675
2676         /* Disable all interrupts */
2677         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2678         writel(ahbcfg, hsotg->regs + GAHBCFG);
2679         writel(0, hsotg->regs + GINTMSK);
2680
2681         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2682                 dctl = readl(hsotg->regs + DCTL);
2683                 dctl |= DCTL_SFTDISCON;
2684                 writel(dctl, hsotg->regs + DCTL);
2685         }
2686
2687         if (hsotg->wq_otg) {
2688                 if (!cancel_work_sync(&hsotg->wf_otg))
2689                         flush_workqueue(hsotg->wq_otg);
2690                 destroy_workqueue(hsotg->wq_otg);
2691         }
2692
2693         kfree(hsotg->core_params);
2694         hsotg->core_params = NULL;
2695         del_timer(&hsotg->wkp_timer);
2696 }
2697
2698 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2699 {
2700         /* Turn off all host-specific interrupts */
2701         dwc2_disable_host_interrupts(hsotg);
2702
2703         dwc2_hcd_free(hsotg);
2704 }
2705
2706 /*
2707  * Sets all parameters to the given value.
2708  *
2709  * Assumes that the dwc2_core_params struct contains only integers.
2710  */
2711 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
2712 {
2713         int *p = (int *)params;
2714         size_t size = sizeof(*params) / sizeof(*p);
2715         int i;
2716
2717         for (i = 0; i < size; i++)
2718                 p[i] = value;
2719 }
2720 EXPORT_SYMBOL_GPL(dwc2_set_all_params);
2721
2722 /*
2723  * Initializes the HCD. This function allocates memory for and initializes the
2724  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2725  * USB bus with the core and calls the hc_driver->start() function. It returns
2726  * a negative error on failure.
2727  */
2728 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
2729                   const struct dwc2_core_params *params)
2730 {
2731         struct usb_hcd *hcd;
2732         struct dwc2_host_chan *channel;
2733         u32 hcfg;
2734         int i, num_channels;
2735         int retval;
2736
2737         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2738
2739         /* Detect config values from hardware */
2740         retval = dwc2_get_hwparams(hsotg);
2741
2742         if (retval)
2743                 return retval;
2744
2745         retval = -ENOMEM;
2746
2747         hcfg = readl(hsotg->regs + HCFG);
2748         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2749
2750 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2751         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2752                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2753         if (!hsotg->frame_num_array)
2754                 goto error1;
2755         hsotg->last_frame_num_array = kzalloc(
2756                         sizeof(*hsotg->last_frame_num_array) *
2757                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2758         if (!hsotg->last_frame_num_array)
2759                 goto error1;
2760         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2761 #endif
2762
2763         hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL);
2764         if (!hsotg->core_params)
2765                 goto error1;
2766
2767         dwc2_set_all_params(hsotg->core_params, -1);
2768
2769         /* Validate parameter values */
2770         dwc2_set_parameters(hsotg, params);
2771
2772         /* Check if the bus driver or platform code has setup a dma_mask */
2773         if (hsotg->core_params->dma_enable > 0 &&
2774             hsotg->dev->dma_mask == NULL) {
2775                 dev_warn(hsotg->dev,
2776                          "dma_mask not set, disabling DMA\n");
2777                 hsotg->core_params->dma_enable = 0;
2778                 hsotg->core_params->dma_desc_enable = 0;
2779         }
2780
2781         /* Set device flags indicating whether the HCD supports DMA */
2782         if (hsotg->core_params->dma_enable > 0) {
2783                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2784                         dev_warn(hsotg->dev, "can't set DMA mask\n");
2785                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2786                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
2787         }
2788
2789         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2790         if (!hcd)
2791                 goto error1;
2792
2793         if (hsotg->core_params->dma_enable <= 0)
2794                 hcd->self.uses_dma = 0;
2795
2796         hcd->has_tt = 1;
2797
2798         spin_lock_init(&hsotg->lock);
2799         ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2800         hsotg->priv = hcd;
2801
2802         /*
2803          * Disable the global interrupt until all the interrupt handlers are
2804          * installed
2805          */
2806         dwc2_disable_global_interrupts(hsotg);
2807
2808         /* Initialize the DWC_otg core, and select the Phy type */
2809         retval = dwc2_core_init(hsotg, true, irq);
2810         if (retval)
2811                 goto error2;
2812
2813         /* Create new workqueue and init work */
2814         retval = -ENOMEM;
2815         hsotg->wq_otg = create_singlethread_workqueue("dwc2");
2816         if (!hsotg->wq_otg) {
2817                 dev_err(hsotg->dev, "Failed to create workqueue\n");
2818                 goto error2;
2819         }
2820         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2821
2822         setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2823                     (unsigned long)hsotg);
2824
2825         /* Initialize the non-periodic schedule */
2826         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2827         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2828
2829         /* Initialize the periodic schedule */
2830         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2831         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2832         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2833         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2834
2835         /*
2836          * Create a host channel descriptor for each host channel implemented
2837          * in the controller. Initialize the channel descriptor array.
2838          */
2839         INIT_LIST_HEAD(&hsotg->free_hc_list);
2840         num_channels = hsotg->core_params->host_channels;
2841         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2842
2843         for (i = 0; i < num_channels; i++) {
2844                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2845                 if (channel == NULL)
2846                         goto error3;
2847                 channel->hc_num = i;
2848                 hsotg->hc_ptr_array[i] = channel;
2849         }
2850
2851         /* Initialize hsotg start work */
2852         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2853
2854         /* Initialize port reset work */
2855         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2856
2857         /*
2858          * Allocate space for storing data on status transactions. Normally no
2859          * data is sent, but this space acts as a bit bucket. This must be
2860          * done after usb_add_hcd since that function allocates the DMA buffer
2861          * pool.
2862          */
2863         if (hsotg->core_params->dma_enable > 0)
2864                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2865                                         DWC2_HCD_STATUS_BUF_SIZE,
2866                                         &hsotg->status_buf_dma, GFP_KERNEL);
2867         else
2868                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2869                                           GFP_KERNEL);
2870
2871         if (!hsotg->status_buf)
2872                 goto error3;
2873
2874         hsotg->otg_port = 1;
2875         hsotg->frame_list = NULL;
2876         hsotg->frame_list_dma = 0;
2877         hsotg->periodic_qh_count = 0;
2878
2879         /* Initiate lx_state to L3 disconnected state */
2880         hsotg->lx_state = DWC2_L3;
2881
2882         hcd->self.otg_port = hsotg->otg_port;
2883
2884         /* Don't support SG list at this point */
2885         hcd->self.sg_tablesize = 0;
2886
2887         /*
2888          * Finish generic HCD initialization and start the HCD. This function
2889          * allocates the DMA buffer pool, registers the USB bus, requests the
2890          * IRQ line, and calls hcd_start method.
2891          */
2892         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
2893         if (retval < 0)
2894                 goto error3;
2895
2896         dwc2_hcd_dump_state(hsotg);
2897
2898         dwc2_enable_global_interrupts(hsotg);
2899
2900         return 0;
2901
2902 error3:
2903         dwc2_hcd_release(hsotg);
2904 error2:
2905         usb_put_hcd(hcd);
2906 error1:
2907         kfree(hsotg->core_params);
2908
2909 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2910         kfree(hsotg->last_frame_num_array);
2911         kfree(hsotg->frame_num_array);
2912 #endif
2913
2914         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
2915         return retval;
2916 }
2917 EXPORT_SYMBOL_GPL(dwc2_hcd_init);
2918
2919 /*
2920  * Removes the HCD.
2921  * Frees memory and resources associated with the HCD and deregisters the bus.
2922  */
2923 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
2924 {
2925         struct usb_hcd *hcd;
2926
2927         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
2928
2929         hcd = dwc2_hsotg_to_hcd(hsotg);
2930         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
2931
2932         if (!hcd) {
2933                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
2934                         __func__);
2935                 return;
2936         }
2937
2938         usb_remove_hcd(hcd);
2939         hsotg->priv = NULL;
2940         dwc2_hcd_release(hsotg);
2941         usb_put_hcd(hcd);
2942
2943 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2944         kfree(hsotg->last_frame_num_array);
2945         kfree(hsotg->frame_num_array);
2946 #endif
2947 }
2948 EXPORT_SYMBOL_GPL(dwc2_hcd_remove);