3 Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan,
4 Jason Lapenta, Scott Smedley
6 This file is part of the DT3155 Device Driver.
8 The DT3155 Device Driver is free software; you can redistribute it
9 and/or modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2 of the
11 License, or (at your option) any later version.
13 The DT3155 Device Driver is distributed in the hope that it will be
14 useful, but WITHOUT ANY WARRANTY; without even the implied warranty
15 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with the DT3155 Device Driver; if not, write to the Free
20 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 Date Programmer Description of changes made
27 -------------------------------------------------------------------
28 24-Jul-2002 SS GPL licence.
32 /* This code is a modified version of examples provided by Data Translations.*/
37 /* macros to access registers */
39 #define WriteMReg(Address, Data) * ((u_long *) (Address)) = Data
40 #define ReadMReg(Address, Data) Data = * ((u_long *) (Address))
42 /***************** 32 bit register globals **************/
44 /* offsets for 32-bit memory mapped registers */
46 #define EVEN_DMA_START 0x000
47 #define ODD_DMA_START 0x00C
48 #define EVEN_DMA_STRIDE 0x018
49 #define ODD_DMA_STRIDE 0x024
50 #define EVEN_PIXEL_FMT 0x030
51 #define ODD_PIXEL_FMT 0x034
52 #define FIFO_TRIGGER 0x038
53 #define XFER_MODE 0x03C
55 #define RETRY_WAIT_CNT 0x044
57 #define EVEN_FLD_MASK 0x04C
58 #define ODD_FLD_MASK 0x050
59 #define MASK_LENGTH 0x054
60 #define FIFO_FLAG_CNT 0x058
61 #define IIC_CLK_DUR 0x05C
62 #define IIC_CSR1 0x060
63 #define IIC_CSR2 0x064
64 #define EVEN_DMA_UPPR_LMT 0x08C
65 #define ODD_DMA_UPPR_LMT 0x090
67 #define CLK_DUR_VAL 0x01010101
71 /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/
73 /**********************************
76 typedef union fifo_trigger_tag {
87 /**********************************
90 typedef union xfer_mode_tag {
95 u_long FIELD_TOGGLE : 1;
102 /**********************************
105 typedef union csr1_tag {
109 u_long CAP_CONT_EVE : 1;
110 u_long CAP_CONT_ODD : 1;
111 u_long CAP_SNGL_EVE : 1;
112 u_long CAP_SNGL_ODD : 1;
113 u_long FLD_DN_EVE : 1;
114 u_long FLD_DN_ODD : 1;
117 u_long FLD_CRPT_EVE : 1;
118 u_long FLD_CRPT_ODD : 1;
119 u_long ADDR_ERR_EVE : 1;
120 u_long ADDR_ERR_ODD : 1;
127 /**********************************
130 typedef union retry_wait_cnt_tag {
134 u_long RTRY_WAIT_CNT : 8;
139 /**********************************
142 typedef union int_csr_tag {
146 u_long FLD_END_EVE : 1;
147 u_long FLD_END_ODD : 1;
148 u_long FLD_START : 1;
150 u_long FLD_END_EVE_EN : 1;
151 u_long FLD_END_ODD_EN : 1;
152 u_long FLD_START_EN : 1;
157 /**********************************
160 typedef union mask_length_tag {
164 u_long MASK_LEN_EVE : 5;
166 u_long MASK_LEN_ODD : 5;
171 /**********************************
174 typedef union fifo_flag_cnt_tag {
185 /**********************************
188 typedef union iic_clk_dur {
199 /**********************************
202 typedef union iic_csr1_tag {
211 u_long AUTO_ABORT : 1;
212 u_long DIRECT_ABORT : 1;
216 u_long AUTO_ADDR : 8;
221 /**********************************
224 typedef union iic_csr2_tag {
228 u_long DIR_WR_DATA : 8;
229 u_long DIR_SUB_ADDR : 8;
232 u_long NEW_CYCLE : 1;
237 /* use for both EVEN and ODD DMA UPPER LIMITS */
239 /**********************************
242 typedef union dma_upper_lmt_tag {
246 u_long DMA_UPPER_LMT_VAL : 24;
252 /***************************************
253 * Global declarations of local copies
254 * of boards' 32 bit registers
255 ***************************************/
256 extern u_long even_dma_start_r; /* bit 0 should always be 0 */
257 extern u_long odd_dma_start_r; /* .. */
258 extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */
259 extern u_long odd_dma_stride_r; /* .. */
260 extern u_long even_pixel_fmt_r;
261 extern u_long odd_pixel_fmt_r;
263 extern FIFO_TRIGGER_R fifo_trigger_r;
264 extern XFER_MODE_R xfer_mode_r;
265 extern CSR1_R csr1_r;
266 extern RETRY_WAIT_CNT_R retry_wait_cnt_r;
267 extern INT_CSR_R int_csr_r;
269 extern u_long even_fld_mask_r;
270 extern u_long odd_fld_mask_r;
272 extern MASK_LENGTH_R mask_length_r;
273 extern FIFO_FLAG_CNT_R fifo_flag_cnt_r;
274 extern IIC_CLK_DUR_R iic_clk_dur_r;
275 extern IIC_CSR1_R iic_csr1_r;
276 extern IIC_CSR2_R iic_csr2_r;
277 extern DMA_UPPER_LMT_R even_dma_upper_lmt_r;
278 extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r;
282 /***************** 8 bit I2C register globals ***********/
284 #define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/
285 #define EVEN_CSR 0x011
286 #define ODD_CSR 0x012
289 #define X_CLIP_START 0x020
290 #define Y_CLIP_START 0x022
291 #define X_CLIP_END 0x024
292 #define Y_CLIP_END 0x026
293 #define AD_ADDR 0x030
296 #define DIG_OUT 0x040
297 #define PM_LUT_ADDR 0x050
298 #define PM_LUT_DATA 0x051
301 /******** Assignments and Typedefs for 8 bit I2C Registers********************/
303 typedef union i2c_csr2_tag {
307 u_char CHROM_FIL : 1;
308 u_char SYNC_SNTL : 1;
310 u_char SYNC_PRESENT : 1;
313 u_char DISP_PASS : 1;
317 typedef union i2c_even_csr_tag {
323 u_char ERROR_EVE : 1;
328 typedef union i2c_odd_csr_tag {
334 u_char ERROR_ODD : 1;
339 typedef union i2c_config_tag {
344 u_char EXT_TRIG_EN : 1;
345 u_char EXT_TRIG_POL : 1;
348 u_char PM_LUT_SEL : 1;
349 u_char PM_LUT_PGM : 1;
354 typedef union i2c_ad_cmd_tag { /* bits can have 3 different meanings
355 depending on value of AD_ADDR */
360 u_char SYNC_LVL_SEL : 2;
361 u_char SYNC_CNL_SEL : 2;
362 u_char DIGITIZE_CNL_SEL1 : 2;
363 } bt252_command; /* Bt252 Command Register */
364 struct /* if AD_ADDR = 00h */
366 u_char IOUT_DATA : 8;
367 } bt252_iout0; /* Bt252 IOUT0 register */
368 struct /* if AD_ADDR = 01h */
370 u_char IOUT_DATA : 8;
371 } bt252_iout1; /* BT252 IOUT1 register */
372 } I2C_AD_CMD; /* if AD_ADDR = 02h */
375 /***** Global declarations of local copies of boards' 8 bit I2C registers ***/
377 extern I2C_CSR2 i2c_csr2;
378 extern I2C_EVEN_CSR i2c_even_csr;
379 extern I2C_ODD_CSR i2c_odd_csr;
380 extern I2C_CONFIG i2c_config;
381 extern u_char i2c_dt_id;
382 extern u_char i2c_x_clip_start;
383 extern u_char i2c_y_clip_start;
384 extern u_char i2c_x_clip_end;
385 extern u_char i2c_y_clip_end;
386 extern u_char i2c_ad_addr;
387 extern u_char i2c_ad_lut;
388 extern I2C_AD_CMD i2c_ad_cmd;
389 extern u_char i2c_dig_out;
390 extern u_char i2c_pm_lut_addr;
391 extern u_char i2c_pm_lut_data;
393 /* Functions for Global use */
395 /* access 8-bit IIC registers */
397 extern int ReadI2C (u_char * lpReg, u_short wIregIndex, u_char * byVal);
398 extern int WriteI2C (u_char * lpReg, u_short wIregIndex, u_char byVal);