1 /* Copyright (C) 2003-2005 SBE, Inc.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/slab.h>
18 #include <asm/byteorder.h>
19 #include <linux/netdevice.h>
20 #include <linux/delay.h>
21 #include <linux/hdlc.h>
22 #include "pmcc4_sysdep.h"
23 #include "sbecom_inline_linux.h"
27 #if defined(CONFIG_SBE_HDLC_V7) || defined(CONFIG_SBE_WAN256T3_HDLC_V7) || \
28 defined(CONFIG_SBE_HDLC_V7_MODULE) || defined(CONFIG_SBE_WAN256T3_HDLC_V7_MODULE)
35 #define V7(x) (x ## _v7)
36 extern int hdlc_netif_rx_v7 (hdlc_device *, struct sk_buff *);
37 extern int register_hdlc_device_v7 (hdlc_device *);
38 extern int unregister_hdlc_device_v7 (hdlc_device *);
45 #ifndef USE_MAX_INT_DELAY
50 extern int cxt1e1_log_level;
51 extern int drvr_state;
56 pci_read_32 (u_int32_t *p)
63 if (cxt1e1_log_level >= LOG_DEBUG)
64 pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
67 FLUSH_PCI_READ (); /* */
68 return le32_to_cpu (*p);
73 pci_write_32 (u_int32_t *p, u_int32_t v)
76 if (cxt1e1_log_level >= LOG_DEBUG)
77 pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
80 FLUSH_PCI_WRITE (); /* This routine is called from routines
81 * which do multiple register writes
82 * which themselves need flushing between
83 * writes in order to guarantee write
84 * ordering. It is less code-cumbersome
85 * to flush here-in then to investigate
86 * and code the many other register
87 * writing routines. */
93 pci_flush_write (ci_t *ci)
97 /* issue a PCI read to flush PCI write thru bridge */
98 v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */
101 * return nothing, this just reads PCI bridge interface to flush
102 * previously written data
108 watchdog_func (unsigned long arg)
110 struct watchdog *wd = (void *) arg;
112 if (drvr_state != SBE_DRVR_AVAILABLE)
114 if (cxt1e1_log_level >= LOG_MONITOR)
115 pr_warning("%s: drvr not available (%x)\n", __func__, drvr_state);
118 schedule_work (&wd->work);
119 mod_timer (&wd->h, jiffies + wd->ticks);
122 int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *), void *c, int usec)
126 wdp->ticks = (HZ) * (usec / 1000) / 1000;
127 INIT_WORK(&wdp->work, (void *)f);
128 init_timer (&wdp->h);
130 ci_t *ci = (ci_t *) c;
132 wdp->h.data = (unsigned long) &ci->wd;
134 wdp->h.function = watchdog_func;
139 OS_uwait (int usec, char *description)
145 mdelay (usec / 1000);
146 /* now delay residual */
147 tmp = (usec / 1000) * 1000; /* round */
148 tmp = usec - tmp; /* residual */
150 { /* wait on residual */
159 /* dummy short delay routine called as a subroutine so that compiler
160 * does not optimize/remove its intent (a short delay)
164 OS_uwait_dummy (void)
166 #ifndef USE_MAX_INT_DELAY
175 OS_sem_init (void *sem, int state)
180 sema_init((struct semaphore *) sem, 0);
183 sema_init((struct semaphore *) sem, 1);
185 default: /* otherwise, set sem.count to state's
187 sema_init (sem, state);
194 sd_line_is_ok (void *user)
196 struct net_device *ndev = (struct net_device *) user;
198 return netif_carrier_ok (ndev);
202 sd_line_is_up (void *user)
204 struct net_device *ndev = (struct net_device *) user;
206 netif_carrier_on (ndev);
211 sd_line_is_down (void *user)
213 struct net_device *ndev = (struct net_device *) user;
215 netif_carrier_off (ndev);
220 sd_disable_xmit (void *user)
222 struct net_device *dev = (struct net_device *) user;
224 netif_stop_queue (dev);
229 sd_enable_xmit (void *user)
231 struct net_device *dev = (struct net_device *) user;
233 netif_wake_queue (dev);
238 sd_queue_stopped (void *user)
240 struct net_device *ndev = (struct net_device *) user;
242 return netif_queue_stopped (ndev);
245 void sd_recv_consume(void *token, size_t len, void *user)
247 struct net_device *ndev = user;
248 struct sk_buff *skb = token;
252 skb->protocol = hdlc_type_trans(skb, ndev);
258 ** Read some reserved location w/in the COMET chip as a usable
259 ** VMETRO trigger point or other trace marking event.
264 extern ci_t *CI; /* dummy pointer to board ZERO's data */
266 VMETRO_TRACE (void *x)
268 u_int32_t y = (u_int32_t) x;
270 pci_write_32 ((u_int32_t *) &CI->cpldbase->leds, y);
275 VMETRO_TRIGGER (ci_t *ci, int x)
277 struct s_comet_reg *comet;
278 volatile u_int32_t data;
280 comet = ci->port[0].cometbase; /* default to COMET # 0 */
286 data = pci_read_32 ((u_int32_t *) &comet->__res24); /* 0x90 */
289 data = pci_read_32 ((u_int32_t *) &comet->__res25); /* 0x94 */
292 data = pci_read_32 ((u_int32_t *) &comet->__res26); /* 0x98 */
295 data = pci_read_32 ((u_int32_t *) &comet->__res27); /* 0x9C */
298 data = pci_read_32 ((u_int32_t *) &comet->__res88); /* 0x220 */
301 data = pci_read_32 ((u_int32_t *) &comet->__res89); /* 0x224 */
304 data = pci_read_32 ((u_int32_t *) &comet->__res8A); /* 0x228 */
307 data = pci_read_32 ((u_int32_t *) &comet->__res8B); /* 0x22C */
310 data = pci_read_32 ((u_int32_t *) &comet->__resA0); /* 0x280 */
313 data = pci_read_32 ((u_int32_t *) &comet->__resA1); /* 0x284 */
316 data = pci_read_32 ((u_int32_t *) &comet->__resA2); /* 0x288 */
319 data = pci_read_32 ((u_int32_t *) &comet->__resA3); /* 0x28C */
322 data = pci_read_32 ((u_int32_t *) &comet->__resA4); /* 0x290 */
325 data = pci_read_32 ((u_int32_t *) &comet->__resA5); /* 0x294 */
328 data = pci_read_32 ((u_int32_t *) &comet->__resA6); /* 0x298 */
331 data = pci_read_32 ((u_int32_t *) &comet->__resA7); /* 0x29C */
334 data = pci_read_32 ((u_int32_t *) &comet->__res74); /* 0x1D0 */
337 data = pci_read_32 ((u_int32_t *) &comet->__res75); /* 0x1D4 */
340 data = pci_read_32 ((u_int32_t *) &comet->__res76); /* 0x1D8 */
343 data = pci_read_32 ((u_int32_t *) &comet->__res77); /* 0x1DC */
349 /*** End-of-File ***/