Pileus Git - ~andy/linux/blob - drivers/staging/cx25821/cx25821-video-upstream.c

   1 /*
   2  *  Driver for the Conexant CX25821 PCIe bridge
   3  *
   4  *  Copyright (C) 2009 Conexant Systems Inc.
   5  *  Authors  <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  24
  25 #include "cx25821-video.h"
  26 #include "cx25821-video-upstream.h"
  27
  28 #include <linux/fs.h>
  29 #include <linux/errno.h>
  30 #include <linux/kernel.h>
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/syscalls.h>
  34 #include <linux/file.h>
  35 #include <linux/fcntl.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38
  39 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
  40 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
  41 MODULE_LICENSE("GPL");
  42
  43 static int _intr_msk =
  44         FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
  45
  46 int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
  47                                         struct sram_channel *ch,
  48                                         unsigned int bpl, u32 risc)
  49 {
  50         unsigned int i, lines;
  51         u32 cdt;
  52
  53         if (ch->cmds_start == 0) {
  54                 cx_write(ch->ptr1_reg, 0);
  55                 cx_write(ch->ptr2_reg, 0);
  56                 cx_write(ch->cnt2_reg, 0);
  57                 cx_write(ch->cnt1_reg, 0);
  58                 return 0;
  59         }
  60
  61         bpl = (bpl + 7) & ~7;   /* alignment */
  62         cdt = ch->cdt;
  63         lines = ch->fifo_size / bpl;
  64
  65         if (lines > 4)
  66                 lines = 4;
  67
  68         BUG_ON(lines < 2);
  69
  70         /* write CDT */
  71         for (i = 0; i < lines; i++) {
  72                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
  73                 cx_write(cdt + 16 * i + 4, 0);
  74                 cx_write(cdt + 16 * i + 8, 0);
  75                 cx_write(cdt + 16 * i + 12, 0);
  76         }
  77
  78         /* write CMDS */
  79         cx_write(ch->cmds_start + 0, risc);
  80
  81         cx_write(ch->cmds_start + 4, 0);
  82         cx_write(ch->cmds_start + 8, cdt);
  83         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
  84         cx_write(ch->cmds_start + 16, ch->ctrl_start);
  85
  86         cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
  87
  88         for (i = 24; i < 80; i += 4)
  89                 cx_write(ch->cmds_start + i, 0);
  90
  91         /* fill registers */
  92         cx_write(ch->ptr1_reg, ch->fifo_start);
  93         cx_write(ch->ptr2_reg, cdt);
  94         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
  95         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
  96
  97         return 0;
  98 }
  99
 100 static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
 101                                           __le32 *rp, unsigned int offset,
 102                                           unsigned int bpl, u32 sync_line,
 103                                           unsigned int lines, int fifo_enable,
 104                                           int field_type)
 105 {
 106         unsigned int line, i;
 107         int dist_betwn_starts = bpl * 2;
 108
 109         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 110
 111         if (USE_RISC_NOOP_VIDEO) {
 112                 for (i = 0; i < NUM_NO_OPS; i++)
 113                         *(rp++) = cpu_to_le32(RISC_NOOP);
 114         }
 115
 116         /* scan lines */
 117         for (line = 0; line < lines; line++) {
 118                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
 119                 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
 120                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
 121
 122                 if ((lines <= NTSC_FIELD_HEIGHT)
 123                     || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
 124                         offset += dist_betwn_starts;
 125                 }
 126         }
 127
 128         return rp;
 129 }
 130
 131 static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
 132                                            dma_addr_t databuf_phys_addr,
 133                                            unsigned int offset, u32 sync_line,
 134                                            unsigned int bpl, unsigned int lines,
 135                                            int fifo_enable, int field_type)
 136 {
 137         unsigned int line, i;
 138         struct sram_channel *sram_ch =
 139            dev->channels[dev->_channel_upstream_select].sram_channels;
 140         int dist_betwn_starts = bpl * 2;
 141
 142         /* sync instruction */
 143         if (sync_line != NO_SYNC_LINE)
 144                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 145
 146         if (USE_RISC_NOOP_VIDEO) {
 147                 for (i = 0; i < NUM_NO_OPS; i++)
 148                         *(rp++) = cpu_to_le32(RISC_NOOP);
 149         }
 150
 151         /* scan lines */
 152         for (line = 0; line < lines; line++) {
 153                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
 154                 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
 155                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
 156
 157                 if ((lines <= NTSC_FIELD_HEIGHT)
 158                     || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC))
 159                         /* to skip the other field line */
 160                         offset += dist_betwn_starts;
 161
 162                 /* check if we need to enable the FIFO after the first 4 lines
 163                  * For the upstream video channel, the risc engine will enable
 164                  * the FIFO. */
 165                 if (fifo_enable && line == 3) {
 166                         *(rp++) = RISC_WRITECR;
 167                         *(rp++) = sram_ch->dma_ctl;
 168                         *(rp++) = FLD_VID_FIFO_EN;
 169                         *(rp++) = 0x00000001;
 170                 }
 171         }
 172
 173         return rp;
 174 }
 175
 176 int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
 177                                  struct pci_dev *pci,
 178                                  unsigned int top_offset,
 179                                  unsigned int bpl, unsigned int lines)
 180 {
 181         __le32 *rp;
 182         int fifo_enable = 0;
 183         /* get line count for single field */
 184         int singlefield_lines = lines >> 1;
 185         int odd_num_lines = singlefield_lines;
 186         int frame = 0;
 187         int frame_size = 0;
 188         int databuf_offset = 0;
 189         int risc_program_size = 0;
 190         int risc_flag = RISC_CNT_RESET;
 191         unsigned int bottom_offset = bpl;
 192         dma_addr_t risc_phys_jump_addr;
 193
 194         if (dev->_isNTSC) {
 195                 odd_num_lines = singlefield_lines + 1;
 196                 risc_program_size = FRAME1_VID_PROG_SIZE;
 197                 frame_size =
 198                     (bpl ==
 199                      Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
 200                     FRAME_SIZE_NTSC_Y422;
 201         } else {
 202                 risc_program_size = PAL_VID_PROG_SIZE;
 203                 frame_size =
 204                     (bpl ==
 205                      Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 206         }
 207
 208         /* Virtual address of Risc buffer program */
 209         rp = dev->_dma_virt_addr;
 210
 211         for (frame = 0; frame < NUM_FRAMES; frame++) {
 212                 databuf_offset = frame_size * frame;
 213
 214                 if (UNSET != top_offset) {
 215                         fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
 216                         rp = cx25821_risc_field_upstream(dev, rp,
 217                                                          dev->
 218                                                          _data_buf_phys_addr +
 219                                                          databuf_offset,
 220                                                          top_offset, 0, bpl,
 221                                                          odd_num_lines,
 222                                                          fifo_enable,
 223                                                          ODD_FIELD);
 224                 }
 225
 226                 fifo_enable = FIFO_DISABLE;
 227
 228                 /* Even Field */
 229                 rp = cx25821_risc_field_upstream(dev, rp,
 230                                                  dev->_data_buf_phys_addr +
 231                                                  databuf_offset, bottom_offset,
 232                                                  0x200, bpl, singlefield_lines,
 233                                                  fifo_enable, EVEN_FIELD);
 234
 235                 if (frame == 0) {
 236                         risc_flag = RISC_CNT_RESET;
 237                         risc_phys_jump_addr =
 238                             dev->_dma_phys_start_addr + risc_program_size;
 239                 } else {
 240                         risc_phys_jump_addr = dev->_dma_phys_start_addr;
 241                         risc_flag = RISC_CNT_INC;
 242                 }
 243
 244                 /* Loop to 2ndFrameRISC or to Start of Risc
 245                  * program & generate IRQ
 246                  */
 247                 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
 248                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 249                 *(rp++) = cpu_to_le32(0);
 250         }
 251
 252         return 0;
 253 }
 254
 255 void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
 256 {
 257         struct sram_channel *sram_ch =
 258            dev->channels[VID_UPSTREAM_SRAM_CHANNEL_I].sram_channels;
 259         u32 tmp = 0;
 260
 261         if (!dev->_is_running) {
 262                 pr_info("No video file is currently running so return!\n");
 263                 return;
 264         }
 265         /* Disable RISC interrupts */
 266         tmp = cx_read(sram_ch->int_msk);
 267         cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
 268
 269         /* Turn OFF risc and fifo enable */
 270         tmp = cx_read(sram_ch->dma_ctl);
 271         cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
 272
 273         /* Clear data buffer memory */
 274         if (dev->_data_buf_virt_addr)
 275                 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
 276
 277         dev->_is_running = 0;
 278         dev->_is_first_frame = 0;
 279         dev->_frame_count = 0;
 280         dev->_file_status = END_OF_FILE;
 281
 282         if (dev->_irq_queues) {
 283                 kfree(dev->_irq_queues);
 284                 dev->_irq_queues = NULL;
 285         }
 286
 287         if (dev->_filename != NULL)
 288                 kfree(dev->_filename);
 289
 290         tmp = cx_read(VID_CH_MODE_SEL);
 291         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
 292 }
 293
 294 void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
 295 {
 296         if (dev->_is_running)
 297                 cx25821_stop_upstream_video_ch1(dev);
 298
 299         if (dev->_dma_virt_addr) {
 300                 pci_free_consistent(dev->pci, dev->_risc_size,
 301                                     dev->_dma_virt_addr, dev->_dma_phys_addr);
 302                 dev->_dma_virt_addr = NULL;
 303         }
 304
 305         if (dev->_data_buf_virt_addr) {
 306                 pci_free_consistent(dev->pci, dev->_data_buf_size,
 307                                     dev->_data_buf_virt_addr,
 308                                     dev->_data_buf_phys_addr);
 309                 dev->_data_buf_virt_addr = NULL;
 310         }
 311 }
 312
 313 int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
 314 {
 315         struct file *myfile;
 316         int frame_index_temp = dev->_frame_index;
 317         int i = 0;
 318         int line_size =
 319             (dev->_pixel_format ==
 320              PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
 321         int frame_size = 0;
 322         int frame_offset = 0;
 323         ssize_t vfs_read_retval = 0;
 324         char mybuf[line_size];
 325         loff_t file_offset;
 326         loff_t pos;
 327         mm_segment_t old_fs;
 328
 329         if (dev->_file_status == END_OF_FILE)
 330                 return 0;
 331
 332         if (dev->_isNTSC) {
 333                 frame_size =
 334                     (line_size ==
 335                      Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
 336                     FRAME_SIZE_NTSC_Y422;
 337         } else {
 338                 frame_size =
 339                     (line_size ==
 340                      Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 341         }
 342
 343         frame_offset = (frame_index_temp > 0) ? frame_size : 0;
 344         file_offset = dev->_frame_count * frame_size;
 345
 346         myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
 347
 348         if (IS_ERR(myfile)) {
 349                 const int open_errno = -PTR_ERR(myfile);
 350                 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
 351                        __func__, dev->_filename, open_errno);
 352                 return PTR_ERR(myfile);
 353         } else {
 354                 if (!(myfile->f_op)) {
 355                         pr_err("%s(): File has no file operations registered!\n",
 356                                __func__);
 357                         filp_close(myfile, NULL);
 358                         return -EIO;
 359                 }
 360
 361                 if (!myfile->f_op->read) {
 362                         pr_err("%s(): File has no READ operations registered!\n",
 363                                __func__);
 364                         filp_close(myfile, NULL);
 365                         return -EIO;
 366                 }
 367
 368                 pos = myfile->f_pos;
 369                 old_fs = get_fs();
 370                 set_fs(KERNEL_DS);
 371
 372                 for (i = 0; i < dev->_lines_count; i++) {
 373                         pos = file_offset;
 374
 375                         vfs_read_retval =
 376                             vfs_read(myfile, mybuf, line_size, &pos);
 377
 378                         if (vfs_read_retval > 0 && vfs_read_retval == line_size
 379                             && dev->_data_buf_virt_addr != NULL) {
 380                                 memcpy((void *)(dev->_data_buf_virt_addr +
 381                                                 frame_offset / 4), mybuf,
 382                                        vfs_read_retval);
 383                         }
 384
 385                         file_offset += vfs_read_retval;
 386                         frame_offset += vfs_read_retval;
 387
 388                         if (vfs_read_retval < line_size) {
 389                                 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
 390                                         __func__);
 391                                 break;
 392                         }
 393                 }
 394
 395                 if (i > 0)
 396                         dev->_frame_count++;
 397
 398                 dev->_file_status =
 399                     (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
 400
 401                 set_fs(old_fs);
 402                 filp_close(myfile, NULL);
 403         }
 404
 405         return 0;
 406 }
 407
 408 static void cx25821_vidups_handler(struct work_struct *work)
 409 {
 410         struct cx25821_dev *dev =
 411             container_of(work, struct cx25821_dev, _irq_work_entry);
 412
 413         if (!dev) {
 414                 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
 415                        __func__);
 416                 return;
 417         }
 418
 419         cx25821_get_frame(dev,
 420                          dev->channels[dev->_channel_upstream_select].
 421                                                sram_channels);
 422 }
 423
 424 int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
 425 {
 426         struct file *myfile;
 427         int i = 0, j = 0;
 428         int line_size =
 429             (dev->_pixel_format ==
 430              PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
 431         ssize_t vfs_read_retval = 0;
 432         char mybuf[line_size];
 433         loff_t pos;
 434         loff_t offset = (unsigned long)0;
 435         mm_segment_t old_fs;
 436
 437         myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
 438
 439         if (IS_ERR(myfile)) {
 440                 const int open_errno = -PTR_ERR(myfile);
 441                 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
 442                        __func__, dev->_filename, open_errno);
 443                 return PTR_ERR(myfile);
 444         } else {
 445                 if (!(myfile->f_op)) {
 446                         pr_err("%s(): File has no file operations registered!\n",
 447                                __func__);
 448                         filp_close(myfile, NULL);
 449                         return -EIO;
 450                 }
 451
 452                 if (!myfile->f_op->read) {
 453                         pr_err("%s(): File has no READ operations registered!  Returning\n",
 454                                __func__);
 455                         filp_close(myfile, NULL);
 456                         return -EIO;
 457                 }
 458
 459                 pos = myfile->f_pos;
 460                 old_fs = get_fs();
 461                 set_fs(KERNEL_DS);
 462
 463                 for (j = 0; j < NUM_FRAMES; j++) {
 464                         for (i = 0; i < dev->_lines_count; i++) {
 465                                 pos = offset;
 466
 467                                 vfs_read_retval =
 468                                     vfs_read(myfile, mybuf, line_size, &pos);
 469
 470                                 if (vfs_read_retval > 0
 471                                     && vfs_read_retval == line_size
 472                                     && dev->_data_buf_virt_addr != NULL) {
 473                                         memcpy((void *)(dev->
 474                                                         _data_buf_virt_addr +
 475                                                         offset / 4), mybuf,
 476                                                vfs_read_retval);
 477                                 }
 478
 479                                 offset += vfs_read_retval;
 480
 481                                 if (vfs_read_retval < line_size) {
 482                                         pr_info("Done: exit %s() since no more bytes to read from Video file\n",
 483                                                 __func__);
 484                                         break;
 485                                 }
 486                         }
 487
 488                         if (i > 0)
 489                                 dev->_frame_count++;
 490
 491                         if (vfs_read_retval < line_size)
 492                                 break;
 493                 }
 494
 495                 dev->_file_status =
 496                     (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
 497
 498                 set_fs(old_fs);
 499                 myfile->f_pos = 0;
 500                 filp_close(myfile, NULL);
 501         }
 502
 503         return 0;
 504 }
 505
 506 int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
 507                                     struct sram_channel *sram_ch, int bpl)
 508 {
 509         int ret = 0;
 510         dma_addr_t dma_addr;
 511         dma_addr_t data_dma_addr;
 512
 513         if (dev->_dma_virt_addr != NULL) {
 514                 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
 515                                     dev->_dma_virt_addr, dev->_dma_phys_addr);
 516         }
 517
 518         dev->_dma_virt_addr =
 519             pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
 520                                  &dma_addr);
 521         dev->_dma_virt_start_addr = dev->_dma_virt_addr;
 522         dev->_dma_phys_start_addr = dma_addr;
 523         dev->_dma_phys_addr = dma_addr;
 524         dev->_risc_size = dev->upstream_riscbuf_size;
 525
 526         if (!dev->_dma_virt_addr) {
 527                 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
 528                 return -ENOMEM;
 529         }
 530
 531         /* Clear memory at address */
 532         memset(dev->_dma_virt_addr, 0, dev->_risc_size);
 533
 534         if (dev->_data_buf_virt_addr != NULL) {
 535                 pci_free_consistent(dev->pci, dev->upstream_databuf_size,
 536                                     dev->_data_buf_virt_addr,
 537                                     dev->_data_buf_phys_addr);
 538         }
 539         /* For Video Data buffer allocation */
 540         dev->_data_buf_virt_addr =
 541             pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
 542                                  &data_dma_addr);
 543         dev->_data_buf_phys_addr = data_dma_addr;
 544         dev->_data_buf_size = dev->upstream_databuf_size;
 545
 546         if (!dev->_data_buf_virt_addr) {
 547                 pr_err("FAILED to allocate memory for data buffer! Returning\n");
 548                 return -ENOMEM;
 549         }
 550
 551         /* Clear memory at address */
 552         memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
 553
 554         ret = cx25821_openfile(dev, sram_ch);
 555         if (ret < 0)
 556                 return ret;
 557
 558         /* Create RISC programs */
 559         ret =
 560             cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
 561                                          dev->_lines_count);
 562         if (ret < 0) {
 563                 pr_info("Failed creating Video Upstream Risc programs!\n");
 564                 goto error;
 565         }
 566
 567         return 0;
 568
 569 error:
 570         return ret;
 571 }
 572
 573 int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
 574                                u32 status)
 575 {
 576         u32 int_msk_tmp;
 577         struct sram_channel *channel = dev->channels[chan_num].sram_channels;
 578         int singlefield_lines = NTSC_FIELD_HEIGHT;
 579         int line_size_in_bytes = Y422_LINE_SZ;
 580         int odd_risc_prog_size = 0;
 581         dma_addr_t risc_phys_jump_addr;
 582         __le32 *rp;
 583
 584         if (status & FLD_VID_SRC_RISC1) {
 585                 /* We should only process one program per call */
 586                 u32 prog_cnt = cx_read(channel->gpcnt);
 587
 588                 /* Since we've identified our IRQ, clear our bits from the
 589                  * interrupt mask and interrupt status registers */
 590                 int_msk_tmp = cx_read(channel->int_msk);
 591                 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
 592                 cx_write(channel->int_stat, _intr_msk);
 593
 594                 spin_lock(&dev->slock);
 595
 596                 dev->_frame_index = prog_cnt;
 597
 598                 queue_work(dev->_irq_queues, &dev->_irq_work_entry);
 599
 600                 if (dev->_is_first_frame) {
 601                         dev->_is_first_frame = 0;
 602
 603                         if (dev->_isNTSC) {
 604                                 singlefield_lines += 1;
 605                                 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
 606                         } else {
 607                                 singlefield_lines = PAL_FIELD_HEIGHT;
 608                                 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
 609                         }
 610
 611                         if (dev->_dma_virt_start_addr != NULL) {
 612                                 line_size_in_bytes =
 613                                     (dev->_pixel_format ==
 614                                      PIXEL_FRMT_411) ? Y411_LINE_SZ :
 615                                     Y422_LINE_SZ;
 616                                 risc_phys_jump_addr =
 617                                     dev->_dma_phys_start_addr +
 618                                     odd_risc_prog_size;
 619
 620                                 rp = cx25821_update_riscprogram(dev,
 621                                                                 dev->
 622                                                                 _dma_virt_start_addr,
 623                                                                 TOP_OFFSET,
 624                                                                 line_size_in_bytes,
 625                                                                 0x0,
 626                                                                 singlefield_lines,
 627                                                                 FIFO_DISABLE,
 628                                                                 ODD_FIELD);
 629
 630                                 /* Jump to Even Risc program of 1st Frame */
 631                                 *(rp++) = cpu_to_le32(RISC_JUMP);
 632                                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 633                                 *(rp++) = cpu_to_le32(0);
 634                         }
 635                 }
 636
 637                 spin_unlock(&dev->slock);
 638         } else {
 639                 if (status & FLD_VID_SRC_UF)
 640                         pr_err("%s(): Video Received Underflow Error Interrupt!\n",
 641                                __func__);
 642
 643                 if (status & FLD_VID_SRC_SYNC)
 644                         pr_err("%s(): Video Received Sync Error Interrupt!\n",
 645                                __func__);
 646
 647                 if (status & FLD_VID_SRC_OPC_ERR)
 648                         pr_err("%s(): Video Received OpCode Error Interrupt!\n",
 649                                __func__);
 650         }
 651
 652         if (dev->_file_status == END_OF_FILE) {
 653                 pr_err("EOF Channel 1 Framecount = %d\n", dev->_frame_count);
 654                 return -1;
 655         }
 656         /* ElSE, set the interrupt mask register, re-enable irq. */
 657         int_msk_tmp = cx_read(channel->int_msk);
 658         cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
 659
 660         return 0;
 661 }
 662
 663 static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
 664 {
 665         struct cx25821_dev *dev = dev_id;
 666         u32 msk_stat, vid_status;
 667         int handled = 0;
 668         int channel_num = 0;
 669         struct sram_channel *sram_ch;
 670
 671         if (!dev)
 672                 return -1;
 673
 674         channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
 675
 676         sram_ch = dev->channels[channel_num].sram_channels;
 677
 678         msk_stat = cx_read(sram_ch->int_mstat);
 679         vid_status = cx_read(sram_ch->int_stat);
 680
 681         /* Only deal with our interrupt */
 682         if (vid_status) {
 683                 handled =
 684                     cx25821_video_upstream_irq(dev, channel_num, vid_status);
 685         }
 686
 687         if (handled < 0)
 688                 cx25821_stop_upstream_video_ch1(dev);
 689         else
 690                 handled += handled;
 691
 692         return IRQ_RETVAL(handled);
 693 }
 694
 695 void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
 696                              int pix_format)
 697 {
 698         int width = WIDTH_D1;
 699         int height = dev->_lines_count;
 700         int num_lines, odd_num_lines;
 701         u32 value;
 702         int vip_mode = OUTPUT_FRMT_656;
 703
 704         value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
 705         value &= 0xFFFFFFEF;
 706         value |= dev->_isNTSC ? 0 : 0x10;
 707         cx_write(ch->vid_fmt_ctl, value);
 708
 709         /* set number of active pixels in each line.
 710          * Default is 720 pixels in both NTSC and PAL format */
 711         cx_write(ch->vid_active_ctl1, width);
 712
 713         num_lines = (height / 2) & 0x3FF;
 714         odd_num_lines = num_lines;
 715
 716         if (dev->_isNTSC)
 717                 odd_num_lines += 1;
 718
 719         value = (num_lines << 16) | odd_num_lines;
 720
 721         /* set number of active lines in field 0 (top) and field 1 (bottom) */
 722         cx_write(ch->vid_active_ctl2, value);
 723
 724         cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
 725 }
 726
 727 int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
 728                                      struct sram_channel *sram_ch)
 729 {
 730         u32 tmp = 0;
 731         int err = 0;
 732
 733         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
 734          * channel A-C
 735          */
 736         tmp = cx_read(VID_CH_MODE_SEL);
 737         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 738
 739         /* Set the physical start address of the RISC program in the initial
 740          * program counter(IPC) member of the cmds.
 741          */
 742         cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
 743         /* Risc IPC High 64 bits 63-32 */
 744         cx_write(sram_ch->cmds_start + 4, 0);
 745
 746         /* reset counter */
 747         cx_write(sram_ch->gpcnt_ctl, 3);
 748
 749         /* Clear our bits from the interrupt status register. */
 750         cx_write(sram_ch->int_stat, _intr_msk);
 751
 752         /* Set the interrupt mask register, enable irq. */
 753         cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
 754         tmp = cx_read(sram_ch->int_msk);
 755         cx_write(sram_ch->int_msk, tmp |= _intr_msk);
 756
 757         err =
 758             request_irq(dev->pci->irq, cx25821_upstream_irq,
 759                         IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
 760         if (err < 0) {
 761                 pr_err("%s: can't get upstream IRQ %d\n",
 762                        dev->name, dev->pci->irq);
 763                 goto fail_irq;
 764         }
 765
 766         /* Start the DMA  engine */
 767         tmp = cx_read(sram_ch->dma_ctl);
 768         cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
 769
 770         dev->_is_running = 1;
 771         dev->_is_first_frame = 1;
 772
 773         return 0;
 774
 775 fail_irq:
 776         cx25821_dev_unregister(dev);
 777         return err;
 778 }
 779
 780 int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
 781                                  int pixel_format)
 782 {
 783         struct sram_channel *sram_ch;
 784         u32 tmp;
 785         int retval = 0;
 786         int err = 0;
 787         int data_frame_size = 0;
 788         int risc_buffer_size = 0;
 789         int str_length = 0;
 790
 791         if (dev->_is_running) {
 792                 pr_info("Video Channel is still running so return!\n");
 793                 return 0;
 794         }
 795
 796         dev->_channel_upstream_select = channel_select;
 797         sram_ch = dev->channels[channel_select].sram_channels;
 798
 799         INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
 800         dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
 801
 802         if (!dev->_irq_queues) {
 803                 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
 804                 return -ENOMEM;
 805         }
 806         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
 807          * channel A-C
 808          */
 809         tmp = cx_read(VID_CH_MODE_SEL);
 810         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 811
 812         dev->_is_running = 0;
 813         dev->_frame_count = 0;
 814         dev->_file_status = RESET_STATUS;
 815         dev->_lines_count = dev->_isNTSC ? 480 : 576;
 816         dev->_pixel_format = pixel_format;
 817         dev->_line_size =
 818             (dev->_pixel_format ==
 819              PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
 820         data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
 821         risc_buffer_size =
 822             dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
 823
 824         if (dev->input_filename) {
 825                 str_length = strlen(dev->input_filename);
 826                 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
 827
 828                 if (!dev->_filename)
 829                         goto error;
 830
 831                 memcpy(dev->_filename, dev->input_filename, str_length + 1);
 832         } else {
 833                 str_length = strlen(dev->_defaultname);
 834                 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
 835
 836                 if (!dev->_filename)
 837                         goto error;
 838
 839                 memcpy(dev->_filename, dev->_defaultname, str_length + 1);
 840         }
 841
 842         /* Default if filename is empty string */
 843         if (strcmp(dev->input_filename, "") == 0) {
 844                 if (dev->_isNTSC) {
 845                         dev->_filename =
 846                             (dev->_pixel_format ==
 847                              PIXEL_FRMT_411) ? "/root/vid411.yuv" :
 848                             "/root/vidtest.yuv";
 849                 } else {
 850                         dev->_filename =
 851                             (dev->_pixel_format ==
 852                              PIXEL_FRMT_411) ? "/root/pal411.yuv" :
 853                             "/root/pal422.yuv";
 854                 }
 855         }
 856
 857         dev->_is_running = 0;
 858         dev->_frame_count = 0;
 859         dev->_file_status = RESET_STATUS;
 860         dev->_lines_count = dev->_isNTSC ? 480 : 576;
 861         dev->_pixel_format = pixel_format;
 862         dev->_line_size =
 863             (dev->_pixel_format ==
 864              PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
 865
 866         retval =
 867             cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
 868                                                 0);
 869
 870         /* setup fifo + format */
 871         cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
 872
 873         dev->upstream_riscbuf_size = risc_buffer_size * 2;
 874         dev->upstream_databuf_size = data_frame_size * 2;
 875
 876         /* Allocating buffers and prepare RISC program */
 877         retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
 878         if (retval < 0) {
 879                 pr_err("%s: Failed to set up Video upstream buffers!\n",
 880                        dev->name);
 881                 goto error;
 882         }
 883
 884         cx25821_start_video_dma_upstream(dev, sram_ch);
 885
 886         return 0;
 887
 888 error:
 889         cx25821_dev_unregister(dev);
 890
 891         return err;
 892 }