Pileus Git - ~andy/linux/blob - drivers/staging/comedi/drivers/ni_tio_internal.h

   1 /*
   2     drivers/ni_tio_internal.h
   3     Header file for NI general purpose counter support code (ni_tio.c and
   4     ni_tiocmd.c)
   5
   6     COMEDI - Linux Control and Measurement Device Interface
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18
  19 #ifndef _COMEDI_NI_TIO_INTERNAL_H
  20 #define _COMEDI_NI_TIO_INTERNAL_H
  21
  22 #include "ni_tio.h"
  23
  24 #define NITIO_AUTO_INC_REG(x)           (NITIO_G0_AUTO_INC + (x))
  25 #define NITIO_CMD_REG(x)                (NITIO_G0_CMD + (x))
  26 #define NITIO_SW_SAVE_REG(x)            (NITIO_G0_SW_SAVE + (x))
  27 #define NITIO_MODE_REG(x)               (NITIO_G0_MODE + (x))
  28 #define NITIO_LOADA_REG(x)              (NITIO_G0_LOADA + (x))
  29 #define NITIO_LOADB_REG(x)              (NITIO_G0_LOADB + (x))
  30 #define NITIO_INPUT_SEL_REG(x)          (NITIO_G0_INPUT_SEL + (x))
  31 #define NITIO_CNT_MODE_REG(x)           (NITIO_G0_CNT_MODE + (x))
  32 #define NITIO_GATE2_REG(x)              (NITIO_G0_GATE2 + (x))
  33 #define NITIO_STATUS_REG(x)             (NITIO_G01_STATUS + ((x) / 2))
  34 #define NITIO_RESET_REG(x)              (NITIO_G01_RESET + ((x) / 2))
  35
  36 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned idx)
  37 {
  38         switch (idx) {
  39         case 0:
  40         case 1:
  41                 return NITIO_G01_STATUS1;
  42         case 2:
  43         case 3:
  44                 return NITIO_G23_STATUS1;
  45         }
  46         return 0;
  47 }
  48
  49 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned idx)
  50 {
  51         switch (idx) {
  52         case 0:
  53         case 1:
  54                 return NITIO_G01_STATUS2;
  55         case 2:
  56         case 3:
  57                 return NITIO_G23_STATUS2;
  58         }
  59         return 0;
  60 }
  61
  62 static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(unsigned idx)
  63 {
  64         switch (idx) {
  65         case 0:
  66                 return NITIO_G0_DMA_CFG;
  67         case 1:
  68                 return NITIO_G1_DMA_CFG;
  69         case 2:
  70                 return NITIO_G2_DMA_CFG;
  71         case 3:
  72                 return NITIO_G3_DMA_CFG;
  73         }
  74         return 0;
  75 }
  76
  77 static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(unsigned idx)
  78 {
  79         switch (idx) {
  80         case 0:
  81                 return NITIO_G0_DMA_STATUS;
  82         case 1:
  83                 return NITIO_G1_DMA_STATUS;
  84         case 2:
  85                 return NITIO_G2_DMA_STATUS;
  86         case 3:
  87                 return NITIO_G3_DMA_STATUS;
  88         }
  89         return 0;
  90 }
  91
  92 static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(unsigned idx)
  93 {
  94         switch (idx) {
  95         case 0:
  96                 return NITIO_G0_ABZ;
  97         case 1:
  98                 return NITIO_G1_ABZ;
  99         }
 100         return 0;
 101 }
 102
 103 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(unsigned idx)
 104 {
 105         switch (idx) {
 106         case 0:
 107                 return NITIO_G0_INT_ACK;
 108         case 1:
 109                 return NITIO_G1_INT_ACK;
 110         case 2:
 111                 return NITIO_G2_INT_ACK;
 112         case 3:
 113                 return NITIO_G3_INT_ACK;
 114         }
 115         return 0;
 116 }
 117
 118 static inline enum ni_gpct_register NITIO_Gi_Status_Reg(unsigned idx)
 119 {
 120         switch (idx) {
 121         case 0:
 122                 return NITIO_G0_STATUS;
 123         case 1:
 124                 return NITIO_G1_STATUS;
 125         case 2:
 126                 return NITIO_G2_STATUS;
 127         case 3:
 128                 return NITIO_G3_STATUS;
 129         }
 130         return 0;
 131 }
 132
 133 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(unsigned idx)
 134 {
 135         switch (idx) {
 136         case 0:
 137                 return NITIO_G0_INT_ENA;
 138         case 1:
 139                 return NITIO_G1_INT_ENA;
 140         case 2:
 141                 return NITIO_G2_INT_ENA;
 142         case 3:
 143                 return NITIO_G3_INT_ENA;
 144         }
 145         return 0;
 146 }
 147
 148 enum Gi_Auto_Increment_Reg_Bits {
 149         Gi_Auto_Increment_Mask = 0xff
 150 };
 151
 152 #define Gi_Up_Down_Shift 5
 153 enum Gi_Command_Reg_Bits {
 154         Gi_Arm_Bit = 0x1,
 155         Gi_Save_Trace_Bit = 0x2,
 156         Gi_Load_Bit = 0x4,
 157         Gi_Disarm_Bit = 0x10,
 158         Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
 159         Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
 160         Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
 161         Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
 162         Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
 163         Gi_Write_Switch_Bit = 0x80,
 164         Gi_Synchronize_Gate_Bit = 0x100,
 165         Gi_Little_Big_Endian_Bit = 0x200,
 166         Gi_Bank_Switch_Start_Bit = 0x400,
 167         Gi_Bank_Switch_Mode_Bit = 0x800,
 168         Gi_Bank_Switch_Enable_Bit = 0x1000,
 169         Gi_Arm_Copy_Bit = 0x2000,
 170         Gi_Save_Trace_Copy_Bit = 0x4000,
 171         Gi_Disarm_Copy_Bit = 0x8000
 172 };
 173
 174 #define Gi_Index_Phase_Bitshift 5
 175 #define Gi_HW_Arm_Select_Shift 8
 176 enum Gi_Counting_Mode_Reg_Bits {
 177         Gi_Counting_Mode_Mask = 0x7,
 178         Gi_Counting_Mode_Normal_Bits = 0x0,
 179         Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
 180         Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
 181         Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
 182         Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
 183         Gi_Counting_Mode_Sync_Source_Bits = 0x6,
 184         Gi_Index_Mode_Bit = 0x10,
 185         Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
 186         Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
 187         Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
 188         Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
 189         Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
 190         /* from m-series example code, not documented in 660x register level
 191          * manual */
 192         Gi_HW_Arm_Enable_Bit = 0x80,
 193         /* from m-series example code, not documented in 660x register level
 194          * manual */
 195         Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
 196         Gi_660x_Prescale_X8_Bit = 0x1000,
 197         Gi_M_Series_Prescale_X8_Bit = 0x2000,
 198         Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
 199         /* must be set for clocks over 40MHz, which includes synchronous
 200          * counting and quadrature modes */
 201         Gi_660x_Alternate_Sync_Bit = 0x2000,
 202         Gi_M_Series_Alternate_Sync_Bit = 0x4000,
 203         /* from m-series example code, not documented in 660x register level
 204          * manual */
 205         Gi_660x_Prescale_X2_Bit = 0x4000,
 206         Gi_M_Series_Prescale_X2_Bit = 0x8000,
 207 };
 208
 209 #define Gi_Source_Select_Shift 2
 210 #define Gi_Gate_Select_Shift 7
 211 enum Gi_Input_Select_Bits {
 212         Gi_Read_Acknowledges_Irq = 0x1, /*  not present on 660x */
 213         Gi_Write_Acknowledges_Irq = 0x2,        /*  not present on 660x */
 214         Gi_Source_Select_Mask = 0x7c,
 215         Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
 216         Gi_Gate_Select_Load_Source_Bit = 0x1000,
 217         Gi_Or_Gate_Bit = 0x2000,
 218         Gi_Output_Polarity_Bit = 0x4000,        /* set to invert */
 219         Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
 220 };
 221
 222 enum Gi_Mode_Bits {
 223         Gi_Gating_Mode_Mask = 0x3,
 224         Gi_Gating_Disabled_Bits = 0x0,
 225         Gi_Level_Gating_Bits = 0x1,
 226         Gi_Rising_Edge_Gating_Bits = 0x2,
 227         Gi_Falling_Edge_Gating_Bits = 0x3,
 228         Gi_Gate_On_Both_Edges_Bit = 0x4,        /* used in conjunction with
 229                                                  * rising edge gating mode */
 230         Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
 231         Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
 232         Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
 233         Gi_Edge_Gate_Starts_Bits = 0x10,
 234         Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
 235         Gi_Stop_Mode_Mask = 0x60,
 236         Gi_Stop_on_Gate_Bits = 0x00,
 237         Gi_Stop_on_Gate_or_TC_Bits = 0x20,
 238         Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
 239         Gi_Load_Source_Select_Bit = 0x80,
 240         Gi_Output_Mode_Mask = 0x300,
 241         Gi_Output_TC_Pulse_Bits = 0x100,
 242         Gi_Output_TC_Toggle_Bits = 0x200,
 243         Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
 244         Gi_Counting_Once_Mask = 0xc00,
 245         Gi_No_Hardware_Disarm_Bits = 0x000,
 246         Gi_Disarm_at_TC_Bits = 0x400,
 247         Gi_Disarm_at_Gate_Bits = 0x800,
 248         Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
 249         Gi_Loading_On_TC_Bit = 0x1000,
 250         Gi_Gate_Polarity_Bit = 0x2000,
 251         Gi_Loading_On_Gate_Bit = 0x4000,
 252         Gi_Reload_Source_Switching_Bit = 0x8000
 253 };
 254
 255 #define Gi_Second_Gate_Select_Shift 7
 256 /*FIXME: m-series has a second gate subselect bit */
 257 /*FIXME: m-series second gate sources are undocumented (by NI)*/
 258 enum Gi_Second_Gate_Bits {
 259         Gi_Second_Gate_Mode_Bit = 0x1,
 260         Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
 261         Gi_Second_Gate_Polarity_Bit = 0x2000,
 262         Gi_Second_Gate_Subselect_Bit = 0x4000,  /* m-series only */
 263         Gi_Source_Subselect_Bit = 0x8000        /* m-series only */
 264 };
 265 static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
 266 {
 267         return (second_gate_select << Gi_Second_Gate_Select_Shift) &
 268             Gi_Second_Gate_Select_Mask;
 269 }
 270
 271 enum Gxx_Status_Bits {
 272         G0_Save_Bit = 0x1,
 273         G1_Save_Bit = 0x2,
 274         G0_Counting_Bit = 0x4,
 275         G1_Counting_Bit = 0x8,
 276         G0_Next_Load_Source_Bit = 0x10,
 277         G1_Next_Load_Source_Bit = 0x20,
 278         G0_Stale_Data_Bit = 0x40,
 279         G1_Stale_Data_Bit = 0x80,
 280         G0_Armed_Bit = 0x100,
 281         G1_Armed_Bit = 0x200,
 282         G0_No_Load_Between_Gates_Bit = 0x400,
 283         G1_No_Load_Between_Gates_Bit = 0x800,
 284         G0_TC_Error_Bit = 0x1000,
 285         G1_TC_Error_Bit = 0x2000,
 286         G0_Gate_Error_Bit = 0x4000,
 287         G1_Gate_Error_Bit = 0x8000
 288 };
 289 static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
 290 {
 291         if (counter_index % 2)
 292                 return G1_Counting_Bit;
 293         return G0_Counting_Bit;
 294 }
 295
 296 static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
 297 {
 298         if (counter_index % 2)
 299                 return G1_Armed_Bit;
 300         return G0_Armed_Bit;
 301 }
 302
 303 static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
 304                                                            counter_index)
 305 {
 306         if (counter_index % 2)
 307                 return G1_Next_Load_Source_Bit;
 308         return G0_Next_Load_Source_Bit;
 309 }
 310
 311 static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
 312 {
 313         if (counter_index % 2)
 314                 return G1_Stale_Data_Bit;
 315         return G0_Stale_Data_Bit;
 316 }
 317
 318 static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
 319 {
 320         if (counter_index % 2)
 321                 return G1_TC_Error_Bit;
 322         return G0_TC_Error_Bit;
 323 }
 324
 325 static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
 326 {
 327         if (counter_index % 2)
 328                 return G1_Gate_Error_Bit;
 329         return G0_Gate_Error_Bit;
 330 }
 331
 332 /* joint reset register bits */
 333 static inline unsigned Gi_Reset_Bit(unsigned counter_index)
 334 {
 335         return 0x1 << (2 + (counter_index % 2));
 336 }
 337
 338 enum Gxx_Joint_Status2_Bits {
 339         G0_Output_Bit = 0x1,
 340         G1_Output_Bit = 0x2,
 341         G0_HW_Save_Bit = 0x1000,
 342         G1_HW_Save_Bit = 0x2000,
 343         G0_Permanent_Stale_Bit = 0x4000,
 344         G1_Permanent_Stale_Bit = 0x8000
 345 };
 346 static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
 347                                                                  counter_index)
 348 {
 349         if (counter_index % 2)
 350                 return G1_Permanent_Stale_Bit;
 351         return G0_Permanent_Stale_Bit;
 352 }
 353
 354 enum Gi_DMA_Config_Reg_Bits {
 355         Gi_DMA_Enable_Bit = 0x1,
 356         Gi_DMA_Write_Bit = 0x2,
 357         Gi_DMA_Int_Bit = 0x4
 358 };
 359
 360 enum Gi_DMA_Status_Reg_Bits {
 361         Gi_DMA_Readbank_Bit = 0x2000,
 362         Gi_DRQ_Error_Bit = 0x4000,
 363         Gi_DRQ_Status_Bit = 0x8000
 364 };
 365
 366 enum G02_Interrupt_Acknowledge_Bits {
 367         G0_Gate_Error_Confirm_Bit = 0x20,
 368         G0_TC_Error_Confirm_Bit = 0x40
 369 };
 370 enum G13_Interrupt_Acknowledge_Bits {
 371         G1_Gate_Error_Confirm_Bit = 0x2,
 372         G1_TC_Error_Confirm_Bit = 0x4
 373 };
 374 static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
 375 {
 376         if (counter_index % 2)
 377                 return G1_Gate_Error_Confirm_Bit;
 378         return G0_Gate_Error_Confirm_Bit;
 379 }
 380
 381 static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
 382 {
 383         if (counter_index % 2)
 384                 return G1_TC_Error_Confirm_Bit;
 385         return G0_TC_Error_Confirm_Bit;
 386 }
 387
 388 /* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
 389 enum Gxx_Interrupt_Acknowledge_Bits {
 390         Gi_TC_Interrupt_Ack_Bit = 0x4000,
 391         Gi_Gate_Interrupt_Ack_Bit = 0x8000
 392 };
 393
 394 enum Gi_Status_Bits {
 395         Gi_Gate_Interrupt_Bit = 0x4,
 396         Gi_TC_Bit = 0x8,
 397         Gi_Interrupt_Bit = 0x8000
 398 };
 399
 400 enum G02_Interrupt_Enable_Bits {
 401         G0_TC_Interrupt_Enable_Bit = 0x40,
 402         G0_Gate_Interrupt_Enable_Bit = 0x100
 403 };
 404 enum G13_Interrupt_Enable_Bits {
 405         G1_TC_Interrupt_Enable_Bit = 0x200,
 406         G1_Gate_Interrupt_Enable_Bit = 0x400
 407 };
 408 static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
 409 {
 410         unsigned bit;
 411
 412         if (counter_index % 2)
 413                 bit = G1_Gate_Interrupt_Enable_Bit;
 414         else
 415                 bit = G0_Gate_Interrupt_Enable_Bit;
 416         return bit;
 417 }
 418
 419 static inline void write_register(struct ni_gpct *counter, unsigned bits,
 420                                   enum ni_gpct_register reg)
 421 {
 422         BUG_ON(reg >= NITIO_NUM_REGS);
 423         counter->counter_dev->write_register(counter, bits, reg);
 424 }
 425
 426 static inline unsigned read_register(struct ni_gpct *counter,
 427                                      enum ni_gpct_register reg)
 428 {
 429         BUG_ON(reg >= NITIO_NUM_REGS);
 430         return counter->counter_dev->read_register(counter, reg);
 431 }
 432
 433 static inline int ni_tio_counting_mode_registers_present(const struct
 434                                                          ni_gpct_device
 435                                                          *counter_dev)
 436 {
 437         switch (counter_dev->variant) {
 438         case ni_gpct_variant_e_series:
 439                 return 0;
 440                 break;
 441         case ni_gpct_variant_m_series:
 442         case ni_gpct_variant_660x:
 443                 return 1;
 444                 break;
 445         default:
 446                 BUG();
 447                 break;
 448         }
 449         return 0;
 450 }
 451
 452 static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
 453                                              enum ni_gpct_register
 454                                              register_index, unsigned bit_mask,
 455                                              unsigned bit_values,
 456                                              unsigned transient_bit_values)
 457 {
 458         struct ni_gpct_device *counter_dev = counter->counter_dev;
 459         unsigned long flags;
 460
 461         BUG_ON(register_index >= NITIO_NUM_REGS);
 462         spin_lock_irqsave(&counter_dev->regs_lock, flags);
 463         counter_dev->regs[register_index] &= ~bit_mask;
 464         counter_dev->regs[register_index] |= (bit_values & bit_mask);
 465         write_register(counter,
 466                        counter_dev->regs[register_index] | transient_bit_values,
 467                        register_index);
 468         mmiowb();
 469         spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 470 }
 471
 472 /* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
 473  * twiddled in interrupt context, or whose software copy may be read in
 474  * interrupt context.
 475  */
 476 static inline void ni_tio_set_bits(struct ni_gpct *counter,
 477                                    enum ni_gpct_register register_index,
 478                                    unsigned bit_mask, unsigned bit_values)
 479 {
 480         ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
 481                                   0x0);
 482 }
 483
 484 /* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
 485 whose bits might be modified in interrupt context, or whose software copy
 486 might need to be read in interrupt context.
 487 */
 488 static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
 489                                             enum ni_gpct_register
 490                                             register_index)
 491 {
 492         struct ni_gpct_device *counter_dev = counter->counter_dev;
 493         unsigned long flags;
 494         unsigned value;
 495
 496         BUG_ON(register_index >= NITIO_NUM_REGS);
 497         spin_lock_irqsave(&counter_dev->regs_lock, flags);
 498         value = counter_dev->regs[register_index];
 499         spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 500         return value;
 501 }
 502
 503 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
 504 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
 505                         unsigned int gate_source);
 506
 507 #endif /* _COMEDI_NI_TIO_INTERNAL_H */