Pileus Git - ~andy/linux/blob - drivers/staging/comedi/drivers/ni_pcidio.c

   1 /*
   2     comedi/drivers/ni_pcidio.c
   3     driver for National Instruments PCI-DIO-32HS
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23 /*
  24 Driver: ni_pcidio
  25 Description: National Instruments PCI-DIO32HS, PCI-6533
  26 Author: ds
  27 Status: works
  28 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
  29          [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
  30          [National Instruments] PCI-6534 (pci-6534)
  31 Updated: Mon, 09 Jan 2012 14:27:23 +0000
  32
  33 The DIO32HS board appears as one subdevice, with 32 channels.
  34 Each channel is individually I/O configurable.  The channel order
  35 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0.  The driver only
  36 supports simple digital I/O; no handshaking is supported.
  37
  38 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  39
  40 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  41 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  42 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  43 trailing edge.
  44
  45 This driver could be easily modified to support AT-MIO32HS and
  46 AT-MIO96.
  47
  48 The PCI-6534 requires a firmware upload after power-up to work, the
  49 firmware data and instructions for loading it with comedi_config
  50 it are contained in the
  51 comedi_nonfree_firmware tarball available from http://www.comedi.org
  52 */
  53
  54 #define USE_DMA
  55 /* #define DEBUG 1 */
  56 /* #define DEBUG_FLAGS */
  57
  58 #include <linux/delay.h>
  59 #include <linux/interrupt.h>
  60 #include <linux/sched.h>
  61 #include <linux/firmware.h>
  62
  63 #include "../comedidev.h"
  64
  65 #include "comedi_fc.h"
  66 #include "mite.h"
  67
  68 #undef DPRINTK
  69 #ifdef DEBUG
  70 #define DPRINTK(format, args...) pr_debug(format, ## args)
  71 #else
  72 #define DPRINTK(format, args...) do { } while (0)
  73 #endif
  74
  75 #define PCI_DIO_SIZE 4096
  76 #define PCI_MITE_SIZE 4096
  77
  78 /* defines for the PCI-DIO-32HS */
  79
  80 #define Window_Address                  4       /* W */
  81 #define Interrupt_And_Window_Status     4       /* R */
  82 #define IntStatus1                              (1<<0)
  83 #define IntStatus2                              (1<<1)
  84 #define WindowAddressStatus_mask                0x7c
  85
  86 #define Master_DMA_And_Interrupt_Control 5      /* W */
  87 #define InterruptLine(x)                        ((x)&3)
  88 #define OpenInt                         (1<<2)
  89 #define Group_Status                    5       /* R */
  90 #define DataLeft                                (1<<0)
  91 #define Req                                     (1<<2)
  92 #define StopTrig                                (1<<3)
  93
  94 #define Group_1_Flags                   6       /* R */
  95 #define Group_2_Flags                   7       /* R */
  96 #define TransferReady                           (1<<0)
  97 #define CountExpired                            (1<<1)
  98 #define Waited                          (1<<5)
  99 #define PrimaryTC                               (1<<6)
 100 #define SecondaryTC                             (1<<7)
 101   /* #define SerialRose */
 102   /* #define ReqRose */
 103   /* #define Paused */
 104
 105 #define Group_1_First_Clear             6       /* W */
 106 #define Group_2_First_Clear             7       /* W */
 107 #define ClearWaited                             (1<<3)
 108 #define ClearPrimaryTC                  (1<<4)
 109 #define ClearSecondaryTC                        (1<<5)
 110 #define DMAReset                                (1<<6)
 111 #define FIFOReset                               (1<<7)
 112 #define ClearAll                                0xf8
 113
 114 #define Group_1_FIFO                    8       /* W */
 115 #define Group_2_FIFO                    12      /* W */
 116
 117 #define Transfer_Count                  20
 118 #define Chip_ID_D                       24
 119 #define Chip_ID_I                       25
 120 #define Chip_ID_O                       26
 121 #define Chip_Version                    27
 122 #define Port_IO(x)                      (28+(x))
 123 #define Port_Pin_Directions(x)          (32+(x))
 124 #define Port_Pin_Mask(x)                (36+(x))
 125 #define Port_Pin_Polarities(x)          (40+(x))
 126
 127 #define Master_Clock_Routing            45
 128 #define RTSIClocking(x)                 (((x)&3)<<4)
 129
 130 #define Group_1_Second_Clear            46      /* W */
 131 #define Group_2_Second_Clear            47      /* W */
 132 #define ClearExpired                            (1<<0)
 133
 134 #define Port_Pattern(x)                 (48+(x))
 135
 136 #define Data_Path                       64
 137 #define FIFOEnableA             (1<<0)
 138 #define FIFOEnableB             (1<<1)
 139 #define FIFOEnableC             (1<<2)
 140 #define FIFOEnableD             (1<<3)
 141 #define Funneling(x)            (((x)&3)<<4)
 142 #define GroupDirection  (1<<7)
 143
 144 #define Protocol_Register_1             65
 145 #define OpMode                          Protocol_Register_1
 146 #define RunMode(x)              ((x)&7)
 147 #define Numbered                (1<<3)
 148
 149 #define Protocol_Register_2             66
 150 #define ClockReg                        Protocol_Register_2
 151 #define ClockLine(x)            (((x)&3)<<5)
 152 #define InvertStopTrig  (1<<7)
 153 #define DataLatching(x)       (((x)&3)<<5)
 154
 155 #define Protocol_Register_3             67
 156 #define Sequence                        Protocol_Register_3
 157
 158 #define Protocol_Register_14            68      /* 16 bit */
 159 #define ClockSpeed                      Protocol_Register_14
 160
 161 #define Protocol_Register_4             70
 162 #define ReqReg                          Protocol_Register_4
 163 #define ReqConditioning(x)      (((x)&7)<<3)
 164
 165 #define Protocol_Register_5             71
 166 #define BlockMode                       Protocol_Register_5
 167
 168 #define FIFO_Control                    72
 169 #define ReadyLevel(x)           ((x)&7)
 170
 171 #define Protocol_Register_6             73
 172 #define LinePolarities                  Protocol_Register_6
 173 #define InvertAck               (1<<0)
 174 #define InvertReq               (1<<1)
 175 #define InvertClock             (1<<2)
 176 #define InvertSerial            (1<<3)
 177 #define OpenAck         (1<<4)
 178 #define OpenClock               (1<<5)
 179
 180 #define Protocol_Register_7             74
 181 #define AckSer                          Protocol_Register_7
 182 #define AckLine(x)              (((x)&3)<<2)
 183 #define ExchangePins            (1<<7)
 184
 185 #define Interrupt_Control               75
 186   /* bits same as flags */
 187
 188 #define DMA_Line_Control_Group1         76
 189 #define DMA_Line_Control_Group2         108
 190 /* channel zero is none */
 191 static inline unsigned primary_DMAChannel_bits(unsigned channel)
 192 {
 193         return channel & 0x3;
 194 }
 195
 196 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
 197 {
 198         return (channel << 2) & 0xc;
 199 }
 200
 201 #define Transfer_Size_Control           77
 202 #define TransferWidth(x)        ((x)&3)
 203 #define TransferLength(x)       (((x)&3)<<3)
 204 #define RequireRLevel           (1<<5)
 205
 206 #define Protocol_Register_15            79
 207 #define DAQOptions                      Protocol_Register_15
 208 #define StartSource(x)                  ((x)&0x3)
 209 #define InvertStart                             (1<<2)
 210 #define StopSource(x)                           (((x)&0x3)<<3)
 211 #define ReqStart                                (1<<6)
 212 #define PreStart                                (1<<7)
 213
 214 #define Pattern_Detection               81
 215 #define DetectionMethod                 (1<<0)
 216 #define InvertMatch                             (1<<1)
 217 #define IE_Pattern_Detection                    (1<<2)
 218
 219 #define Protocol_Register_9             82
 220 #define ReqDelay                        Protocol_Register_9
 221
 222 #define Protocol_Register_10            83
 223 #define ReqNotDelay                     Protocol_Register_10
 224
 225 #define Protocol_Register_11            84
 226 #define AckDelay                        Protocol_Register_11
 227
 228 #define Protocol_Register_12            85
 229 #define AckNotDelay                     Protocol_Register_12
 230
 231 #define Protocol_Register_13            86
 232 #define Data1Delay                      Protocol_Register_13
 233
 234 #define Protocol_Register_8             88      /* 32 bit */
 235 #define StartDelay                      Protocol_Register_8
 236
 237 /* Firmware files for PCI-6524 */
 238 #define FW_PCI_6534_MAIN                "ni6534a.bin"
 239 #define FW_PCI_6534_SCARAB_DI           "niscrb01.bin"
 240 #define FW_PCI_6534_SCARAB_DO           "niscrb02.bin"
 241 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
 242 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
 243 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
 244
 245 enum pci_6534_firmware_registers {      /* 16 bit */
 246         Firmware_Control_Register = 0x100,
 247         Firmware_Status_Register = 0x104,
 248         Firmware_Data_Register = 0x108,
 249         Firmware_Mask_Register = 0x10c,
 250         Firmware_Debug_Register = 0x110,
 251 };
 252 /* main fpga registers (32 bit)*/
 253 enum pci_6534_fpga_registers {
 254         FPGA_Control1_Register = 0x200,
 255         FPGA_Control2_Register = 0x204,
 256         FPGA_Irq_Mask_Register = 0x208,
 257         FPGA_Status_Register = 0x20c,
 258         FPGA_Signature_Register = 0x210,
 259         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 260         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 261         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 262         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 263         FPGA_Temp_Control_Register = 0x2a0,
 264         FPGA_DAR_Register = 0x2a8,
 265         FPGA_ELC_Read_Register = 0x2b8,
 266         FPGA_ELC_Write_Register = 0x2bc,
 267 };
 268 enum FPGA_Control_Bits {
 269         FPGA_Enable_Bit = 0x8000,
 270 };
 271
 272 #define TIMER_BASE 50           /* nanoseconds */
 273
 274 #ifdef USE_DMA
 275 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
 276 #else
 277 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
 278 #endif
 279
 280 static int ni_pcidio_cancel(struct comedi_device *dev,
 281                             struct comedi_subdevice *s);
 282
 283 struct nidio_board {
 284         int dev_id;
 285         const char *name;
 286         unsigned int uses_firmware:1;
 287 };
 288
 289 static const struct nidio_board nidio_boards[] = {
 290         {
 291                 .dev_id         = 0x1150,
 292                 .name           = "pci-dio-32hs",
 293         }, {
 294                 .dev_id         = 0x1320,
 295                 .name           = "pxi-6533",
 296         }, {
 297                 .dev_id         = 0x12b0,
 298                 .name           = "pci-6534",
 299                 .uses_firmware  = 1,
 300         },
 301 };
 302
 303 #define n_nidio_boards ARRAY_SIZE(nidio_boards)
 304 #define this_board ((const struct nidio_board *)dev->board_ptr)
 305
 306 struct nidio96_private {
 307         struct mite_struct *mite;
 308         int boardtype;
 309         int dio;
 310         unsigned short OpModeBits;
 311         struct mite_channel *di_mite_chan;
 312         struct mite_dma_descriptor_ring *di_mite_ring;
 313         spinlock_t mite_channel_lock;
 314 };
 315
 316 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 317                              struct comedi_subdevice *s,
 318                              struct comedi_cmd *cmd);
 319 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 320 static int ni_pcidio_inttrig(struct comedi_device *dev,
 321                              struct comedi_subdevice *s, unsigned int trignum);
 322 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode);
 323 static int setup_mite_dma(struct comedi_device *dev,
 324                           struct comedi_subdevice *s);
 325
 326 #ifdef DEBUG_FLAGS
 327 static void ni_pcidio_print_flags(unsigned int flags);
 328 static void ni_pcidio_print_status(unsigned int status);
 329 #else
 330 #define ni_pcidio_print_flags(x)
 331 #define ni_pcidio_print_status(x)
 332 #endif
 333
 334 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 335 {
 336         struct nidio96_private *devpriv = dev->private;
 337         unsigned long flags;
 338
 339         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 340         BUG_ON(devpriv->di_mite_chan);
 341         devpriv->di_mite_chan =
 342             mite_request_channel_in_range(devpriv->mite,
 343                                           devpriv->di_mite_ring, 1, 2);
 344         if (devpriv->di_mite_chan == NULL) {
 345                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 346                 comedi_error(dev, "failed to reserve mite dma channel.");
 347                 return -EBUSY;
 348         }
 349         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 350         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 351                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 352                devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 353         mmiowb();
 354         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 355         return 0;
 356 }
 357
 358 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 359 {
 360         struct nidio96_private *devpriv = dev->private;
 361         unsigned long flags;
 362
 363         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 364         if (devpriv->di_mite_chan) {
 365                 mite_dma_disarm(devpriv->di_mite_chan);
 366                 mite_dma_reset(devpriv->di_mite_chan);
 367                 mite_release_channel(devpriv->di_mite_chan);
 368                 devpriv->di_mite_chan = NULL;
 369                 writeb(primary_DMAChannel_bits(0) |
 370                        secondary_DMAChannel_bits(0),
 371                        devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 372                 mmiowb();
 373         }
 374         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 375 }
 376
 377 static void ni_pcidio_event(struct comedi_device *dev,
 378                             struct comedi_subdevice *s)
 379 {
 380         if (s->
 381             async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
 382                              COMEDI_CB_OVERFLOW)) {
 383                 ni_pcidio_cancel(dev, s);
 384         }
 385         comedi_event(dev, s);
 386 }
 387
 388 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 389 {
 390         struct nidio96_private *devpriv = dev->private;
 391         unsigned long irq_flags;
 392         int count;
 393
 394         spin_lock_irqsave(&dev->spinlock, irq_flags);
 395         spin_lock(&devpriv->mite_channel_lock);
 396         if (devpriv->di_mite_chan)
 397                 mite_sync_input_dma(devpriv->di_mite_chan, s->async);
 398         spin_unlock(&devpriv->mite_channel_lock);
 399         count = s->async->buf_write_count - s->async->buf_read_count;
 400         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 401         return count;
 402 }
 403
 404 static irqreturn_t nidio_interrupt(int irq, void *d)
 405 {
 406         struct comedi_device *dev = d;
 407         struct nidio96_private *devpriv = dev->private;
 408         struct comedi_subdevice *s = &dev->subdevices[0];
 409         struct comedi_async *async = s->async;
 410         struct mite_struct *mite = devpriv->mite;
 411
 412         /* int i, j; */
 413         long int AuxData = 0;
 414         short data1 = 0;
 415         short data2 = 0;
 416         int flags;
 417         int status;
 418         int work = 0;
 419         unsigned int m_status = 0;
 420
 421         /* interrupcions parasites */
 422         if (dev->attached == 0) {
 423                 /* assume it's from another card */
 424                 return IRQ_NONE;
 425         }
 426
 427         /* Lock to avoid race with comedi_poll */
 428         spin_lock(&dev->spinlock);
 429
 430         status = readb(devpriv->mite->daq_io_addr +
 431                        Interrupt_And_Window_Status);
 432         flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 433
 434         DPRINTK("ni_pcidio_interrupt: status=0x%02x,flags=0x%02x\n",
 435                 status, flags);
 436         ni_pcidio_print_flags(flags);
 437         ni_pcidio_print_status(status);
 438
 439         spin_lock(&devpriv->mite_channel_lock);
 440         if (devpriv->di_mite_chan)
 441                 m_status = mite_get_status(devpriv->di_mite_chan);
 442 #ifdef MITE_DEBUG
 443         mite_print_chsr(m_status);
 444 #endif
 445
 446         /* mite_dump_regs(mite); */
 447         if (m_status & CHSR_INT) {
 448                 if (m_status & CHSR_LINKC) {
 449                         writel(CHOR_CLRLC,
 450                                mite->mite_io_addr +
 451                                MITE_CHOR(devpriv->di_mite_chan->channel));
 452                         mite_sync_input_dma(devpriv->di_mite_chan, s->async);
 453                         /* XXX need to byteswap */
 454                 }
 455                 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
 456                                  CHSR_DRQ1 | CHSR_MRDY)) {
 457                         DPRINTK("unknown mite interrupt, disabling IRQ\n");
 458                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 459                         disable_irq(dev->irq);
 460                 }
 461         }
 462         spin_unlock(&devpriv->mite_channel_lock);
 463
 464         while (status & DataLeft) {
 465                 work++;
 466                 if (work > 20) {
 467                         DPRINTK("too much work in interrupt\n");
 468                         writeb(0x00,
 469                                devpriv->mite->daq_io_addr +
 470                                Master_DMA_And_Interrupt_Control);
 471                         break;
 472                 }
 473
 474                 flags &= IntEn;
 475
 476                 if (flags & TransferReady) {
 477                         /* DPRINTK("TransferReady\n"); */
 478                         while (flags & TransferReady) {
 479                                 work++;
 480                                 if (work > 100) {
 481                                         DPRINTK("too much work in interrupt\n");
 482                                         writeb(0x00,
 483                                                devpriv->mite->daq_io_addr +
 484                                                Master_DMA_And_Interrupt_Control
 485                                               );
 486                                         goto out;
 487                                 }
 488                                 AuxData =
 489                                     readl(devpriv->mite->daq_io_addr +
 490                                           Group_1_FIFO);
 491                                 data1 = AuxData & 0xffff;
 492                                 data2 = (AuxData & 0xffff0000) >> 16;
 493                                 comedi_buf_put(async, data1);
 494                                 comedi_buf_put(async, data2);
 495                                 /* DPRINTK("read:%d, %d\n",data1,data2); */
 496                                 flags = readb(devpriv->mite->daq_io_addr +
 497                                               Group_1_Flags);
 498                         }
 499                         /* DPRINTK("buf_int_count: %d\n",
 500                                 async->buf_int_count); */
 501                         /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",
 502                                 IntEn,flags,status); */
 503                         /* ni_pcidio_print_flags(flags); */
 504                         /* ni_pcidio_print_status(status); */
 505                         async->events |= COMEDI_CB_BLOCK;
 506                 }
 507
 508                 if (flags & CountExpired) {
 509                         DPRINTK("CountExpired\n");
 510                         writeb(ClearExpired,
 511                                devpriv->mite->daq_io_addr +
 512                                Group_1_Second_Clear);
 513                         async->events |= COMEDI_CB_EOA;
 514
 515                         writeb(0x00, devpriv->mite->daq_io_addr + OpMode);
 516                         break;
 517                 } else if (flags & Waited) {
 518                         DPRINTK("Waited\n");
 519                         writeb(ClearWaited,
 520                                devpriv->mite->daq_io_addr +
 521                                Group_1_First_Clear);
 522                         async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 523                         break;
 524                 } else if (flags & PrimaryTC) {
 525                         DPRINTK("PrimaryTC\n");
 526                         writeb(ClearPrimaryTC,
 527                                devpriv->mite->daq_io_addr +
 528                                Group_1_First_Clear);
 529                         async->events |= COMEDI_CB_EOA;
 530                 } else if (flags & SecondaryTC) {
 531                         DPRINTK("SecondaryTC\n");
 532                         writeb(ClearSecondaryTC,
 533                                devpriv->mite->daq_io_addr +
 534                                Group_1_First_Clear);
 535                         async->events |= COMEDI_CB_EOA;
 536                 }
 537 #if 0
 538                 else {
 539                         DPRINTK("ni_pcidio: unknown interrupt\n");
 540                         async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 541                         writeb(0x00,
 542                                devpriv->mite->daq_io_addr +
 543                                Master_DMA_And_Interrupt_Control);
 544                 }
 545 #endif
 546                 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 547                 status = readb(devpriv->mite->daq_io_addr +
 548                                Interrupt_And_Window_Status);
 549                 /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,"
 550                         "status=0x%02x\n", IntEn, flags, status); */
 551                 /* ni_pcidio_print_flags(flags); */
 552                 /* ni_pcidio_print_status(status); */
 553         }
 554
 555 out:
 556         ni_pcidio_event(dev, s);
 557 #if 0
 558         if (!tag) {
 559                 writeb(0x03,
 560                        devpriv->mite->daq_io_addr +
 561                        Master_DMA_And_Interrupt_Control);
 562         }
 563 #endif
 564
 565         spin_unlock(&dev->spinlock);
 566         return IRQ_HANDLED;
 567 }
 568
 569 #ifdef DEBUG_FLAGS
 570 static const char *bit_set_string(unsigned int bits, unsigned int bit,
 571                                   const char *const strings[])
 572 {
 573         return (bits & (1U << bit)) ? strings[bit] : "";
 574 }
 575
 576 static const char *const flags_strings[] = {
 577         " TransferReady", " CountExpired", " 2", " 3",
 578         " 4", " Waited", " PrimaryTC", " SecondaryTC",
 579 };
 580
 581
 582 static void ni_pcidio_print_flags(unsigned int flags)
 583 {
 584         pr_debug("group_1_flags:%s%s%s%s%s%s%s%s\n",
 585                  bit_set_string(flags, 7, flags_strings),
 586                  bit_set_string(flags, 6, flags_strings),
 587                  bit_set_string(flags, 5, flags_strings),
 588                  bit_set_string(flags, 4, flags_strings),
 589                  bit_set_string(flags, 3, flags_strings),
 590                  bit_set_string(flags, 2, flags_strings),
 591                  bit_set_string(flags, 1, flags_strings),
 592                  bit_set_string(flags, 0, flags_strings));
 593 }
 594
 595 static const char *const status_strings[] = {
 596         " DataLeft1", " Reserved1", " Req1", " StopTrig1",
 597         " DataLeft2", " Reserved2", " Req2", " StopTrig2",
 598 };
 599
 600 static void ni_pcidio_print_status(unsigned int flags)
 601 {
 602         pr_debug("group_status:%s%s%s%s%s%s%s%s\n",
 603                  bit_set_string(flags, 7, status_strings),
 604                  bit_set_string(flags, 6, status_strings),
 605                  bit_set_string(flags, 5, status_strings),
 606                  bit_set_string(flags, 4, status_strings),
 607                  bit_set_string(flags, 3, status_strings),
 608                  bit_set_string(flags, 2, status_strings),
 609                  bit_set_string(flags, 1, status_strings),
 610                  bit_set_string(flags, 0, status_strings));
 611 }
 612 #endif
 613
 614 #ifdef unused
 615 static void debug_int(struct comedi_device *dev)
 616 {
 617         struct nidio96_private *devpriv = dev->private;
 618         int a, b;
 619         static int n_int;
 620         struct timeval tv;
 621
 622         do_gettimeofday(&tv);
 623         a = readb(devpriv->mite->daq_io_addr + Group_Status);
 624         b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 625
 626         if (n_int < 10) {
 627                 DPRINTK("status 0x%02x flags 0x%02x time %06d\n", a, b,
 628                         (int)tv.tv_usec);
 629         }
 630
 631         while (b & 1) {
 632                 writew(0xff, devpriv->mite->daq_io_addr + Group_1_FIFO);
 633                 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 634         }
 635
 636         b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
 637
 638         if (n_int < 10) {
 639                 DPRINTK("new status 0x%02x\n", b);
 640                 n_int++;
 641         }
 642 }
 643 #endif
 644
 645 static int ni_pcidio_insn_config(struct comedi_device *dev,
 646                                  struct comedi_subdevice *s,
 647                                  struct comedi_insn *insn, unsigned int *data)
 648 {
 649         struct nidio96_private *devpriv = dev->private;
 650
 651         if (insn->n != 1)
 652                 return -EINVAL;
 653         switch (data[0]) {
 654         case INSN_CONFIG_DIO_OUTPUT:
 655                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
 656                 break;
 657         case INSN_CONFIG_DIO_INPUT:
 658                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
 659                 break;
 660         case INSN_CONFIG_DIO_QUERY:
 661                 data[1] =
 662                     (s->
 663                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
 664                     COMEDI_INPUT;
 665                 return insn->n;
 666                 break;
 667         default:
 668                 return -EINVAL;
 669         }
 670         writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
 671
 672         return 1;
 673 }
 674
 675 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 676                                struct comedi_subdevice *s,
 677                                struct comedi_insn *insn, unsigned int *data)
 678 {
 679         struct nidio96_private *devpriv = dev->private;
 680
 681         if (data[0]) {
 682                 s->state &= ~data[0];
 683                 s->state |= (data[0] & data[1]);
 684                 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0));
 685         }
 686         data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0));
 687
 688         return insn->n;
 689 }
 690
 691 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 692                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 693 {
 694         int err = 0;
 695         int tmp;
 696
 697         /* Step 1 : check if triggers are trivially valid */
 698
 699         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
 700         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
 701                                         TRIG_TIMER | TRIG_EXT);
 702         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 703         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 704         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 705
 706         if (err)
 707                 return 1;
 708
 709         /* Step 2a : make sure trigger sources are unique */
 710
 711         err |= cfc_check_trigger_is_unique(cmd->start_src);
 712         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
 713         err |= cfc_check_trigger_is_unique(cmd->stop_src);
 714
 715         /* Step 2b : and mutually compatible */
 716
 717         if (err)
 718                 return 2;
 719
 720         /* Step 3: check if arguments are trivially valid */
 721
 722         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
 723
 724 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 725
 726         if (cmd->scan_begin_src == TRIG_TIMER) {
 727                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
 728                                                  MAX_SPEED);
 729                 /* no minimum speed */
 730         } else {
 731                 /* TRIG_EXT */
 732                 /* should be level/edge, hi/lo specification here */
 733                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 734                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 735                         err |= -EINVAL;
 736                 }
 737         }
 738
 739         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
 740         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
 741
 742         if (cmd->stop_src == TRIG_COUNT) {
 743                 /* no limit */
 744         } else {        /* TRIG_NONE */
 745                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
 746         }
 747
 748         if (err)
 749                 return 3;
 750
 751         /* step 4: fix up any arguments */
 752
 753         if (cmd->scan_begin_src == TRIG_TIMER) {
 754                 tmp = cmd->scan_begin_arg;
 755                 ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 756                                       cmd->flags & TRIG_ROUND_MASK);
 757                 if (tmp != cmd->scan_begin_arg)
 758                         err++;
 759         }
 760
 761         if (err)
 762                 return 4;
 763
 764         return 0;
 765 }
 766
 767 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode)
 768 {
 769         int divider, base;
 770
 771         base = TIMER_BASE;
 772
 773         switch (round_mode) {
 774         case TRIG_ROUND_NEAREST:
 775         default:
 776                 divider = (*nanosec + base / 2) / base;
 777                 break;
 778         case TRIG_ROUND_DOWN:
 779                 divider = (*nanosec) / base;
 780                 break;
 781         case TRIG_ROUND_UP:
 782                 divider = (*nanosec + base - 1) / base;
 783                 break;
 784         }
 785
 786         *nanosec = base * divider;
 787         return divider;
 788 }
 789
 790 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 791 {
 792         struct nidio96_private *devpriv = dev->private;
 793         struct comedi_cmd *cmd = &s->async->cmd;
 794
 795         /* XXX configure ports for input */
 796         writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
 797
 798         if (1) {
 799                 /* enable fifos A B C D */
 800                 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path);
 801
 802                 /* set transfer width a 32 bits */
 803                 writeb(TransferWidth(0) | TransferLength(0),
 804                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
 805         } else {
 806                 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path);
 807                 writeb(TransferWidth(3) | TransferLength(0),
 808                        devpriv->mite->daq_io_addr + Transfer_Size_Control);
 809         }
 810
 811         /* protocol configuration */
 812         if (cmd->scan_begin_src == TRIG_TIMER) {
 813                 /* page 4-5, "input with internal REQs" */
 814                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
 815                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
 816                 writeb(1, devpriv->mite->daq_io_addr + Sequence);
 817                 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg);
 818                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
 819                 writeb(3, devpriv->mite->daq_io_addr + LinePolarities);
 820                 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer);
 821                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 822                                              TRIG_ROUND_NEAREST),
 823                        devpriv->mite->daq_io_addr + StartDelay);
 824                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
 825                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
 826                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
 827                 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay);
 828                 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay);
 829                 /* manual, page 4-5: ClockSpeed comment is incorrectly listed
 830                  * on DAQOptions */
 831                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
 832                 writeb(0, devpriv->mite->daq_io_addr + DAQOptions);
 833         } else {
 834                 /* TRIG_EXT */
 835                 /* page 4-5, "input with external REQs" */
 836                 writeb(0, devpriv->mite->daq_io_addr + OpMode);
 837                 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
 838                 writeb(0, devpriv->mite->daq_io_addr + Sequence);
 839                 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg);
 840                 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
 841                 if (!(cmd->scan_begin_arg & CR_INVERT)) {
 842                         /* Leading Edge pulse mode */
 843                         writeb(0, devpriv->mite->daq_io_addr + LinePolarities);
 844                 } else {
 845                         /* Trailing Edge pulse mode */
 846                         writeb(2, devpriv->mite->daq_io_addr + LinePolarities);
 847                 }
 848                 writeb(0x00, devpriv->mite->daq_io_addr + AckSer);
 849                 writel(1, devpriv->mite->daq_io_addr + StartDelay);
 850                 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
 851                 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
 852                 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
 853                 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay);
 854                 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay);
 855                 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
 856                 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions);
 857         }
 858
 859         if (cmd->stop_src == TRIG_COUNT) {
 860                 writel(cmd->stop_arg,
 861                        devpriv->mite->daq_io_addr + Transfer_Count);
 862         } else {
 863                 /* XXX */
 864         }
 865
 866 #ifdef USE_DMA
 867         writeb(ClearPrimaryTC | ClearSecondaryTC,
 868                devpriv->mite->daq_io_addr + Group_1_First_Clear);
 869
 870         {
 871                 int retval = setup_mite_dma(dev, s);
 872                 if (retval)
 873                         return retval;
 874         }
 875 #else
 876         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
 877 #endif
 878         writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2);
 879
 880         /* clear and enable interrupts */
 881         writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear);
 882         /* writeb(ClearExpired,
 883                devpriv->mite->daq_io_addr+Group_1_Second_Clear); */
 884
 885         writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control);
 886         writeb(0x03,
 887                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
 888
 889         if (cmd->stop_src == TRIG_NONE) {
 890                 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
 891         } else {                /* TRIG_TIMER */
 892                 devpriv->OpModeBits = Numbered | RunMode(7);
 893         }
 894         if (cmd->start_src == TRIG_NOW) {
 895                 /* start */
 896                 writeb(devpriv->OpModeBits,
 897                        devpriv->mite->daq_io_addr + OpMode);
 898                 s->async->inttrig = NULL;
 899         } else {
 900                 /* TRIG_INT */
 901                 s->async->inttrig = ni_pcidio_inttrig;
 902         }
 903
 904         DPRINTK("ni_pcidio: command started\n");
 905         return 0;
 906 }
 907
 908 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
 909 {
 910         struct nidio96_private *devpriv = dev->private;
 911         int retval;
 912         unsigned long flags;
 913
 914         retval = ni_pcidio_request_di_mite_channel(dev);
 915         if (retval)
 916                 return retval;
 917
 918         /* write alloc the entire buffer */
 919         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
 920
 921         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 922         if (devpriv->di_mite_chan) {
 923                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
 924                 mite_dma_arm(devpriv->di_mite_chan);
 925         } else
 926                 retval = -EIO;
 927         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 928
 929         return retval;
 930 }
 931
 932 static int ni_pcidio_inttrig(struct comedi_device *dev,
 933                              struct comedi_subdevice *s, unsigned int trignum)
 934 {
 935         struct nidio96_private *devpriv = dev->private;
 936
 937         if (trignum != 0)
 938                 return -EINVAL;
 939
 940         writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode);
 941         s->async->inttrig = NULL;
 942
 943         return 1;
 944 }
 945
 946 static int ni_pcidio_cancel(struct comedi_device *dev,
 947                             struct comedi_subdevice *s)
 948 {
 949         struct nidio96_private *devpriv = dev->private;
 950
 951         writeb(0x00,
 952                devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
 953         ni_pcidio_release_di_mite_channel(dev);
 954
 955         return 0;
 956 }
 957
 958 static int ni_pcidio_change(struct comedi_device *dev,
 959                             struct comedi_subdevice *s, unsigned long new_size)
 960 {
 961         struct nidio96_private *devpriv = dev->private;
 962         int ret;
 963
 964         ret = mite_buf_change(devpriv->di_mite_ring, s->async);
 965         if (ret < 0)
 966                 return ret;
 967
 968         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
 969
 970         return 0;
 971 }
 972
 973 static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index,
 974                               const u8 *data, size_t data_len)
 975 {
 976         struct nidio96_private *devpriv = dev->private;
 977         static const int timeout = 1000;
 978         int i;
 979         size_t j;
 980
 981         writew(0x80 | fpga_index,
 982                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 983         writew(0xc0 | fpga_index,
 984                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 985         for (i = 0;
 986              (readw(devpriv->mite->daq_io_addr +
 987                     Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) {
 988                 udelay(1);
 989         }
 990         if (i == timeout) {
 991                 dev_warn(dev->class_dev,
 992                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
 993                          fpga_index);
 994                 return -EIO;
 995         }
 996         writew(0x80 | fpga_index,
 997                devpriv->mite->daq_io_addr + Firmware_Control_Register);
 998         for (i = 0;
 999              readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) !=
1000              0x3 && i < timeout; ++i) {
1001                 udelay(1);
1002         }
1003         if (i == timeout) {
1004                 dev_warn(dev->class_dev,
1005                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
1006                          fpga_index);
1007                 return -EIO;
1008         }
1009         for (j = 0; j + 1 < data_len;) {
1010                 unsigned int value = data[j++];
1011                 value |= data[j++] << 8;
1012                 writew(value,
1013                        devpriv->mite->daq_io_addr + Firmware_Data_Register);
1014                 for (i = 0;
1015                      (readw(devpriv->mite->daq_io_addr +
1016                             Firmware_Status_Register) & 0x2) == 0
1017                      && i < timeout; ++i) {
1018                         udelay(1);
1019                 }
1020                 if (i == timeout) {
1021                         dev_warn(dev->class_dev,
1022                                  "ni_pcidio: failed to load word into fpga %i\n",
1023                                  fpga_index);
1024                         return -EIO;
1025                 }
1026                 if (need_resched())
1027                         schedule();
1028         }
1029         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1030         return 0;
1031 }
1032
1033 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
1034 {
1035         return pci_6534_load_fpga(dev, fpga_index, NULL, 0);
1036 }
1037
1038 static int pci_6534_reset_fpgas(struct comedi_device *dev)
1039 {
1040         struct nidio96_private *devpriv = dev->private;
1041         int ret;
1042         int i;
1043
1044         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1045         for (i = 0; i < 3; ++i) {
1046                 ret = pci_6534_reset_fpga(dev, i);
1047                 if (ret < 0)
1048                         break;
1049         }
1050         writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register);
1051         return ret;
1052 }
1053
1054 static void pci_6534_init_main_fpga(struct comedi_device *dev)
1055 {
1056         struct nidio96_private *devpriv = dev->private;
1057
1058         writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register);
1059         writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register);
1060         writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register);
1061         writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register);
1062         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register);
1063         writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register);
1064 }
1065
1066 static int pci_6534_upload_firmware(struct comedi_device *dev)
1067 {
1068         struct nidio96_private *devpriv = dev->private;
1069         int ret;
1070         const struct firmware *fw;
1071         static const char *const fw_file[3] = {
1072                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
1073                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
1074                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
1075         };
1076         int n;
1077
1078         ret = pci_6534_reset_fpgas(dev);
1079         if (ret < 0)
1080                 return ret;
1081         /* load main FPGA first, then the two scarabs */
1082         for (n = 2; n >= 0; n--) {
1083                 ret = request_firmware(&fw, fw_file[n],
1084                                        &devpriv->mite->pcidev->dev);
1085                 if (ret == 0) {
1086                         ret = pci_6534_load_fpga(dev, n, fw->data, fw->size);
1087                         if (ret == 0 && n == 2)
1088                                 pci_6534_init_main_fpga(dev);
1089                         release_firmware(fw);
1090                 }
1091                 if (ret < 0)
1092                         break;
1093         }
1094         return ret;
1095 }
1096
1097 static const struct nidio_board *
1098 nidio_find_boardinfo(struct pci_dev *pcidev)
1099 {
1100         unsigned int dev_id = pcidev->device;
1101         unsigned int n;
1102
1103         for (n = 0; n < ARRAY_SIZE(nidio_boards); n++) {
1104                 const struct nidio_board *board = &nidio_boards[n];
1105                 if (board->dev_id == dev_id)
1106                         return board;
1107         }
1108         return NULL;
1109 }
1110
1111 static int nidio_auto_attach(struct comedi_device *dev,
1112                                        unsigned long context_unused)
1113 {
1114         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1115         struct nidio96_private *devpriv;
1116         struct comedi_subdevice *s;
1117         int ret;
1118         unsigned int irq;
1119
1120         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1121         if (!devpriv)
1122                 return -ENOMEM;
1123         dev->private = devpriv;
1124
1125         spin_lock_init(&devpriv->mite_channel_lock);
1126
1127         dev->board_ptr = nidio_find_boardinfo(pcidev);
1128         if (!dev->board_ptr)
1129                 return -ENODEV;
1130         devpriv->mite = mite_alloc(pcidev);
1131         if (!devpriv->mite)
1132                 return -ENOMEM;
1133
1134         ret = mite_setup(devpriv->mite);
1135         if (ret < 0) {
1136                 dev_warn(dev->class_dev, "error setting up mite\n");
1137                 return ret;
1138         }
1139
1140         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
1141         if (devpriv->di_mite_ring == NULL)
1142                 return -ENOMEM;
1143
1144         dev->board_name = this_board->name;
1145         irq = mite_irq(devpriv->mite);
1146         if (this_board->uses_firmware) {
1147                 ret = pci_6534_upload_firmware(dev);
1148                 if (ret < 0)
1149                         return ret;
1150         }
1151
1152         ret = comedi_alloc_subdevices(dev, 1);
1153         if (ret)
1154                 return ret;
1155
1156         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
1157                  readb(devpriv->mite->daq_io_addr + Chip_Version));
1158
1159         s = &dev->subdevices[0];
1160
1161         dev->read_subdev = s;
1162         s->type = COMEDI_SUBD_DIO;
1163         s->subdev_flags =
1164                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
1165                 SDF_CMD_READ;
1166         s->n_chan = 32;
1167         s->range_table = &range_digital;
1168         s->maxdata = 1;
1169         s->insn_config = &ni_pcidio_insn_config;
1170         s->insn_bits = &ni_pcidio_insn_bits;
1171         s->do_cmd = &ni_pcidio_cmd;
1172         s->do_cmdtest = &ni_pcidio_cmdtest;
1173         s->cancel = &ni_pcidio_cancel;
1174         s->len_chanlist = 32;   /* XXX */
1175         s->buf_change = &ni_pcidio_change;
1176         s->async_dma_dir = DMA_BIDIRECTIONAL;
1177         s->poll = &ni_pcidio_poll;
1178
1179         writel(0, devpriv->mite->daq_io_addr + Port_IO(0));
1180         writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
1181         writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0));
1182
1183         /* disable interrupts on board */
1184         writeb(0x00,
1185                 devpriv->mite->daq_io_addr +
1186                 Master_DMA_And_Interrupt_Control);
1187
1188         ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
1189                                 "ni_pcidio", dev);
1190         if (ret < 0)
1191                 dev_warn(dev->class_dev, "irq not available\n");
1192
1193         dev->irq = irq;
1194
1195         return 0;
1196 }
1197
1198 static void nidio_detach(struct comedi_device *dev)
1199 {
1200         struct nidio96_private *devpriv = dev->private;
1201
1202         if (dev->irq)
1203                 free_irq(dev->irq, dev);
1204         if (devpriv) {
1205                 if (devpriv->di_mite_ring) {
1206                         mite_free_ring(devpriv->di_mite_ring);
1207                         devpriv->di_mite_ring = NULL;
1208                 }
1209                 if (devpriv->mite) {
1210                         mite_unsetup(devpriv->mite);
1211                         mite_free(devpriv->mite);
1212                 }
1213         }
1214 }
1215
1216 static struct comedi_driver ni_pcidio_driver = {
1217         .driver_name    = "ni_pcidio",
1218         .module         = THIS_MODULE,
1219         .auto_attach    = nidio_auto_attach,
1220         .detach         = nidio_detach,
1221 };
1222
1223 static int ni_pcidio_pci_probe(struct pci_dev *dev,
1224                                          const struct pci_device_id *ent)
1225 {
1226         return comedi_pci_auto_config(dev, &ni_pcidio_driver);
1227 }
1228
1229 static DEFINE_PCI_DEVICE_TABLE(ni_pcidio_pci_table) = {
1230         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1150) },
1231         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1320) },
1232         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x12b0) },
1233         { 0 }
1234 };
1235 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1236
1237 static struct pci_driver ni_pcidio_pci_driver = {
1238         .name           = "ni_pcidio",
1239         .id_table       = ni_pcidio_pci_table,
1240         .probe          = ni_pcidio_pci_probe,
1241         .remove         = comedi_pci_auto_unconfig,
1242 };
1243 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1244
1245 MODULE_AUTHOR("Comedi http://www.comedi.org");
1246 MODULE_DESCRIPTION("Comedi low-level driver");
1247 MODULE_LICENSE("GPL");