2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
24 Interrupt support originally added by Truxton Fulton
27 References (from ftp://ftp.natinst.com/support/manuals):
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
35 Other possibly relevant info:
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
40 320906c.pdf maximum signal ratings
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
49 - the interrupt routine needs to be cleaned up
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
55 /* #define DEBUG_INTERRUPT */
56 /* #define DEBUG_STATUS_A */
57 /* #define DEBUG_STATUS_B */
59 #include <linux/interrupt.h>
60 #include <linux/sched.h>
61 #include <linux/delay.h>
64 #include "comedi_fc.h"
67 #define MDPRINTK(format, args...)
71 #define NI_TIMEOUT 1000
72 static const unsigned old_RTSI_clock_channel = 7;
74 /* Note: this table must match the ai_gain_* definitions */
75 static const short ni_gainlkup[][16] = {
76 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
77 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
78 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
79 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
80 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
81 [ai_gain_4] = {0, 1, 4, 7},
82 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
83 0x003, 0x004, 0x005, 0x006},
84 [ai_gain_622x] = {0, 1, 4, 5},
85 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
86 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
89 static const struct comedi_lrange range_ni_E_ai = { 16, {
109 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
122 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
147 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
157 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
169 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
177 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
188 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
196 static const struct comedi_lrange *const ni_range_lkup[] = {
197 [ai_gain_16] = &range_ni_E_ai,
198 [ai_gain_8] = &range_ni_E_ai_limited,
199 [ai_gain_14] = &range_ni_E_ai_limited14,
200 [ai_gain_4] = &range_ni_E_ai_bipolar4,
201 [ai_gain_611x] = &range_ni_E_ai_611x,
202 [ai_gain_622x] = &range_ni_M_ai_622x,
203 [ai_gain_628x] = &range_ni_M_ai_628x,
204 [ai_gain_6143] = &range_bipolar5
207 static int ni_dio_insn_config(struct comedi_device *dev,
208 struct comedi_subdevice *s,
209 struct comedi_insn *insn, unsigned int *data);
210 static int ni_dio_insn_bits(struct comedi_device *dev,
211 struct comedi_subdevice *s,
212 struct comedi_insn *insn, unsigned int *data);
213 static int ni_cdio_cmdtest(struct comedi_device *dev,
214 struct comedi_subdevice *s, struct comedi_cmd *cmd);
215 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
216 static int ni_cdio_cancel(struct comedi_device *dev,
217 struct comedi_subdevice *s);
218 static void handle_cdio_interrupt(struct comedi_device *dev);
219 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
220 unsigned int trignum);
222 static int ni_serial_insn_config(struct comedi_device *dev,
223 struct comedi_subdevice *s,
224 struct comedi_insn *insn, unsigned int *data);
225 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
226 struct comedi_subdevice *s,
227 unsigned char data_out,
228 unsigned char *data_in);
229 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 unsigned char data_out,
232 unsigned char *data_in);
234 static int ni_calib_insn_read(struct comedi_device *dev,
235 struct comedi_subdevice *s,
236 struct comedi_insn *insn, unsigned int *data);
237 static int ni_calib_insn_write(struct comedi_device *dev,
238 struct comedi_subdevice *s,
239 struct comedi_insn *insn, unsigned int *data);
241 static int ni_eeprom_insn_read(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_insn *insn, unsigned int *data);
244 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
245 struct comedi_subdevice *s,
246 struct comedi_insn *insn,
249 static int ni_pfi_insn_bits(struct comedi_device *dev,
250 struct comedi_subdevice *s,
251 struct comedi_insn *insn, unsigned int *data);
252 static int ni_pfi_insn_config(struct comedi_device *dev,
253 struct comedi_subdevice *s,
254 struct comedi_insn *insn, unsigned int *data);
255 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
258 static void ni_rtsi_init(struct comedi_device *dev);
259 static int ni_rtsi_insn_bits(struct comedi_device *dev,
260 struct comedi_subdevice *s,
261 struct comedi_insn *insn, unsigned int *data);
262 static int ni_rtsi_insn_config(struct comedi_device *dev,
263 struct comedi_subdevice *s,
264 struct comedi_insn *insn, unsigned int *data);
266 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
267 static int ni_read_eeprom(struct comedi_device *dev, int addr);
269 #ifdef DEBUG_STATUS_A
270 static void ni_mio_print_status_a(int status);
272 #define ni_mio_print_status_a(a)
274 #ifdef DEBUG_STATUS_B
275 static void ni_mio_print_status_b(int status);
277 #define ni_mio_print_status_b(a)
280 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
282 static void ni_handle_fifo_half_full(struct comedi_device *dev);
283 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
284 struct comedi_subdevice *s);
286 static void ni_handle_fifo_dregs(struct comedi_device *dev);
287 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
288 unsigned int trignum);
289 static void ni_load_channelgain_list(struct comedi_device *dev,
290 unsigned int n_chan, unsigned int *list);
291 static void shutdown_ai_command(struct comedi_device *dev);
293 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
294 unsigned int trignum);
296 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
298 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
300 static int ni_gpct_insn_write(struct comedi_device *dev,
301 struct comedi_subdevice *s,
302 struct comedi_insn *insn, unsigned int *data);
303 static int ni_gpct_insn_read(struct comedi_device *dev,
304 struct comedi_subdevice *s,
305 struct comedi_insn *insn, unsigned int *data);
306 static int ni_gpct_insn_config(struct comedi_device *dev,
307 struct comedi_subdevice *s,
308 struct comedi_insn *insn, unsigned int *data);
310 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
311 static int ni_gpct_cmdtest(struct comedi_device *dev,
312 struct comedi_subdevice *s, struct comedi_cmd *cmd);
314 static int ni_gpct_cancel(struct comedi_device *dev,
315 struct comedi_subdevice *s);
316 static void handle_gpct_interrupt(struct comedi_device *dev,
317 unsigned short counter_index);
319 static int init_cs5529(struct comedi_device *dev);
320 static int cs5529_do_conversion(struct comedi_device *dev,
321 unsigned short *data);
322 static int cs5529_ai_insn_read(struct comedi_device *dev,
323 struct comedi_subdevice *s,
324 struct comedi_insn *insn, unsigned int *data);
325 #ifdef NI_CS5529_DEBUG
326 static unsigned int cs5529_config_read(struct comedi_device *dev,
327 unsigned int reg_select_bits);
329 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
330 unsigned int reg_select_bits);
332 static int ni_m_series_pwm_config(struct comedi_device *dev,
333 struct comedi_subdevice *s,
334 struct comedi_insn *insn, unsigned int *data);
335 static int ni_6143_pwm_config(struct comedi_device *dev,
336 struct comedi_subdevice *s,
337 struct comedi_insn *insn, unsigned int *data);
339 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
341 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
342 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
346 AIMODE_HALF_FULL = 1,
351 enum ni_common_subdevices {
357 NI_CALIBRATION_SUBDEV,
360 NI_CS5529_CALIBRATION_SUBDEV,
368 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
370 switch (counter_index) {
372 return NI_GPCT0_SUBDEV;
375 return NI_GPCT1_SUBDEV;
381 return NI_GPCT0_SUBDEV;
384 enum timebase_nanoseconds {
386 TIMEBASE_2_NS = 10000
389 #define SERIAL_DISABLED 0
390 #define SERIAL_600NS 600
391 #define SERIAL_1_2US 1200
392 #define SERIAL_10US 10000
394 static const int num_adc_stages_611x = 3;
396 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
397 unsigned ai_mite_status);
398 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
399 unsigned ao_mite_status);
400 static void get_last_sample_611x(struct comedi_device *dev);
401 static void get_last_sample_6143(struct comedi_device *dev);
403 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
404 unsigned bit_mask, unsigned bit_values)
406 struct ni_private *devpriv = dev->private;
409 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
411 case Interrupt_A_Enable_Register:
412 devpriv->int_a_enable_reg &= ~bit_mask;
413 devpriv->int_a_enable_reg |= bit_values & bit_mask;
414 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
415 Interrupt_A_Enable_Register);
417 case Interrupt_B_Enable_Register:
418 devpriv->int_b_enable_reg &= ~bit_mask;
419 devpriv->int_b_enable_reg |= bit_values & bit_mask;
420 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
421 Interrupt_B_Enable_Register);
423 case IO_Bidirection_Pin_Register:
424 devpriv->io_bidirection_pin_reg &= ~bit_mask;
425 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
426 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
427 IO_Bidirection_Pin_Register);
430 devpriv->ai_ao_select_reg &= ~bit_mask;
431 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
432 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
435 devpriv->g0_g1_select_reg &= ~bit_mask;
436 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
437 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
440 printk("Warning %s() called with invalid register\n", __func__);
441 printk("reg is %d\n", reg);
445 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
449 static int ni_ai_drain_dma(struct comedi_device *dev);
451 /* DMA channel setup */
453 /* negative channel means no channel */
454 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
460 (ni_stc_dma_channel_select_bitfield(channel) <<
461 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
465 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
468 /* negative channel means no channel */
469 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
475 (ni_stc_dma_channel_select_bitfield(channel) <<
476 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
480 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
483 /* negative mite_channel means no channel */
484 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
490 if (mite_channel >= 0) {
491 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
495 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
499 /* negative mite_channel means no channel */
500 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
503 struct ni_private *devpriv = dev->private;
506 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
507 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
508 if (mite_channel >= 0) {
509 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
510 under the assumption the cdio dma selection works just like ai/ao/gpct.
511 Definitely works for dma channels 0 and 1. */
512 devpriv->cdio_dma_select_reg |=
513 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
514 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
516 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
518 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
521 static int ni_request_ai_mite_channel(struct comedi_device *dev)
523 struct ni_private *devpriv = dev->private;
526 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
527 BUG_ON(devpriv->ai_mite_chan);
528 devpriv->ai_mite_chan =
529 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
530 if (devpriv->ai_mite_chan == NULL) {
531 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
533 "failed to reserve mite dma channel for analog input.");
536 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
537 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
538 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
542 static int ni_request_ao_mite_channel(struct comedi_device *dev)
544 struct ni_private *devpriv = dev->private;
547 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
548 BUG_ON(devpriv->ao_mite_chan);
549 devpriv->ao_mite_chan =
550 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
551 if (devpriv->ao_mite_chan == NULL) {
552 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
554 "failed to reserve mite dma channel for analog outut.");
557 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
558 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
559 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
563 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
565 enum comedi_io_direction direction)
567 struct ni_private *devpriv = dev->private;
569 struct mite_channel *mite_chan;
571 BUG_ON(gpct_index >= NUM_GPCT);
572 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
573 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
575 mite_request_channel(devpriv->mite,
576 devpriv->gpct_mite_ring[gpct_index]);
577 if (mite_chan == NULL) {
578 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
580 "failed to reserve mite dma channel for counter.");
583 mite_chan->dir = direction;
584 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
586 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
587 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
593 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
596 struct ni_private *devpriv = dev->private;
599 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
600 BUG_ON(devpriv->cdo_mite_chan);
601 devpriv->cdo_mite_chan =
602 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
603 if (devpriv->cdo_mite_chan == NULL) {
604 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
606 "failed to reserve mite dma channel for correlated digital outut.");
609 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
610 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
611 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
616 static void ni_release_ai_mite_channel(struct comedi_device *dev)
619 struct ni_private *devpriv = dev->private;
622 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
623 if (devpriv->ai_mite_chan) {
624 ni_set_ai_dma_channel(dev, -1);
625 mite_release_channel(devpriv->ai_mite_chan);
626 devpriv->ai_mite_chan = NULL;
628 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
632 static void ni_release_ao_mite_channel(struct comedi_device *dev)
635 struct ni_private *devpriv = dev->private;
638 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
639 if (devpriv->ao_mite_chan) {
640 ni_set_ao_dma_channel(dev, -1);
641 mite_release_channel(devpriv->ao_mite_chan);
642 devpriv->ao_mite_chan = NULL;
644 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
649 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
652 struct ni_private *devpriv = dev->private;
655 BUG_ON(gpct_index >= NUM_GPCT);
656 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
657 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
658 struct mite_channel *mite_chan =
659 devpriv->counter_dev->counters[gpct_index].mite_chan;
661 ni_set_gpct_dma_channel(dev, gpct_index, -1);
662 ni_tio_set_mite_channel(&devpriv->
663 counter_dev->counters[gpct_index],
665 mite_release_channel(mite_chan);
667 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
671 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
674 struct ni_private *devpriv = dev->private;
677 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
678 if (devpriv->cdo_mite_chan) {
679 ni_set_cdo_dma_channel(dev, -1);
680 mite_release_channel(devpriv->cdo_mite_chan);
681 devpriv->cdo_mite_chan = NULL;
683 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
687 /* e-series boards use the second irq signals to generate dma requests for their counters */
689 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
690 unsigned gpct_index, short enable)
692 const struct ni_board_struct *board = comedi_board(dev);
693 struct ni_private *devpriv = dev->private;
695 if (board->reg_type & ni_reg_m_series_mask)
697 switch (gpct_index) {
700 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
701 Second_IRQ_A_Enable_Register);
703 devpriv->stc_writew(dev, 0,
704 Second_IRQ_A_Enable_Register);
709 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
710 Second_IRQ_B_Enable_Register);
712 devpriv->stc_writew(dev, 0,
713 Second_IRQ_B_Enable_Register);
723 static void ni_clear_ai_fifo(struct comedi_device *dev)
725 const struct ni_board_struct *board = comedi_board(dev);
726 struct ni_private *devpriv = dev->private;
728 if (board->reg_type == ni_reg_6143) {
729 /* Flush the 6143 data FIFO */
730 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
731 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
732 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
734 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
735 if (board->reg_type == ni_reg_625x) {
736 ni_writeb(0, M_Offset_Static_AI_Control(0));
737 ni_writeb(1, M_Offset_Static_AI_Control(0));
739 /* the NI example code does 3 convert pulses for 625x boards,
740 but that appears to be wrong in practice. */
741 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
742 AI_Command_1_Register);
743 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
744 AI_Command_1_Register);
745 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
746 AI_Command_1_Register);
752 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
754 struct ni_private *devpriv = dev->private;
756 devpriv->stc_writew(dev, data >> 16, reg);
757 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
760 static uint32_t win_in2(struct comedi_device *dev, int reg)
762 struct ni_private *devpriv = dev->private;
765 bits = devpriv->stc_readw(dev, reg) << 16;
766 bits |= devpriv->stc_readw(dev, reg + 1);
770 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
771 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
774 struct ni_private *devpriv = dev->private;
777 spin_lock_irqsave(&devpriv->window_lock, flags);
778 ni_writew(addr, AO_Window_Address_611x);
779 ni_writew(data, AO_Window_Data_611x);
780 spin_unlock_irqrestore(&devpriv->window_lock, flags);
783 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
786 struct ni_private *devpriv = dev->private;
789 spin_lock_irqsave(&devpriv->window_lock, flags);
790 ni_writew(addr, AO_Window_Address_611x);
791 ni_writel(data, AO_Window_Data_611x);
792 spin_unlock_irqrestore(&devpriv->window_lock, flags);
795 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
797 struct ni_private *devpriv = dev->private;
801 spin_lock_irqsave(&devpriv->window_lock, flags);
802 ni_writew(addr, AO_Window_Address_611x);
803 data = ni_readw(AO_Window_Data_611x);
804 spin_unlock_irqrestore(&devpriv->window_lock, flags);
808 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
809 * share registers (such as Interrupt_A_Register) without interfering with
812 * NOTE: the switch/case statements are optimized out for a constant argument
813 * so this is actually quite fast--- If you must wrap another function around this
814 * make it inline to avoid a large speed penalty.
816 * value should only be 1 or 0.
818 static inline void ni_set_bits(struct comedi_device *dev, int reg,
819 unsigned bits, unsigned value)
827 ni_set_bitfield(dev, reg, bits, bit_values);
830 static irqreturn_t ni_E_interrupt(int irq, void *d)
832 struct comedi_device *dev = d;
833 struct ni_private *devpriv = dev->private;
834 unsigned short a_status;
835 unsigned short b_status;
836 unsigned int ai_mite_status = 0;
837 unsigned int ao_mite_status = 0;
840 struct mite_struct *mite = devpriv->mite;
845 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
847 /* lock to avoid race with comedi_poll */
848 spin_lock_irqsave(&dev->spinlock, flags);
849 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
850 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
853 unsigned long flags_too;
855 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
856 if (devpriv->ai_mite_chan) {
857 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
858 if (ai_mite_status & CHSR_LINKC)
860 devpriv->mite->mite_io_addr +
862 ai_mite_chan->channel));
864 if (devpriv->ao_mite_chan) {
865 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
866 if (ao_mite_status & CHSR_LINKC)
870 ao_mite_chan->channel));
872 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
875 ack_a_interrupt(dev, a_status);
876 ack_b_interrupt(dev, b_status);
877 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
878 handle_a_interrupt(dev, a_status, ai_mite_status);
879 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
880 handle_b_interrupt(dev, b_status, ao_mite_status);
881 handle_gpct_interrupt(dev, 0);
882 handle_gpct_interrupt(dev, 1);
883 handle_cdio_interrupt(dev);
885 spin_unlock_irqrestore(&dev->spinlock, flags);
890 static void ni_sync_ai_dma(struct comedi_device *dev)
892 struct ni_private *devpriv = dev->private;
893 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
896 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
897 if (devpriv->ai_mite_chan)
898 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
899 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
902 static void mite_handle_b_linkc(struct mite_struct *mite,
903 struct comedi_device *dev)
905 struct ni_private *devpriv = dev->private;
906 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
909 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
910 if (devpriv->ao_mite_chan) {
911 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
913 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
916 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
918 struct ni_private *devpriv = dev->private;
919 static const int timeout = 10000;
921 for (i = 0; i < timeout; i++) {
922 unsigned short b_status;
924 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
925 if (b_status & AO_FIFO_Half_Full_St)
927 /* if we poll too often, the pci bus activity seems
928 to slow the dma transfer down */
932 comedi_error(dev, "timed out waiting for dma load");
939 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
941 struct ni_private *devpriv = dev->private;
943 if (devpriv->aimode == AIMODE_SCAN) {
945 static const int timeout = 10;
948 for (i = 0; i < timeout; i++) {
950 if ((s->async->events & COMEDI_CB_EOS))
955 ni_handle_fifo_dregs(dev);
956 s->async->events |= COMEDI_CB_EOS;
959 /* handle special case of single scan using AI_End_On_End_Of_Scan */
960 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
961 shutdown_ai_command(dev);
965 static void shutdown_ai_command(struct comedi_device *dev)
967 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
970 ni_ai_drain_dma(dev);
972 ni_handle_fifo_dregs(dev);
973 get_last_sample_611x(dev);
974 get_last_sample_6143(dev);
976 s->async->events |= COMEDI_CB_EOA;
979 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
982 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
991 case NI_GPCT0_SUBDEV:
992 case NI_GPCT1_SUBDEV:
993 ni_gpct_cancel(dev, s);
996 ni_cdio_cancel(dev, s);
1002 comedi_event(dev, s);
1005 static void handle_gpct_interrupt(struct comedi_device *dev,
1006 unsigned short counter_index)
1009 struct ni_private *devpriv = dev->private;
1010 struct comedi_subdevice *s;
1012 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1014 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1016 if (s->async->events)
1021 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1023 struct ni_private *devpriv = dev->private;
1024 unsigned short ack = 0;
1026 if (a_status & AI_SC_TC_St) {
1027 ack |= AI_SC_TC_Interrupt_Ack;
1029 if (a_status & AI_START1_St) {
1030 ack |= AI_START1_Interrupt_Ack;
1032 if (a_status & AI_START_St) {
1033 ack |= AI_START_Interrupt_Ack;
1035 if (a_status & AI_STOP_St) {
1036 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1037 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1040 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1043 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1044 unsigned ai_mite_status)
1046 struct ni_private *devpriv = dev->private;
1047 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1049 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1050 if (s->type == COMEDI_SUBD_UNUSED)
1053 #ifdef DEBUG_INTERRUPT
1055 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1056 status, ai_mite_status);
1057 ni_mio_print_status_a(status);
1060 if (ai_mite_status & CHSR_LINKC) {
1061 ni_sync_ai_dma(dev);
1064 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1065 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1066 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1068 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1070 /* mite_print_chsr(ai_mite_status); */
1071 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1072 /* disable_irq(dev->irq); */
1076 /* test for all uncommon interrupt events at the same time */
1077 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1078 AI_SC_TC_St | AI_START1_St)) {
1079 if (status == 0xffff) {
1081 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1082 /* we probably aren't even running a command now,
1083 * so it's a good idea to be careful. */
1084 if (comedi_is_subdevice_running(s)) {
1086 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1091 if (status & (AI_Overrun_St | AI_Overflow_St |
1092 AI_SC_TC_Error_St)) {
1093 printk("ni_mio_common: ai error a_status=%04x\n",
1095 ni_mio_print_status_a(status);
1097 shutdown_ai_command(dev);
1099 s->async->events |= COMEDI_CB_ERROR;
1100 if (status & (AI_Overrun_St | AI_Overflow_St))
1101 s->async->events |= COMEDI_CB_OVERFLOW;
1107 if (status & AI_SC_TC_St) {
1108 #ifdef DEBUG_INTERRUPT
1109 printk("ni_mio_common: SC_TC interrupt\n");
1111 if (!devpriv->ai_continuous) {
1112 shutdown_ai_command(dev);
1117 if (status & AI_FIFO_Half_Full_St) {
1119 static const int timeout = 10;
1120 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1121 *fail to get the fifo less than half full, so loop to be sure.*/
1122 for (i = 0; i < timeout; ++i) {
1123 ni_handle_fifo_half_full(dev);
1124 if ((devpriv->stc_readw(dev,
1125 AI_Status_1_Register) &
1126 AI_FIFO_Half_Full_St) == 0)
1130 #endif /* !PCIDMA */
1132 if ((status & AI_STOP_St)) {
1133 ni_handle_eos(dev, s);
1138 #ifdef DEBUG_INTERRUPT
1139 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1140 if (status & Interrupt_A_St) {
1142 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1148 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1150 struct ni_private *devpriv = dev->private;
1151 unsigned short ack = 0;
1153 if (b_status & AO_BC_TC_St) {
1154 ack |= AO_BC_TC_Interrupt_Ack;
1156 if (b_status & AO_Overrun_St) {
1157 ack |= AO_Error_Interrupt_Ack;
1159 if (b_status & AO_START_St) {
1160 ack |= AO_START_Interrupt_Ack;
1162 if (b_status & AO_START1_St) {
1163 ack |= AO_START1_Interrupt_Ack;
1165 if (b_status & AO_UC_TC_St) {
1166 ack |= AO_UC_TC_Interrupt_Ack;
1168 if (b_status & AO_UI2_TC_St) {
1169 ack |= AO_UI2_TC_Interrupt_Ack;
1171 if (b_status & AO_UPDATE_St) {
1172 ack |= AO_UPDATE_Interrupt_Ack;
1175 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1178 static void handle_b_interrupt(struct comedi_device *dev,
1179 unsigned short b_status, unsigned ao_mite_status)
1181 struct ni_private *devpriv = dev->private;
1182 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1183 /* unsigned short ack=0; */
1185 #ifdef DEBUG_INTERRUPT
1186 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1187 b_status, ao_mite_status);
1188 ni_mio_print_status_b(b_status);
1192 /* Currently, mite.c requires us to handle LINKC */
1193 if (ao_mite_status & CHSR_LINKC) {
1194 mite_handle_b_linkc(devpriv->mite, dev);
1197 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1198 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1199 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1201 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1203 /* mite_print_chsr(ao_mite_status); */
1204 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1208 if (b_status == 0xffff)
1210 if (b_status & AO_Overrun_St) {
1212 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1213 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1214 s->async->events |= COMEDI_CB_OVERFLOW;
1217 if (b_status & AO_BC_TC_St) {
1219 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1220 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1221 s->async->events |= COMEDI_CB_EOA;
1224 if (b_status & AO_FIFO_Request_St) {
1227 ret = ni_ao_fifo_half_empty(dev, s);
1229 printk("ni_mio_common: AO buffer underrun\n");
1230 ni_set_bits(dev, Interrupt_B_Enable_Register,
1231 AO_FIFO_Interrupt_Enable |
1232 AO_Error_Interrupt_Enable, 0);
1233 s->async->events |= COMEDI_CB_OVERFLOW;
1241 #ifdef DEBUG_STATUS_A
1242 static const char *const status_a_strings[] = {
1243 "passthru0", "fifo", "G0_gate", "G0_TC",
1244 "stop", "start", "sc_tc", "start1",
1245 "start2", "sc_tc_error", "overflow", "overrun",
1246 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1249 static void ni_mio_print_status_a(int status)
1253 printk("A status:");
1254 for (i = 15; i >= 0; i--) {
1255 if (status & (1 << i)) {
1256 printk(" %s", status_a_strings[i]);
1263 #ifdef DEBUG_STATUS_B
1264 static const char *const status_b_strings[] = {
1265 "passthru1", "fifo", "G1_gate", "G1_TC",
1266 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1267 "start1", "overrun", "start", "bc_tc_error",
1268 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1271 static void ni_mio_print_status_b(int status)
1275 printk("B status:");
1276 for (i = 15; i >= 0; i--) {
1277 if (status & (1 << i)) {
1278 printk(" %s", status_b_strings[i]);
1287 static void ni_ao_fifo_load(struct comedi_device *dev,
1288 struct comedi_subdevice *s, int n)
1290 const struct ni_board_struct *board = comedi_board(dev);
1291 struct comedi_async *async = s->async;
1292 struct comedi_cmd *cmd = &async->cmd;
1300 chan = async->cur_chan;
1301 for (i = 0; i < n; i++) {
1302 err &= comedi_buf_get(async, &d);
1306 range = CR_RANGE(cmd->chanlist[chan]);
1308 if (board->reg_type & ni_reg_6xxx_mask) {
1309 packed_data = d & 0xffff;
1310 /* 6711 only has 16 bit wide ao fifo */
1311 if (board->reg_type != ni_reg_6711) {
1312 err &= comedi_buf_get(async, &d);
1317 packed_data |= (d << 16) & 0xffff0000;
1319 ni_writel(packed_data, DAC_FIFO_Data_611x);
1321 ni_writew(d, DAC_FIFO_Data);
1324 chan %= cmd->chanlist_len;
1326 async->cur_chan = chan;
1328 async->events |= COMEDI_CB_OVERFLOW;
1333 * There's a small problem if the FIFO gets really low and we
1334 * don't have the data to fill it. Basically, if after we fill
1335 * the FIFO with all the data available, the FIFO is _still_
1336 * less than half full, we never clear the interrupt. If the
1337 * IRQ is in edge mode, we never get another interrupt, because
1338 * this one wasn't cleared. If in level mode, we get flooded
1339 * with interrupts that we can't fulfill, because nothing ever
1340 * gets put into the buffer.
1342 * This kind of situation is recoverable, but it is easier to
1343 * just pretend we had a FIFO underrun, since there is a good
1344 * chance it will happen anyway. This is _not_ the case for
1345 * RT code, as RT code might purposely be running close to the
1346 * metal. Needs to be fixed eventually.
1348 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1349 struct comedi_subdevice *s)
1351 const struct ni_board_struct *board = comedi_board(dev);
1354 n = comedi_buf_read_n_available(s->async);
1356 s->async->events |= COMEDI_CB_OVERFLOW;
1361 if (n > board->ao_fifo_depth / 2)
1362 n = board->ao_fifo_depth / 2;
1364 ni_ao_fifo_load(dev, s, n);
1366 s->async->events |= COMEDI_CB_BLOCK;
1371 static int ni_ao_prep_fifo(struct comedi_device *dev,
1372 struct comedi_subdevice *s)
1374 const struct ni_board_struct *board = comedi_board(dev);
1375 struct ni_private *devpriv = dev->private;
1379 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1380 if (board->reg_type & ni_reg_6xxx_mask)
1381 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1383 /* load some data */
1384 n = comedi_buf_read_n_available(s->async);
1389 if (n > board->ao_fifo_depth)
1390 n = board->ao_fifo_depth;
1392 ni_ao_fifo_load(dev, s, n);
1397 static void ni_ai_fifo_read(struct comedi_device *dev,
1398 struct comedi_subdevice *s, int n)
1400 const struct ni_board_struct *board = comedi_board(dev);
1401 struct ni_private *devpriv = dev->private;
1402 struct comedi_async *async = s->async;
1405 if (board->reg_type == ni_reg_611x) {
1409 for (i = 0; i < n / 2; i++) {
1410 dl = ni_readl(ADC_FIFO_Data_611x);
1411 /* This may get the hi/lo data in the wrong order */
1412 data[0] = (dl >> 16) & 0xffff;
1413 data[1] = dl & 0xffff;
1414 cfc_write_array_to_buffer(s, data, sizeof(data));
1416 /* Check if there's a single sample stuck in the FIFO */
1418 dl = ni_readl(ADC_FIFO_Data_611x);
1419 data[0] = dl & 0xffff;
1420 cfc_write_to_buffer(s, data[0]);
1422 } else if (board->reg_type == ni_reg_6143) {
1426 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1427 for (i = 0; i < n / 2; i++) {
1428 dl = ni_readl(AIFIFO_Data_6143);
1430 data[0] = (dl >> 16) & 0xffff;
1431 data[1] = dl & 0xffff;
1432 cfc_write_array_to_buffer(s, data, sizeof(data));
1435 /* Assume there is a single sample stuck in the FIFO */
1436 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1437 dl = ni_readl(AIFIFO_Data_6143);
1438 data[0] = (dl >> 16) & 0xffff;
1439 cfc_write_to_buffer(s, data[0]);
1442 if (n > sizeof(devpriv->ai_fifo_buffer) /
1443 sizeof(devpriv->ai_fifo_buffer[0])) {
1444 comedi_error(dev, "bug! ai_fifo_buffer too small");
1445 async->events |= COMEDI_CB_ERROR;
1448 for (i = 0; i < n; i++) {
1449 devpriv->ai_fifo_buffer[i] =
1450 ni_readw(ADC_FIFO_Data_Register);
1452 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1454 sizeof(devpriv->ai_fifo_buffer[0]));
1458 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1460 const struct ni_board_struct *board = comedi_board(dev);
1461 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1464 n = board->ai_fifo_depth / 2;
1466 ni_ai_fifo_read(dev, s, n);
1471 static int ni_ai_drain_dma(struct comedi_device *dev)
1473 struct ni_private *devpriv = dev->private;
1475 static const int timeout = 10000;
1476 unsigned long flags;
1479 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1480 if (devpriv->ai_mite_chan) {
1481 for (i = 0; i < timeout; i++) {
1482 if ((devpriv->stc_readw(dev,
1483 AI_Status_1_Register) &
1485 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1491 printk("ni_mio_common: wait for dma drain timed out\n");
1493 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1494 mite_bytes_in_transit(devpriv->ai_mite_chan),
1495 devpriv->stc_readw(dev, AI_Status_1_Register));
1499 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1501 ni_sync_ai_dma(dev);
1509 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1511 const struct ni_board_struct *board = comedi_board(dev);
1512 struct ni_private *devpriv = dev->private;
1513 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1519 if (board->reg_type == ni_reg_611x) {
1520 while ((devpriv->stc_readw(dev,
1521 AI_Status_1_Register) &
1522 AI_FIFO_Empty_St) == 0) {
1523 dl = ni_readl(ADC_FIFO_Data_611x);
1525 /* This may get the hi/lo data in the wrong order */
1526 data[0] = (dl >> 16);
1527 data[1] = (dl & 0xffff);
1528 cfc_write_array_to_buffer(s, data, sizeof(data));
1530 } else if (board->reg_type == ni_reg_6143) {
1532 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1533 dl = ni_readl(AIFIFO_Data_6143);
1535 /* This may get the hi/lo data in the wrong order */
1536 data[0] = (dl >> 16);
1537 data[1] = (dl & 0xffff);
1538 cfc_write_array_to_buffer(s, data, sizeof(data));
1541 /* Check if stranded sample is present */
1542 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1543 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1544 dl = ni_readl(AIFIFO_Data_6143);
1545 data[0] = (dl >> 16) & 0xffff;
1546 cfc_write_to_buffer(s, data[0]);
1551 devpriv->stc_readw(dev,
1552 AI_Status_1_Register) & AI_FIFO_Empty_St;
1553 while (fifo_empty == 0) {
1556 sizeof(devpriv->ai_fifo_buffer) /
1557 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1559 devpriv->stc_readw(dev,
1560 AI_Status_1_Register) &
1564 devpriv->ai_fifo_buffer[i] =
1565 ni_readw(ADC_FIFO_Data_Register);
1567 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1570 ai_fifo_buffer[0]));
1575 static void get_last_sample_611x(struct comedi_device *dev)
1577 const struct ni_board_struct *board = comedi_board(dev);
1578 struct ni_private *devpriv __maybe_unused = dev->private;
1579 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1583 if (board->reg_type != ni_reg_611x)
1586 /* Check if there's a single sample stuck in the FIFO */
1587 if (ni_readb(XXX_Status) & 0x80) {
1588 dl = ni_readl(ADC_FIFO_Data_611x);
1589 data = (dl & 0xffff);
1590 cfc_write_to_buffer(s, data);
1594 static void get_last_sample_6143(struct comedi_device *dev)
1596 const struct ni_board_struct *board = comedi_board(dev);
1597 struct ni_private *devpriv __maybe_unused = dev->private;
1598 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1602 if (board->reg_type != ni_reg_6143)
1605 /* Check if there's a single sample stuck in the FIFO */
1606 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1607 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1608 dl = ni_readl(AIFIFO_Data_6143);
1610 /* This may get the hi/lo data in the wrong order */
1611 data = (dl >> 16) & 0xffff;
1612 cfc_write_to_buffer(s, data);
1616 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1617 void *data, unsigned int num_bytes,
1618 unsigned int chan_index)
1620 struct ni_private *devpriv = dev->private;
1621 struct comedi_async *async = s->async;
1623 unsigned int length = num_bytes / bytes_per_sample(s);
1624 short *array = data;
1625 unsigned int *larray = data;
1627 for (i = 0; i < length; i++) {
1629 if (s->subdev_flags & SDF_LSAMPL)
1630 larray[i] = le32_to_cpu(larray[i]);
1632 array[i] = le16_to_cpu(array[i]);
1634 if (s->subdev_flags & SDF_LSAMPL)
1635 larray[i] += devpriv->ai_offset[chan_index];
1637 array[i] += devpriv->ai_offset[chan_index];
1639 chan_index %= async->cmd.chanlist_len;
1645 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1647 const struct ni_board_struct *board = comedi_board(dev);
1648 struct ni_private *devpriv = dev->private;
1649 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1651 unsigned long flags;
1653 retval = ni_request_ai_mite_channel(dev);
1656 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1658 /* write alloc the entire buffer */
1659 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1661 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1662 if (devpriv->ai_mite_chan == NULL) {
1663 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1667 switch (board->reg_type) {
1670 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1673 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1676 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1680 mite_dma_arm(devpriv->ai_mite_chan);
1681 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1686 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1688 const struct ni_board_struct *board = comedi_board(dev);
1689 struct ni_private *devpriv = dev->private;
1690 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1692 unsigned long flags;
1694 retval = ni_request_ao_mite_channel(dev);
1698 /* read alloc the entire buffer */
1699 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1701 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1702 if (devpriv->ao_mite_chan) {
1703 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1704 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1706 /* doing 32 instead of 16 bit wide transfers from memory
1707 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1708 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1710 mite_dma_arm(devpriv->ao_mite_chan);
1713 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1721 used for both cancel ioctl and board initialization
1723 this is pretty harsh for a cancel, but it works...
1726 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1728 const struct ni_board_struct *board = comedi_board(dev);
1729 struct ni_private *devpriv = dev->private;
1731 ni_release_ai_mite_channel(dev);
1732 /* ai configuration */
1733 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1734 Joint_Reset_Register);
1736 ni_set_bits(dev, Interrupt_A_Enable_Register,
1737 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1738 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1739 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1740 AI_FIFO_Interrupt_Enable, 0);
1742 ni_clear_ai_fifo(dev);
1744 if (board->reg_type != ni_reg_6143)
1745 ni_writeb(0, Misc_Command);
1747 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1748 devpriv->stc_writew(dev,
1749 AI_Start_Stop | AI_Mode_1_Reserved
1750 /*| AI_Trigger_Once */ ,
1751 AI_Mode_1_Register);
1752 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1753 /* generate FIFO interrupts on non-empty */
1754 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1755 if (board->reg_type == ni_reg_611x) {
1756 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1758 AI_LOCALMUX_CLK_Pulse_Width,
1759 AI_Personal_Register);
1760 devpriv->stc_writew(dev,
1761 AI_SCAN_IN_PROG_Output_Select(3) |
1762 AI_EXTMUX_CLK_Output_Select(0) |
1763 AI_LOCALMUX_CLK_Output_Select(2) |
1764 AI_SC_TC_Output_Select(3) |
1765 AI_CONVERT_Output_Select
1766 (AI_CONVERT_Output_Enable_High),
1767 AI_Output_Control_Register);
1768 } else if (board->reg_type == ni_reg_6143) {
1769 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1771 AI_LOCALMUX_CLK_Pulse_Width,
1772 AI_Personal_Register);
1773 devpriv->stc_writew(dev,
1774 AI_SCAN_IN_PROG_Output_Select(3) |
1775 AI_EXTMUX_CLK_Output_Select(0) |
1776 AI_LOCALMUX_CLK_Output_Select(2) |
1777 AI_SC_TC_Output_Select(3) |
1778 AI_CONVERT_Output_Select
1779 (AI_CONVERT_Output_Enable_Low),
1780 AI_Output_Control_Register);
1782 unsigned ai_output_control_bits;
1783 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1785 AI_CONVERT_Pulse_Width |
1786 AI_LOCALMUX_CLK_Pulse_Width,
1787 AI_Personal_Register);
1788 ai_output_control_bits =
1789 AI_SCAN_IN_PROG_Output_Select(3) |
1790 AI_EXTMUX_CLK_Output_Select(0) |
1791 AI_LOCALMUX_CLK_Output_Select(2) |
1792 AI_SC_TC_Output_Select(3);
1793 if (board->reg_type == ni_reg_622x)
1794 ai_output_control_bits |=
1795 AI_CONVERT_Output_Select
1796 (AI_CONVERT_Output_Enable_High);
1798 ai_output_control_bits |=
1799 AI_CONVERT_Output_Select
1800 (AI_CONVERT_Output_Enable_Low);
1801 devpriv->stc_writew(dev, ai_output_control_bits,
1802 AI_Output_Control_Register);
1804 /* the following registers should not be changed, because there
1805 * are no backup registers in devpriv. If you want to change
1806 * any of these, add a backup register and other appropriate code:
1807 * AI_Mode_1_Register
1808 * AI_Mode_3_Register
1809 * AI_Personal_Register
1810 * AI_Output_Control_Register
1812 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1814 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1819 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1821 unsigned long flags;
1824 /* lock to avoid race with interrupt handler */
1825 spin_lock_irqsave(&dev->spinlock, flags);
1827 ni_handle_fifo_dregs(dev);
1829 ni_sync_ai_dma(dev);
1831 count = s->async->buf_write_count - s->async->buf_read_count;
1832 spin_unlock_irqrestore(&dev->spinlock, flags);
1837 static int ni_ai_insn_read(struct comedi_device *dev,
1838 struct comedi_subdevice *s, struct comedi_insn *insn,
1841 const struct ni_board_struct *board = comedi_board(dev);
1842 struct ni_private *devpriv = dev->private;
1844 const unsigned int mask = (1 << board->adbits) - 1;
1849 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1851 ni_clear_ai_fifo(dev);
1853 signbits = devpriv->ai_offset[0];
1854 if (board->reg_type == ni_reg_611x) {
1855 for (n = 0; n < num_adc_stages_611x; n++) {
1856 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1857 AI_Command_1_Register);
1860 for (n = 0; n < insn->n; n++) {
1861 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1862 AI_Command_1_Register);
1863 /* The 611x has screwy 32-bit FIFOs. */
1865 for (i = 0; i < NI_TIMEOUT; i++) {
1866 if (ni_readb(XXX_Status) & 0x80) {
1867 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1871 if (!(devpriv->stc_readw(dev,
1872 AI_Status_1_Register) &
1873 AI_FIFO_Empty_St)) {
1874 d = ni_readl(ADC_FIFO_Data_611x) &
1879 if (i == NI_TIMEOUT) {
1881 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1887 } else if (board->reg_type == ni_reg_6143) {
1888 for (n = 0; n < insn->n; n++) {
1889 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1890 AI_Command_1_Register);
1892 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1894 for (i = 0; i < NI_TIMEOUT; i++) {
1895 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1896 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1897 dl = ni_readl(AIFIFO_Data_6143);
1901 if (i == NI_TIMEOUT) {
1903 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1906 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1909 for (n = 0; n < insn->n; n++) {
1910 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1911 AI_Command_1_Register);
1912 for (i = 0; i < NI_TIMEOUT; i++) {
1913 if (!(devpriv->stc_readw(dev,
1914 AI_Status_1_Register) &
1918 if (i == NI_TIMEOUT) {
1920 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1923 if (board->reg_type & ni_reg_m_series_mask) {
1925 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1927 d = ni_readw(ADC_FIFO_Data_Register);
1928 d += signbits; /* subtle: needs to be short addition */
1936 static void ni_prime_channelgain_list(struct comedi_device *dev)
1938 struct ni_private *devpriv = dev->private;
1941 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1942 for (i = 0; i < NI_TIMEOUT; ++i) {
1943 if (!(devpriv->stc_readw(dev,
1944 AI_Status_1_Register) &
1945 AI_FIFO_Empty_St)) {
1946 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1951 printk("ni_mio_common: timeout loading channel/gain list\n");
1954 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1955 unsigned int n_chan,
1958 const struct ni_board_struct *board = comedi_board(dev);
1959 struct ni_private *devpriv = dev->private;
1960 unsigned int chan, range, aref;
1963 unsigned int dither;
1964 unsigned range_code;
1966 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1968 /* offset = 1 << (board->adbits - 1); */
1969 if ((list[0] & CR_ALT_SOURCE)) {
1970 unsigned bypass_bits;
1971 chan = CR_CHAN(list[0]);
1972 range = CR_RANGE(list[0]);
1973 range_code = ni_gainlkup[board->gainlkup][range];
1974 dither = ((list[0] & CR_ALT_FILTER) != 0);
1975 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1976 bypass_bits |= chan;
1978 (devpriv->ai_calib_source) &
1979 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1980 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1981 MSeries_AI_Bypass_Mode_Mux_Mask |
1982 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1983 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1985 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1986 /* don't use 2's complement encoding */
1987 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1988 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1990 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1993 for (i = 0; i < n_chan; i++) {
1994 unsigned config_bits = 0;
1995 chan = CR_CHAN(list[i]);
1996 aref = CR_AREF(list[i]);
1997 range = CR_RANGE(list[i]);
1998 dither = ((list[i] & CR_ALT_FILTER) != 0);
2000 range_code = ni_gainlkup[board->gainlkup][range];
2001 devpriv->ai_offset[i] = offset;
2005 MSeries_AI_Config_Channel_Type_Differential_Bits;
2009 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2013 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2018 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2020 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2021 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2022 if (i == n_chan - 1)
2023 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2025 config_bits |= MSeries_AI_Config_Dither_Bit;
2026 /* don't use 2's complement encoding */
2027 config_bits |= MSeries_AI_Config_Polarity_Bit;
2028 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2030 ni_prime_channelgain_list(dev);
2034 * Notes on the 6110 and 6111:
2035 * These boards a slightly different than the rest of the series, since
2036 * they have multiple A/D converters.
2037 * From the driver side, the configuration memory is a
2039 * Configuration Memory Low:
2041 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2042 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2043 * 1001 gain=0.1 (+/- 50)
2052 * Configuration Memory High:
2053 * bits 12-14: Channel Type
2054 * 001 for differential
2055 * 000 for calibration
2056 * bit 11: coupling (this is not currently handled)
2060 * valid channels are 0-3
2062 static void ni_load_channelgain_list(struct comedi_device *dev,
2063 unsigned int n_chan, unsigned int *list)
2065 const struct ni_board_struct *board = comedi_board(dev);
2066 struct ni_private *devpriv = dev->private;
2067 unsigned int chan, range, aref;
2069 unsigned int hi, lo;
2071 unsigned int dither;
2073 if (board->reg_type & ni_reg_m_series_mask) {
2074 ni_m_series_load_channelgain_list(dev, n_chan, list);
2077 if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2078 && (board->reg_type != ni_reg_6143)) {
2079 if (devpriv->changain_state
2080 && devpriv->changain_spec == list[0]) {
2084 devpriv->changain_state = 1;
2085 devpriv->changain_spec = list[0];
2087 devpriv->changain_state = 0;
2090 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2092 /* Set up Calibration mode if required */
2093 if (board->reg_type == ni_reg_6143) {
2094 if ((list[0] & CR_ALT_SOURCE)
2095 && !devpriv->ai_calib_source_enabled) {
2096 /* Strobe Relay enable bit */
2097 ni_writew(devpriv->ai_calib_source |
2098 Calibration_Channel_6143_RelayOn,
2099 Calibration_Channel_6143);
2100 ni_writew(devpriv->ai_calib_source,
2101 Calibration_Channel_6143);
2102 devpriv->ai_calib_source_enabled = 1;
2103 msleep_interruptible(100); /* Allow relays to change */
2104 } else if (!(list[0] & CR_ALT_SOURCE)
2105 && devpriv->ai_calib_source_enabled) {
2106 /* Strobe Relay disable bit */
2107 ni_writew(devpriv->ai_calib_source |
2108 Calibration_Channel_6143_RelayOff,
2109 Calibration_Channel_6143);
2110 ni_writew(devpriv->ai_calib_source,
2111 Calibration_Channel_6143);
2112 devpriv->ai_calib_source_enabled = 0;
2113 msleep_interruptible(100); /* Allow relays to change */
2117 offset = 1 << (board->adbits - 1);
2118 for (i = 0; i < n_chan; i++) {
2119 if ((board->reg_type != ni_reg_6143)
2120 && (list[i] & CR_ALT_SOURCE)) {
2121 chan = devpriv->ai_calib_source;
2123 chan = CR_CHAN(list[i]);
2125 aref = CR_AREF(list[i]);
2126 range = CR_RANGE(list[i]);
2127 dither = ((list[i] & CR_ALT_FILTER) != 0);
2129 /* fix the external/internal range differences */
2130 range = ni_gainlkup[board->gainlkup][range];
2131 if (board->reg_type == ni_reg_611x)
2132 devpriv->ai_offset[i] = offset;
2134 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2137 if ((list[i] & CR_ALT_SOURCE)) {
2138 if (board->reg_type == ni_reg_611x)
2139 ni_writew(CR_CHAN(list[i]) & 0x0003,
2140 Calibration_Channel_Select_611x);
2142 if (board->reg_type == ni_reg_611x)
2144 else if (board->reg_type == ni_reg_6143)
2148 hi |= AI_DIFFERENTIAL;
2160 hi |= AI_CONFIG_CHANNEL(chan);
2162 ni_writew(hi, Configuration_Memory_High);
2164 if (board->reg_type != ni_reg_6143) {
2166 if (i == n_chan - 1)
2167 lo |= AI_LAST_CHANNEL;
2171 ni_writew(lo, Configuration_Memory_Low);
2175 /* prime the channel/gain list */
2176 if ((board->reg_type != ni_reg_611x)
2177 && (board->reg_type != ni_reg_6143)) {
2178 ni_prime_channelgain_list(dev);
2182 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2185 struct ni_private *devpriv = dev->private;
2188 switch (round_mode) {
2189 case TRIG_ROUND_NEAREST:
2191 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2193 case TRIG_ROUND_DOWN:
2194 divider = (nanosec) / devpriv->clock_ns;
2197 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2203 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2205 struct ni_private *devpriv = dev->private;
2207 return devpriv->clock_ns * (timer + 1);
2210 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2211 unsigned num_channels)
2213 const struct ni_board_struct *board = comedi_board(dev);
2215 switch (board->reg_type) {
2218 /* simultaneously-sampled inputs */
2219 return board->ai_speed;
2222 /* multiplexed inputs */
2225 return board->ai_speed * num_channels;
2228 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2229 struct comedi_cmd *cmd)
2231 const struct ni_board_struct *board = comedi_board(dev);
2232 struct ni_private *devpriv = dev->private;
2235 unsigned int sources;
2237 /* Step 1 : check if triggers are trivially valid */
2239 if ((cmd->flags & CMDF_WRITE))
2240 cmd->flags &= ~CMDF_WRITE;
2242 err |= cfc_check_trigger_src(&cmd->start_src,
2243 TRIG_NOW | TRIG_INT | TRIG_EXT);
2244 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2245 TRIG_TIMER | TRIG_EXT);
2247 sources = TRIG_TIMER | TRIG_EXT;
2248 if (board->reg_type == ni_reg_611x ||
2249 board->reg_type == ni_reg_6143)
2250 sources |= TRIG_NOW;
2251 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2253 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2254 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2259 /* Step 2a : make sure trigger sources are unique */
2261 err |= cfc_check_trigger_is_unique(cmd->start_src);
2262 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2263 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2264 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2266 /* Step 2b : and mutually compatible */
2271 /* Step 3: check if arguments are trivially valid */
2273 if (cmd->start_src == TRIG_EXT) {
2274 /* external trigger */
2275 unsigned int tmp = CR_CHAN(cmd->start_arg);
2279 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2280 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2282 /* true for both TRIG_NOW and TRIG_INT */
2283 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2286 if (cmd->scan_begin_src == TRIG_TIMER) {
2287 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2288 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2289 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2290 devpriv->clock_ns * 0xffffff);
2291 } else if (cmd->scan_begin_src == TRIG_EXT) {
2292 /* external trigger */
2293 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2297 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2298 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2299 } else { /* TRIG_OTHER */
2300 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2303 if (cmd->convert_src == TRIG_TIMER) {
2304 if ((board->reg_type == ni_reg_611x)
2305 || (board->reg_type == ni_reg_6143)) {
2306 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2308 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2310 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2311 devpriv->clock_ns * 0xffff);
2313 } else if (cmd->convert_src == TRIG_EXT) {
2314 /* external trigger */
2315 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2319 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2320 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2321 } else if (cmd->convert_src == TRIG_NOW) {
2322 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2325 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2327 if (cmd->stop_src == TRIG_COUNT) {
2328 unsigned int max_count = 0x01000000;
2330 if (board->reg_type == ni_reg_611x)
2331 max_count -= num_adc_stages_611x;
2332 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2333 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2336 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2342 /* step 4: fix up any arguments */
2344 if (cmd->scan_begin_src == TRIG_TIMER) {
2345 tmp = cmd->scan_begin_arg;
2346 cmd->scan_begin_arg =
2347 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2348 cmd->scan_begin_arg,
2352 if (tmp != cmd->scan_begin_arg)
2355 if (cmd->convert_src == TRIG_TIMER) {
2356 if ((board->reg_type != ni_reg_611x)
2357 && (board->reg_type != ni_reg_6143)) {
2358 tmp = cmd->convert_arg;
2360 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2365 if (tmp != cmd->convert_arg)
2367 if (cmd->scan_begin_src == TRIG_TIMER &&
2368 cmd->scan_begin_arg <
2369 cmd->convert_arg * cmd->scan_end_arg) {
2370 cmd->scan_begin_arg =
2371 cmd->convert_arg * cmd->scan_end_arg;
2383 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2385 const struct ni_board_struct *board = comedi_board(dev);
2386 struct ni_private *devpriv = dev->private;
2387 const struct comedi_cmd *cmd = &s->async->cmd;
2389 int mode1 = 0; /* mode1 is needed for both stop and convert */
2391 int start_stop_select = 0;
2392 unsigned int stop_count;
2393 int interrupt_a_enable = 0;
2395 MDPRINTK("ni_ai_cmd\n");
2396 if (dev->irq == 0) {
2397 comedi_error(dev, "cannot run command without an irq");
2400 ni_clear_ai_fifo(dev);
2402 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2404 /* start configuration */
2405 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2407 /* disable analog triggering for now, since it
2408 * interferes with the use of pfi0 */
2409 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2410 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2411 Analog_Trigger_Etc_Register);
2413 switch (cmd->start_src) {
2416 devpriv->stc_writew(dev, AI_START2_Select(0) |
2417 AI_START1_Sync | AI_START1_Edge |
2418 AI_START1_Select(0),
2419 AI_Trigger_Select_Register);
2423 int chan = CR_CHAN(cmd->start_arg);
2424 unsigned int bits = AI_START2_Select(0) |
2425 AI_START1_Sync | AI_START1_Select(chan + 1);
2427 if (cmd->start_arg & CR_INVERT)
2428 bits |= AI_START1_Polarity;
2429 if (cmd->start_arg & CR_EDGE)
2430 bits |= AI_START1_Edge;
2431 devpriv->stc_writew(dev, bits,
2432 AI_Trigger_Select_Register);
2437 mode2 &= ~AI_Pre_Trigger;
2438 mode2 &= ~AI_SC_Initial_Load_Source;
2439 mode2 &= ~AI_SC_Reload_Mode;
2440 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2442 if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2443 || (board->reg_type == ni_reg_6143)) {
2444 start_stop_select |= AI_STOP_Polarity;
2445 start_stop_select |= AI_STOP_Select(31); /* logic low */
2446 start_stop_select |= AI_STOP_Sync;
2448 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2450 devpriv->stc_writew(dev, start_stop_select,
2451 AI_START_STOP_Select_Register);
2453 devpriv->ai_cmd2 = 0;
2454 switch (cmd->stop_src) {
2456 stop_count = cmd->stop_arg - 1;
2458 if (board->reg_type == ni_reg_611x) {
2459 /* have to take 3 stage adc pipeline into account */
2460 stop_count += num_adc_stages_611x;
2462 /* stage number of scans */
2463 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2465 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2466 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2467 /* load SC (Scan Count) */
2468 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2470 devpriv->ai_continuous = 0;
2471 if (stop_count == 0) {
2472 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2473 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2474 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2475 if (cmd->chanlist_len > 1)
2476 start_stop_select |=
2477 AI_STOP_Polarity | AI_STOP_Edge;
2481 /* stage number of scans */
2482 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2484 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2485 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2487 /* load SC (Scan Count) */
2488 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2490 devpriv->ai_continuous = 1;
2495 switch (cmd->scan_begin_src) {
2498 stop bits for non 611x boards
2499 AI_SI_Special_Trigger_Delay=0
2501 AI_START_STOP_Select_Register:
2502 AI_START_Polarity=0 (?) rising edge
2503 AI_START_Edge=1 edge triggered
2505 AI_START_Select=0 SI_TC
2506 AI_STOP_Polarity=0 rising edge
2507 AI_STOP_Edge=0 level
2509 AI_STOP_Select=19 external pin (configuration mem)
2511 start_stop_select |= AI_START_Edge | AI_START_Sync;
2512 devpriv->stc_writew(dev, start_stop_select,
2513 AI_START_STOP_Select_Register);
2515 mode2 |= AI_SI_Reload_Mode(0);
2516 /* AI_SI_Initial_Load_Source=A */
2517 mode2 &= ~AI_SI_Initial_Load_Source;
2518 /* mode2 |= AI_SC_Reload_Mode; */
2519 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2522 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2523 TRIG_ROUND_NEAREST);
2524 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2525 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2528 if (cmd->scan_begin_arg & CR_EDGE)
2529 start_stop_select |= AI_START_Edge;
2530 /* AI_START_Polarity==1 is falling edge */
2531 if (cmd->scan_begin_arg & CR_INVERT)
2532 start_stop_select |= AI_START_Polarity;
2533 if (cmd->scan_begin_src != cmd->convert_src ||
2534 (cmd->scan_begin_arg & ~CR_EDGE) !=
2535 (cmd->convert_arg & ~CR_EDGE))
2536 start_stop_select |= AI_START_Sync;
2537 start_stop_select |=
2538 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2539 devpriv->stc_writew(dev, start_stop_select,
2540 AI_START_STOP_Select_Register);
2544 switch (cmd->convert_src) {
2547 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2550 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2551 TRIG_ROUND_NEAREST);
2552 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2553 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2555 /* AI_SI2_Reload_Mode = alternate */
2556 /* AI_SI2_Initial_Load_Source = A */
2557 mode2 &= ~AI_SI2_Initial_Load_Source;
2558 mode2 |= AI_SI2_Reload_Mode;
2559 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2562 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2564 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2565 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2567 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2570 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2571 if ((cmd->convert_arg & CR_INVERT) == 0)
2572 mode1 |= AI_CONVERT_Source_Polarity;
2573 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2575 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2576 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2583 /* interrupt on FIFO, errors, SC_TC */
2584 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2585 AI_SC_TC_Interrupt_Enable;
2588 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2591 if (cmd->flags & TRIG_WAKE_EOS
2592 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2593 /* wake on end-of-scan */
2594 devpriv->aimode = AIMODE_SCAN;
2596 devpriv->aimode = AIMODE_HALF_FULL;
2599 switch (devpriv->aimode) {
2600 case AIMODE_HALF_FULL:
2601 /*generate FIFO interrupts and DMA requests on half-full */
2603 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2604 AI_Mode_3_Register);
2606 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2607 AI_Mode_3_Register);
2611 /*generate FIFO interrupts on non-empty */
2612 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2613 AI_Mode_3_Register);
2617 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2618 AI_Mode_3_Register);
2620 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2621 AI_Mode_3_Register);
2623 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2629 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2631 ni_set_bits(dev, Interrupt_A_Enable_Register,
2632 interrupt_a_enable, 1);
2634 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2635 devpriv->int_a_enable_reg);
2637 /* interrupt on nothing */
2638 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2640 /* XXX start polling if necessary */
2641 MDPRINTK("interrupting on nothing\n");
2644 /* end configuration */
2645 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2647 switch (cmd->scan_begin_src) {
2649 devpriv->stc_writew(dev,
2650 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2651 AI_SC_Arm, AI_Command_1_Register);
2654 /* XXX AI_SI_Arm? */
2655 devpriv->stc_writew(dev,
2656 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2657 AI_SC_Arm, AI_Command_1_Register);
2663 int retval = ni_ai_setup_MITE_dma(dev);
2667 /* mite_dump_regs(devpriv->mite); */
2670 switch (cmd->start_src) {
2672 /* AI_START1_Pulse */
2673 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2674 AI_Command_2_Register);
2675 s->async->inttrig = NULL;
2678 s->async->inttrig = NULL;
2681 s->async->inttrig = &ni_ai_inttrig;
2685 MDPRINTK("exit ni_ai_cmd\n");
2690 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2691 unsigned int trignum)
2693 struct ni_private *devpriv = dev->private;
2698 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2699 AI_Command_2_Register);
2700 s->async->inttrig = NULL;
2705 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2706 struct comedi_subdevice *s,
2707 struct comedi_insn *insn,
2708 unsigned int *data);
2710 static int ni_ai_insn_config(struct comedi_device *dev,
2711 struct comedi_subdevice *s,
2712 struct comedi_insn *insn, unsigned int *data)
2714 const struct ni_board_struct *board = comedi_board(dev);
2715 struct ni_private *devpriv = dev->private;
2721 case INSN_CONFIG_ANALOG_TRIG:
2722 return ni_ai_config_analog_trig(dev, s, insn, data);
2723 case INSN_CONFIG_ALT_SOURCE:
2724 if (board->reg_type & ni_reg_m_series_mask) {
2725 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2726 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2727 MSeries_AI_Bypass_Mode_Mux_Mask |
2728 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2731 devpriv->ai_calib_source = data[1];
2732 } else if (board->reg_type == ni_reg_6143) {
2733 unsigned int calib_source;
2735 calib_source = data[1] & 0xf;
2737 if (calib_source > 0xF)
2740 devpriv->ai_calib_source = calib_source;
2741 ni_writew(calib_source, Calibration_Channel_6143);
2743 unsigned int calib_source;
2744 unsigned int calib_source_adjust;
2746 calib_source = data[1] & 0xf;
2747 calib_source_adjust = (data[1] >> 4) & 0xff;
2749 if (calib_source >= 8)
2751 devpriv->ai_calib_source = calib_source;
2752 if (board->reg_type == ni_reg_611x) {
2753 ni_writeb(calib_source_adjust,
2754 Cal_Gain_Select_611x);
2765 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2766 struct comedi_subdevice *s,
2767 struct comedi_insn *insn,
2770 const struct ni_board_struct *board = comedi_board(dev);
2771 struct ni_private *devpriv = dev->private;
2772 unsigned int a, b, modebits;
2776 * data[2] is analog line
2777 * data[3] is set level
2778 * data[4] is reset level */
2779 if (!board->has_analog_trig)
2781 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2782 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2785 if (data[2] >= board->n_adchan) {
2786 data[2] = board->n_adchan - 1;
2789 if (data[3] > 255) { /* a */
2793 if (data[4] > 255) { /* b */
2804 * high mode 00 00 01 10
2805 * low mode 00 00 10 01
2807 * hysteresis low mode 10 00 00 01
2808 * hysteresis high mode 01 00 00 10
2809 * middle mode 10 01 01 10
2814 modebits = data[1] & 0xff;
2815 if (modebits & 0xf0) {
2816 /* two level mode */
2822 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2824 devpriv->atrig_low = a;
2825 devpriv->atrig_high = b;
2827 case 0x81: /* low hysteresis mode */
2828 devpriv->atrig_mode = 6;
2830 case 0x42: /* high hysteresis mode */
2831 devpriv->atrig_mode = 3;
2833 case 0x96: /* middle window mode */
2834 devpriv->atrig_mode = 2;
2841 /* one level mode */
2847 case 0x06: /* high window mode */
2848 devpriv->atrig_high = a;
2849 devpriv->atrig_mode = 0;
2851 case 0x09: /* low window mode */
2852 devpriv->atrig_low = a;
2853 devpriv->atrig_mode = 1;
2865 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2866 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2867 void *data, unsigned int num_bytes,
2868 unsigned int chan_index)
2870 const struct ni_board_struct *board = comedi_board(dev);
2871 struct comedi_async *async = s->async;
2874 unsigned int offset;
2875 unsigned int length = num_bytes / sizeof(short);
2876 short *array = data;
2878 offset = 1 << (board->aobits - 1);
2879 for (i = 0; i < length; i++) {
2880 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2881 if (board->ao_unipolar == 0 || (range & 1) == 0)
2884 array[i] = cpu_to_le16(array[i]);
2887 chan_index %= async->cmd.chanlist_len;
2891 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2892 struct comedi_subdevice *s,
2893 unsigned int chanspec[],
2894 unsigned int n_chans, int timed)
2896 const struct ni_board_struct *board = comedi_board(dev);
2897 struct ni_private *devpriv = dev->private;
2905 for (i = 0; i < board->n_aochan; ++i) {
2906 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2907 ni_writeb(devpriv->ao_conf[i],
2908 M_Offset_AO_Config_Bank(i));
2909 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2912 for (i = 0; i < n_chans; i++) {
2913 const struct comedi_krange *krange;
2914 chan = CR_CHAN(chanspec[i]);
2915 range = CR_RANGE(chanspec[i]);
2916 krange = s->range_table->range + range;
2919 switch (krange->max - krange->min) {
2921 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2922 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2925 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2926 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2929 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2930 ni_writeb(MSeries_Attenuate_x5_Bit,
2931 M_Offset_AO_Reference_Attenuation(chan));
2934 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2935 ni_writeb(MSeries_Attenuate_x5_Bit,
2936 M_Offset_AO_Reference_Attenuation(chan));
2939 printk("%s: bug! unhandled ao reference voltage\n",
2943 switch (krange->max + krange->min) {
2945 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2948 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2951 printk("%s: bug! unhandled ao offset voltage\n",
2956 conf |= MSeries_AO_Update_Timed_Bit;
2957 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2958 devpriv->ao_conf[chan] = conf;
2959 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2964 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2965 struct comedi_subdevice *s,
2966 unsigned int chanspec[],
2967 unsigned int n_chans)
2969 const struct ni_board_struct *board = comedi_board(dev);
2970 struct ni_private *devpriv = dev->private;
2977 for (i = 0; i < n_chans; i++) {
2978 chan = CR_CHAN(chanspec[i]);
2979 range = CR_RANGE(chanspec[i]);
2980 conf = AO_Channel(chan);
2982 if (board->ao_unipolar) {
2983 if ((range & 1) == 0) {
2985 invert = (1 << (board->aobits - 1));
2993 invert = (1 << (board->aobits - 1));
2996 /* not all boards can deglitch, but this shouldn't hurt */
2997 if (chanspec[i] & CR_DEGLITCH)
2998 conf |= AO_Deglitch;
3000 /* analog reference */
3001 /* AREF_OTHER connects AO ground to AI ground, i think */
3002 conf |= (CR_AREF(chanspec[i]) ==
3003 AREF_OTHER) ? AO_Ground_Ref : 0;
3005 ni_writew(conf, AO_Configuration);
3006 devpriv->ao_conf[chan] = conf;
3011 static int ni_ao_config_chanlist(struct comedi_device *dev,
3012 struct comedi_subdevice *s,
3013 unsigned int chanspec[], unsigned int n_chans,
3016 const struct ni_board_struct *board = comedi_board(dev);
3018 if (board->reg_type & ni_reg_m_series_mask)
3019 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3022 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3025 static int ni_ao_insn_read(struct comedi_device *dev,
3026 struct comedi_subdevice *s, struct comedi_insn *insn,
3029 struct ni_private *devpriv = dev->private;
3031 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3036 static int ni_ao_insn_write(struct comedi_device *dev,
3037 struct comedi_subdevice *s,
3038 struct comedi_insn *insn, unsigned int *data)
3040 const struct ni_board_struct *board = comedi_board(dev);
3041 struct ni_private *devpriv = dev->private;
3042 unsigned int chan = CR_CHAN(insn->chanspec);
3043 unsigned int invert;
3045 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3047 devpriv->ao[chan] = data[0];
3049 if (board->reg_type & ni_reg_m_series_mask) {
3050 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3052 ni_writew(data[0] ^ invert,
3053 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3058 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3059 struct comedi_subdevice *s,
3060 struct comedi_insn *insn, unsigned int *data)
3062 const struct ni_board_struct *board = comedi_board(dev);
3063 struct ni_private *devpriv = dev->private;
3064 unsigned int chan = CR_CHAN(insn->chanspec);
3065 unsigned int invert;
3067 ao_win_out(1 << chan, AO_Immediate_671x);
3068 invert = 1 << (board->aobits - 1);
3070 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3072 devpriv->ao[chan] = data[0];
3073 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3078 static int ni_ao_insn_config(struct comedi_device *dev,
3079 struct comedi_subdevice *s,
3080 struct comedi_insn *insn, unsigned int *data)
3082 const struct ni_board_struct *board = comedi_board(dev);
3083 struct ni_private *devpriv = dev->private;
3086 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3089 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3091 data[2] += devpriv->mite->fifo_size;
3108 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3109 unsigned int trignum)
3111 const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3112 struct ni_private *devpriv = dev->private;
3114 int interrupt_b_bits;
3116 static const int timeout = 1000;
3121 /* Null trig at beginning prevent ao start trigger from executing more than
3122 once per command (and doing things like trying to allocate the ao dma channel
3124 s->async->inttrig = NULL;
3126 ni_set_bits(dev, Interrupt_B_Enable_Register,
3127 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3128 interrupt_b_bits = AO_Error_Interrupt_Enable;
3130 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3131 if (board->reg_type & ni_reg_6xxx_mask)
3132 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3133 ret = ni_ao_setup_MITE_dma(dev);
3136 ret = ni_ao_wait_for_dma_load(dev);
3140 ret = ni_ao_prep_fifo(dev, s);
3144 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3147 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3148 AO_Mode_3_Register);
3149 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3150 /* wait for DACs to be loaded */
3151 for (i = 0; i < timeout; i++) {
3153 if ((devpriv->stc_readw(dev,
3154 Joint_Status_2_Register) &
3155 AO_TMRDACWRs_In_Progress_St) == 0)
3160 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3163 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3164 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3165 Interrupt_B_Ack_Register);
3167 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3169 devpriv->stc_writew(dev,
3170 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3171 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3172 AO_Command_1_Register);
3174 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3175 AO_Command_2_Register);
3180 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3182 const struct ni_board_struct *board = comedi_board(dev);
3183 struct ni_private *devpriv = dev->private;
3184 const struct comedi_cmd *cmd = &s->async->cmd;
3189 if (dev->irq == 0) {
3190 comedi_error(dev, "cannot run command without an irq");
3194 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3196 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3198 if (board->reg_type & ni_reg_6xxx_mask) {
3199 ao_win_out(CLEAR_WG, AO_Misc_611x);
3202 for (i = 0; i < cmd->chanlist_len; i++) {
3205 chan = CR_CHAN(cmd->chanlist[i]);
3207 ao_win_out(chan, AO_Waveform_Generation_611x);
3209 ao_win_out(bits, AO_Timed_611x);
3212 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3214 if (cmd->stop_src == TRIG_NONE) {
3215 devpriv->ao_mode1 |= AO_Continuous;
3216 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3218 devpriv->ao_mode1 &= ~AO_Continuous;
3219 devpriv->ao_mode1 |= AO_Trigger_Once;
3221 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3222 switch (cmd->start_src) {
3225 devpriv->ao_trigger_select &=
3226 ~(AO_START1_Polarity | AO_START1_Select(-1));
3227 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3228 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3229 AO_Trigger_Select_Register);
3232 devpriv->ao_trigger_select =
3233 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3234 if (cmd->start_arg & CR_INVERT)
3235 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3236 if (cmd->start_arg & CR_EDGE)
3237 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3238 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3239 AO_Trigger_Select_Register);
3245 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3246 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3248 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3249 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3250 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3251 if (cmd->stop_src == TRIG_NONE) {
3252 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3254 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3256 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3257 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3258 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3259 switch (cmd->stop_src) {
3261 if (board->reg_type & ni_reg_m_series_mask) {
3262 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3263 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3264 AO_UC_Load_A_Register);
3265 devpriv->stc_writew(dev, AO_UC_Load,
3266 AO_Command_1_Register);
3268 devpriv->stc_writel(dev, cmd->stop_arg,
3269 AO_UC_Load_A_Register);
3270 devpriv->stc_writew(dev, AO_UC_Load,
3271 AO_Command_1_Register);
3272 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3273 AO_UC_Load_A_Register);
3277 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3278 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3279 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3282 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3283 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3284 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3287 devpriv->ao_mode1 &=
3288 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3289 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3290 switch (cmd->scan_begin_src) {
3292 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3294 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3295 TRIG_ROUND_NEAREST);
3296 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3297 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3298 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3301 devpriv->ao_mode1 |=
3302 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3303 if (cmd->scan_begin_arg & CR_INVERT)
3304 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3305 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3311 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3312 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3313 devpriv->ao_mode2 &=
3314 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3315 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3317 if (cmd->scan_end_arg > 1) {
3318 devpriv->ao_mode1 |= AO_Multiple_Channels;
3319 devpriv->stc_writew(dev,
3320 AO_Number_Of_Channels(cmd->scan_end_arg -
3322 AO_UPDATE_Output_Select
3323 (AO_Update_Output_High_Z),
3324 AO_Output_Control_Register);
3327 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3328 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3329 if (board->reg_type &
3330 (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3331 bits |= AO_Number_Of_Channels(0);
3334 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3336 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3338 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3340 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3341 AO_Command_1_Register);
3343 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3344 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3346 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3348 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3350 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3352 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3353 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3355 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3356 AO_TMRDACWR_Pulse_Width;
3357 if (board->ao_fifo_depth)
3358 bits |= AO_FIFO_Enable;
3360 bits |= AO_DMA_PIO_Control;
3362 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3363 verified with bus analyzer. */
3364 if (board->reg_type & ni_reg_m_series_mask)
3365 bits |= AO_Number_Of_DAC_Packages;
3367 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3368 /* enable sending of ao dma requests */
3369 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3371 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3373 if (cmd->stop_src == TRIG_COUNT) {
3374 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3375 Interrupt_B_Ack_Register);
3376 ni_set_bits(dev, Interrupt_B_Enable_Register,
3377 AO_BC_TC_Interrupt_Enable, 1);
3380 s->async->inttrig = &ni_ao_inttrig;
3385 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3386 struct comedi_cmd *cmd)
3388 const struct ni_board_struct *board = comedi_board(dev);
3389 struct ni_private *devpriv = dev->private;
3393 /* Step 1 : check if triggers are trivially valid */
3395 if ((cmd->flags & CMDF_WRITE) == 0)
3396 cmd->flags |= CMDF_WRITE;
3398 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3399 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3400 TRIG_TIMER | TRIG_EXT);
3401 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3402 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3403 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3408 /* Step 2a : make sure trigger sources are unique */
3410 err |= cfc_check_trigger_is_unique(cmd->start_src);
3411 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3412 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3414 /* Step 2b : and mutually compatible */
3419 /* Step 3: check if arguments are trivially valid */
3421 if (cmd->start_src == TRIG_EXT) {
3422 /* external trigger */
3423 unsigned int tmp = CR_CHAN(cmd->start_arg);
3427 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3428 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3430 /* true for both TRIG_NOW and TRIG_INT */
3431 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3434 if (cmd->scan_begin_src == TRIG_TIMER) {
3435 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3437 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3438 devpriv->clock_ns * 0xffffff);
3441 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3442 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3444 if (cmd->stop_src == TRIG_COUNT)
3445 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3446 else /* TRIG_NONE */
3447 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3452 /* step 4: fix up any arguments */
3453 if (cmd->scan_begin_src == TRIG_TIMER) {
3454 tmp = cmd->scan_begin_arg;
3455 cmd->scan_begin_arg =
3456 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3457 cmd->scan_begin_arg,
3461 if (tmp != cmd->scan_begin_arg)
3467 /* step 5: fix up chanlist */
3475 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3477 const struct ni_board_struct *board = comedi_board(dev);
3478 struct ni_private *devpriv = dev->private;
3480 /* devpriv->ao0p=0x0000; */
3481 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3483 /* devpriv->ao1p=AO_Channel(1); */
3484 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3486 ni_release_ao_mite_channel(dev);
3488 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3489 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3490 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3491 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3492 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3493 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3494 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3495 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3496 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3497 devpriv->ao_cmd1 = 0;
3498 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3499 devpriv->ao_cmd2 = 0;
3500 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3501 devpriv->ao_mode1 = 0;
3502 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3503 devpriv->ao_mode2 = 0;
3504 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3505 if (board->reg_type & ni_reg_m_series_mask)
3506 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3508 devpriv->ao_mode3 = 0;
3509 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3510 devpriv->ao_trigger_select = 0;
3511 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3512 AO_Trigger_Select_Register);
3513 if (board->reg_type & ni_reg_6xxx_mask) {
3514 unsigned immediate_bits = 0;
3516 for (i = 0; i < s->n_chan; ++i) {
3517 immediate_bits |= 1 << i;
3519 ao_win_out(immediate_bits, AO_Immediate_671x);
3520 ao_win_out(CLEAR_WG, AO_Misc_611x);
3522 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3529 static int ni_dio_insn_config(struct comedi_device *dev,
3530 struct comedi_subdevice *s,
3531 struct comedi_insn *insn,
3534 struct ni_private *devpriv = dev->private;
3537 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3541 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3542 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3543 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3548 static int ni_dio_insn_bits(struct comedi_device *dev,
3549 struct comedi_subdevice *s,
3550 struct comedi_insn *insn, unsigned int *data)
3552 struct ni_private *devpriv = dev->private;
3555 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3559 /* Perform check to make sure we're not using the
3560 serial part of the dio */
3561 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3562 && devpriv->serial_interval_ns)
3565 s->state &= ~data[0];
3566 s->state |= (data[0] & data[1]);
3567 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3568 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3569 devpriv->stc_writew(dev, devpriv->dio_output,
3570 DIO_Output_Register);
3572 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3577 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3578 struct comedi_subdevice *s,
3579 struct comedi_insn *insn,
3582 struct ni_private *devpriv __maybe_unused = dev->private;
3585 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3589 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3594 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3595 struct comedi_subdevice *s,
3596 struct comedi_insn *insn,
3599 struct ni_private *devpriv __maybe_unused = dev->private;
3602 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3607 s->state &= ~data[0];
3608 s->state |= (data[0] & data[1]);
3609 ni_writel(s->state, M_Offset_Static_Digital_Output);
3611 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3616 static int ni_cdio_cmdtest(struct comedi_device *dev,
3617 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3623 /* Step 1 : check if triggers are trivially valid */
3625 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3626 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3627 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3628 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3629 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3634 /* Step 2a : make sure trigger sources are unique */
3635 /* Step 2b : and mutually compatible */
3640 /* Step 3: check if arguments are trivially valid */
3642 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3644 tmp = cmd->scan_begin_arg;
3645 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3646 if (tmp != cmd->scan_begin_arg)
3649 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3650 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3651 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3656 /* step 4: fix up any arguments */
3661 /* step 5: check chanlist */
3663 for (i = 0; i < cmd->chanlist_len; ++i) {
3664 if (cmd->chanlist[i] != i)
3674 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3676 struct ni_private *devpriv __maybe_unused = dev->private;
3677 const struct comedi_cmd *cmd = &s->async->cmd;
3678 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3681 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3682 switch (cmd->scan_begin_src) {
3685 CR_CHAN(cmd->scan_begin_arg) &
3686 CDO_Sample_Source_Select_Mask;
3692 if (cmd->scan_begin_arg & CR_INVERT)
3693 cdo_mode_bits |= CDO_Polarity_Bit;
3694 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3696 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3697 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3698 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3701 "attempted to run digital output command with no lines configured as outputs");
3704 retval = ni_request_cdo_mite_channel(dev);
3708 s->async->inttrig = &ni_cdo_inttrig;
3712 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3713 unsigned int trignum)
3716 struct ni_private *devpriv = dev->private;
3717 unsigned long flags;
3721 const unsigned timeout = 1000;
3723 s->async->inttrig = NULL;
3725 /* read alloc the entire buffer */
3726 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3729 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3730 if (devpriv->cdo_mite_chan) {
3731 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3732 mite_dma_arm(devpriv->cdo_mite_chan);
3734 comedi_error(dev, "BUG: no cdo mite channel?");
3737 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3742 * XXX not sure what interrupt C group does
3743 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3744 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3746 for (i = 0; i < timeout; ++i) {
3747 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3752 comedi_error(dev, "dma failed to fill cdo fifo!");
3753 ni_cdio_cancel(dev, s);
3756 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3757 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3758 M_Offset_CDIO_Command);
3762 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3764 struct ni_private *devpriv __maybe_unused = dev->private;
3766 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3767 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3768 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3769 M_Offset_CDIO_Command);
3771 * XXX not sure what interrupt C group does ni_writeb(0,
3772 * M_Offset_Interrupt_C_Enable);
3774 ni_writel(0, M_Offset_CDO_Mask_Enable);
3775 ni_release_cdo_mite_channel(dev);
3779 static void handle_cdio_interrupt(struct comedi_device *dev)
3781 const struct ni_board_struct *board = comedi_board(dev);
3782 struct ni_private *devpriv __maybe_unused = dev->private;
3783 unsigned cdio_status;
3784 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3786 unsigned long flags;
3789 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3793 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3794 if (devpriv->cdo_mite_chan) {
3795 unsigned cdo_mite_status =
3796 mite_get_status(devpriv->cdo_mite_chan);
3797 if (cdo_mite_status & CHSR_LINKC) {
3799 devpriv->mite->mite_io_addr +
3800 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3802 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3804 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3807 cdio_status = ni_readl(M_Offset_CDIO_Status);
3808 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3809 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3810 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3811 s->async->events |= COMEDI_CB_OVERFLOW;
3813 if (cdio_status & CDO_FIFO_Empty_Bit) {
3814 /* printk("cdio fifo empty\n"); */
3815 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3816 M_Offset_CDIO_Command);
3817 /* s->async->events |= COMEDI_CB_EOA; */
3822 static int ni_serial_insn_config(struct comedi_device *dev,
3823 struct comedi_subdevice *s,
3824 struct comedi_insn *insn, unsigned int *data)
3826 struct ni_private *devpriv = dev->private;
3828 unsigned char byte_out, byte_in = 0;
3834 case INSN_CONFIG_SERIAL_CLOCK:
3837 printk("SPI serial clock Config cd\n", data[1]);
3839 devpriv->serial_hw_mode = 1;
3840 devpriv->dio_control |= DIO_HW_Serial_Enable;
3842 if (data[1] == SERIAL_DISABLED) {
3843 devpriv->serial_hw_mode = 0;
3844 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3845 DIO_Software_Serial_Control);
3846 data[1] = SERIAL_DISABLED;
3847 devpriv->serial_interval_ns = data[1];
3848 } else if (data[1] <= SERIAL_600NS) {
3849 /* Warning: this clock speed is too fast to reliably
3851 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3852 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3853 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3854 data[1] = SERIAL_600NS;
3855 devpriv->serial_interval_ns = data[1];
3856 } else if (data[1] <= SERIAL_1_2US) {
3857 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3858 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3859 DIO_Serial_Out_Divide_By_2;
3860 data[1] = SERIAL_1_2US;
3861 devpriv->serial_interval_ns = data[1];
3862 } else if (data[1] <= SERIAL_10US) {
3863 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3864 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3865 DIO_Serial_Out_Divide_By_2;
3866 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3867 600ns/1.2us. If you turn divide_by_2 off with the
3868 slow clock, you will still get 10us, except then
3869 all your delays are wrong. */
3870 data[1] = SERIAL_10US;
3871 devpriv->serial_interval_ns = data[1];
3873 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3874 DIO_Software_Serial_Control);
3875 devpriv->serial_hw_mode = 0;
3876 data[1] = (data[1] / 1000) * 1000;
3877 devpriv->serial_interval_ns = data[1];
3880 devpriv->stc_writew(dev, devpriv->dio_control,
3881 DIO_Control_Register);
3882 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3883 Clock_and_FOUT_Register);
3888 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3890 if (devpriv->serial_interval_ns == 0) {
3894 byte_out = data[1] & 0xFF;
3896 if (devpriv->serial_hw_mode) {
3897 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3899 } else if (devpriv->serial_interval_ns > 0) {
3900 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3903 printk("ni_serial_insn_config: serial disabled!\n");
3908 data[1] = byte_in & 0xFF;
3918 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3919 struct comedi_subdevice *s,
3920 unsigned char data_out,
3921 unsigned char *data_in)
3923 struct ni_private *devpriv = dev->private;
3924 unsigned int status1;
3925 int err = 0, count = 20;
3928 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3931 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3932 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3933 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3935 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3936 if (status1 & DIO_Serial_IO_In_Progress_St) {
3941 devpriv->dio_control |= DIO_HW_Serial_Start;
3942 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3943 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3945 /* Wait until STC says we're done, but don't loop infinitely. */
3947 devpriv->stc_readw(dev,
3948 Joint_Status_1_Register)) &
3949 DIO_Serial_IO_In_Progress_St) {
3950 /* Delay one bit per loop */
3951 udelay((devpriv->serial_interval_ns + 999) / 1000);
3954 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3960 /* Delay for last bit. This delay is absolutely necessary, because
3961 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3962 udelay((devpriv->serial_interval_ns + 999) / 1000);
3964 if (data_in != NULL) {
3965 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3967 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3972 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3977 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3978 struct comedi_subdevice *s,
3979 unsigned char data_out,
3980 unsigned char *data_in)
3982 struct ni_private *devpriv = dev->private;
3983 unsigned char mask, input = 0;
3986 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3989 /* Wait for one bit before transfer */
3990 udelay((devpriv->serial_interval_ns + 999) / 1000);
3992 for (mask = 0x80; mask; mask >>= 1) {
3993 /* Output current bit; note that we cannot touch s->state
3994 because it is a per-subdevice field, and serial is
3995 a separate subdevice from DIO. */
3996 devpriv->dio_output &= ~DIO_SDOUT;
3997 if (data_out & mask) {
3998 devpriv->dio_output |= DIO_SDOUT;
4000 devpriv->stc_writew(dev, devpriv->dio_output,
4001 DIO_Output_Register);
4003 /* Assert SDCLK (active low, inverted), wait for half of
4004 the delay, deassert SDCLK, and wait for the other half. */
4005 devpriv->dio_control |= DIO_Software_Serial_Control;
4006 devpriv->stc_writew(dev, devpriv->dio_control,
4007 DIO_Control_Register);
4009 udelay((devpriv->serial_interval_ns + 999) / 2000);
4011 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4012 devpriv->stc_writew(dev, devpriv->dio_control,
4013 DIO_Control_Register);
4015 udelay((devpriv->serial_interval_ns + 999) / 2000);
4017 /* Input current bit */
4018 if (devpriv->stc_readw(dev,
4019 DIO_Parallel_Input_Register) & DIO_SDIN)
4021 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4026 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4034 static void mio_common_detach(struct comedi_device *dev)
4036 struct ni_private *devpriv = dev->private;
4039 if (devpriv->counter_dev) {
4040 ni_gpct_device_destroy(devpriv->counter_dev);
4045 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4049 for (i = 0; i < s->n_chan; i++) {
4050 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4051 AO_Configuration_2_67xx);
4053 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4056 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4058 unsigned stc_register;
4060 case NITIO_G0_Autoincrement_Reg:
4061 stc_register = G_Autoincrement_Register(0);
4063 case NITIO_G1_Autoincrement_Reg:
4064 stc_register = G_Autoincrement_Register(1);
4066 case NITIO_G0_Command_Reg:
4067 stc_register = G_Command_Register(0);
4069 case NITIO_G1_Command_Reg:
4070 stc_register = G_Command_Register(1);
4072 case NITIO_G0_HW_Save_Reg:
4073 stc_register = G_HW_Save_Register(0);
4075 case NITIO_G1_HW_Save_Reg:
4076 stc_register = G_HW_Save_Register(1);
4078 case NITIO_G0_SW_Save_Reg:
4079 stc_register = G_Save_Register(0);
4081 case NITIO_G1_SW_Save_Reg:
4082 stc_register = G_Save_Register(1);
4084 case NITIO_G0_Mode_Reg:
4085 stc_register = G_Mode_Register(0);
4087 case NITIO_G1_Mode_Reg:
4088 stc_register = G_Mode_Register(1);
4090 case NITIO_G0_LoadA_Reg:
4091 stc_register = G_Load_A_Register(0);
4093 case NITIO_G1_LoadA_Reg:
4094 stc_register = G_Load_A_Register(1);
4096 case NITIO_G0_LoadB_Reg:
4097 stc_register = G_Load_B_Register(0);
4099 case NITIO_G1_LoadB_Reg:
4100 stc_register = G_Load_B_Register(1);
4102 case NITIO_G0_Input_Select_Reg:
4103 stc_register = G_Input_Select_Register(0);
4105 case NITIO_G1_Input_Select_Reg:
4106 stc_register = G_Input_Select_Register(1);
4108 case NITIO_G01_Status_Reg:
4109 stc_register = G_Status_Register;
4111 case NITIO_G01_Joint_Reset_Reg:
4112 stc_register = Joint_Reset_Register;
4114 case NITIO_G01_Joint_Status1_Reg:
4115 stc_register = Joint_Status_1_Register;
4117 case NITIO_G01_Joint_Status2_Reg:
4118 stc_register = Joint_Status_2_Register;
4120 case NITIO_G0_Interrupt_Acknowledge_Reg:
4121 stc_register = Interrupt_A_Ack_Register;
4123 case NITIO_G1_Interrupt_Acknowledge_Reg:
4124 stc_register = Interrupt_B_Ack_Register;
4126 case NITIO_G0_Status_Reg:
4127 stc_register = AI_Status_1_Register;
4129 case NITIO_G1_Status_Reg:
4130 stc_register = AO_Status_1_Register;
4132 case NITIO_G0_Interrupt_Enable_Reg:
4133 stc_register = Interrupt_A_Enable_Register;
4135 case NITIO_G1_Interrupt_Enable_Reg:
4136 stc_register = Interrupt_B_Enable_Register;
4139 printk("%s: unhandled register 0x%x in switch.\n",
4145 return stc_register;
4148 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4149 enum ni_gpct_register reg)
4151 struct comedi_device *dev = counter->counter_dev->dev;
4152 struct ni_private *devpriv = dev->private;
4153 unsigned stc_register;
4154 /* bits in the join reset register which are relevant to counters */
4155 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4156 static const unsigned gpct_interrupt_a_enable_mask =
4157 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4158 static const unsigned gpct_interrupt_b_enable_mask =
4159 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4162 /* m-series-only registers */
4163 case NITIO_G0_Counting_Mode_Reg:
4164 ni_writew(bits, M_Offset_G0_Counting_Mode);
4166 case NITIO_G1_Counting_Mode_Reg:
4167 ni_writew(bits, M_Offset_G1_Counting_Mode);
4169 case NITIO_G0_Second_Gate_Reg:
4170 ni_writew(bits, M_Offset_G0_Second_Gate);
4172 case NITIO_G1_Second_Gate_Reg:
4173 ni_writew(bits, M_Offset_G1_Second_Gate);
4175 case NITIO_G0_DMA_Config_Reg:
4176 ni_writew(bits, M_Offset_G0_DMA_Config);
4178 case NITIO_G1_DMA_Config_Reg:
4179 ni_writew(bits, M_Offset_G1_DMA_Config);
4181 case NITIO_G0_ABZ_Reg:
4182 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4184 case NITIO_G1_ABZ_Reg:
4185 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4188 /* 32 bit registers */
4189 case NITIO_G0_LoadA_Reg:
4190 case NITIO_G1_LoadA_Reg:
4191 case NITIO_G0_LoadB_Reg:
4192 case NITIO_G1_LoadB_Reg:
4193 stc_register = ni_gpct_to_stc_register(reg);
4194 devpriv->stc_writel(dev, bits, stc_register);
4197 /* 16 bit registers */
4198 case NITIO_G0_Interrupt_Enable_Reg:
4199 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4200 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4201 gpct_interrupt_a_enable_mask, bits);
4203 case NITIO_G1_Interrupt_Enable_Reg:
4204 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4205 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4206 gpct_interrupt_b_enable_mask, bits);
4208 case NITIO_G01_Joint_Reset_Reg:
4209 BUG_ON(bits & ~gpct_joint_reset_mask);
4212 stc_register = ni_gpct_to_stc_register(reg);
4213 devpriv->stc_writew(dev, bits, stc_register);
4217 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4218 enum ni_gpct_register reg)
4220 struct comedi_device *dev = counter->counter_dev->dev;
4221 struct ni_private *devpriv = dev->private;
4222 unsigned stc_register;
4225 /* m-series only registers */
4226 case NITIO_G0_DMA_Status_Reg:
4227 return ni_readw(M_Offset_G0_DMA_Status);
4229 case NITIO_G1_DMA_Status_Reg:
4230 return ni_readw(M_Offset_G1_DMA_Status);
4233 /* 32 bit registers */
4234 case NITIO_G0_HW_Save_Reg:
4235 case NITIO_G1_HW_Save_Reg:
4236 case NITIO_G0_SW_Save_Reg:
4237 case NITIO_G1_SW_Save_Reg:
4238 stc_register = ni_gpct_to_stc_register(reg);
4239 return devpriv->stc_readl(dev, stc_register);
4242 /* 16 bit registers */
4244 stc_register = ni_gpct_to_stc_register(reg);
4245 return devpriv->stc_readw(dev, stc_register);
4251 static int ni_freq_out_insn_read(struct comedi_device *dev,
4252 struct comedi_subdevice *s,
4253 struct comedi_insn *insn, unsigned int *data)
4255 struct ni_private *devpriv = dev->private;
4257 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4261 static int ni_freq_out_insn_write(struct comedi_device *dev,
4262 struct comedi_subdevice *s,
4263 struct comedi_insn *insn, unsigned int *data)
4265 struct ni_private *devpriv = dev->private;
4267 devpriv->clock_and_fout &= ~FOUT_Enable;
4268 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4269 Clock_and_FOUT_Register);
4270 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4271 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4272 devpriv->clock_and_fout |= FOUT_Enable;
4273 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4274 Clock_and_FOUT_Register);
4278 static int ni_set_freq_out_clock(struct comedi_device *dev,
4279 unsigned int clock_source)
4281 struct ni_private *devpriv = dev->private;
4283 switch (clock_source) {
4284 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4285 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4287 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4288 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4293 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4294 Clock_and_FOUT_Register);
4298 static void ni_get_freq_out_clock(struct comedi_device *dev,
4299 unsigned int *clock_source,
4300 unsigned int *clock_period_ns)
4302 struct ni_private *devpriv = dev->private;
4304 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4305 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4306 *clock_period_ns = TIMEBASE_2_NS;
4308 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4309 *clock_period_ns = TIMEBASE_1_NS * 2;
4313 static int ni_freq_out_insn_config(struct comedi_device *dev,
4314 struct comedi_subdevice *s,
4315 struct comedi_insn *insn, unsigned int *data)
4318 case INSN_CONFIG_SET_CLOCK_SRC:
4319 return ni_set_freq_out_clock(dev, data[1]);
4321 case INSN_CONFIG_GET_CLOCK_SRC:
4322 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4330 static int ni_alloc_private(struct comedi_device *dev)
4332 struct ni_private *devpriv;
4334 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
4338 spin_lock_init(&devpriv->window_lock);
4339 spin_lock_init(&devpriv->soft_reg_copy_lock);
4340 spin_lock_init(&devpriv->mite_channel_lock);
4345 static int ni_E_init(struct comedi_device *dev)
4347 const struct ni_board_struct *board = comedi_board(dev);
4348 struct ni_private *devpriv = dev->private;
4349 struct comedi_subdevice *s;
4351 enum ni_gpct_variant counter_variant;
4354 if (board->n_aochan > MAX_N_AO_CHAN) {
4355 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4359 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4363 /* analog input subdevice */
4365 s = &dev->subdevices[NI_AI_SUBDEV];
4366 dev->read_subdev = s;
4367 if (board->n_adchan) {
4368 s->type = COMEDI_SUBD_AI;
4370 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4371 if (board->reg_type != ni_reg_611x)
4372 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4373 if (board->adbits > 16)
4374 s->subdev_flags |= SDF_LSAMPL;
4375 if (board->reg_type & ni_reg_m_series_mask)
4376 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4377 s->n_chan = board->n_adchan;
4378 s->len_chanlist = 512;
4379 s->maxdata = (1 << board->adbits) - 1;
4380 s->range_table = ni_range_lkup[board->gainlkup];
4381 s->insn_read = &ni_ai_insn_read;
4382 s->insn_config = &ni_ai_insn_config;
4383 s->do_cmdtest = &ni_ai_cmdtest;
4384 s->do_cmd = &ni_ai_cmd;
4385 s->cancel = &ni_ai_reset;
4386 s->poll = &ni_ai_poll;
4387 s->munge = &ni_ai_munge;
4389 s->async_dma_dir = DMA_FROM_DEVICE;
4392 s->type = COMEDI_SUBD_UNUSED;
4395 /* analog output subdevice */
4397 s = &dev->subdevices[NI_AO_SUBDEV];
4398 if (board->n_aochan) {
4399 s->type = COMEDI_SUBD_AO;
4400 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4401 if (board->reg_type & ni_reg_m_series_mask)
4402 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4403 s->n_chan = board->n_aochan;
4404 s->maxdata = (1 << board->aobits) - 1;
4405 s->range_table = board->ao_range_table;
4406 s->insn_read = &ni_ao_insn_read;
4407 if (board->reg_type & ni_reg_6xxx_mask) {
4408 s->insn_write = &ni_ao_insn_write_671x;
4410 s->insn_write = &ni_ao_insn_write;
4412 s->insn_config = &ni_ao_insn_config;
4414 if (board->n_aochan) {
4415 s->async_dma_dir = DMA_TO_DEVICE;
4417 if (board->ao_fifo_depth) {
4419 dev->write_subdev = s;
4420 s->subdev_flags |= SDF_CMD_WRITE;
4421 s->do_cmd = &ni_ao_cmd;
4422 s->do_cmdtest = &ni_ao_cmdtest;
4423 s->len_chanlist = board->n_aochan;
4424 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4425 s->munge = ni_ao_munge;
4427 s->cancel = &ni_ao_reset;
4429 s->type = COMEDI_SUBD_UNUSED;
4431 if ((board->reg_type & ni_reg_67xx_mask))
4432 init_ao_67xx(dev, s);
4434 /* digital i/o subdevice */
4436 s = &dev->subdevices[NI_DIO_SUBDEV];
4437 s->type = COMEDI_SUBD_DIO;
4438 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4440 s->io_bits = 0; /* all bits input */
4441 s->range_table = &range_digital;
4442 s->n_chan = board->num_p0_dio_channels;
4443 if (board->reg_type & ni_reg_m_series_mask) {
4445 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4446 s->insn_bits = &ni_m_series_dio_insn_bits;
4447 s->insn_config = &ni_m_series_dio_insn_config;
4448 s->do_cmd = &ni_cdio_cmd;
4449 s->do_cmdtest = &ni_cdio_cmdtest;
4450 s->cancel = &ni_cdio_cancel;
4451 s->async_dma_dir = DMA_BIDIRECTIONAL;
4452 s->len_chanlist = s->n_chan;
4454 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4455 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4457 s->insn_bits = &ni_dio_insn_bits;
4458 s->insn_config = &ni_dio_insn_config;
4459 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4460 ni_writew(devpriv->dio_control, DIO_Control_Register);
4464 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4465 if (board->has_8255) {
4466 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4468 s->type = COMEDI_SUBD_UNUSED;
4471 /* formerly general purpose counter/timer device, but no longer used */
4472 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4473 s->type = COMEDI_SUBD_UNUSED;
4475 /* calibration subdevice -- ai and ao */
4476 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4477 s->type = COMEDI_SUBD_CALIB;
4478 if (board->reg_type & ni_reg_m_series_mask) {
4479 /* internal PWM analog output used for AI nonlinearity calibration */
4480 s->subdev_flags = SDF_INTERNAL;
4481 s->insn_config = &ni_m_series_pwm_config;
4484 ni_writel(0x0, M_Offset_Cal_PWM);
4485 } else if (board->reg_type == ni_reg_6143) {
4486 /* internal PWM analog output used for AI nonlinearity calibration */
4487 s->subdev_flags = SDF_INTERNAL;
4488 s->insn_config = &ni_6143_pwm_config;
4492 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4493 s->insn_read = &ni_calib_insn_read;
4494 s->insn_write = &ni_calib_insn_write;
4495 caldac_setup(dev, s);
4499 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4500 s->type = COMEDI_SUBD_MEMORY;
4501 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4503 if (board->reg_type & ni_reg_m_series_mask) {
4504 s->n_chan = M_SERIES_EEPROM_SIZE;
4505 s->insn_read = &ni_m_series_eeprom_insn_read;
4508 s->insn_read = &ni_eeprom_insn_read;
4512 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4513 s->type = COMEDI_SUBD_DIO;
4514 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4515 if (board->reg_type & ni_reg_m_series_mask) {
4518 ni_writew(s->state, M_Offset_PFI_DO);
4519 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4520 ni_writew(devpriv->pfi_output_select_reg[i],
4521 M_Offset_PFI_Output_Select(i + 1));
4527 if (board->reg_type & ni_reg_m_series_mask) {
4528 s->insn_bits = &ni_pfi_insn_bits;
4530 s->insn_config = &ni_pfi_insn_config;
4531 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4533 /* cs5529 calibration adc */
4534 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4535 if (board->reg_type & ni_reg_67xx_mask) {
4536 s->type = COMEDI_SUBD_AI;
4537 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4538 /* one channel for each analog output channel */
4539 s->n_chan = board->n_aochan;
4540 s->maxdata = (1 << 16) - 1;
4541 s->range_table = &range_unknown; /* XXX */
4542 s->insn_read = cs5529_ai_insn_read;
4543 s->insn_config = NULL;
4546 s->type = COMEDI_SUBD_UNUSED;
4550 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4551 s->type = COMEDI_SUBD_SERIAL;
4552 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4555 s->insn_config = ni_serial_insn_config;
4556 devpriv->serial_interval_ns = 0;
4557 devpriv->serial_hw_mode = 0;
4560 s = &dev->subdevices[NI_RTSI_SUBDEV];
4561 s->type = COMEDI_SUBD_DIO;
4562 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4565 s->insn_bits = ni_rtsi_insn_bits;
4566 s->insn_config = ni_rtsi_insn_config;
4569 if (board->reg_type & ni_reg_m_series_mask) {
4570 counter_variant = ni_gpct_variant_m_series;
4572 counter_variant = ni_gpct_variant_e_series;
4574 devpriv->counter_dev = ni_gpct_device_construct(dev,
4575 &ni_gpct_write_register,
4576 &ni_gpct_read_register,
4579 /* General purpose counters */
4580 for (j = 0; j < NUM_GPCT; ++j) {
4581 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4582 s->type = COMEDI_SUBD_COUNTER;
4583 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4585 if (board->reg_type & ni_reg_m_series_mask)
4586 s->maxdata = 0xffffffff;
4588 s->maxdata = 0xffffff;
4589 s->insn_read = &ni_gpct_insn_read;
4590 s->insn_write = &ni_gpct_insn_write;
4591 s->insn_config = &ni_gpct_insn_config;
4593 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4594 s->do_cmd = &ni_gpct_cmd;
4595 s->len_chanlist = 1;
4596 s->do_cmdtest = &ni_gpct_cmdtest;
4597 s->cancel = &ni_gpct_cancel;
4598 s->async_dma_dir = DMA_BIDIRECTIONAL;
4600 s->private = &devpriv->counter_dev->counters[j];
4602 devpriv->counter_dev->counters[j].chip_index = 0;
4603 devpriv->counter_dev->counters[j].counter_index = j;
4604 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4607 /* Frequency output */
4608 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4609 s->type = COMEDI_SUBD_COUNTER;
4610 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4613 s->insn_read = &ni_freq_out_insn_read;
4614 s->insn_write = &ni_freq_out_insn_write;
4615 s->insn_config = &ni_freq_out_insn_config;
4617 /* ai configuration */
4618 s = &dev->subdevices[NI_AI_SUBDEV];
4619 ni_ai_reset(dev, s);
4620 if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4621 /* BEAM is this needed for PCI-6143 ?? */
4622 devpriv->clock_and_fout =
4623 Slow_Internal_Time_Divide_By_2 |
4624 Slow_Internal_Timebase |
4625 Clock_To_Board_Divide_By_2 |
4627 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4629 devpriv->clock_and_fout =
4630 Slow_Internal_Time_Divide_By_2 |
4631 Slow_Internal_Timebase |
4632 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4634 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4635 Clock_and_FOUT_Register);
4637 /* analog output configuration */
4638 s = &dev->subdevices[NI_AO_SUBDEV];
4639 ni_ao_reset(dev, s);
4642 devpriv->stc_writew(dev,
4643 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4644 0) | (Interrupt_Output_On_3_Pins & 0) |
4645 Interrupt_A_Enable | Interrupt_B_Enable |
4646 Interrupt_A_Output_Select(interrupt_pin
4648 Interrupt_B_Output_Select(interrupt_pin
4650 Interrupt_Control_Register);
4654 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4655 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4657 if (board->reg_type & ni_reg_6xxx_mask) {
4658 ni_writeb(0, Magic_611x);
4659 } else if (board->reg_type & ni_reg_m_series_mask) {
4661 for (channel = 0; channel < board->n_aochan; ++channel) {
4662 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4664 M_Offset_AO_Reference_Attenuation(channel));
4666 ni_writeb(0x0, M_Offset_AO_Calibration);
4673 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4675 struct comedi_device *dev = (struct comedi_device *)arg;
4676 struct ni_private *devpriv __maybe_unused = dev->private;
4679 ni_writeb(data, Port_A + 2 * port);
4682 return ni_readb(Port_A + 2 * port);
4687 presents the EEPROM as a subdevice
4690 static int ni_eeprom_insn_read(struct comedi_device *dev,
4691 struct comedi_subdevice *s,
4692 struct comedi_insn *insn, unsigned int *data)
4694 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4700 reads bytes out of eeprom
4703 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4705 struct ni_private *devpriv __maybe_unused = dev->private;
4709 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4710 ni_writeb(0x04, Serial_Command);
4711 for (bit = 0x8000; bit; bit >>= 1) {
4712 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4714 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4718 for (bit = 0x80; bit; bit >>= 1) {
4719 ni_writeb(0x04, Serial_Command);
4720 ni_writeb(0x05, Serial_Command);
4721 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4723 ni_writeb(0x00, Serial_Command);
4728 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4729 struct comedi_subdevice *s,
4730 struct comedi_insn *insn,
4733 struct ni_private *devpriv = dev->private;
4735 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4740 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4742 struct ni_private *devpriv = dev->private;
4744 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4745 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4749 static int ni_m_series_pwm_config(struct comedi_device *dev,
4750 struct comedi_subdevice *s,
4751 struct comedi_insn *insn, unsigned int *data)
4753 struct ni_private *devpriv = dev->private;
4754 unsigned up_count, down_count;
4757 case INSN_CONFIG_PWM_OUTPUT:
4759 case TRIG_ROUND_NEAREST:
4762 devpriv->clock_ns / 2) / devpriv->clock_ns;
4764 case TRIG_ROUND_DOWN:
4765 up_count = data[2] / devpriv->clock_ns;
4769 (data[2] + devpriv->clock_ns -
4770 1) / devpriv->clock_ns;
4777 case TRIG_ROUND_NEAREST:
4780 devpriv->clock_ns / 2) / devpriv->clock_ns;
4782 case TRIG_ROUND_DOWN:
4783 down_count = data[4] / devpriv->clock_ns;
4787 (data[4] + devpriv->clock_ns -
4788 1) / devpriv->clock_ns;
4794 if (up_count * devpriv->clock_ns != data[2] ||
4795 down_count * devpriv->clock_ns != data[4]) {
4796 data[2] = up_count * devpriv->clock_ns;
4797 data[4] = down_count * devpriv->clock_ns;
4800 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4801 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4803 devpriv->pwm_up_count = up_count;
4804 devpriv->pwm_down_count = down_count;
4807 case INSN_CONFIG_GET_PWM_OUTPUT:
4808 return ni_get_pwm_config(dev, data);
4817 static int ni_6143_pwm_config(struct comedi_device *dev,
4818 struct comedi_subdevice *s,
4819 struct comedi_insn *insn, unsigned int *data)
4821 struct ni_private *devpriv = dev->private;
4822 unsigned up_count, down_count;
4825 case INSN_CONFIG_PWM_OUTPUT:
4827 case TRIG_ROUND_NEAREST:
4830 devpriv->clock_ns / 2) / devpriv->clock_ns;
4832 case TRIG_ROUND_DOWN:
4833 up_count = data[2] / devpriv->clock_ns;
4837 (data[2] + devpriv->clock_ns -
4838 1) / devpriv->clock_ns;
4845 case TRIG_ROUND_NEAREST:
4848 devpriv->clock_ns / 2) / devpriv->clock_ns;
4850 case TRIG_ROUND_DOWN:
4851 down_count = data[4] / devpriv->clock_ns;
4855 (data[4] + devpriv->clock_ns -
4856 1) / devpriv->clock_ns;
4862 if (up_count * devpriv->clock_ns != data[2] ||
4863 down_count * devpriv->clock_ns != data[4]) {
4864 data[2] = up_count * devpriv->clock_ns;
4865 data[4] = down_count * devpriv->clock_ns;
4868 ni_writel(up_count, Calibration_HighTime_6143);
4869 devpriv->pwm_up_count = up_count;
4870 ni_writel(down_count, Calibration_LowTime_6143);
4871 devpriv->pwm_down_count = down_count;
4874 case INSN_CONFIG_GET_PWM_OUTPUT:
4875 return ni_get_pwm_config(dev, data);
4883 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4885 calibration subdevice
4887 static int ni_calib_insn_write(struct comedi_device *dev,
4888 struct comedi_subdevice *s,
4889 struct comedi_insn *insn, unsigned int *data)
4891 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4896 static int ni_calib_insn_read(struct comedi_device *dev,
4897 struct comedi_subdevice *s,
4898 struct comedi_insn *insn, unsigned int *data)
4900 struct ni_private *devpriv = dev->private;
4902 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4907 static int pack_mb88341(int addr, int val, int *bitstring);
4908 static int pack_dac8800(int addr, int val, int *bitstring);
4909 static int pack_dac8043(int addr, int val, int *bitstring);
4910 static int pack_ad8522(int addr, int val, int *bitstring);
4911 static int pack_ad8804(int addr, int val, int *bitstring);
4912 static int pack_ad8842(int addr, int val, int *bitstring);
4914 struct caldac_struct {
4917 int (*packbits) (int, int, int *);
4920 static struct caldac_struct caldacs[] = {
4921 [mb88341] = {12, 8, pack_mb88341},
4922 [dac8800] = {8, 8, pack_dac8800},
4923 [dac8043] = {1, 12, pack_dac8043},
4924 [ad8522] = {2, 12, pack_ad8522},
4925 [ad8804] = {12, 8, pack_ad8804},
4926 [ad8842] = {8, 8, pack_ad8842},
4927 [ad8804_debug] = {16, 8, pack_ad8804},
4930 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4932 const struct ni_board_struct *board = comedi_board(dev);
4933 struct ni_private *devpriv = dev->private;
4942 type = board->caldac[0];
4943 if (type == caldac_none)
4945 n_bits = caldacs[type].n_bits;
4946 for (i = 0; i < 3; i++) {
4947 type = board->caldac[i];
4948 if (type == caldac_none)
4950 if (caldacs[type].n_bits != n_bits)
4952 n_chans += caldacs[type].n_chans;
4955 s->n_chan = n_chans;
4958 unsigned int *maxdata_list;
4960 if (n_chans > MAX_N_CALDACS) {
4961 printk("BUG! MAX_N_CALDACS too small\n");
4963 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4965 for (i = 0; i < n_dacs; i++) {
4966 type = board->caldac[i];
4967 for (j = 0; j < caldacs[type].n_chans; j++) {
4968 maxdata_list[chan] =
4969 (1 << caldacs[type].n_bits) - 1;
4974 for (chan = 0; chan < s->n_chan; chan++)
4975 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4977 type = board->caldac[0];
4978 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4980 for (chan = 0; chan < s->n_chan; chan++)
4981 ni_write_caldac(dev, i, s->maxdata / 2);
4985 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4987 const struct ni_board_struct *board = comedi_board(dev);
4988 struct ni_private *devpriv = dev->private;
4989 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4993 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4994 if (devpriv->caldacs[addr] == val)
4996 devpriv->caldacs[addr] = val;
4998 for (i = 0; i < 3; i++) {
4999 type = board->caldac[i];
5000 if (type == caldac_none)
5002 if (addr < caldacs[type].n_chans) {
5003 bits = caldacs[type].packbits(addr, val, &bitstring);
5004 loadbit = SerDacLd(i);
5005 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5008 addr -= caldacs[type].n_chans;
5011 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5012 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5014 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5017 ni_writeb(loadbit, Serial_Command);
5019 ni_writeb(0, Serial_Command);
5022 static int pack_mb88341(int addr, int val, int *bitstring)
5026 Note that address bits are reversed. Thanks to
5027 Ingo Keen for noticing this.
5029 Note also that the 88341 expects address values from
5030 1-12, whereas we use channel numbers 0-11. The NI
5031 docs use 1-12, also, so be careful here.
5034 *bitstring = ((addr & 0x1) << 11) |
5035 ((addr & 0x2) << 9) |
5036 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5040 static int pack_dac8800(int addr, int val, int *bitstring)
5042 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5046 static int pack_dac8043(int addr, int val, int *bitstring)
5048 *bitstring = val & 0xfff;
5052 static int pack_ad8522(int addr, int val, int *bitstring)
5054 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5058 static int pack_ad8804(int addr, int val, int *bitstring)
5060 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5064 static int pack_ad8842(int addr, int val, int *bitstring)
5066 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5072 * Read the GPCTs current value.
5074 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5076 unsigned int hi1, hi2, lo;
5078 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5079 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5080 G_Command_Register(chan));
5082 devpriv->gpct_command[chan] |= G_Save_Trace;
5083 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5084 G_Command_Register(chan));
5086 /* This procedure is used because the two registers cannot
5087 * be read atomically. */
5089 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5090 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5091 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5092 } while (hi1 != hi2);
5094 return (hi1 << 16) | lo;
5097 static void GPCT_Reset(struct comedi_device *dev, int chan)
5099 int temp_ack_reg = 0;
5101 /* printk("GPCT_Reset..."); */
5102 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5106 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5107 ni_set_bits(dev, Interrupt_A_Enable_Register,
5108 G0_TC_Interrupt_Enable, 0);
5109 ni_set_bits(dev, Interrupt_A_Enable_Register,
5110 G0_Gate_Interrupt_Enable, 0);
5111 temp_ack_reg |= G0_Gate_Error_Confirm;
5112 temp_ack_reg |= G0_TC_Error_Confirm;
5113 temp_ack_reg |= G0_TC_Interrupt_Ack;
5114 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5115 devpriv->stc_writew(dev, temp_ack_reg,
5116 Interrupt_A_Ack_Register);
5118 /* problem...this interferes with the other ctr... */
5119 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5120 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5121 Analog_Trigger_Etc_Register);
5124 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5125 ni_set_bits(dev, Interrupt_B_Enable_Register,
5126 G1_TC_Interrupt_Enable, 0);
5127 ni_set_bits(dev, Interrupt_B_Enable_Register,
5128 G0_Gate_Interrupt_Enable, 0);
5129 temp_ack_reg |= G1_Gate_Error_Confirm;
5130 temp_ack_reg |= G1_TC_Error_Confirm;
5131 temp_ack_reg |= G1_TC_Interrupt_Ack;
5132 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5133 devpriv->stc_writew(dev, temp_ack_reg,
5134 Interrupt_B_Ack_Register);
5136 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5137 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5138 Analog_Trigger_Etc_Register);
5142 devpriv->gpct_mode[chan] = 0;
5143 devpriv->gpct_input_select[chan] = 0;
5144 devpriv->gpct_command[chan] = 0;
5146 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5148 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5149 G_Mode_Register(chan));
5150 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5151 G_Input_Select_Register(chan));
5152 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5154 /* printk("exit GPCT_Reset\n"); */
5159 static int ni_gpct_insn_config(struct comedi_device *dev,
5160 struct comedi_subdevice *s,
5161 struct comedi_insn *insn, unsigned int *data)
5163 struct ni_gpct *counter = s->private;
5164 return ni_tio_insn_config(counter, insn, data);
5167 static int ni_gpct_insn_read(struct comedi_device *dev,
5168 struct comedi_subdevice *s,
5169 struct comedi_insn *insn, unsigned int *data)
5171 struct ni_gpct *counter = s->private;
5172 return ni_tio_rinsn(counter, insn, data);
5175 static int ni_gpct_insn_write(struct comedi_device *dev,
5176 struct comedi_subdevice *s,
5177 struct comedi_insn *insn, unsigned int *data)
5179 struct ni_gpct *counter = s->private;
5180 return ni_tio_winsn(counter, insn, data);
5184 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5187 struct ni_gpct *counter = s->private;
5188 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5190 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5194 "no dma channel available for use by counter");
5197 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5198 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5199 retval = ni_tio_cmd(counter, s->async);
5205 static int ni_gpct_cmdtest(struct comedi_device *dev,
5206 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5208 struct ni_gpct *counter = s->private;
5210 return ni_tio_cmdtest(counter, cmd);
5215 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5218 struct ni_gpct *counter = s->private;
5221 retval = ni_tio_cancel(counter);
5222 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5223 ni_release_gpct_mite_channel(dev, counter->counter_index);
5232 * Programmable Function Inputs
5236 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5239 struct ni_private *devpriv = dev->private;
5240 unsigned pfi_reg_index;
5241 unsigned array_offset;
5243 if ((source & 0x1f) != source)
5245 pfi_reg_index = 1 + chan / 3;
5246 array_offset = pfi_reg_index - 1;
5247 devpriv->pfi_output_select_reg[array_offset] &=
5248 ~MSeries_PFI_Output_Select_Mask(chan);
5249 devpriv->pfi_output_select_reg[array_offset] |=
5250 MSeries_PFI_Output_Select_Bits(chan, source);
5251 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5252 M_Offset_PFI_Output_Select(pfi_reg_index));
5256 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5259 /* pre-m-series boards have fixed signals on pfi pins */
5260 if (source != ni_old_get_pfi_routing(dev, chan))
5265 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5268 const struct ni_board_struct *board = comedi_board(dev);
5270 if (board->reg_type & ni_reg_m_series_mask)
5271 return ni_m_series_set_pfi_routing(dev, chan, source);
5273 return ni_old_set_pfi_routing(dev, chan, source);
5276 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5279 struct ni_private *devpriv = dev->private;
5280 const unsigned array_offset = chan / 3;
5282 return MSeries_PFI_Output_Select_Source(chan,
5284 pfi_output_select_reg
5288 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5290 /* pre-m-series boards have fixed signals on pfi pins */
5293 return NI_PFI_OUTPUT_AI_START1;
5296 return NI_PFI_OUTPUT_AI_START2;
5299 return NI_PFI_OUTPUT_AI_CONVERT;
5302 return NI_PFI_OUTPUT_G_SRC1;
5305 return NI_PFI_OUTPUT_G_GATE1;
5308 return NI_PFI_OUTPUT_AO_UPDATE_N;
5311 return NI_PFI_OUTPUT_AO_START1;
5314 return NI_PFI_OUTPUT_AI_START_PULSE;
5317 return NI_PFI_OUTPUT_G_SRC0;
5320 return NI_PFI_OUTPUT_G_GATE0;
5323 printk("%s: bug, unhandled case in switch.\n", __func__);
5329 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5331 const struct ni_board_struct *board = comedi_board(dev);
5333 if (board->reg_type & ni_reg_m_series_mask)
5334 return ni_m_series_get_pfi_routing(dev, chan);
5336 return ni_old_get_pfi_routing(dev, chan);
5339 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5340 enum ni_pfi_filter_select filter)
5342 const struct ni_board_struct *board = comedi_board(dev);
5343 struct ni_private *devpriv __maybe_unused = dev->private;
5346 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5349 bits = ni_readl(M_Offset_PFI_Filter);
5350 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5351 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5352 ni_writel(bits, M_Offset_PFI_Filter);
5356 static int ni_pfi_insn_bits(struct comedi_device *dev,
5357 struct comedi_subdevice *s,
5358 struct comedi_insn *insn, unsigned int *data)
5360 const struct ni_board_struct *board = comedi_board(dev);
5361 struct ni_private *devpriv __maybe_unused = dev->private;
5363 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5367 s->state &= ~data[0];
5368 s->state |= (data[0] & data[1]);
5369 ni_writew(s->state, M_Offset_PFI_DO);
5371 data[1] = ni_readw(M_Offset_PFI_DI);
5375 static int ni_pfi_insn_config(struct comedi_device *dev,
5376 struct comedi_subdevice *s,
5377 struct comedi_insn *insn, unsigned int *data)
5379 struct ni_private *devpriv = dev->private;
5385 chan = CR_CHAN(insn->chanspec);
5389 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5392 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5394 case INSN_CONFIG_DIO_QUERY:
5396 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5397 COMEDI_OUTPUT : COMEDI_INPUT;
5400 case INSN_CONFIG_SET_ROUTING:
5401 return ni_set_pfi_routing(dev, chan, data[1]);
5403 case INSN_CONFIG_GET_ROUTING:
5404 data[1] = ni_get_pfi_routing(dev, chan);
5406 case INSN_CONFIG_FILTER:
5407 return ni_config_filter(dev, chan, data[1]);
5417 * NI RTSI Bus Functions
5420 static void ni_rtsi_init(struct comedi_device *dev)
5422 const struct ni_board_struct *board = comedi_board(dev);
5423 struct ni_private *devpriv = dev->private;
5425 /* Initialises the RTSI bus signal switch to a default state */
5427 /* Set clock mode to internal */
5428 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5429 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5430 printk("ni_set_master_clock failed, bug?");
5432 /* default internal lines routing to RTSI bus lines */
5433 devpriv->rtsi_trig_a_output_reg =
5434 RTSI_Trig_Output_Bits(0,
5435 NI_RTSI_OUTPUT_ADR_START1) |
5436 RTSI_Trig_Output_Bits(1,
5437 NI_RTSI_OUTPUT_ADR_START2) |
5438 RTSI_Trig_Output_Bits(2,
5439 NI_RTSI_OUTPUT_SCLKG) |
5440 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5441 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5442 RTSI_Trig_A_Output_Register);
5443 devpriv->rtsi_trig_b_output_reg =
5444 RTSI_Trig_Output_Bits(4,
5445 NI_RTSI_OUTPUT_DA_START1) |
5446 RTSI_Trig_Output_Bits(5,
5447 NI_RTSI_OUTPUT_G_SRC0) |
5448 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5449 if (board->reg_type & ni_reg_m_series_mask)
5450 devpriv->rtsi_trig_b_output_reg |=
5451 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5452 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5453 RTSI_Trig_B_Output_Register);
5456 * Sets the source and direction of the 4 on board lines
5457 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5461 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5462 struct comedi_subdevice *s,
5463 struct comedi_insn *insn, unsigned int *data)
5470 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5471 * given an arbitrary frequency input clock */
5472 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5473 unsigned *freq_divider,
5474 unsigned *freq_multiplier,
5475 unsigned *actual_period_ns)
5478 unsigned best_div = 1;
5479 static const unsigned max_div = 0x10;
5481 unsigned best_mult = 1;
5482 static const unsigned max_mult = 0x100;
5483 static const unsigned pico_per_nano = 1000;
5485 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5486 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5487 * 20 MHz for most timing clocks */
5488 static const unsigned target_picosec = 12500;
5489 static const unsigned fudge_factor_80_to_20Mhz = 4;
5490 int best_period_picosec = 0;
5491 for (div = 1; div <= max_div; ++div) {
5492 for (mult = 1; mult <= max_mult; ++mult) {
5493 unsigned new_period_ps =
5494 (reference_picosec * div) / mult;
5495 if (abs(new_period_ps - target_picosec) <
5496 abs(best_period_picosec - target_picosec)) {
5497 best_period_picosec = new_period_ps;
5503 if (best_period_picosec == 0) {
5504 printk("%s: bug, failed to find pll parameters\n", __func__);
5507 *freq_divider = best_div;
5508 *freq_multiplier = best_mult;
5510 (best_period_picosec * fudge_factor_80_to_20Mhz +
5511 (pico_per_nano / 2)) / pico_per_nano;
5515 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5517 const struct ni_board_struct *board = comedi_board(dev);
5519 if (board->reg_type & ni_reg_m_series_mask)
5525 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5526 unsigned source, unsigned period_ns)
5528 struct ni_private *devpriv = dev->private;
5529 static const unsigned min_period_ns = 50;
5530 static const unsigned max_period_ns = 1000;
5531 static const unsigned timeout = 1000;
5532 unsigned pll_control_bits;
5533 unsigned freq_divider;
5534 unsigned freq_multiplier;
5538 if (source == NI_MIO_PLL_PXI10_CLOCK)
5540 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5541 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5543 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5544 "for the phased-lock loop.\n", __func__,
5545 min_period_ns, max_period_ns);
5548 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5549 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5550 RTSI_Trig_Direction_Register);
5552 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5553 devpriv->clock_and_fout2 |=
5554 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5555 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5557 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5558 devpriv->clock_and_fout2 |=
5559 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5560 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5562 &devpriv->clock_ns);
5566 case NI_MIO_PLL_PXI10_CLOCK:
5567 /* pxi clock is 10MHz */
5568 devpriv->clock_and_fout2 |=
5569 MSeries_PLL_In_Source_Select_PXI_Clock10;
5570 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5572 &devpriv->clock_ns);
5578 unsigned rtsi_channel;
5579 static const unsigned max_rtsi_channel = 7;
5580 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5583 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5584 devpriv->clock_and_fout2 |=
5585 MSeries_PLL_In_Source_Select_RTSI_Bits
5590 if (rtsi_channel > max_rtsi_channel)
5592 retval = ni_mseries_get_pll_parameters(period_ns,
5602 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5604 MSeries_PLL_Divisor_Bits(freq_divider) |
5605 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5607 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5608 * freq_divider, freq_multiplier, pll_control_bits); */
5609 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5610 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5611 devpriv->clock_source = source;
5612 /* it seems to typically take a few hundred microseconds for PLL to lock */
5613 for (i = 0; i < timeout; ++i) {
5614 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5621 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5622 __func__, source, period_ns);
5628 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5631 const struct ni_board_struct *board = comedi_board(dev);
5632 struct ni_private *devpriv = dev->private;
5634 if (source == NI_MIO_INTERNAL_CLOCK) {
5635 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5636 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5637 RTSI_Trig_Direction_Register);
5638 devpriv->clock_ns = TIMEBASE_1_NS;
5639 if (board->reg_type & ni_reg_m_series_mask) {
5640 devpriv->clock_and_fout2 &=
5641 ~(MSeries_Timebase1_Select_Bit |
5642 MSeries_Timebase3_Select_Bit);
5643 ni_writew(devpriv->clock_and_fout2,
5644 M_Offset_Clock_and_Fout2);
5645 ni_writew(0, M_Offset_PLL_Control);
5647 devpriv->clock_source = source;
5649 if (board->reg_type & ni_reg_m_series_mask) {
5650 return ni_mseries_set_pll_master_clock(dev, source,
5653 if (source == NI_MIO_RTSI_CLOCK) {
5654 devpriv->rtsi_trig_direction_reg |=
5656 devpriv->stc_writew(dev,
5658 rtsi_trig_direction_reg,
5659 RTSI_Trig_Direction_Register);
5660 if (period_ns == 0) {
5662 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5666 devpriv->clock_ns = period_ns;
5668 devpriv->clock_source = source;
5676 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5679 const struct ni_board_struct *board = comedi_board(dev);
5681 if (chan >= num_configurable_rtsi_channels(dev)) {
5682 if (chan == old_RTSI_clock_channel) {
5683 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5687 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5688 __func__, chan, old_RTSI_clock_channel);
5695 case NI_RTSI_OUTPUT_ADR_START1:
5696 case NI_RTSI_OUTPUT_ADR_START2:
5697 case NI_RTSI_OUTPUT_SCLKG:
5698 case NI_RTSI_OUTPUT_DACUPDN:
5699 case NI_RTSI_OUTPUT_DA_START1:
5700 case NI_RTSI_OUTPUT_G_SRC0:
5701 case NI_RTSI_OUTPUT_G_GATE0:
5702 case NI_RTSI_OUTPUT_RGOUT0:
5703 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5706 case NI_RTSI_OUTPUT_RTSI_OSC:
5707 if (board->reg_type & ni_reg_m_series_mask)
5718 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5721 struct ni_private *devpriv = dev->private;
5723 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5726 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5727 devpriv->rtsi_trig_a_output_reg |=
5728 RTSI_Trig_Output_Bits(chan, source);
5729 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5730 RTSI_Trig_A_Output_Register);
5731 } else if (chan < 8) {
5732 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5733 devpriv->rtsi_trig_b_output_reg |=
5734 RTSI_Trig_Output_Bits(chan, source);
5735 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5736 RTSI_Trig_B_Output_Register);
5741 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5743 struct ni_private *devpriv = dev->private;
5746 return RTSI_Trig_Output_Source(chan,
5747 devpriv->rtsi_trig_a_output_reg);
5748 } else if (chan < num_configurable_rtsi_channels(dev)) {
5749 return RTSI_Trig_Output_Source(chan,
5750 devpriv->rtsi_trig_b_output_reg);
5752 if (chan == old_RTSI_clock_channel)
5753 return NI_RTSI_OUTPUT_RTSI_OSC;
5754 printk("%s: bug! should never get here?\n", __func__);
5759 static int ni_rtsi_insn_config(struct comedi_device *dev,
5760 struct comedi_subdevice *s,
5761 struct comedi_insn *insn, unsigned int *data)
5763 const struct ni_board_struct *board = comedi_board(dev);
5764 struct ni_private *devpriv = dev->private;
5765 unsigned int chan = CR_CHAN(insn->chanspec);
5768 case INSN_CONFIG_DIO_OUTPUT:
5769 if (chan < num_configurable_rtsi_channels(dev)) {
5770 devpriv->rtsi_trig_direction_reg |=
5771 RTSI_Output_Bit(chan,
5772 (board->reg_type & ni_reg_m_series_mask) != 0);
5773 } else if (chan == old_RTSI_clock_channel) {
5774 devpriv->rtsi_trig_direction_reg |=
5775 Drive_RTSI_Clock_Bit;
5777 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5778 RTSI_Trig_Direction_Register);
5780 case INSN_CONFIG_DIO_INPUT:
5781 if (chan < num_configurable_rtsi_channels(dev)) {
5782 devpriv->rtsi_trig_direction_reg &=
5783 ~RTSI_Output_Bit(chan,
5784 (board->reg_type & ni_reg_m_series_mask) != 0);
5785 } else if (chan == old_RTSI_clock_channel) {
5786 devpriv->rtsi_trig_direction_reg &=
5787 ~Drive_RTSI_Clock_Bit;
5789 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5790 RTSI_Trig_Direction_Register);
5792 case INSN_CONFIG_DIO_QUERY:
5793 if (chan < num_configurable_rtsi_channels(dev)) {
5795 (devpriv->rtsi_trig_direction_reg &
5796 RTSI_Output_Bit(chan,
5797 (board->reg_type & ni_reg_m_series_mask) != 0))
5798 ? INSN_CONFIG_DIO_OUTPUT
5799 : INSN_CONFIG_DIO_INPUT;
5800 } else if (chan == old_RTSI_clock_channel) {
5802 (devpriv->rtsi_trig_direction_reg &
5803 Drive_RTSI_Clock_Bit)
5804 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5808 case INSN_CONFIG_SET_CLOCK_SRC:
5809 return ni_set_master_clock(dev, data[1], data[2]);
5811 case INSN_CONFIG_GET_CLOCK_SRC:
5812 data[1] = devpriv->clock_source;
5813 data[2] = devpriv->clock_ns;
5816 case INSN_CONFIG_SET_ROUTING:
5817 return ni_set_rtsi_routing(dev, chan, data[1]);
5819 case INSN_CONFIG_GET_ROUTING:
5820 data[1] = ni_get_rtsi_routing(dev, chan);
5830 static int cs5529_wait_for_idle(struct comedi_device *dev)
5832 unsigned short status;
5833 const int timeout = HZ;
5836 for (i = 0; i < timeout; i++) {
5837 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5838 if ((status & CSS_ADC_BUSY) == 0) {
5841 set_current_state(TASK_INTERRUPTIBLE);
5842 if (schedule_timeout(1)) {
5846 /* printk("looped %i times waiting for idle\n", i); */
5848 printk("%s: %s: timeout\n", __FILE__, __func__);
5854 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5856 static const int timeout = 100;
5859 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5860 /* give time for command to start being serially clocked into cs5529.
5861 * this insures that the CSS_ADC_BUSY bit will get properly
5862 * set before we exit this function.
5864 for (i = 0; i < timeout; i++) {
5865 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5869 /* printk("looped %i times writing command to cs5529\n", i); */
5871 comedi_error(dev, "possible problem - never saw adc go busy?");
5875 /* write to cs5529 register */
5876 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5877 unsigned int reg_select_bits)
5879 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5880 CAL_ADC_Config_Data_High_Word_67xx);
5881 ni_ao_win_outw(dev, (value & 0xffff),
5882 CAL_ADC_Config_Data_Low_Word_67xx);
5883 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5884 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5885 if (cs5529_wait_for_idle(dev))
5886 comedi_error(dev, "time or signal in cs5529_config_write()");
5889 #ifdef NI_CS5529_DEBUG
5890 /* read from cs5529 register */
5891 static unsigned int cs5529_config_read(struct comedi_device *dev,
5892 unsigned int reg_select_bits)
5896 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5897 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5898 if (cs5529_wait_for_idle(dev))
5899 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5900 value = (ni_ao_win_inw(dev,
5901 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5903 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5908 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5911 unsigned short status;
5913 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5914 retval = cs5529_wait_for_idle(dev);
5917 "timeout or signal in cs5529_do_conversion()");
5920 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5921 if (status & CSS_OSC_DETECT) {
5923 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5926 if (status & CSS_OVERRANGE) {
5928 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5931 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5932 /* cs5529 returns 16 bit signed data in bipolar mode */
5938 static int cs5529_ai_insn_read(struct comedi_device *dev,
5939 struct comedi_subdevice *s,
5940 struct comedi_insn *insn, unsigned int *data)
5943 unsigned short sample;
5944 unsigned int channel_select;
5945 const unsigned int INTERNAL_REF = 0x1000;
5947 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5948 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5949 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5950 if (insn->chanspec & CR_ALT_SOURCE)
5951 channel_select = INTERNAL_REF;
5953 channel_select = CR_CHAN(insn->chanspec);
5954 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5956 for (n = 0; n < insn->n; n++) {
5957 retval = cs5529_do_conversion(dev, &sample);
5965 static int init_cs5529(struct comedi_device *dev)
5967 unsigned int config_bits =
5968 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5971 /* do self-calibration */
5972 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5973 CSCMD_CONFIG_REGISTER);
5974 /* need to force a conversion for calibration to run */
5975 cs5529_do_conversion(dev, NULL);
5977 /* force gain calibration to 1 */
5978 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5979 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5980 CSCMD_CONFIG_REGISTER);
5981 if (cs5529_wait_for_idle(dev))
5982 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5984 #ifdef NI_CS5529_DEBUG
5985 printk("config: 0x%x\n", cs5529_config_read(dev,
5986 CSCMD_CONFIG_REGISTER));
5987 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
5988 printk("offset: 0x%x\n", cs5529_config_read(dev,
5989 CSCMD_OFFSET_REGISTER));