2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 Description: National Instruments AT-MIO-16D
24 Author: Chris R. Baugher <baugher@enteract.com>
26 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
29 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
30 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
31 * handling code from his driver as an example for this one.
38 #include <linux/interrupt.h>
39 #include "../comedidev.h"
41 #include <linux/ioport.h>
43 #include "comedi_fc.h"
46 /* Configuration and Status Registers */
47 #define COM_REG_1 0x00 /* wo 16 */
48 #define STAT_REG 0x00 /* ro 16 */
49 #define COM_REG_2 0x02 /* wo 16 */
50 /* Event Strobe Registers */
51 #define START_CONVERT_REG 0x08 /* wo 16 */
52 #define START_DAQ_REG 0x0A /* wo 16 */
53 #define AD_CLEAR_REG 0x0C /* wo 16 */
54 #define EXT_STROBE_REG 0x0E /* wo 16 */
55 /* Analog Output Registers */
56 #define DAC0_REG 0x10 /* wo 16 */
57 #define DAC1_REG 0x12 /* wo 16 */
58 #define INT2CLR_REG 0x14 /* wo 16 */
59 /* Analog Input Registers */
60 #define MUX_CNTR_REG 0x04 /* wo 16 */
61 #define MUX_GAIN_REG 0x06 /* wo 16 */
62 #define AD_FIFO_REG 0x16 /* ro 16 */
63 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
64 /* AM9513A Counter/Timer Registers */
65 #define AM9513A_DATA_REG 0x18 /* rw 16 */
66 #define AM9513A_COM_REG 0x1A /* wo 16 */
67 #define AM9513A_STAT_REG 0x1A /* ro 16 */
68 /* MIO-16 Digital I/O Registers */
69 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
70 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
71 /* RTSI Switch Registers */
72 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
73 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
74 /* DIO-24 Registers */
75 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
76 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
77 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
78 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
80 /* Command Register bits */
81 #define COMREG1_2SCADC 0x0001
82 #define COMREG1_1632CNT 0x0002
83 #define COMREG1_SCANEN 0x0008
84 #define COMREG1_DAQEN 0x0010
85 #define COMREG1_DMAEN 0x0020
86 #define COMREG1_CONVINTEN 0x0080
87 #define COMREG2_SCN2 0x0010
88 #define COMREG2_INTEN 0x0080
89 #define COMREG2_DOUTEN0 0x0100
90 #define COMREG2_DOUTEN1 0x0200
91 /* Status Register bits */
92 #define STAT_AD_OVERRUN 0x0100
93 #define STAT_AD_OVERFLOW 0x0200
94 #define STAT_AD_DAQPROG 0x0800
95 #define STAT_AD_CONVAVAIL 0x2000
96 #define STAT_AD_DAQSTOPINT 0x4000
97 /* AM9513A Counter/Timer defines */
98 #define CLOCK_1_MHZ 0x8B25
99 #define CLOCK_100_KHZ 0x8C25
100 #define CLOCK_10_KHZ 0x8D25
101 #define CLOCK_1_KHZ 0x8E25
102 #define CLOCK_100_HZ 0x8F25
103 /* Other miscellaneous defines */
104 #define ATMIO16D_SIZE 32 /* bus address range */
105 #define ATMIO16D_TIMEOUT 10
107 struct atmio16_board_t {
114 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, {
126 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, {
138 static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, {
150 /* private data struct */
151 struct atmio16d_private {
152 enum { adc_diff, adc_singleended } adc_mux;
153 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
154 enum { adc_2comp, adc_straight } adc_coding;
155 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
156 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
157 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
158 const struct comedi_lrange *ao_range_type_list[2];
159 unsigned int ao_readback[2];
160 unsigned int com_reg_1_state; /* current state of command register 1 */
161 unsigned int com_reg_2_state; /* current state of command register 2 */
164 static void reset_counters(struct comedi_device *dev)
167 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
168 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
169 outw(0x4, dev->iobase + AM9513A_DATA_REG);
170 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
171 outw(0x3, dev->iobase + AM9513A_DATA_REG);
172 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
173 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
175 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
176 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
177 outw(0x4, dev->iobase + AM9513A_DATA_REG);
178 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
179 outw(0x3, dev->iobase + AM9513A_DATA_REG);
180 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
181 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
183 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
184 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
185 outw(0x4, dev->iobase + AM9513A_DATA_REG);
186 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
187 outw(0x3, dev->iobase + AM9513A_DATA_REG);
188 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
189 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
191 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
192 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
193 outw(0x4, dev->iobase + AM9513A_DATA_REG);
194 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
195 outw(0x3, dev->iobase + AM9513A_DATA_REG);
196 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
197 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
199 outw(0, dev->iobase + AD_CLEAR_REG);
202 static void reset_atmio16d(struct comedi_device *dev)
204 struct atmio16d_private *devpriv = dev->private;
207 /* now we need to initialize the board */
208 outw(0, dev->iobase + COM_REG_1);
209 outw(0, dev->iobase + COM_REG_2);
210 outw(0, dev->iobase + MUX_GAIN_REG);
211 /* init AM9513A timer */
212 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
213 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
214 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
215 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
216 for (i = 1; i <= 5; ++i) {
217 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
218 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
219 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
220 outw(0x3, dev->iobase + AM9513A_DATA_REG);
222 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
223 /* timer init done */
224 outw(0, dev->iobase + AD_CLEAR_REG);
225 outw(0, dev->iobase + INT2CLR_REG);
226 /* select straight binary mode for Analog Input */
227 devpriv->com_reg_1_state |= 1;
228 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
229 devpriv->adc_coding = adc_straight;
230 /* zero the analog outputs */
231 outw(2048, dev->iobase + DAC0_REG);
232 outw(2048, dev->iobase + DAC1_REG);
235 static irqreturn_t atmio16d_interrupt(int irq, void *d)
237 struct comedi_device *dev = d;
238 struct comedi_subdevice *s = &dev->subdevices[0];
240 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG));
242 comedi_event(dev, s);
246 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
247 struct comedi_subdevice *s,
248 struct comedi_cmd *cmd)
252 /* Step 1 : check if triggers are trivially valid */
254 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
255 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
256 TRIG_FOLLOW | TRIG_TIMER);
257 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
258 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
259 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
264 /* Step 2a : make sure trigger sources are unique */
266 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
267 err |= cfc_check_trigger_is_unique(cmd->stop_src);
269 /* Step 2b : and mutually compatible */
274 /* step 3: make sure arguments are trivially compatible */
276 if (cmd->start_arg != 0) {
280 if (cmd->scan_begin_src == TRIG_FOLLOW) {
281 /* internal trigger */
282 if (cmd->scan_begin_arg != 0) {
283 cmd->scan_begin_arg = 0;
288 /* external trigger */
289 /* should be level/edge, hi/lo specification here */
290 if (cmd->scan_begin_arg != 0) {
291 cmd->scan_begin_arg = 0;
297 if (cmd->convert_arg < 10000) {
298 cmd->convert_arg = 10000;
302 if (cmd->convert_arg > SLOWEST_TIMER) {
303 cmd->convert_arg = SLOWEST_TIMER;
307 if (cmd->scan_end_arg != cmd->chanlist_len) {
308 cmd->scan_end_arg = cmd->chanlist_len;
311 if (cmd->stop_src == TRIG_COUNT) {
312 /* any count is allowed */
315 if (cmd->stop_arg != 0) {
327 static int atmio16d_ai_cmd(struct comedi_device *dev,
328 struct comedi_subdevice *s)
330 struct atmio16d_private *devpriv = dev->private;
331 struct comedi_cmd *cmd = &s->async->cmd;
332 unsigned int timer, base_clock;
333 unsigned int sample_count, tmp, chan, gain;
336 /* This is slowly becoming a working command interface. *
337 * It is still uber-experimental */
340 s->async->cur_chan = 0;
342 /* check if scanning multiple channels */
343 if (cmd->chanlist_len < 2) {
344 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
345 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
347 devpriv->com_reg_1_state |= COMREG1_SCANEN;
348 devpriv->com_reg_2_state |= COMREG2_SCN2;
349 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
350 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
353 /* Setup the Mux-Gain Counter */
354 for (i = 0; i < cmd->chanlist_len; ++i) {
355 chan = CR_CHAN(cmd->chanlist[i]);
356 gain = CR_RANGE(cmd->chanlist[i]);
357 outw(i, dev->iobase + MUX_CNTR_REG);
358 tmp = chan | (gain << 6);
359 if (i == cmd->scan_end_arg - 1)
360 tmp |= 0x0010; /* set LASTONE bit */
361 outw(tmp, dev->iobase + MUX_GAIN_REG);
364 /* Now program the sample interval timer */
365 /* Figure out which clock to use then get an
366 * appropriate timer value */
367 if (cmd->convert_arg < 65536000) {
368 base_clock = CLOCK_1_MHZ;
369 timer = cmd->convert_arg / 1000;
370 } else if (cmd->convert_arg < 655360000) {
371 base_clock = CLOCK_100_KHZ;
372 timer = cmd->convert_arg / 10000;
373 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) {
374 base_clock = CLOCK_10_KHZ;
375 timer = cmd->convert_arg / 100000;
376 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) {
377 base_clock = CLOCK_1_KHZ;
378 timer = cmd->convert_arg / 1000000;
380 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
381 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
382 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
383 outw(0x2, dev->iobase + AM9513A_DATA_REG);
384 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
385 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
386 outw(timer, dev->iobase + AM9513A_DATA_REG);
387 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
389 /* Now figure out how many samples to get */
390 /* and program the sample counter */
391 sample_count = cmd->stop_arg * cmd->scan_end_arg;
392 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
393 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
394 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
395 if (sample_count < 65536) {
396 /* use only Counter 4 */
397 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
398 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
399 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
400 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
401 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
402 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
404 /* Counter 4 and 5 are needed */
406 tmp = sample_count & 0xFFFF;
408 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
410 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
412 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
413 outw(0, dev->iobase + AM9513A_DATA_REG);
414 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
415 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
416 outw(0x25, dev->iobase + AM9513A_DATA_REG);
417 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
418 tmp = sample_count & 0xFFFF;
419 if ((tmp == 0) || (tmp == 1)) {
420 outw((sample_count >> 16) & 0xFFFF,
421 dev->iobase + AM9513A_DATA_REG);
423 outw(((sample_count >> 16) & 0xFFFF) + 1,
424 dev->iobase + AM9513A_DATA_REG);
426 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
427 devpriv->com_reg_1_state |= COMREG1_1632CNT;
428 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
431 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
432 /* Figure out which clock to use then get an
433 * appropriate timer value */
434 if (cmd->chanlist_len > 1) {
435 if (cmd->scan_begin_arg < 65536000) {
436 base_clock = CLOCK_1_MHZ;
437 timer = cmd->scan_begin_arg / 1000;
438 } else if (cmd->scan_begin_arg < 655360000) {
439 base_clock = CLOCK_100_KHZ;
440 timer = cmd->scan_begin_arg / 10000;
441 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) {
442 base_clock = CLOCK_10_KHZ;
443 timer = cmd->scan_begin_arg / 100000;
444 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) {
445 base_clock = CLOCK_1_KHZ;
446 timer = cmd->scan_begin_arg / 1000000;
448 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
449 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
450 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
451 outw(0x2, dev->iobase + AM9513A_DATA_REG);
452 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
453 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
454 outw(timer, dev->iobase + AM9513A_DATA_REG);
455 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
458 /* Clear the A/D FIFO and reset the MUX counter */
459 outw(0, dev->iobase + AD_CLEAR_REG);
460 outw(0, dev->iobase + MUX_CNTR_REG);
461 outw(0, dev->iobase + INT2CLR_REG);
462 /* enable this acquisition operation */
463 devpriv->com_reg_1_state |= COMREG1_DAQEN;
464 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
465 /* enable interrupts for conversion completion */
466 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
467 devpriv->com_reg_2_state |= COMREG2_INTEN;
468 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
469 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
470 /* apply a trigger. this starts the counters! */
471 outw(0, dev->iobase + START_DAQ_REG);
476 /* This will cancel a running acquisition operation */
477 static int atmio16d_ai_cancel(struct comedi_device *dev,
478 struct comedi_subdevice *s)
485 /* Mode 0 is used to get a single conversion on demand */
486 static int atmio16d_ai_insn_read(struct comedi_device *dev,
487 struct comedi_subdevice *s,
488 struct comedi_insn *insn, unsigned int *data)
490 struct atmio16d_private *devpriv = dev->private;
496 chan = CR_CHAN(insn->chanspec);
497 gain = CR_RANGE(insn->chanspec);
499 /* reset the Analog input circuitry */
500 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
501 /* reset the Analog Input MUX Counter to 0 */
502 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
504 /* set the Input MUX gain */
505 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
507 for (i = 0; i < insn->n; i++) {
508 /* start the conversion */
509 outw(0, dev->iobase + START_CONVERT_REG);
510 /* wait for it to finish */
511 for (t = 0; t < ATMIO16D_TIMEOUT; t++) {
512 /* check conversion status */
513 status = inw(dev->iobase + STAT_REG);
514 if (status & STAT_AD_CONVAVAIL) {
515 /* read the data now */
516 data[i] = inw(dev->iobase + AD_FIFO_REG);
517 /* change to two's complement if need be */
518 if (devpriv->adc_coding == adc_2comp)
522 if (status & STAT_AD_OVERFLOW) {
523 printk(KERN_INFO "atmio16d: a/d FIFO overflow\n");
524 outw(0, dev->iobase + AD_CLEAR_REG);
529 /* end waiting, now check if it timed out */
530 if (t == ATMIO16D_TIMEOUT) {
531 printk(KERN_INFO "atmio16d: timeout\n");
540 static int atmio16d_ao_insn_read(struct comedi_device *dev,
541 struct comedi_subdevice *s,
542 struct comedi_insn *insn, unsigned int *data)
544 struct atmio16d_private *devpriv = dev->private;
547 for (i = 0; i < insn->n; i++)
548 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
552 static int atmio16d_ao_insn_write(struct comedi_device *dev,
553 struct comedi_subdevice *s,
554 struct comedi_insn *insn, unsigned int *data)
556 struct atmio16d_private *devpriv = dev->private;
561 chan = CR_CHAN(insn->chanspec);
563 for (i = 0; i < insn->n; i++) {
567 if (devpriv->dac0_coding == dac_2comp)
569 outw(d, dev->iobase + DAC0_REG);
572 if (devpriv->dac1_coding == dac_2comp)
574 outw(d, dev->iobase + DAC1_REG);
579 devpriv->ao_readback[chan] = data[i];
584 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
585 struct comedi_subdevice *s,
586 struct comedi_insn *insn, unsigned int *data)
589 s->state &= ~data[0];
590 s->state |= (data[0] | data[1]);
591 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
593 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
598 static int atmio16d_dio_insn_config(struct comedi_device *dev,
599 struct comedi_subdevice *s,
600 struct comedi_insn *insn,
603 struct atmio16d_private *devpriv = dev->private;
607 for (i = 0; i < insn->n; i++) {
608 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0;
613 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
614 if (s->io_bits & 0x0f)
615 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
616 if (s->io_bits & 0xf0)
617 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
618 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
624 options[0] - I/O port
627 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
630 N == irq N {3,4,5,6,7,9}
631 options[3] - DMA1 channel
634 options[4] - DMA2 channel
639 0=differential, 1=single
640 options[6] - a/d range
641 0=bipolar10, 1=bipolar5, 2=unipolar10
643 options[7] - dac0 range
644 0=bipolar, 1=unipolar
645 options[8] - dac0 reference
646 0=internal, 1=external
647 options[9] - dac0 coding
648 0=2's comp, 1=straight binary
650 options[10] - dac1 range
651 options[11] - dac1 reference
652 options[12] - dac1 coding
655 static int atmio16d_attach(struct comedi_device *dev,
656 struct comedi_devconfig *it)
658 const struct atmio16_board_t *board = comedi_board(dev);
659 struct atmio16d_private *devpriv;
661 unsigned long iobase;
664 struct comedi_subdevice *s;
666 /* make sure the address range is free and allocate it */
667 iobase = it->options[0];
668 printk(KERN_INFO "comedi%d: atmio16d: 0x%04lx ", dev->minor, iobase);
669 if (!request_region(iobase, ATMIO16D_SIZE, "ni_atmio16d")) {
670 printk("I/O port conflict\n");
673 dev->iobase = iobase;
675 dev->board_name = board->name;
677 ret = comedi_alloc_subdevices(dev, 4);
681 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
684 dev->private = devpriv;
686 /* reset the atmio16d hardware */
689 /* check if our interrupt is available and get it */
690 irq = it->options[1];
693 ret = request_irq(irq, atmio16d_interrupt, 0, "atmio16d", dev);
695 printk(KERN_INFO "failed to allocate irq %u\n", irq);
699 printk(KERN_INFO "( irq = %u )\n", irq);
701 printk(KERN_INFO "( no irq )");
704 /* set device options */
705 devpriv->adc_mux = it->options[5];
706 devpriv->adc_range = it->options[6];
708 devpriv->dac0_range = it->options[7];
709 devpriv->dac0_reference = it->options[8];
710 devpriv->dac0_coding = it->options[9];
711 devpriv->dac1_range = it->options[10];
712 devpriv->dac1_reference = it->options[11];
713 devpriv->dac1_coding = it->options[12];
715 /* setup sub-devices */
716 s = &dev->subdevices[0];
717 dev->read_subdev = s;
719 s->type = COMEDI_SUBD_AI;
720 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ;
721 s->n_chan = (devpriv->adc_mux ? 16 : 8);
722 s->len_chanlist = 16;
723 s->insn_read = atmio16d_ai_insn_read;
724 s->do_cmdtest = atmio16d_ai_cmdtest;
725 s->do_cmd = atmio16d_ai_cmd;
726 s->cancel = atmio16d_ai_cancel;
727 s->maxdata = 0xfff; /* 4095 decimal */
728 switch (devpriv->adc_range) {
730 s->range_table = &range_atmio16d_ai_10_bipolar;
733 s->range_table = &range_atmio16d_ai_5_bipolar;
736 s->range_table = &range_atmio16d_ai_unipolar;
741 s = &dev->subdevices[1];
742 s->type = COMEDI_SUBD_AO;
743 s->subdev_flags = SDF_WRITABLE;
745 s->insn_read = atmio16d_ao_insn_read;
746 s->insn_write = atmio16d_ao_insn_write;
747 s->maxdata = 0xfff; /* 4095 decimal */
748 s->range_table_list = devpriv->ao_range_type_list;
749 switch (devpriv->dac0_range) {
751 devpriv->ao_range_type_list[0] = &range_bipolar10;
754 devpriv->ao_range_type_list[0] = &range_unipolar10;
757 switch (devpriv->dac1_range) {
759 devpriv->ao_range_type_list[1] = &range_bipolar10;
762 devpriv->ao_range_type_list[1] = &range_unipolar10;
767 s = &dev->subdevices[2];
768 s->type = COMEDI_SUBD_DIO;
769 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
771 s->insn_bits = atmio16d_dio_insn_bits;
772 s->insn_config = atmio16d_dio_insn_config;
774 s->range_table = &range_digital;
777 s = &dev->subdevices[3];
779 subdev_8255_init(dev, s, NULL, dev->iobase);
781 s->type = COMEDI_SUBD_UNUSED;
783 /* don't yet know how to deal with counter/timers */
785 s = &dev->subdevices[4];
787 s->type = COMEDI_SUBD_TIMER;
796 static void atmio16d_detach(struct comedi_device *dev)
798 const struct atmio16_board_t *board = comedi_board(dev);
799 struct comedi_subdevice *s;
801 if (dev->subdevices && board->has_8255) {
802 s = &dev->subdevices[3];
803 subdev_8255_cleanup(dev, s);
806 free_irq(dev->irq, dev);
809 release_region(dev->iobase, ATMIO16D_SIZE);
812 static const struct atmio16_board_t atmio16_boards[] = {
822 static struct comedi_driver atmio16d_driver = {
823 .driver_name = "atmio16",
824 .module = THIS_MODULE,
825 .attach = atmio16d_attach,
826 .detach = atmio16d_detach,
827 .board_name = &atmio16_boards[0].name,
828 .num_names = ARRAY_SIZE(atmio16_boards),
829 .offset = sizeof(struct atmio16_board_t),
831 module_comedi_driver(atmio16d_driver);
833 MODULE_AUTHOR("Comedi http://www.comedi.org");
834 MODULE_DESCRIPTION("Comedi low-level driver");
835 MODULE_LICENSE("GPL");