Pileus Git - ~andy/linux/blob - drivers/staging/comedi/drivers/ni_660x.c

   1 /*
   2   comedi/drivers/ni_660x.c
   3   Hardware driver for NI 660x devices
   4
   5   This program is free software; you can redistribute it and/or modify
   6   it under the terms of the GNU General Public License as published by
   7   the Free Software Foundation; either version 2 of the License, or
   8   (at your option) any later version.
   9
  10   This program is distributed in the hope that it will be useful,
  11   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13   GNU General Public License for more details.
  14
  15   You should have received a copy of the GNU General Public License
  16   along with this program; if not, write to the Free Software
  17   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20 /*
  21 Driver: ni_660x
  22 Description: National Instruments 660x counter/timer boards
  23 Devices:
  24 [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
  25         PXI-6608
  26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  27         Herman.Bruyninckx@mech.kuleuven.ac.be,
  28         Wim.Meeussen@mech.kuleuven.ac.be,
  29         Klaas.Gadeyne@mech.kuleuven.ac.be,
  30         Frank Mori Hess <fmhess@users.sourceforge.net>
  31 Updated: Thu Oct 18 12:56:06 EDT 2007
  32 Status: experimental
  33
  34 Encoders work.  PulseGeneration (both single pulse and pulse train)
  35 works. Buffered commands work for input but not output.
  36
  37 References:
  38 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  39 DAQ 6601/6602 User Manual (NI 322137B-01)
  40
  41 */
  42
  43 #include <linux/interrupt.h>
  44 #include "../comedidev.h"
  45 #include "mite.h"
  46 #include "ni_tio.h"
  47
  48 enum ni_660x_constants {
  49         min_counter_pfi_chan = 8,
  50         max_dio_pfi_chan = 31,
  51         counters_per_chip = 4
  52 };
  53
  54 #define NUM_PFI_CHANNELS 40
  55 /* really there are only up to 3 dma channels, but the register layout allows
  56 for 4 */
  57 #define MAX_DMA_CHANNEL 4
  58
  59 /* See Register-Level Programmer Manual page 3.1 */
  60 enum NI_660x_Register {
  61         G0InterruptAcknowledge,
  62         G0StatusRegister,
  63         G1InterruptAcknowledge,
  64         G1StatusRegister,
  65         G01StatusRegister,
  66         G0CommandRegister,
  67         STCDIOParallelInput,
  68         G1CommandRegister,
  69         G0HWSaveRegister,
  70         G1HWSaveRegister,
  71         STCDIOOutput,
  72         STCDIOControl,
  73         G0SWSaveRegister,
  74         G1SWSaveRegister,
  75         G0ModeRegister,
  76         G01JointStatus1Register,
  77         G1ModeRegister,
  78         STCDIOSerialInput,
  79         G0LoadARegister,
  80         G01JointStatus2Register,
  81         G0LoadBRegister,
  82         G1LoadARegister,
  83         G1LoadBRegister,
  84         G0InputSelectRegister,
  85         G1InputSelectRegister,
  86         G0AutoincrementRegister,
  87         G1AutoincrementRegister,
  88         G01JointResetRegister,
  89         G0InterruptEnable,
  90         G1InterruptEnable,
  91         G0CountingModeRegister,
  92         G1CountingModeRegister,
  93         G0SecondGateRegister,
  94         G1SecondGateRegister,
  95         G0DMAConfigRegister,
  96         G0DMAStatusRegister,
  97         G1DMAConfigRegister,
  98         G1DMAStatusRegister,
  99         G2InterruptAcknowledge,
 100         G2StatusRegister,
 101         G3InterruptAcknowledge,
 102         G3StatusRegister,
 103         G23StatusRegister,
 104         G2CommandRegister,
 105         G3CommandRegister,
 106         G2HWSaveRegister,
 107         G3HWSaveRegister,
 108         G2SWSaveRegister,
 109         G3SWSaveRegister,
 110         G2ModeRegister,
 111         G23JointStatus1Register,
 112         G3ModeRegister,
 113         G2LoadARegister,
 114         G23JointStatus2Register,
 115         G2LoadBRegister,
 116         G3LoadARegister,
 117         G3LoadBRegister,
 118         G2InputSelectRegister,
 119         G3InputSelectRegister,
 120         G2AutoincrementRegister,
 121         G3AutoincrementRegister,
 122         G23JointResetRegister,
 123         G2InterruptEnable,
 124         G3InterruptEnable,
 125         G2CountingModeRegister,
 126         G3CountingModeRegister,
 127         G3SecondGateRegister,
 128         G2SecondGateRegister,
 129         G2DMAConfigRegister,
 130         G2DMAStatusRegister,
 131         G3DMAConfigRegister,
 132         G3DMAStatusRegister,
 133         DIO32Input,
 134         DIO32Output,
 135         ClockConfigRegister,
 136         GlobalInterruptStatusRegister,
 137         DMAConfigRegister,
 138         GlobalInterruptConfigRegister,
 139         IOConfigReg0_1,
 140         IOConfigReg2_3,
 141         IOConfigReg4_5,
 142         IOConfigReg6_7,
 143         IOConfigReg8_9,
 144         IOConfigReg10_11,
 145         IOConfigReg12_13,
 146         IOConfigReg14_15,
 147         IOConfigReg16_17,
 148         IOConfigReg18_19,
 149         IOConfigReg20_21,
 150         IOConfigReg22_23,
 151         IOConfigReg24_25,
 152         IOConfigReg26_27,
 153         IOConfigReg28_29,
 154         IOConfigReg30_31,
 155         IOConfigReg32_33,
 156         IOConfigReg34_35,
 157         IOConfigReg36_37,
 158         IOConfigReg38_39,
 159         NumRegisters,
 160 };
 161
 162 static inline unsigned IOConfigReg(unsigned pfi_channel)
 163 {
 164         unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
 165         BUG_ON(reg > IOConfigReg38_39);
 166         return reg;
 167 }
 168
 169 enum ni_660x_register_width {
 170         DATA_1B,
 171         DATA_2B,
 172         DATA_4B
 173 };
 174
 175 enum ni_660x_register_direction {
 176         NI_660x_READ,
 177         NI_660x_WRITE,
 178         NI_660x_READ_WRITE
 179 };
 180
 181 enum ni_660x_pfi_output_select {
 182         pfi_output_select_high_Z = 0,
 183         pfi_output_select_counter = 1,
 184         pfi_output_select_do = 2,
 185         num_pfi_output_selects
 186 };
 187
 188 enum ni_660x_subdevices {
 189         NI_660X_DIO_SUBDEV = 1,
 190         NI_660X_GPCT_SUBDEV_0 = 2
 191 };
 192 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
 193 {
 194         return NI_660X_GPCT_SUBDEV_0 + index;
 195 }
 196
 197 struct NI_660xRegisterData {
 198
 199         const char *name;       /*  Register Name */
 200         int offset;             /*  Offset from base address from GPCT chip */
 201         enum ni_660x_register_direction direction;
 202         enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
 203 };
 204
 205 static const struct NI_660xRegisterData registerData[NumRegisters] = {
 206         {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
 207         {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
 208         {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
 209         {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
 210         {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
 211         {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
 212         {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
 213         {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
 214         {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
 215         {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
 216         {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
 217         {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
 218         {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
 219         {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
 220         {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
 221         {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
 222         {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
 223         {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
 224         {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
 225         {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
 226         {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
 227         {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
 228         {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
 229         {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
 230         {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
 231         {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
 232         {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
 233         {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
 234         {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
 235         {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
 236         {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
 237         {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
 238         {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
 239         {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
 240         {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
 241         {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
 242         {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
 243         {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
 244         {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
 245         {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
 246         {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
 247         {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
 248         {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
 249         {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
 250         {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
 251         {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
 252         {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
 253         {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
 254         {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
 255         {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
 256         {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
 257         {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
 258         {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
 259         {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
 260         {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
 261         {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
 262         {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
 263         {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
 264         {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
 265         {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
 266         {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
 267         {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
 268         {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
 269         {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
 270         {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
 271         {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
 272         {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
 273         {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
 274         {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
 275         {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
 276         {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
 277         {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
 278         {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
 279         {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
 280         {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
 281         {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
 282         {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
 283         {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
 284         {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
 285         {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
 286         {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
 287         {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
 288         {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
 289         {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
 290         {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
 291         {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
 292         {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
 293         {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
 294         {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
 295         {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
 296         {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
 297         {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
 298         {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
 299         {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
 300         {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
 301         {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
 302         {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
 303         {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
 304 };
 305
 306 /* kind of ENABLE for the second counter */
 307 enum clock_config_register_bits {
 308         CounterSwap = 0x1 << 21
 309 };
 310
 311 /* ioconfigreg */
 312 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
 313 {
 314         if (pfi_channel % 2)
 315                 return 0;
 316         else
 317                 return 8;
 318 }
 319
 320 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
 321 {
 322         return 0x3 << ioconfig_bitshift(pfi_channel);
 323 }
 324
 325 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
 326                                               unsigned output_select)
 327 {
 328         return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
 329 }
 330
 331 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
 332 {
 333         return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
 334 }
 335
 336 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
 337                                              unsigned input_select)
 338 {
 339         return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
 340 }
 341
 342 /* dma configuration register bits */
 343 static inline unsigned dma_select_mask(unsigned dma_channel)
 344 {
 345         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 346         return 0x1f << (8 * dma_channel);
 347 }
 348
 349 enum dma_selection {
 350         dma_selection_none = 0x1f,
 351 };
 352 static inline unsigned dma_selection_counter(unsigned counter_index)
 353 {
 354         BUG_ON(counter_index >= counters_per_chip);
 355         return counter_index;
 356 }
 357
 358 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
 359 {
 360         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 361         return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
 362 }
 363
 364 static inline unsigned dma_reset_bit(unsigned dma_channel)
 365 {
 366         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 367         return 0x80 << (8 * dma_channel);
 368 }
 369
 370 enum global_interrupt_status_register_bits {
 371         Counter_0_Int_Bit = 0x100,
 372         Counter_1_Int_Bit = 0x200,
 373         Counter_2_Int_Bit = 0x400,
 374         Counter_3_Int_Bit = 0x800,
 375         Cascade_Int_Bit = 0x20000000,
 376         Global_Int_Bit = 0x80000000
 377 };
 378
 379 enum global_interrupt_config_register_bits {
 380         Cascade_Int_Enable_Bit = 0x20000000,
 381         Global_Int_Polarity_Bit = 0x40000000,
 382         Global_Int_Enable_Bit = 0x80000000
 383 };
 384
 385 /* Offset of the GPCT chips from the base-address of the card */
 386 /* First chip is at base-address + 0x00, etc. */
 387 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
 388
 389 /* Board description*/
 390 struct ni_660x_board {
 391         unsigned short dev_id;  /* `lspci` will show you this */
 392         const char *name;
 393         unsigned n_chips;       /* total number of TIO chips */
 394 };
 395
 396 static const struct ni_660x_board ni_660x_boards[] = {
 397         {
 398          .dev_id = 0x2c60,
 399          .name = "PCI-6601",
 400          .n_chips = 1,
 401          },
 402         {
 403          .dev_id = 0x1310,
 404          .name = "PCI-6602",
 405          .n_chips = 2,
 406          },
 407         {
 408          .dev_id = 0x1360,
 409          .name = "PXI-6602",
 410          .n_chips = 2,
 411          },
 412         {
 413          .dev_id = 0x2cc0,
 414          .name = "PXI-6608",
 415          .n_chips = 2,
 416          },
 417 };
 418
 419 #define NI_660X_MAX_NUM_CHIPS 2
 420 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
 421
 422 static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
 423         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c60)},
 424         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1310)},
 425         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1360)},
 426         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2cc0)},
 427         {0}
 428 };
 429
 430 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
 431
 432 struct ni_660x_private {
 433         struct mite_struct *mite;
 434         struct ni_gpct_device *counter_dev;
 435         uint64_t pfi_direction_bits;
 436         struct mite_dma_descriptor_ring
 437         *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
 438         spinlock_t mite_channel_lock;
 439         /* interrupt_lock prevents races between interrupt and comedi_poll */
 440         spinlock_t interrupt_lock;
 441         unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
 442         spinlock_t soft_reg_copy_lock;
 443         unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
 444 };
 445
 446 /* initialized in ni_660x_attach_pci() */
 447 static inline const struct ni_660x_board *board(struct comedi_device *dev)
 448 {
 449         return dev->board_ptr;
 450 }
 451
 452 static int ni_660x_attach_pci(struct comedi_device *dev,
 453                               struct pci_dev *pcidev);
 454 static void ni_660x_detach(struct comedi_device *dev);
 455 static void init_tio_chip(struct comedi_device *dev, int chipset);
 456 static void ni_660x_select_pfi_output(struct comedi_device *dev,
 457                                       unsigned pfi_channel,
 458                                       unsigned output_select);
 459
 460 static struct comedi_driver ni_660x_driver = {
 461         .driver_name = "ni_660x",
 462         .module = THIS_MODULE,
 463         .attach_pci = ni_660x_attach_pci,
 464         .detach = ni_660x_detach,
 465 };
 466
 467 static int __devinit ni_660x_pci_probe(struct pci_dev *dev,
 468                                        const struct pci_device_id *ent)
 469 {
 470         return comedi_pci_auto_config(dev, &ni_660x_driver);
 471 }
 472
 473 static void __devexit ni_660x_pci_remove(struct pci_dev *dev)
 474 {
 475         comedi_pci_auto_unconfig(dev);
 476 }
 477
 478 static struct pci_driver ni_660x_pci_driver = {
 479         .name = "ni_660x",
 480         .id_table = ni_660x_pci_table,
 481         .probe = ni_660x_pci_probe,
 482         .remove = __devexit_p(ni_660x_pci_remove)
 483 };
 484 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
 485
 486 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
 487                                    unsigned source);
 488
 489 /* Possible instructions for a GPCT */
 490 static int ni_660x_GPCT_rinsn(struct comedi_device *dev,
 491                               struct comedi_subdevice *s,
 492                               struct comedi_insn *insn, unsigned int *data);
 493 static int ni_660x_GPCT_insn_config(struct comedi_device *dev,
 494                                     struct comedi_subdevice *s,
 495                                     struct comedi_insn *insn,
 496                                     unsigned int *data);
 497 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
 498                               struct comedi_subdevice *s,
 499                               struct comedi_insn *insn, unsigned int *data);
 500
 501 /* Possible instructions for Digital IO */
 502 static int ni_660x_dio_insn_config(struct comedi_device *dev,
 503                                    struct comedi_subdevice *s,
 504                                    struct comedi_insn *insn,
 505                                    unsigned int *data);
 506 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
 507                                  struct comedi_subdevice *s,
 508                                  struct comedi_insn *insn, unsigned int *data);
 509
 510 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
 511 {
 512         return board(dev)->n_chips * counters_per_chip;
 513 }
 514
 515 static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
 516 {
 517         enum NI_660x_Register ni_660x_register;
 518         switch (reg) {
 519         case NITIO_G0_Autoincrement_Reg:
 520                 ni_660x_register = G0AutoincrementRegister;
 521                 break;
 522         case NITIO_G1_Autoincrement_Reg:
 523                 ni_660x_register = G1AutoincrementRegister;
 524                 break;
 525         case NITIO_G2_Autoincrement_Reg:
 526                 ni_660x_register = G2AutoincrementRegister;
 527                 break;
 528         case NITIO_G3_Autoincrement_Reg:
 529                 ni_660x_register = G3AutoincrementRegister;
 530                 break;
 531         case NITIO_G0_Command_Reg:
 532                 ni_660x_register = G0CommandRegister;
 533                 break;
 534         case NITIO_G1_Command_Reg:
 535                 ni_660x_register = G1CommandRegister;
 536                 break;
 537         case NITIO_G2_Command_Reg:
 538                 ni_660x_register = G2CommandRegister;
 539                 break;
 540         case NITIO_G3_Command_Reg:
 541                 ni_660x_register = G3CommandRegister;
 542                 break;
 543         case NITIO_G0_HW_Save_Reg:
 544                 ni_660x_register = G0HWSaveRegister;
 545                 break;
 546         case NITIO_G1_HW_Save_Reg:
 547                 ni_660x_register = G1HWSaveRegister;
 548                 break;
 549         case NITIO_G2_HW_Save_Reg:
 550                 ni_660x_register = G2HWSaveRegister;
 551                 break;
 552         case NITIO_G3_HW_Save_Reg:
 553                 ni_660x_register = G3HWSaveRegister;
 554                 break;
 555         case NITIO_G0_SW_Save_Reg:
 556                 ni_660x_register = G0SWSaveRegister;
 557                 break;
 558         case NITIO_G1_SW_Save_Reg:
 559                 ni_660x_register = G1SWSaveRegister;
 560                 break;
 561         case NITIO_G2_SW_Save_Reg:
 562                 ni_660x_register = G2SWSaveRegister;
 563                 break;
 564         case NITIO_G3_SW_Save_Reg:
 565                 ni_660x_register = G3SWSaveRegister;
 566                 break;
 567         case NITIO_G0_Mode_Reg:
 568                 ni_660x_register = G0ModeRegister;
 569                 break;
 570         case NITIO_G1_Mode_Reg:
 571                 ni_660x_register = G1ModeRegister;
 572                 break;
 573         case NITIO_G2_Mode_Reg:
 574                 ni_660x_register = G2ModeRegister;
 575                 break;
 576         case NITIO_G3_Mode_Reg:
 577                 ni_660x_register = G3ModeRegister;
 578                 break;
 579         case NITIO_G0_LoadA_Reg:
 580                 ni_660x_register = G0LoadARegister;
 581                 break;
 582         case NITIO_G1_LoadA_Reg:
 583                 ni_660x_register = G1LoadARegister;
 584                 break;
 585         case NITIO_G2_LoadA_Reg:
 586                 ni_660x_register = G2LoadARegister;
 587                 break;
 588         case NITIO_G3_LoadA_Reg:
 589                 ni_660x_register = G3LoadARegister;
 590                 break;
 591         case NITIO_G0_LoadB_Reg:
 592                 ni_660x_register = G0LoadBRegister;
 593                 break;
 594         case NITIO_G1_LoadB_Reg:
 595                 ni_660x_register = G1LoadBRegister;
 596                 break;
 597         case NITIO_G2_LoadB_Reg:
 598                 ni_660x_register = G2LoadBRegister;
 599                 break;
 600         case NITIO_G3_LoadB_Reg:
 601                 ni_660x_register = G3LoadBRegister;
 602                 break;
 603         case NITIO_G0_Input_Select_Reg:
 604                 ni_660x_register = G0InputSelectRegister;
 605                 break;
 606         case NITIO_G1_Input_Select_Reg:
 607                 ni_660x_register = G1InputSelectRegister;
 608                 break;
 609         case NITIO_G2_Input_Select_Reg:
 610                 ni_660x_register = G2InputSelectRegister;
 611                 break;
 612         case NITIO_G3_Input_Select_Reg:
 613                 ni_660x_register = G3InputSelectRegister;
 614                 break;
 615         case NITIO_G01_Status_Reg:
 616                 ni_660x_register = G01StatusRegister;
 617                 break;
 618         case NITIO_G23_Status_Reg:
 619                 ni_660x_register = G23StatusRegister;
 620                 break;
 621         case NITIO_G01_Joint_Reset_Reg:
 622                 ni_660x_register = G01JointResetRegister;
 623                 break;
 624         case NITIO_G23_Joint_Reset_Reg:
 625                 ni_660x_register = G23JointResetRegister;
 626                 break;
 627         case NITIO_G01_Joint_Status1_Reg:
 628                 ni_660x_register = G01JointStatus1Register;
 629                 break;
 630         case NITIO_G23_Joint_Status1_Reg:
 631                 ni_660x_register = G23JointStatus1Register;
 632                 break;
 633         case NITIO_G01_Joint_Status2_Reg:
 634                 ni_660x_register = G01JointStatus2Register;
 635                 break;
 636         case NITIO_G23_Joint_Status2_Reg:
 637                 ni_660x_register = G23JointStatus2Register;
 638                 break;
 639         case NITIO_G0_Counting_Mode_Reg:
 640                 ni_660x_register = G0CountingModeRegister;
 641                 break;
 642         case NITIO_G1_Counting_Mode_Reg:
 643                 ni_660x_register = G1CountingModeRegister;
 644                 break;
 645         case NITIO_G2_Counting_Mode_Reg:
 646                 ni_660x_register = G2CountingModeRegister;
 647                 break;
 648         case NITIO_G3_Counting_Mode_Reg:
 649                 ni_660x_register = G3CountingModeRegister;
 650                 break;
 651         case NITIO_G0_Second_Gate_Reg:
 652                 ni_660x_register = G0SecondGateRegister;
 653                 break;
 654         case NITIO_G1_Second_Gate_Reg:
 655                 ni_660x_register = G1SecondGateRegister;
 656                 break;
 657         case NITIO_G2_Second_Gate_Reg:
 658                 ni_660x_register = G2SecondGateRegister;
 659                 break;
 660         case NITIO_G3_Second_Gate_Reg:
 661                 ni_660x_register = G3SecondGateRegister;
 662                 break;
 663         case NITIO_G0_DMA_Config_Reg:
 664                 ni_660x_register = G0DMAConfigRegister;
 665                 break;
 666         case NITIO_G0_DMA_Status_Reg:
 667                 ni_660x_register = G0DMAStatusRegister;
 668                 break;
 669         case NITIO_G1_DMA_Config_Reg:
 670                 ni_660x_register = G1DMAConfigRegister;
 671                 break;
 672         case NITIO_G1_DMA_Status_Reg:
 673                 ni_660x_register = G1DMAStatusRegister;
 674                 break;
 675         case NITIO_G2_DMA_Config_Reg:
 676                 ni_660x_register = G2DMAConfigRegister;
 677                 break;
 678         case NITIO_G2_DMA_Status_Reg:
 679                 ni_660x_register = G2DMAStatusRegister;
 680                 break;
 681         case NITIO_G3_DMA_Config_Reg:
 682                 ni_660x_register = G3DMAConfigRegister;
 683                 break;
 684         case NITIO_G3_DMA_Status_Reg:
 685                 ni_660x_register = G3DMAStatusRegister;
 686                 break;
 687         case NITIO_G0_Interrupt_Acknowledge_Reg:
 688                 ni_660x_register = G0InterruptAcknowledge;
 689                 break;
 690         case NITIO_G1_Interrupt_Acknowledge_Reg:
 691                 ni_660x_register = G1InterruptAcknowledge;
 692                 break;
 693         case NITIO_G2_Interrupt_Acknowledge_Reg:
 694                 ni_660x_register = G2InterruptAcknowledge;
 695                 break;
 696         case NITIO_G3_Interrupt_Acknowledge_Reg:
 697                 ni_660x_register = G3InterruptAcknowledge;
 698                 break;
 699         case NITIO_G0_Status_Reg:
 700                 ni_660x_register = G0StatusRegister;
 701                 break;
 702         case NITIO_G1_Status_Reg:
 703                 ni_660x_register = G1StatusRegister;
 704                 break;
 705         case NITIO_G2_Status_Reg:
 706                 ni_660x_register = G2StatusRegister;
 707                 break;
 708         case NITIO_G3_Status_Reg:
 709                 ni_660x_register = G3StatusRegister;
 710                 break;
 711         case NITIO_G0_Interrupt_Enable_Reg:
 712                 ni_660x_register = G0InterruptEnable;
 713                 break;
 714         case NITIO_G1_Interrupt_Enable_Reg:
 715                 ni_660x_register = G1InterruptEnable;
 716                 break;
 717         case NITIO_G2_Interrupt_Enable_Reg:
 718                 ni_660x_register = G2InterruptEnable;
 719                 break;
 720         case NITIO_G3_Interrupt_Enable_Reg:
 721                 ni_660x_register = G3InterruptEnable;
 722                 break;
 723         default:
 724                 BUG();
 725                 return 0;
 726                 break;
 727         }
 728         return ni_660x_register;
 729 }
 730
 731 static inline void ni_660x_write_register(struct comedi_device *dev,
 732                                           unsigned chip_index, unsigned bits,
 733                                           enum NI_660x_Register reg)
 734 {
 735         struct ni_660x_private *devpriv = dev->private;
 736         void __iomem *write_address =
 737             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 738             registerData[reg].offset;
 739
 740         switch (registerData[reg].size) {
 741         case DATA_2B:
 742                 writew(bits, write_address);
 743                 break;
 744         case DATA_4B:
 745                 writel(bits, write_address);
 746                 break;
 747         default:
 748                 BUG();
 749                 break;
 750         }
 751 }
 752
 753 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
 754                                              unsigned chip_index,
 755                                              enum NI_660x_Register reg)
 756 {
 757         struct ni_660x_private *devpriv = dev->private;
 758         void __iomem *read_address =
 759             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 760             registerData[reg].offset;
 761
 762         switch (registerData[reg].size) {
 763         case DATA_2B:
 764                 return readw(read_address);
 765                 break;
 766         case DATA_4B:
 767                 return readl(read_address);
 768                 break;
 769         default:
 770                 BUG();
 771                 break;
 772         }
 773         return 0;
 774 }
 775
 776 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
 777                                    enum ni_gpct_register reg)
 778 {
 779         struct comedi_device *dev = counter->counter_dev->dev;
 780         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 781         ni_660x_write_register(dev, counter->chip_index, bits,
 782                                ni_660x_register);
 783 }
 784
 785 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
 786                                       enum ni_gpct_register reg)
 787 {
 788         struct comedi_device *dev = counter->counter_dev->dev;
 789         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 790         return ni_660x_read_register(dev, counter->chip_index,
 791                                      ni_660x_register);
 792 }
 793
 794 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
 795                                                          *priv,
 796                                                          struct ni_gpct
 797                                                          *counter)
 798 {
 799         return priv->mite_rings[counter->chip_index][counter->counter_index];
 800 }
 801
 802 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
 803                                            unsigned mite_channel,
 804                                            struct ni_gpct *counter)
 805 {
 806         struct ni_660x_private *devpriv = dev->private;
 807         unsigned long flags;
 808
 809         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 810         devpriv->dma_configuration_soft_copies[counter->chip_index] &=
 811             ~dma_select_mask(mite_channel);
 812         devpriv->dma_configuration_soft_copies[counter->chip_index] |=
 813             dma_select_bits(mite_channel,
 814                             dma_selection_counter(counter->counter_index));
 815         ni_660x_write_register(dev, counter->chip_index,
 816                                devpriv->dma_configuration_soft_copies
 817                                [counter->chip_index] |
 818                                dma_reset_bit(mite_channel), DMAConfigRegister);
 819         mmiowb();
 820         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 821 }
 822
 823 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
 824                                              unsigned mite_channel,
 825                                              struct ni_gpct *counter)
 826 {
 827         struct ni_660x_private *devpriv = dev->private;
 828         unsigned long flags;
 829
 830         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 831         devpriv->dma_configuration_soft_copies[counter->chip_index] &=
 832             ~dma_select_mask(mite_channel);
 833         devpriv->dma_configuration_soft_copies[counter->chip_index] |=
 834             dma_select_bits(mite_channel, dma_selection_none);
 835         ni_660x_write_register(dev, counter->chip_index,
 836                                devpriv->dma_configuration_soft_copies
 837                                [counter->chip_index], DMAConfigRegister);
 838         mmiowb();
 839         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 840 }
 841
 842 static int ni_660x_request_mite_channel(struct comedi_device *dev,
 843                                         struct ni_gpct *counter,
 844                                         enum comedi_io_direction direction)
 845 {
 846         struct ni_660x_private *devpriv = dev->private;
 847         unsigned long flags;
 848         struct mite_channel *mite_chan;
 849
 850         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 851         BUG_ON(counter->mite_chan);
 852         mite_chan = mite_request_channel(devpriv->mite,
 853                                          mite_ring(devpriv, counter));
 854         if (mite_chan == NULL) {
 855                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 856                 comedi_error(dev,
 857                              "failed to reserve mite dma channel for counter.");
 858                 return -EBUSY;
 859         }
 860         mite_chan->dir = direction;
 861         ni_tio_set_mite_channel(counter, mite_chan);
 862         ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
 863         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 864         return 0;
 865 }
 866
 867 static void ni_660x_release_mite_channel(struct comedi_device *dev,
 868                                          struct ni_gpct *counter)
 869 {
 870         struct ni_660x_private *devpriv = dev->private;
 871         unsigned long flags;
 872
 873         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 874         if (counter->mite_chan) {
 875                 struct mite_channel *mite_chan = counter->mite_chan;
 876
 877                 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
 878                 ni_tio_set_mite_channel(counter, NULL);
 879                 mite_release_channel(mite_chan);
 880         }
 881         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 882 }
 883
 884 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 885 {
 886         int retval;
 887
 888         struct ni_gpct *counter = subdev_to_counter(s);
 889 /* const struct comedi_cmd *cmd = &s->async->cmd; */
 890
 891         retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
 892         if (retval) {
 893                 comedi_error(dev,
 894                              "no dma channel available for use by counter");
 895                 return retval;
 896         }
 897         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
 898         retval = ni_tio_cmd(counter, s->async);
 899
 900         return retval;
 901 }
 902
 903 static int ni_660x_cmdtest(struct comedi_device *dev,
 904                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
 905 {
 906         struct ni_gpct *counter = subdev_to_counter(s);
 907
 908         return ni_tio_cmdtest(counter, cmd);
 909 }
 910
 911 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
 912 {
 913         struct ni_gpct *counter = subdev_to_counter(s);
 914         int retval;
 915
 916         retval = ni_tio_cancel(counter);
 917         ni_660x_release_mite_channel(dev, counter);
 918         return retval;
 919 }
 920
 921 static void set_tio_counterswap(struct comedi_device *dev, int chipset)
 922 {
 923         /* See P. 3.5 of the Register-Level Programming manual.  The
 924            CounterSwap bit has to be set on the second chip, otherwise
 925            it will try to use the same pins as the first chip.
 926          */
 927         if (chipset)
 928                 ni_660x_write_register(dev, chipset, CounterSwap,
 929                                        ClockConfigRegister);
 930         else
 931                 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
 932 }
 933
 934 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
 935                                           struct comedi_subdevice *s)
 936 {
 937         ni_tio_handle_interrupt(subdev_to_counter(s), s);
 938         if (s->async->events) {
 939                 if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
 940                                         COMEDI_CB_OVERFLOW)) {
 941                         ni_660x_cancel(dev, s);
 942                 }
 943                 comedi_event(dev, s);
 944         }
 945 }
 946
 947 static irqreturn_t ni_660x_interrupt(int irq, void *d)
 948 {
 949         struct comedi_device *dev = d;
 950         struct ni_660x_private *devpriv = dev->private;
 951         struct comedi_subdevice *s;
 952         unsigned i;
 953         unsigned long flags;
 954
 955         if (dev->attached == 0)
 956                 return IRQ_NONE;
 957         /* lock to avoid race with comedi_poll */
 958         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
 959         smp_mb();
 960         for (i = 0; i < ni_660x_num_counters(dev); ++i) {
 961                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
 962                 ni_660x_handle_gpct_interrupt(dev, s);
 963         }
 964         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
 965         return IRQ_HANDLED;
 966 }
 967
 968 static int ni_660x_input_poll(struct comedi_device *dev,
 969                               struct comedi_subdevice *s)
 970 {
 971         struct ni_660x_private *devpriv = dev->private;
 972         unsigned long flags;
 973
 974         /* lock to avoid race with comedi_poll */
 975         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
 976         mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
 977         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
 978         return comedi_buf_read_n_available(s->async);
 979 }
 980
 981 static int ni_660x_buf_change(struct comedi_device *dev,
 982                               struct comedi_subdevice *s,
 983                               unsigned long new_size)
 984 {
 985         struct ni_660x_private *devpriv = dev->private;
 986         int ret;
 987
 988         ret = mite_buf_change(mite_ring(devpriv, subdev_to_counter(s)),
 989                               s->async);
 990         if (ret < 0)
 991                 return ret;
 992
 993         return 0;
 994 }
 995
 996 static int ni_660x_allocate_private(struct comedi_device *dev)
 997 {
 998         struct ni_660x_private *devpriv;
 999         unsigned i;
1000
1001         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1002         if (!devpriv)
1003                 return -ENOMEM;
1004         dev->private = devpriv;
1005
1006         spin_lock_init(&devpriv->mite_channel_lock);
1007         spin_lock_init(&devpriv->interrupt_lock);
1008         spin_lock_init(&devpriv->soft_reg_copy_lock);
1009         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1010                 devpriv->pfi_output_selects[i] = pfi_output_select_counter;
1011
1012         return 0;
1013 }
1014
1015 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
1016 {
1017         struct ni_660x_private *devpriv = dev->private;
1018         unsigned i;
1019         unsigned j;
1020
1021         for (i = 0; i < board(dev)->n_chips; ++i) {
1022                 for (j = 0; j < counters_per_chip; ++j) {
1023                         devpriv->mite_rings[i][j] =
1024                             mite_alloc_ring(devpriv->mite);
1025                         if (devpriv->mite_rings[i][j] == NULL)
1026                                 return -ENOMEM;
1027                 }
1028         }
1029         return 0;
1030 }
1031
1032 static void ni_660x_free_mite_rings(struct comedi_device *dev)
1033 {
1034         struct ni_660x_private *devpriv = dev->private;
1035         unsigned i;
1036         unsigned j;
1037
1038         for (i = 0; i < board(dev)->n_chips; ++i) {
1039                 for (j = 0; j < counters_per_chip; ++j)
1040                         mite_free_ring(devpriv->mite_rings[i][j]);
1041         }
1042 }
1043
1044 static const struct ni_660x_board *
1045 ni_660x_find_boardinfo(struct pci_dev *pcidev)
1046 {
1047         unsigned int dev_id = pcidev->device;
1048         unsigned int n;
1049
1050         for (n = 0; n < ARRAY_SIZE(ni_660x_boards); n++) {
1051                 const struct ni_660x_board *board = &ni_660x_boards[n];
1052                 if (board->dev_id == dev_id)
1053                         return board;
1054         }
1055         return NULL;
1056 }
1057
1058 static int __devinit ni_660x_attach_pci(struct comedi_device *dev,
1059                                         struct pci_dev *pcidev)
1060 {
1061         struct ni_660x_private *devpriv;
1062         struct comedi_subdevice *s;
1063         int ret;
1064         unsigned i;
1065         unsigned global_interrupt_config_bits;
1066
1067         ret = ni_660x_allocate_private(dev);
1068         if (ret < 0)
1069                 return ret;
1070         devpriv = dev->private;
1071
1072         dev->board_ptr = ni_660x_find_boardinfo(pcidev);
1073         if (!dev->board_ptr)
1074                 return -ENODEV;
1075         devpriv->mite = mite_alloc(pcidev);
1076         if (!devpriv->mite)
1077                 return -ENOMEM;
1078
1079         dev->board_name = board(dev)->name;
1080
1081         ret = mite_setup2(devpriv->mite, 1);
1082         if (ret < 0) {
1083                 dev_warn(dev->class_dev, "error setting up mite\n");
1084                 return ret;
1085         }
1086         comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1087         ret = ni_660x_alloc_mite_rings(dev);
1088         if (ret < 0)
1089                 return ret;
1090
1091         ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS);
1092         if (ret)
1093                 return ret;
1094
1095         s = &dev->subdevices[0];
1096         /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1097         s->type = COMEDI_SUBD_UNUSED;
1098
1099         s = &dev->subdevices[NI_660X_DIO_SUBDEV];
1100         /* DIGITAL I/O SUBDEVICE */
1101         s->type = COMEDI_SUBD_DIO;
1102         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1103         s->n_chan = NUM_PFI_CHANNELS;
1104         s->maxdata = 1;
1105         s->range_table = &range_digital;
1106         s->insn_bits = ni_660x_dio_insn_bits;
1107         s->insn_config = ni_660x_dio_insn_config;
1108         s->io_bits = 0;         /* all bits default to input */
1109         /*  we use the ioconfig registers to control dio direction, so zero
1110         output enables in stc dio control reg */
1111         ni_660x_write_register(dev, 0, 0, STCDIOControl);
1112
1113         devpriv->counter_dev = ni_gpct_device_construct(dev,
1114                                                      &ni_gpct_write_register,
1115                                                      &ni_gpct_read_register,
1116                                                      ni_gpct_variant_660x,
1117                                                      ni_660x_num_counters
1118                                                      (dev));
1119         if (devpriv->counter_dev == NULL)
1120                 return -ENOMEM;
1121         for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1122                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
1123                 if (i < ni_660x_num_counters(dev)) {
1124                         s->type = COMEDI_SUBD_COUNTER;
1125                         s->subdev_flags =
1126                             SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1127                             SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1128                         s->n_chan = 3;
1129                         s->maxdata = 0xffffffff;
1130                         s->insn_read = ni_660x_GPCT_rinsn;
1131                         s->insn_write = ni_660x_GPCT_winsn;
1132                         s->insn_config = ni_660x_GPCT_insn_config;
1133                         s->do_cmd = &ni_660x_cmd;
1134                         s->len_chanlist = 1;
1135                         s->do_cmdtest = &ni_660x_cmdtest;
1136                         s->cancel = &ni_660x_cancel;
1137                         s->poll = &ni_660x_input_poll;
1138                         s->async_dma_dir = DMA_BIDIRECTIONAL;
1139                         s->buf_change = &ni_660x_buf_change;
1140                         s->private = &devpriv->counter_dev->counters[i];
1141
1142                         devpriv->counter_dev->counters[i].chip_index =
1143                             i / counters_per_chip;
1144                         devpriv->counter_dev->counters[i].counter_index =
1145                             i % counters_per_chip;
1146                 } else {
1147                         s->type = COMEDI_SUBD_UNUSED;
1148                 }
1149         }
1150         for (i = 0; i < board(dev)->n_chips; ++i)
1151                 init_tio_chip(dev, i);
1152
1153         for (i = 0; i < ni_660x_num_counters(dev); ++i)
1154                 ni_tio_init_counter(&devpriv->counter_dev->counters[i]);
1155
1156         for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1157                 if (i < min_counter_pfi_chan)
1158                         ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1159                 else
1160                         ni_660x_set_pfi_routing(dev, i,
1161                                                 pfi_output_select_counter);
1162                 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1163         }
1164         /* to be safe, set counterswap bits on tio chips after all the counter
1165            outputs have been set to high impedance mode */
1166         for (i = 0; i < board(dev)->n_chips; ++i)
1167                 set_tio_counterswap(dev, i);
1168
1169         ret = request_irq(mite_irq(devpriv->mite), ni_660x_interrupt,
1170                           IRQF_SHARED, "ni_660x", dev);
1171         if (ret < 0) {
1172                 dev_warn(dev->class_dev, " irq not available\n");
1173                 return ret;
1174         }
1175         dev->irq = mite_irq(devpriv->mite);
1176         global_interrupt_config_bits = Global_Int_Enable_Bit;
1177         if (board(dev)->n_chips > 1)
1178                 global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1179         ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1180                                GlobalInterruptConfigRegister);
1181         dev_info(dev->class_dev, "ni_660x: %s attached\n", dev->board_name);
1182         return 0;
1183 }
1184
1185 static void ni_660x_detach(struct comedi_device *dev)
1186 {
1187         struct ni_660x_private *devpriv = dev->private;
1188
1189         if (dev->irq)
1190                 free_irq(dev->irq, dev);
1191         if (devpriv) {
1192                 if (devpriv->counter_dev)
1193                         ni_gpct_device_destroy(devpriv->counter_dev);
1194                 if (devpriv->mite) {
1195                         ni_660x_free_mite_rings(dev);
1196                         mite_unsetup(devpriv->mite);
1197                         mite_free(devpriv->mite);
1198                 }
1199         }
1200 }
1201
1202 static int
1203 ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1204                    struct comedi_insn *insn, unsigned int *data)
1205 {
1206         return ni_tio_rinsn(subdev_to_counter(s), insn, data);
1207 }
1208
1209 static void init_tio_chip(struct comedi_device *dev, int chipset)
1210 {
1211         struct ni_660x_private *devpriv = dev->private;
1212         unsigned i;
1213
1214         /*  init dma configuration register */
1215         devpriv->dma_configuration_soft_copies[chipset] = 0;
1216         for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
1217                 devpriv->dma_configuration_soft_copies[chipset] |=
1218                     dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
1219         }
1220         ni_660x_write_register(dev, chipset,
1221                                devpriv->dma_configuration_soft_copies[chipset],
1222                                DMAConfigRegister);
1223         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1224                 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1225 }
1226
1227 static int
1228 ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1229                          struct comedi_insn *insn, unsigned int *data)
1230 {
1231         return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1232 }
1233
1234 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1235                               struct comedi_subdevice *s,
1236                               struct comedi_insn *insn, unsigned int *data)
1237 {
1238         return ni_tio_winsn(subdev_to_counter(s), insn, data);
1239 }
1240
1241 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1242                                  struct comedi_subdevice *s,
1243                                  struct comedi_insn *insn, unsigned int *data)
1244 {
1245         unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1246
1247         /*  Check if we have to write some bits */
1248         if (data[0]) {
1249                 s->state &= ~(data[0] << base_bitfield_channel);
1250                 s->state |= (data[0] & data[1]) << base_bitfield_channel;
1251                 /* Write out the new digital output lines */
1252                 ni_660x_write_register(dev, 0, s->state, DIO32Output);
1253         }
1254         /* on return, data[1] contains the value of the digital
1255          * input and output lines. */
1256         data[1] =
1257             (ni_660x_read_register(dev, 0,
1258                                    DIO32Input) >> base_bitfield_channel);
1259         return insn->n;
1260 }
1261
1262 static void ni_660x_select_pfi_output(struct comedi_device *dev,
1263                                       unsigned pfi_channel,
1264                                       unsigned output_select)
1265 {
1266         static const unsigned counter_4_7_first_pfi = 8;
1267         static const unsigned counter_4_7_last_pfi = 23;
1268         unsigned active_chipset = 0;
1269         unsigned idle_chipset = 0;
1270         unsigned active_bits;
1271         unsigned idle_bits;
1272
1273         if (board(dev)->n_chips > 1) {
1274                 if (output_select == pfi_output_select_counter &&
1275                     pfi_channel >= counter_4_7_first_pfi &&
1276                     pfi_channel <= counter_4_7_last_pfi) {
1277                         active_chipset = 1;
1278                         idle_chipset = 0;
1279                 } else {
1280                         active_chipset = 0;
1281                         idle_chipset = 1;
1282                 }
1283         }
1284
1285         if (idle_chipset != active_chipset) {
1286                 idle_bits =
1287                     ni_660x_read_register(dev, idle_chipset,
1288                                           IOConfigReg(pfi_channel));
1289                 idle_bits &= ~pfi_output_select_mask(pfi_channel);
1290                 idle_bits |=
1291                     pfi_output_select_bits(pfi_channel,
1292                                            pfi_output_select_high_Z);
1293                 ni_660x_write_register(dev, idle_chipset, idle_bits,
1294                                        IOConfigReg(pfi_channel));
1295         }
1296
1297         active_bits =
1298             ni_660x_read_register(dev, active_chipset,
1299                                   IOConfigReg(pfi_channel));
1300         active_bits &= ~pfi_output_select_mask(pfi_channel);
1301         active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1302         ni_660x_write_register(dev, active_chipset, active_bits,
1303                                IOConfigReg(pfi_channel));
1304 }
1305
1306 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1307                                    unsigned source)
1308 {
1309         struct ni_660x_private *devpriv = dev->private;
1310
1311         if (source > num_pfi_output_selects)
1312                 return -EINVAL;
1313         if (source == pfi_output_select_high_Z)
1314                 return -EINVAL;
1315         if (chan < min_counter_pfi_chan) {
1316                 if (source == pfi_output_select_counter)
1317                         return -EINVAL;
1318         } else if (chan > max_dio_pfi_chan) {
1319                 if (source == pfi_output_select_do)
1320                         return -EINVAL;
1321         }
1322         BUG_ON(chan >= NUM_PFI_CHANNELS);
1323
1324         devpriv->pfi_output_selects[chan] = source;
1325         if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan))
1326                 ni_660x_select_pfi_output(dev, chan,
1327                                           devpriv->pfi_output_selects[chan]);
1328         return 0;
1329 }
1330
1331 static unsigned ni_660x_get_pfi_routing(struct comedi_device *dev,
1332                                         unsigned chan)
1333 {
1334         struct ni_660x_private *devpriv = dev->private;
1335
1336         BUG_ON(chan >= NUM_PFI_CHANNELS);
1337         return devpriv->pfi_output_selects[chan];
1338 }
1339
1340 static void ni660x_config_filter(struct comedi_device *dev,
1341                                  unsigned pfi_channel,
1342                                  enum ni_gpct_filter_select filter)
1343 {
1344         unsigned bits = ni_660x_read_register(dev, 0, IOConfigReg(pfi_channel));
1345         bits &= ~pfi_input_select_mask(pfi_channel);
1346         bits |= pfi_input_select_bits(pfi_channel, filter);
1347         ni_660x_write_register(dev, 0, bits, IOConfigReg(pfi_channel));
1348 }
1349
1350 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1351                                    struct comedi_subdevice *s,
1352                                    struct comedi_insn *insn, unsigned int *data)
1353 {
1354         struct ni_660x_private *devpriv = dev->private;
1355         int chan = CR_CHAN(insn->chanspec);
1356
1357         /* The input or output configuration of each digital line is
1358          * configured by a special insn_config instruction.  chanspec
1359          * contains the channel to be changed, and data[0] contains the
1360          * value COMEDI_INPUT or COMEDI_OUTPUT. */
1361
1362         switch (data[0]) {
1363         case INSN_CONFIG_DIO_OUTPUT:
1364                 devpriv->pfi_direction_bits |= ((uint64_t) 1) << chan;
1365                 ni_660x_select_pfi_output(dev, chan,
1366                                           devpriv->pfi_output_selects[chan]);
1367                 break;
1368         case INSN_CONFIG_DIO_INPUT:
1369                 devpriv->pfi_direction_bits &= ~(((uint64_t) 1) << chan);
1370                 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1371                 break;
1372         case INSN_CONFIG_DIO_QUERY:
1373                 data[1] =
1374                     (devpriv->pfi_direction_bits &
1375                      (((uint64_t) 1) << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1376                 return 0;
1377         case INSN_CONFIG_SET_ROUTING:
1378                 return ni_660x_set_pfi_routing(dev, chan, data[1]);
1379                 break;
1380         case INSN_CONFIG_GET_ROUTING:
1381                 data[1] = ni_660x_get_pfi_routing(dev, chan);
1382                 break;
1383         case INSN_CONFIG_FILTER:
1384                 ni660x_config_filter(dev, chan, data[1]);
1385                 break;
1386         default:
1387                 return -EINVAL;
1388                 break;
1389         }
1390         return 0;
1391 }
1392
1393 MODULE_AUTHOR("Comedi http://www.comedi.org");
1394 MODULE_DESCRIPTION("Comedi low-level driver");
1395 MODULE_LICENSE("GPL");