Pileus Git - ~andy/linux/blob - drivers/staging/comedi/drivers/ni_660x.c

   1 /*
   2   comedi/drivers/ni_660x.c
   3   Hardware driver for NI 660x devices
   4
   5   This program is free software; you can redistribute it and/or modify
   6   it under the terms of the GNU General Public License as published by
   7   the Free Software Foundation; either version 2 of the License, or
   8   (at your option) any later version.
   9
  10   This program is distributed in the hope that it will be useful,
  11   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13   GNU General Public License for more details.
  14
  15   You should have received a copy of the GNU General Public License
  16   along with this program; if not, write to the Free Software
  17   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20 /*
  21 Driver: ni_660x
  22 Description: National Instruments 660x counter/timer boards
  23 Devices:
  24 [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
  25         PXI-6608
  26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  27         Herman.Bruyninckx@mech.kuleuven.ac.be,
  28         Wim.Meeussen@mech.kuleuven.ac.be,
  29         Klaas.Gadeyne@mech.kuleuven.ac.be,
  30         Frank Mori Hess <fmhess@users.sourceforge.net>
  31 Updated: Thu Oct 18 12:56:06 EDT 2007
  32 Status: experimental
  33
  34 Encoders work.  PulseGeneration (both single pulse and pulse train)
  35 works. Buffered commands work for input but not output.
  36
  37 References:
  38 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  39 DAQ 6601/6602 User Manual (NI 322137B-01)
  40
  41 */
  42
  43 #include <linux/interrupt.h>
  44 #include "../comedidev.h"
  45 #include "mite.h"
  46 #include "ni_tio.h"
  47
  48 enum ni_660x_constants {
  49         min_counter_pfi_chan = 8,
  50         max_dio_pfi_chan = 31,
  51         counters_per_chip = 4
  52 };
  53
  54 #define NUM_PFI_CHANNELS 40
  55 /* really there are only up to 3 dma channels, but the register layout allows
  56 for 4 */
  57 #define MAX_DMA_CHANNEL 4
  58
  59 /* See Register-Level Programmer Manual page 3.1 */
  60 enum NI_660x_Register {
  61         G0InterruptAcknowledge,
  62         G0StatusRegister,
  63         G1InterruptAcknowledge,
  64         G1StatusRegister,
  65         G01StatusRegister,
  66         G0CommandRegister,
  67         STCDIOParallelInput,
  68         G1CommandRegister,
  69         G0HWSaveRegister,
  70         G1HWSaveRegister,
  71         STCDIOOutput,
  72         STCDIOControl,
  73         G0SWSaveRegister,
  74         G1SWSaveRegister,
  75         G0ModeRegister,
  76         G01JointStatus1Register,
  77         G1ModeRegister,
  78         STCDIOSerialInput,
  79         G0LoadARegister,
  80         G01JointStatus2Register,
  81         G0LoadBRegister,
  82         G1LoadARegister,
  83         G1LoadBRegister,
  84         G0InputSelectRegister,
  85         G1InputSelectRegister,
  86         G0AutoincrementRegister,
  87         G1AutoincrementRegister,
  88         G01JointResetRegister,
  89         G0InterruptEnable,
  90         G1InterruptEnable,
  91         G0CountingModeRegister,
  92         G1CountingModeRegister,
  93         G0SecondGateRegister,
  94         G1SecondGateRegister,
  95         G0DMAConfigRegister,
  96         G0DMAStatusRegister,
  97         G1DMAConfigRegister,
  98         G1DMAStatusRegister,
  99         G2InterruptAcknowledge,
 100         G2StatusRegister,
 101         G3InterruptAcknowledge,
 102         G3StatusRegister,
 103         G23StatusRegister,
 104         G2CommandRegister,
 105         G3CommandRegister,
 106         G2HWSaveRegister,
 107         G3HWSaveRegister,
 108         G2SWSaveRegister,
 109         G3SWSaveRegister,
 110         G2ModeRegister,
 111         G23JointStatus1Register,
 112         G3ModeRegister,
 113         G2LoadARegister,
 114         G23JointStatus2Register,
 115         G2LoadBRegister,
 116         G3LoadARegister,
 117         G3LoadBRegister,
 118         G2InputSelectRegister,
 119         G3InputSelectRegister,
 120         G2AutoincrementRegister,
 121         G3AutoincrementRegister,
 122         G23JointResetRegister,
 123         G2InterruptEnable,
 124         G3InterruptEnable,
 125         G2CountingModeRegister,
 126         G3CountingModeRegister,
 127         G3SecondGateRegister,
 128         G2SecondGateRegister,
 129         G2DMAConfigRegister,
 130         G2DMAStatusRegister,
 131         G3DMAConfigRegister,
 132         G3DMAStatusRegister,
 133         DIO32Input,
 134         DIO32Output,
 135         ClockConfigRegister,
 136         GlobalInterruptStatusRegister,
 137         DMAConfigRegister,
 138         GlobalInterruptConfigRegister,
 139         IOConfigReg0_1,
 140         IOConfigReg2_3,
 141         IOConfigReg4_5,
 142         IOConfigReg6_7,
 143         IOConfigReg8_9,
 144         IOConfigReg10_11,
 145         IOConfigReg12_13,
 146         IOConfigReg14_15,
 147         IOConfigReg16_17,
 148         IOConfigReg18_19,
 149         IOConfigReg20_21,
 150         IOConfigReg22_23,
 151         IOConfigReg24_25,
 152         IOConfigReg26_27,
 153         IOConfigReg28_29,
 154         IOConfigReg30_31,
 155         IOConfigReg32_33,
 156         IOConfigReg34_35,
 157         IOConfigReg36_37,
 158         IOConfigReg38_39,
 159         NumRegisters,
 160 };
 161
 162 static inline unsigned IOConfigReg(unsigned pfi_channel)
 163 {
 164         unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
 165         BUG_ON(reg > IOConfigReg38_39);
 166         return reg;
 167 }
 168
 169 enum ni_660x_register_width {
 170         DATA_1B,
 171         DATA_2B,
 172         DATA_4B
 173 };
 174
 175 enum ni_660x_register_direction {
 176         NI_660x_READ,
 177         NI_660x_WRITE,
 178         NI_660x_READ_WRITE
 179 };
 180
 181 enum ni_660x_pfi_output_select {
 182         pfi_output_select_high_Z = 0,
 183         pfi_output_select_counter = 1,
 184         pfi_output_select_do = 2,
 185         num_pfi_output_selects
 186 };
 187
 188 enum ni_660x_subdevices {
 189         NI_660X_DIO_SUBDEV = 1,
 190         NI_660X_GPCT_SUBDEV_0 = 2
 191 };
 192 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
 193 {
 194         return NI_660X_GPCT_SUBDEV_0 + index;
 195 }
 196
 197 struct NI_660xRegisterData {
 198
 199         const char *name;       /*  Register Name */
 200         int offset;             /*  Offset from base address from GPCT chip */
 201         enum ni_660x_register_direction direction;
 202         enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
 203 };
 204
 205 static const struct NI_660xRegisterData registerData[NumRegisters] = {
 206         {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
 207         {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
 208         {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
 209         {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
 210         {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
 211         {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
 212         {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
 213         {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
 214         {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
 215         {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
 216         {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
 217         {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
 218         {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
 219         {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
 220         {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
 221         {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
 222         {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
 223         {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
 224         {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
 225         {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
 226         {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
 227         {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
 228         {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
 229         {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
 230         {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
 231         {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
 232         {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
 233         {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
 234         {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
 235         {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
 236         {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
 237         {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
 238         {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
 239         {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
 240         {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
 241         {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
 242         {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
 243         {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
 244         {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
 245         {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
 246         {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
 247         {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
 248         {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
 249         {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
 250         {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
 251         {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
 252         {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
 253         {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
 254         {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
 255         {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
 256         {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
 257         {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
 258         {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
 259         {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
 260         {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
 261         {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
 262         {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
 263         {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
 264         {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
 265         {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
 266         {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
 267         {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
 268         {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
 269         {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
 270         {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
 271         {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
 272         {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
 273         {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
 274         {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
 275         {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
 276         {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
 277         {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
 278         {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
 279         {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
 280         {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
 281         {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
 282         {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
 283         {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
 284         {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
 285         {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
 286         {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
 287         {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
 288         {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
 289         {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
 290         {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
 291         {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
 292         {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
 293         {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
 294         {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
 295         {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
 296         {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
 297         {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
 298         {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
 299         {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
 300         {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
 301         {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
 302         {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
 303         {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
 304 };
 305
 306 /* kind of ENABLE for the second counter */
 307 enum clock_config_register_bits {
 308         CounterSwap = 0x1 << 21
 309 };
 310
 311 /* ioconfigreg */
 312 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
 313 {
 314         if (pfi_channel % 2)
 315                 return 0;
 316         else
 317                 return 8;
 318 }
 319
 320 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
 321 {
 322         return 0x3 << ioconfig_bitshift(pfi_channel);
 323 }
 324
 325 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
 326                                               unsigned output_select)
 327 {
 328         return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
 329 }
 330
 331 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
 332 {
 333         return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
 334 }
 335
 336 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
 337                                              unsigned input_select)
 338 {
 339         return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
 340 }
 341
 342 /* dma configuration register bits */
 343 static inline unsigned dma_select_mask(unsigned dma_channel)
 344 {
 345         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 346         return 0x1f << (8 * dma_channel);
 347 }
 348
 349 enum dma_selection {
 350         dma_selection_none = 0x1f,
 351 };
 352 static inline unsigned dma_selection_counter(unsigned counter_index)
 353 {
 354         BUG_ON(counter_index >= counters_per_chip);
 355         return counter_index;
 356 }
 357
 358 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
 359 {
 360         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 361         return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
 362 }
 363
 364 static inline unsigned dma_reset_bit(unsigned dma_channel)
 365 {
 366         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 367         return 0x80 << (8 * dma_channel);
 368 }
 369
 370 enum global_interrupt_status_register_bits {
 371         Counter_0_Int_Bit = 0x100,
 372         Counter_1_Int_Bit = 0x200,
 373         Counter_2_Int_Bit = 0x400,
 374         Counter_3_Int_Bit = 0x800,
 375         Cascade_Int_Bit = 0x20000000,
 376         Global_Int_Bit = 0x80000000
 377 };
 378
 379 enum global_interrupt_config_register_bits {
 380         Cascade_Int_Enable_Bit = 0x20000000,
 381         Global_Int_Polarity_Bit = 0x40000000,
 382         Global_Int_Enable_Bit = 0x80000000
 383 };
 384
 385 /* Offset of the GPCT chips from the base-address of the card */
 386 /* First chip is at base-address + 0x00, etc. */
 387 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
 388
 389 /* Board description*/
 390 struct ni_660x_board {
 391         unsigned short dev_id;  /* `lspci` will show you this */
 392         const char *name;
 393         unsigned n_chips;       /* total number of TIO chips */
 394 };
 395
 396 static const struct ni_660x_board ni_660x_boards[] = {
 397         {
 398          .dev_id = 0x2c60,
 399          .name = "PCI-6601",
 400          .n_chips = 1,
 401          },
 402         {
 403          .dev_id = 0x1310,
 404          .name = "PCI-6602",
 405          .n_chips = 2,
 406          },
 407         {
 408          .dev_id = 0x1360,
 409          .name = "PXI-6602",
 410          .n_chips = 2,
 411          },
 412         {
 413          .dev_id = 0x2cc0,
 414          .name = "PXI-6608",
 415          .n_chips = 2,
 416          },
 417 };
 418
 419 #define NI_660X_MAX_NUM_CHIPS 2
 420 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
 421
 422 struct ni_660x_private {
 423         struct mite_struct *mite;
 424         struct ni_gpct_device *counter_dev;
 425         uint64_t pfi_direction_bits;
 426         struct mite_dma_descriptor_ring
 427         *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
 428         spinlock_t mite_channel_lock;
 429         /* interrupt_lock prevents races between interrupt and comedi_poll */
 430         spinlock_t interrupt_lock;
 431         unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
 432         spinlock_t soft_reg_copy_lock;
 433         unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
 434 };
 435
 436 /* initialized in ni_660x_attach_pci() */
 437 static inline const struct ni_660x_board *board(struct comedi_device *dev)
 438 {
 439         return dev->board_ptr;
 440 }
 441
 442 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
 443 {
 444         return board(dev)->n_chips * counters_per_chip;
 445 }
 446
 447 static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
 448 {
 449         enum NI_660x_Register ni_660x_register;
 450         switch (reg) {
 451         case NITIO_G0_Autoincrement_Reg:
 452                 ni_660x_register = G0AutoincrementRegister;
 453                 break;
 454         case NITIO_G1_Autoincrement_Reg:
 455                 ni_660x_register = G1AutoincrementRegister;
 456                 break;
 457         case NITIO_G2_Autoincrement_Reg:
 458                 ni_660x_register = G2AutoincrementRegister;
 459                 break;
 460         case NITIO_G3_Autoincrement_Reg:
 461                 ni_660x_register = G3AutoincrementRegister;
 462                 break;
 463         case NITIO_G0_Command_Reg:
 464                 ni_660x_register = G0CommandRegister;
 465                 break;
 466         case NITIO_G1_Command_Reg:
 467                 ni_660x_register = G1CommandRegister;
 468                 break;
 469         case NITIO_G2_Command_Reg:
 470                 ni_660x_register = G2CommandRegister;
 471                 break;
 472         case NITIO_G3_Command_Reg:
 473                 ni_660x_register = G3CommandRegister;
 474                 break;
 475         case NITIO_G0_HW_Save_Reg:
 476                 ni_660x_register = G0HWSaveRegister;
 477                 break;
 478         case NITIO_G1_HW_Save_Reg:
 479                 ni_660x_register = G1HWSaveRegister;
 480                 break;
 481         case NITIO_G2_HW_Save_Reg:
 482                 ni_660x_register = G2HWSaveRegister;
 483                 break;
 484         case NITIO_G3_HW_Save_Reg:
 485                 ni_660x_register = G3HWSaveRegister;
 486                 break;
 487         case NITIO_G0_SW_Save_Reg:
 488                 ni_660x_register = G0SWSaveRegister;
 489                 break;
 490         case NITIO_G1_SW_Save_Reg:
 491                 ni_660x_register = G1SWSaveRegister;
 492                 break;
 493         case NITIO_G2_SW_Save_Reg:
 494                 ni_660x_register = G2SWSaveRegister;
 495                 break;
 496         case NITIO_G3_SW_Save_Reg:
 497                 ni_660x_register = G3SWSaveRegister;
 498                 break;
 499         case NITIO_G0_Mode_Reg:
 500                 ni_660x_register = G0ModeRegister;
 501                 break;
 502         case NITIO_G1_Mode_Reg:
 503                 ni_660x_register = G1ModeRegister;
 504                 break;
 505         case NITIO_G2_Mode_Reg:
 506                 ni_660x_register = G2ModeRegister;
 507                 break;
 508         case NITIO_G3_Mode_Reg:
 509                 ni_660x_register = G3ModeRegister;
 510                 break;
 511         case NITIO_G0_LoadA_Reg:
 512                 ni_660x_register = G0LoadARegister;
 513                 break;
 514         case NITIO_G1_LoadA_Reg:
 515                 ni_660x_register = G1LoadARegister;
 516                 break;
 517         case NITIO_G2_LoadA_Reg:
 518                 ni_660x_register = G2LoadARegister;
 519                 break;
 520         case NITIO_G3_LoadA_Reg:
 521                 ni_660x_register = G3LoadARegister;
 522                 break;
 523         case NITIO_G0_LoadB_Reg:
 524                 ni_660x_register = G0LoadBRegister;
 525                 break;
 526         case NITIO_G1_LoadB_Reg:
 527                 ni_660x_register = G1LoadBRegister;
 528                 break;
 529         case NITIO_G2_LoadB_Reg:
 530                 ni_660x_register = G2LoadBRegister;
 531                 break;
 532         case NITIO_G3_LoadB_Reg:
 533                 ni_660x_register = G3LoadBRegister;
 534                 break;
 535         case NITIO_G0_Input_Select_Reg:
 536                 ni_660x_register = G0InputSelectRegister;
 537                 break;
 538         case NITIO_G1_Input_Select_Reg:
 539                 ni_660x_register = G1InputSelectRegister;
 540                 break;
 541         case NITIO_G2_Input_Select_Reg:
 542                 ni_660x_register = G2InputSelectRegister;
 543                 break;
 544         case NITIO_G3_Input_Select_Reg:
 545                 ni_660x_register = G3InputSelectRegister;
 546                 break;
 547         case NITIO_G01_Status_Reg:
 548                 ni_660x_register = G01StatusRegister;
 549                 break;
 550         case NITIO_G23_Status_Reg:
 551                 ni_660x_register = G23StatusRegister;
 552                 break;
 553         case NITIO_G01_Joint_Reset_Reg:
 554                 ni_660x_register = G01JointResetRegister;
 555                 break;
 556         case NITIO_G23_Joint_Reset_Reg:
 557                 ni_660x_register = G23JointResetRegister;
 558                 break;
 559         case NITIO_G01_Joint_Status1_Reg:
 560                 ni_660x_register = G01JointStatus1Register;
 561                 break;
 562         case NITIO_G23_Joint_Status1_Reg:
 563                 ni_660x_register = G23JointStatus1Register;
 564                 break;
 565         case NITIO_G01_Joint_Status2_Reg:
 566                 ni_660x_register = G01JointStatus2Register;
 567                 break;
 568         case NITIO_G23_Joint_Status2_Reg:
 569                 ni_660x_register = G23JointStatus2Register;
 570                 break;
 571         case NITIO_G0_Counting_Mode_Reg:
 572                 ni_660x_register = G0CountingModeRegister;
 573                 break;
 574         case NITIO_G1_Counting_Mode_Reg:
 575                 ni_660x_register = G1CountingModeRegister;
 576                 break;
 577         case NITIO_G2_Counting_Mode_Reg:
 578                 ni_660x_register = G2CountingModeRegister;
 579                 break;
 580         case NITIO_G3_Counting_Mode_Reg:
 581                 ni_660x_register = G3CountingModeRegister;
 582                 break;
 583         case NITIO_G0_Second_Gate_Reg:
 584                 ni_660x_register = G0SecondGateRegister;
 585                 break;
 586         case NITIO_G1_Second_Gate_Reg:
 587                 ni_660x_register = G1SecondGateRegister;
 588                 break;
 589         case NITIO_G2_Second_Gate_Reg:
 590                 ni_660x_register = G2SecondGateRegister;
 591                 break;
 592         case NITIO_G3_Second_Gate_Reg:
 593                 ni_660x_register = G3SecondGateRegister;
 594                 break;
 595         case NITIO_G0_DMA_Config_Reg:
 596                 ni_660x_register = G0DMAConfigRegister;
 597                 break;
 598         case NITIO_G0_DMA_Status_Reg:
 599                 ni_660x_register = G0DMAStatusRegister;
 600                 break;
 601         case NITIO_G1_DMA_Config_Reg:
 602                 ni_660x_register = G1DMAConfigRegister;
 603                 break;
 604         case NITIO_G1_DMA_Status_Reg:
 605                 ni_660x_register = G1DMAStatusRegister;
 606                 break;
 607         case NITIO_G2_DMA_Config_Reg:
 608                 ni_660x_register = G2DMAConfigRegister;
 609                 break;
 610         case NITIO_G2_DMA_Status_Reg:
 611                 ni_660x_register = G2DMAStatusRegister;
 612                 break;
 613         case NITIO_G3_DMA_Config_Reg:
 614                 ni_660x_register = G3DMAConfigRegister;
 615                 break;
 616         case NITIO_G3_DMA_Status_Reg:
 617                 ni_660x_register = G3DMAStatusRegister;
 618                 break;
 619         case NITIO_G0_Interrupt_Acknowledge_Reg:
 620                 ni_660x_register = G0InterruptAcknowledge;
 621                 break;
 622         case NITIO_G1_Interrupt_Acknowledge_Reg:
 623                 ni_660x_register = G1InterruptAcknowledge;
 624                 break;
 625         case NITIO_G2_Interrupt_Acknowledge_Reg:
 626                 ni_660x_register = G2InterruptAcknowledge;
 627                 break;
 628         case NITIO_G3_Interrupt_Acknowledge_Reg:
 629                 ni_660x_register = G3InterruptAcknowledge;
 630                 break;
 631         case NITIO_G0_Status_Reg:
 632                 ni_660x_register = G0StatusRegister;
 633                 break;
 634         case NITIO_G1_Status_Reg:
 635                 ni_660x_register = G1StatusRegister;
 636                 break;
 637         case NITIO_G2_Status_Reg:
 638                 ni_660x_register = G2StatusRegister;
 639                 break;
 640         case NITIO_G3_Status_Reg:
 641                 ni_660x_register = G3StatusRegister;
 642                 break;
 643         case NITIO_G0_Interrupt_Enable_Reg:
 644                 ni_660x_register = G0InterruptEnable;
 645                 break;
 646         case NITIO_G1_Interrupt_Enable_Reg:
 647                 ni_660x_register = G1InterruptEnable;
 648                 break;
 649         case NITIO_G2_Interrupt_Enable_Reg:
 650                 ni_660x_register = G2InterruptEnable;
 651                 break;
 652         case NITIO_G3_Interrupt_Enable_Reg:
 653                 ni_660x_register = G3InterruptEnable;
 654                 break;
 655         default:
 656                 BUG();
 657                 return 0;
 658                 break;
 659         }
 660         return ni_660x_register;
 661 }
 662
 663 static inline void ni_660x_write_register(struct comedi_device *dev,
 664                                           unsigned chip_index, unsigned bits,
 665                                           enum NI_660x_Register reg)
 666 {
 667         struct ni_660x_private *devpriv = dev->private;
 668         void __iomem *write_address =
 669             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 670             registerData[reg].offset;
 671
 672         switch (registerData[reg].size) {
 673         case DATA_2B:
 674                 writew(bits, write_address);
 675                 break;
 676         case DATA_4B:
 677                 writel(bits, write_address);
 678                 break;
 679         default:
 680                 BUG();
 681                 break;
 682         }
 683 }
 684
 685 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
 686                                              unsigned chip_index,
 687                                              enum NI_660x_Register reg)
 688 {
 689         struct ni_660x_private *devpriv = dev->private;
 690         void __iomem *read_address =
 691             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 692             registerData[reg].offset;
 693
 694         switch (registerData[reg].size) {
 695         case DATA_2B:
 696                 return readw(read_address);
 697                 break;
 698         case DATA_4B:
 699                 return readl(read_address);
 700                 break;
 701         default:
 702                 BUG();
 703                 break;
 704         }
 705         return 0;
 706 }
 707
 708 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
 709                                    enum ni_gpct_register reg)
 710 {
 711         struct comedi_device *dev = counter->counter_dev->dev;
 712         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 713         ni_660x_write_register(dev, counter->chip_index, bits,
 714                                ni_660x_register);
 715 }
 716
 717 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
 718                                       enum ni_gpct_register reg)
 719 {
 720         struct comedi_device *dev = counter->counter_dev->dev;
 721         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 722         return ni_660x_read_register(dev, counter->chip_index,
 723                                      ni_660x_register);
 724 }
 725
 726 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
 727                                                          *priv,
 728                                                          struct ni_gpct
 729                                                          *counter)
 730 {
 731         return priv->mite_rings[counter->chip_index][counter->counter_index];
 732 }
 733
 734 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
 735                                            unsigned mite_channel,
 736                                            struct ni_gpct *counter)
 737 {
 738         struct ni_660x_private *devpriv = dev->private;
 739         unsigned long flags;
 740
 741         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 742         devpriv->dma_configuration_soft_copies[counter->chip_index] &=
 743             ~dma_select_mask(mite_channel);
 744         devpriv->dma_configuration_soft_copies[counter->chip_index] |=
 745             dma_select_bits(mite_channel,
 746                             dma_selection_counter(counter->counter_index));
 747         ni_660x_write_register(dev, counter->chip_index,
 748                                devpriv->dma_configuration_soft_copies
 749                                [counter->chip_index] |
 750                                dma_reset_bit(mite_channel), DMAConfigRegister);
 751         mmiowb();
 752         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 753 }
 754
 755 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
 756                                              unsigned mite_channel,
 757                                              struct ni_gpct *counter)
 758 {
 759         struct ni_660x_private *devpriv = dev->private;
 760         unsigned long flags;
 761
 762         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 763         devpriv->dma_configuration_soft_copies[counter->chip_index] &=
 764             ~dma_select_mask(mite_channel);
 765         devpriv->dma_configuration_soft_copies[counter->chip_index] |=
 766             dma_select_bits(mite_channel, dma_selection_none);
 767         ni_660x_write_register(dev, counter->chip_index,
 768                                devpriv->dma_configuration_soft_copies
 769                                [counter->chip_index], DMAConfigRegister);
 770         mmiowb();
 771         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 772 }
 773
 774 static int ni_660x_request_mite_channel(struct comedi_device *dev,
 775                                         struct ni_gpct *counter,
 776                                         enum comedi_io_direction direction)
 777 {
 778         struct ni_660x_private *devpriv = dev->private;
 779         unsigned long flags;
 780         struct mite_channel *mite_chan;
 781
 782         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 783         BUG_ON(counter->mite_chan);
 784         mite_chan = mite_request_channel(devpriv->mite,
 785                                          mite_ring(devpriv, counter));
 786         if (mite_chan == NULL) {
 787                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 788                 comedi_error(dev,
 789                              "failed to reserve mite dma channel for counter.");
 790                 return -EBUSY;
 791         }
 792         mite_chan->dir = direction;
 793         ni_tio_set_mite_channel(counter, mite_chan);
 794         ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
 795         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 796         return 0;
 797 }
 798
 799 static void ni_660x_release_mite_channel(struct comedi_device *dev,
 800                                          struct ni_gpct *counter)
 801 {
 802         struct ni_660x_private *devpriv = dev->private;
 803         unsigned long flags;
 804
 805         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 806         if (counter->mite_chan) {
 807                 struct mite_channel *mite_chan = counter->mite_chan;
 808
 809                 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
 810                 ni_tio_set_mite_channel(counter, NULL);
 811                 mite_release_channel(mite_chan);
 812         }
 813         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 814 }
 815
 816 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 817 {
 818         int retval;
 819
 820         struct ni_gpct *counter = subdev_to_counter(s);
 821 /* const struct comedi_cmd *cmd = &s->async->cmd; */
 822
 823         retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
 824         if (retval) {
 825                 comedi_error(dev,
 826                              "no dma channel available for use by counter");
 827                 return retval;
 828         }
 829         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
 830         retval = ni_tio_cmd(counter, s->async);
 831
 832         return retval;
 833 }
 834
 835 static int ni_660x_cmdtest(struct comedi_device *dev,
 836                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
 837 {
 838         struct ni_gpct *counter = subdev_to_counter(s);
 839
 840         return ni_tio_cmdtest(counter, cmd);
 841 }
 842
 843 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
 844 {
 845         struct ni_gpct *counter = subdev_to_counter(s);
 846         int retval;
 847
 848         retval = ni_tio_cancel(counter);
 849         ni_660x_release_mite_channel(dev, counter);
 850         return retval;
 851 }
 852
 853 static void set_tio_counterswap(struct comedi_device *dev, int chipset)
 854 {
 855         /* See P. 3.5 of the Register-Level Programming manual.  The
 856            CounterSwap bit has to be set on the second chip, otherwise
 857            it will try to use the same pins as the first chip.
 858          */
 859         if (chipset)
 860                 ni_660x_write_register(dev, chipset, CounterSwap,
 861                                        ClockConfigRegister);
 862         else
 863                 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
 864 }
 865
 866 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
 867                                           struct comedi_subdevice *s)
 868 {
 869         ni_tio_handle_interrupt(subdev_to_counter(s), s);
 870         if (s->async->events) {
 871                 if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
 872                                         COMEDI_CB_OVERFLOW)) {
 873                         ni_660x_cancel(dev, s);
 874                 }
 875                 comedi_event(dev, s);
 876         }
 877 }
 878
 879 static irqreturn_t ni_660x_interrupt(int irq, void *d)
 880 {
 881         struct comedi_device *dev = d;
 882         struct ni_660x_private *devpriv = dev->private;
 883         struct comedi_subdevice *s;
 884         unsigned i;
 885         unsigned long flags;
 886
 887         if (dev->attached == 0)
 888                 return IRQ_NONE;
 889         /* lock to avoid race with comedi_poll */
 890         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
 891         smp_mb();
 892         for (i = 0; i < ni_660x_num_counters(dev); ++i) {
 893                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
 894                 ni_660x_handle_gpct_interrupt(dev, s);
 895         }
 896         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
 897         return IRQ_HANDLED;
 898 }
 899
 900 static int ni_660x_input_poll(struct comedi_device *dev,
 901                               struct comedi_subdevice *s)
 902 {
 903         struct ni_660x_private *devpriv = dev->private;
 904         unsigned long flags;
 905
 906         /* lock to avoid race with comedi_poll */
 907         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
 908         mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
 909         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
 910         return comedi_buf_read_n_available(s->async);
 911 }
 912
 913 static int ni_660x_buf_change(struct comedi_device *dev,
 914                               struct comedi_subdevice *s,
 915                               unsigned long new_size)
 916 {
 917         struct ni_660x_private *devpriv = dev->private;
 918         int ret;
 919
 920         ret = mite_buf_change(mite_ring(devpriv, subdev_to_counter(s)),
 921                               s->async);
 922         if (ret < 0)
 923                 return ret;
 924
 925         return 0;
 926 }
 927
 928 static int ni_660x_allocate_private(struct comedi_device *dev)
 929 {
 930         struct ni_660x_private *devpriv;
 931         unsigned i;
 932
 933         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 934         if (!devpriv)
 935                 return -ENOMEM;
 936         dev->private = devpriv;
 937
 938         spin_lock_init(&devpriv->mite_channel_lock);
 939         spin_lock_init(&devpriv->interrupt_lock);
 940         spin_lock_init(&devpriv->soft_reg_copy_lock);
 941         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
 942                 devpriv->pfi_output_selects[i] = pfi_output_select_counter;
 943
 944         return 0;
 945 }
 946
 947 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
 948 {
 949         struct ni_660x_private *devpriv = dev->private;
 950         unsigned i;
 951         unsigned j;
 952
 953         for (i = 0; i < board(dev)->n_chips; ++i) {
 954                 for (j = 0; j < counters_per_chip; ++j) {
 955                         devpriv->mite_rings[i][j] =
 956                             mite_alloc_ring(devpriv->mite);
 957                         if (devpriv->mite_rings[i][j] == NULL)
 958                                 return -ENOMEM;
 959                 }
 960         }
 961         return 0;
 962 }
 963
 964 static void ni_660x_free_mite_rings(struct comedi_device *dev)
 965 {
 966         struct ni_660x_private *devpriv = dev->private;
 967         unsigned i;
 968         unsigned j;
 969
 970         for (i = 0; i < board(dev)->n_chips; ++i) {
 971                 for (j = 0; j < counters_per_chip; ++j)
 972                         mite_free_ring(devpriv->mite_rings[i][j]);
 973         }
 974 }
 975
 976 static const struct ni_660x_board *
 977 ni_660x_find_boardinfo(struct pci_dev *pcidev)
 978 {
 979         unsigned int dev_id = pcidev->device;
 980         unsigned int n;
 981
 982         for (n = 0; n < ARRAY_SIZE(ni_660x_boards); n++) {
 983                 const struct ni_660x_board *board = &ni_660x_boards[n];
 984                 if (board->dev_id == dev_id)
 985                         return board;
 986         }
 987         return NULL;
 988 }
 989
 990 static int
 991 ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 992                    struct comedi_insn *insn, unsigned int *data)
 993 {
 994         return ni_tio_rinsn(subdev_to_counter(s), insn, data);
 995 }
 996
 997 static void init_tio_chip(struct comedi_device *dev, int chipset)
 998 {
 999         struct ni_660x_private *devpriv = dev->private;
1000         unsigned i;
1001
1002         /*  init dma configuration register */
1003         devpriv->dma_configuration_soft_copies[chipset] = 0;
1004         for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
1005                 devpriv->dma_configuration_soft_copies[chipset] |=
1006                     dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
1007         }
1008         ni_660x_write_register(dev, chipset,
1009                                devpriv->dma_configuration_soft_copies[chipset],
1010                                DMAConfigRegister);
1011         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1012                 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1013 }
1014
1015 static int
1016 ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1017                          struct comedi_insn *insn, unsigned int *data)
1018 {
1019         return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1020 }
1021
1022 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1023                               struct comedi_subdevice *s,
1024                               struct comedi_insn *insn, unsigned int *data)
1025 {
1026         return ni_tio_winsn(subdev_to_counter(s), insn, data);
1027 }
1028
1029 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1030                                  struct comedi_subdevice *s,
1031                                  struct comedi_insn *insn, unsigned int *data)
1032 {
1033         unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1034
1035         /*  Check if we have to write some bits */
1036         if (data[0]) {
1037                 s->state &= ~(data[0] << base_bitfield_channel);
1038                 s->state |= (data[0] & data[1]) << base_bitfield_channel;
1039                 /* Write out the new digital output lines */
1040                 ni_660x_write_register(dev, 0, s->state, DIO32Output);
1041         }
1042         /* on return, data[1] contains the value of the digital
1043          * input and output lines. */
1044         data[1] =
1045             (ni_660x_read_register(dev, 0,
1046                                    DIO32Input) >> base_bitfield_channel);
1047         return insn->n;
1048 }
1049
1050 static void ni_660x_select_pfi_output(struct comedi_device *dev,
1051                                       unsigned pfi_channel,
1052                                       unsigned output_select)
1053 {
1054         static const unsigned counter_4_7_first_pfi = 8;
1055         static const unsigned counter_4_7_last_pfi = 23;
1056         unsigned active_chipset = 0;
1057         unsigned idle_chipset = 0;
1058         unsigned active_bits;
1059         unsigned idle_bits;
1060
1061         if (board(dev)->n_chips > 1) {
1062                 if (output_select == pfi_output_select_counter &&
1063                     pfi_channel >= counter_4_7_first_pfi &&
1064                     pfi_channel <= counter_4_7_last_pfi) {
1065                         active_chipset = 1;
1066                         idle_chipset = 0;
1067                 } else {
1068                         active_chipset = 0;
1069                         idle_chipset = 1;
1070                 }
1071         }
1072
1073         if (idle_chipset != active_chipset) {
1074                 idle_bits =
1075                     ni_660x_read_register(dev, idle_chipset,
1076                                           IOConfigReg(pfi_channel));
1077                 idle_bits &= ~pfi_output_select_mask(pfi_channel);
1078                 idle_bits |=
1079                     pfi_output_select_bits(pfi_channel,
1080                                            pfi_output_select_high_Z);
1081                 ni_660x_write_register(dev, idle_chipset, idle_bits,
1082                                        IOConfigReg(pfi_channel));
1083         }
1084
1085         active_bits =
1086             ni_660x_read_register(dev, active_chipset,
1087                                   IOConfigReg(pfi_channel));
1088         active_bits &= ~pfi_output_select_mask(pfi_channel);
1089         active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1090         ni_660x_write_register(dev, active_chipset, active_bits,
1091                                IOConfigReg(pfi_channel));
1092 }
1093
1094 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1095                                    unsigned source)
1096 {
1097         struct ni_660x_private *devpriv = dev->private;
1098
1099         if (source > num_pfi_output_selects)
1100                 return -EINVAL;
1101         if (source == pfi_output_select_high_Z)
1102                 return -EINVAL;
1103         if (chan < min_counter_pfi_chan) {
1104                 if (source == pfi_output_select_counter)
1105                         return -EINVAL;
1106         } else if (chan > max_dio_pfi_chan) {
1107                 if (source == pfi_output_select_do)
1108                         return -EINVAL;
1109         }
1110         BUG_ON(chan >= NUM_PFI_CHANNELS);
1111
1112         devpriv->pfi_output_selects[chan] = source;
1113         if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan))
1114                 ni_660x_select_pfi_output(dev, chan,
1115                                           devpriv->pfi_output_selects[chan]);
1116         return 0;
1117 }
1118
1119 static unsigned ni_660x_get_pfi_routing(struct comedi_device *dev,
1120                                         unsigned chan)
1121 {
1122         struct ni_660x_private *devpriv = dev->private;
1123
1124         BUG_ON(chan >= NUM_PFI_CHANNELS);
1125         return devpriv->pfi_output_selects[chan];
1126 }
1127
1128 static void ni660x_config_filter(struct comedi_device *dev,
1129                                  unsigned pfi_channel,
1130                                  enum ni_gpct_filter_select filter)
1131 {
1132         unsigned bits = ni_660x_read_register(dev, 0, IOConfigReg(pfi_channel));
1133         bits &= ~pfi_input_select_mask(pfi_channel);
1134         bits |= pfi_input_select_bits(pfi_channel, filter);
1135         ni_660x_write_register(dev, 0, bits, IOConfigReg(pfi_channel));
1136 }
1137
1138 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1139                                    struct comedi_subdevice *s,
1140                                    struct comedi_insn *insn, unsigned int *data)
1141 {
1142         struct ni_660x_private *devpriv = dev->private;
1143         int chan = CR_CHAN(insn->chanspec);
1144
1145         /* The input or output configuration of each digital line is
1146          * configured by a special insn_config instruction.  chanspec
1147          * contains the channel to be changed, and data[0] contains the
1148          * value COMEDI_INPUT or COMEDI_OUTPUT. */
1149
1150         switch (data[0]) {
1151         case INSN_CONFIG_DIO_OUTPUT:
1152                 devpriv->pfi_direction_bits |= ((uint64_t) 1) << chan;
1153                 ni_660x_select_pfi_output(dev, chan,
1154                                           devpriv->pfi_output_selects[chan]);
1155                 break;
1156         case INSN_CONFIG_DIO_INPUT:
1157                 devpriv->pfi_direction_bits &= ~(((uint64_t) 1) << chan);
1158                 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1159                 break;
1160         case INSN_CONFIG_DIO_QUERY:
1161                 data[1] =
1162                     (devpriv->pfi_direction_bits &
1163                      (((uint64_t) 1) << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1164                 return 0;
1165         case INSN_CONFIG_SET_ROUTING:
1166                 return ni_660x_set_pfi_routing(dev, chan, data[1]);
1167                 break;
1168         case INSN_CONFIG_GET_ROUTING:
1169                 data[1] = ni_660x_get_pfi_routing(dev, chan);
1170                 break;
1171         case INSN_CONFIG_FILTER:
1172                 ni660x_config_filter(dev, chan, data[1]);
1173                 break;
1174         default:
1175                 return -EINVAL;
1176                 break;
1177         }
1178         return 0;
1179 }
1180
1181 static int __devinit ni_660x_attach_pci(struct comedi_device *dev,
1182                                         struct pci_dev *pcidev)
1183 {
1184         struct ni_660x_private *devpriv;
1185         struct comedi_subdevice *s;
1186         int ret;
1187         unsigned i;
1188         unsigned global_interrupt_config_bits;
1189
1190         ret = ni_660x_allocate_private(dev);
1191         if (ret < 0)
1192                 return ret;
1193         devpriv = dev->private;
1194
1195         dev->board_ptr = ni_660x_find_boardinfo(pcidev);
1196         if (!dev->board_ptr)
1197                 return -ENODEV;
1198         devpriv->mite = mite_alloc(pcidev);
1199         if (!devpriv->mite)
1200                 return -ENOMEM;
1201
1202         dev->board_name = board(dev)->name;
1203
1204         ret = mite_setup2(devpriv->mite, 1);
1205         if (ret < 0) {
1206                 dev_warn(dev->class_dev, "error setting up mite\n");
1207                 return ret;
1208         }
1209
1210         ret = ni_660x_alloc_mite_rings(dev);
1211         if (ret < 0)
1212                 return ret;
1213
1214         ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS);
1215         if (ret)
1216                 return ret;
1217
1218         s = &dev->subdevices[0];
1219         /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1220         s->type = COMEDI_SUBD_UNUSED;
1221
1222         s = &dev->subdevices[NI_660X_DIO_SUBDEV];
1223         /* DIGITAL I/O SUBDEVICE */
1224         s->type = COMEDI_SUBD_DIO;
1225         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1226         s->n_chan = NUM_PFI_CHANNELS;
1227         s->maxdata = 1;
1228         s->range_table = &range_digital;
1229         s->insn_bits = ni_660x_dio_insn_bits;
1230         s->insn_config = ni_660x_dio_insn_config;
1231         s->io_bits = 0;         /* all bits default to input */
1232         /*  we use the ioconfig registers to control dio direction, so zero
1233         output enables in stc dio control reg */
1234         ni_660x_write_register(dev, 0, 0, STCDIOControl);
1235
1236         devpriv->counter_dev = ni_gpct_device_construct(dev,
1237                                                      &ni_gpct_write_register,
1238                                                      &ni_gpct_read_register,
1239                                                      ni_gpct_variant_660x,
1240                                                      ni_660x_num_counters
1241                                                      (dev));
1242         if (devpriv->counter_dev == NULL)
1243                 return -ENOMEM;
1244         for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1245                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
1246                 if (i < ni_660x_num_counters(dev)) {
1247                         s->type = COMEDI_SUBD_COUNTER;
1248                         s->subdev_flags =
1249                             SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1250                             SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1251                         s->n_chan = 3;
1252                         s->maxdata = 0xffffffff;
1253                         s->insn_read = ni_660x_GPCT_rinsn;
1254                         s->insn_write = ni_660x_GPCT_winsn;
1255                         s->insn_config = ni_660x_GPCT_insn_config;
1256                         s->do_cmd = &ni_660x_cmd;
1257                         s->len_chanlist = 1;
1258                         s->do_cmdtest = &ni_660x_cmdtest;
1259                         s->cancel = &ni_660x_cancel;
1260                         s->poll = &ni_660x_input_poll;
1261                         s->async_dma_dir = DMA_BIDIRECTIONAL;
1262                         s->buf_change = &ni_660x_buf_change;
1263                         s->private = &devpriv->counter_dev->counters[i];
1264
1265                         devpriv->counter_dev->counters[i].chip_index =
1266                             i / counters_per_chip;
1267                         devpriv->counter_dev->counters[i].counter_index =
1268                             i % counters_per_chip;
1269                 } else {
1270                         s->type = COMEDI_SUBD_UNUSED;
1271                 }
1272         }
1273         for (i = 0; i < board(dev)->n_chips; ++i)
1274                 init_tio_chip(dev, i);
1275
1276         for (i = 0; i < ni_660x_num_counters(dev); ++i)
1277                 ni_tio_init_counter(&devpriv->counter_dev->counters[i]);
1278
1279         for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1280                 if (i < min_counter_pfi_chan)
1281                         ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1282                 else
1283                         ni_660x_set_pfi_routing(dev, i,
1284                                                 pfi_output_select_counter);
1285                 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1286         }
1287         /* to be safe, set counterswap bits on tio chips after all the counter
1288            outputs have been set to high impedance mode */
1289         for (i = 0; i < board(dev)->n_chips; ++i)
1290                 set_tio_counterswap(dev, i);
1291
1292         ret = request_irq(mite_irq(devpriv->mite), ni_660x_interrupt,
1293                           IRQF_SHARED, "ni_660x", dev);
1294         if (ret < 0) {
1295                 dev_warn(dev->class_dev, " irq not available\n");
1296                 return ret;
1297         }
1298         dev->irq = mite_irq(devpriv->mite);
1299         global_interrupt_config_bits = Global_Int_Enable_Bit;
1300         if (board(dev)->n_chips > 1)
1301                 global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1302         ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1303                                GlobalInterruptConfigRegister);
1304         dev_info(dev->class_dev, "ni_660x: %s attached\n", dev->board_name);
1305         return 0;
1306 }
1307
1308 static void ni_660x_detach(struct comedi_device *dev)
1309 {
1310         struct ni_660x_private *devpriv = dev->private;
1311
1312         if (dev->irq)
1313                 free_irq(dev->irq, dev);
1314         if (devpriv) {
1315                 if (devpriv->counter_dev)
1316                         ni_gpct_device_destroy(devpriv->counter_dev);
1317                 if (devpriv->mite) {
1318                         ni_660x_free_mite_rings(dev);
1319                         mite_unsetup(devpriv->mite);
1320                         mite_free(devpriv->mite);
1321                 }
1322         }
1323 }
1324
1325 static struct comedi_driver ni_660x_driver = {
1326         .driver_name    = "ni_660x",
1327         .module         = THIS_MODULE,
1328         .attach_pci     = ni_660x_attach_pci,
1329         .detach         = ni_660x_detach,
1330 };
1331
1332 static int __devinit ni_660x_pci_probe(struct pci_dev *dev,
1333                                        const struct pci_device_id *ent)
1334 {
1335         return comedi_pci_auto_config(dev, &ni_660x_driver);
1336 }
1337
1338 static void __devexit ni_660x_pci_remove(struct pci_dev *dev)
1339 {
1340         comedi_pci_auto_unconfig(dev);
1341 }
1342
1343 static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
1344         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c60)},
1345         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1310)},
1346         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1360)},
1347         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2cc0)},
1348         {0}
1349 };
1350 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
1351
1352 static struct pci_driver ni_660x_pci_driver = {
1353         .name           = "ni_660x",
1354         .id_table       = ni_660x_pci_table,
1355         .probe          = ni_660x_pci_probe,
1356         .remove         = __devexit_p(ni_660x_pci_remove),
1357 };
1358 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
1359
1360 MODULE_AUTHOR("Comedi http://www.comedi.org");
1361 MODULE_DESCRIPTION("Comedi low-level driver");
1362 MODULE_LICENSE("GPL");