Pileus Git - ~andy/linux/blob - drivers/staging/comedi/drivers/ni_6527.c

   1 /*
   2     comedi/drivers/ni_6527.c
   3     driver for National Instruments PCI-6527
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23 /*
  24 Driver: ni_6527
  25 Description: National Instruments 6527
  26 Author: ds
  27 Status: works
  28 Devices: [National Instruments] PCI-6527 (ni6527), PXI-6527
  29 Updated: Sat, 25 Jan 2003 13:24:40 -0800
  30
  31
  32 */
  33
  34 /*
  35    Manuals (available from ftp://ftp.natinst.com/support/manuals)
  36
  37         370106b.pdf     6527 Register Level Programmer Manual
  38
  39  */
  40
  41 #define DEBUG 1
  42 #define DEBUG_FLAGS
  43
  44 #include <linux/pci.h>
  45 #include <linux/interrupt.h>
  46
  47 #include "../comedidev.h"
  48
  49 #include "comedi_fc.h"
  50 #include "mite.h"
  51
  52 #define DRIVER_NAME "ni_6527"
  53
  54 #define NI6527_DIO_SIZE 4096
  55 #define NI6527_MITE_SIZE 4096
  56
  57 #define Port_Register(x)                        (0x00+(x))
  58 #define ID_Register                             0x06
  59
  60 #define Clear_Register                          0x07
  61 #define ClrEdge                         0x08
  62 #define ClrOverflow                     0x04
  63 #define ClrFilter                       0x02
  64 #define ClrInterval                     0x01
  65
  66 #define Filter_Interval(x)                      (0x08+(x))
  67 #define Filter_Enable(x)                        (0x0c+(x))
  68
  69 #define Change_Status                           0x14
  70 #define MasterInterruptStatus           0x04
  71 #define Overflow                        0x02
  72 #define EdgeStatus                      0x01
  73
  74 #define Master_Interrupt_Control                0x15
  75 #define FallingEdgeIntEnable            0x10
  76 #define RisingEdgeIntEnable             0x08
  77 #define MasterInterruptEnable           0x04
  78 #define OverflowIntEnable               0x02
  79 #define EdgeIntEnable                   0x01
  80
  81 #define Rising_Edge_Detection_Enable(x)         (0x018+(x))
  82 #define Falling_Edge_Detection_Enable(x)        (0x020+(x))
  83
  84 struct ni6527_board {
  85
  86         int dev_id;
  87         const char *name;
  88 };
  89
  90 static const struct ni6527_board ni6527_boards[] = {
  91         {
  92          .dev_id = 0x2b20,
  93          .name = "pci-6527",
  94          },
  95         {
  96          .dev_id = 0x2b10,
  97          .name = "pxi-6527",
  98          },
  99 };
 100
 101 #define this_board ((const struct ni6527_board *)dev->board_ptr)
 102
 103 static DEFINE_PCI_DEVICE_TABLE(ni6527_pci_table) = {
 104         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b10)},
 105         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b20)},
 106         {0}
 107 };
 108
 109 MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
 110
 111 struct ni6527_private {
 112         struct mite_struct *mite;
 113         unsigned int filter_interval;
 114         unsigned int filter_enable;
 115 };
 116
 117 static int ni6527_di_insn_config(struct comedi_device *dev,
 118                                  struct comedi_subdevice *s,
 119                                  struct comedi_insn *insn, unsigned int *data)
 120 {
 121         struct ni6527_private *devpriv = dev->private;
 122         int chan = CR_CHAN(insn->chanspec);
 123         unsigned int interval;
 124
 125         if (insn->n != 2)
 126                 return -EINVAL;
 127
 128         if (data[0] != INSN_CONFIG_FILTER)
 129                 return -EINVAL;
 130
 131         if (data[1]) {
 132                 interval = (data[1] + 100) / 200;
 133                 data[1] = interval * 200;
 134
 135                 if (interval != devpriv->filter_interval) {
 136                         writeb(interval & 0xff,
 137                                devpriv->mite->daq_io_addr + Filter_Interval(0));
 138                         writeb((interval >> 8) & 0xff,
 139                                devpriv->mite->daq_io_addr + Filter_Interval(1));
 140                         writeb((interval >> 16) & 0x0f,
 141                                devpriv->mite->daq_io_addr + Filter_Interval(2));
 142
 143                         writeb(ClrInterval,
 144                                devpriv->mite->daq_io_addr + Clear_Register);
 145
 146                         devpriv->filter_interval = interval;
 147                 }
 148
 149                 devpriv->filter_enable |= 1 << chan;
 150         } else {
 151                 devpriv->filter_enable &= ~(1 << chan);
 152         }
 153
 154         writeb(devpriv->filter_enable,
 155                devpriv->mite->daq_io_addr + Filter_Enable(0));
 156         writeb(devpriv->filter_enable >> 8,
 157                devpriv->mite->daq_io_addr + Filter_Enable(1));
 158         writeb(devpriv->filter_enable >> 16,
 159                devpriv->mite->daq_io_addr + Filter_Enable(2));
 160
 161         return 2;
 162 }
 163
 164 static int ni6527_di_insn_bits(struct comedi_device *dev,
 165                                struct comedi_subdevice *s,
 166                                struct comedi_insn *insn, unsigned int *data)
 167 {
 168         struct ni6527_private *devpriv = dev->private;
 169
 170         data[1] = readb(devpriv->mite->daq_io_addr + Port_Register(0));
 171         data[1] |= readb(devpriv->mite->daq_io_addr + Port_Register(1)) << 8;
 172         data[1] |= readb(devpriv->mite->daq_io_addr + Port_Register(2)) << 16;
 173
 174         return insn->n;
 175 }
 176
 177 static int ni6527_do_insn_bits(struct comedi_device *dev,
 178                                struct comedi_subdevice *s,
 179                                struct comedi_insn *insn, unsigned int *data)
 180 {
 181         struct ni6527_private *devpriv = dev->private;
 182
 183         if (data[0]) {
 184                 s->state &= ~data[0];
 185                 s->state |= (data[0] & data[1]);
 186
 187                 /* The open relay state on the board cooresponds to 1,
 188                  * but in Comedi, it is represented by 0. */
 189                 if (data[0] & 0x0000ff) {
 190                         writeb((s->state ^ 0xff),
 191                                devpriv->mite->daq_io_addr + Port_Register(3));
 192                 }
 193                 if (data[0] & 0x00ff00) {
 194                         writeb((s->state >> 8) ^ 0xff,
 195                                devpriv->mite->daq_io_addr + Port_Register(4));
 196                 }
 197                 if (data[0] & 0xff0000) {
 198                         writeb((s->state >> 16) ^ 0xff,
 199                                devpriv->mite->daq_io_addr + Port_Register(5));
 200                 }
 201         }
 202         data[1] = s->state;
 203
 204         return insn->n;
 205 }
 206
 207 static irqreturn_t ni6527_interrupt(int irq, void *d)
 208 {
 209         struct comedi_device *dev = d;
 210         struct ni6527_private *devpriv = dev->private;
 211         struct comedi_subdevice *s = &dev->subdevices[2];
 212         unsigned int status;
 213
 214         status = readb(devpriv->mite->daq_io_addr + Change_Status);
 215         if ((status & MasterInterruptStatus) == 0)
 216                 return IRQ_NONE;
 217         if ((status & EdgeStatus) == 0)
 218                 return IRQ_NONE;
 219
 220         writeb(ClrEdge | ClrOverflow,
 221                devpriv->mite->daq_io_addr + Clear_Register);
 222
 223         comedi_buf_put(s->async, 0);
 224         s->async->events |= COMEDI_CB_EOS;
 225         comedi_event(dev, s);
 226         return IRQ_HANDLED;
 227 }
 228
 229 static int ni6527_intr_cmdtest(struct comedi_device *dev,
 230                                struct comedi_subdevice *s,
 231                                struct comedi_cmd *cmd)
 232 {
 233         int err = 0;
 234
 235         /* Step 1 : check if triggers are trivially valid */
 236
 237         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
 238         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
 239         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
 240         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 241         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
 242
 243         if (err)
 244                 return 1;
 245
 246         /* Step 2a : make sure trigger sources are unique */
 247         /* Step 2b : and mutually compatible */
 248
 249         if (err)
 250                 return 2;
 251
 252         /* Step 3: check if arguments are trivially valid */
 253
 254         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
 255         err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
 256         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
 257         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
 258         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
 259
 260         if (err)
 261                 return 3;
 262
 263         /* step 4: fix up any arguments */
 264
 265         if (err)
 266                 return 4;
 267
 268         return 0;
 269 }
 270
 271 static int ni6527_intr_cmd(struct comedi_device *dev,
 272                            struct comedi_subdevice *s)
 273 {
 274         struct ni6527_private *devpriv = dev->private;
 275         /* struct comedi_cmd *cmd = &s->async->cmd; */
 276
 277         writeb(ClrEdge | ClrOverflow,
 278                devpriv->mite->daq_io_addr + Clear_Register);
 279         writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
 280                MasterInterruptEnable | EdgeIntEnable,
 281                devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 282
 283         return 0;
 284 }
 285
 286 static int ni6527_intr_cancel(struct comedi_device *dev,
 287                               struct comedi_subdevice *s)
 288 {
 289         struct ni6527_private *devpriv = dev->private;
 290
 291         writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 292
 293         return 0;
 294 }
 295
 296 static int ni6527_intr_insn_bits(struct comedi_device *dev,
 297                                  struct comedi_subdevice *s,
 298                                  struct comedi_insn *insn, unsigned int *data)
 299 {
 300         data[1] = 0;
 301         return insn->n;
 302 }
 303
 304 static int ni6527_intr_insn_config(struct comedi_device *dev,
 305                                    struct comedi_subdevice *s,
 306                                    struct comedi_insn *insn, unsigned int *data)
 307 {
 308         struct ni6527_private *devpriv = dev->private;
 309
 310         if (insn->n < 1)
 311                 return -EINVAL;
 312         if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
 313                 return -EINVAL;
 314
 315         writeb(data[1],
 316                devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(0));
 317         writeb(data[1] >> 8,
 318                devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(1));
 319         writeb(data[1] >> 16,
 320                devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(2));
 321
 322         writeb(data[2],
 323                devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(0));
 324         writeb(data[2] >> 8,
 325                devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(1));
 326         writeb(data[2] >> 16,
 327                devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(2));
 328
 329         return 2;
 330 }
 331
 332 static const struct ni6527_board *
 333 ni6527_find_boardinfo(struct pci_dev *pcidev)
 334 {
 335         unsigned int dev_id = pcidev->device;
 336         unsigned int n;
 337
 338         for (n = 0; n < ARRAY_SIZE(ni6527_boards); n++) {
 339                 const struct ni6527_board *board = &ni6527_boards[n];
 340                 if (board->dev_id == dev_id)
 341                         return board;
 342         }
 343         return NULL;
 344 }
 345
 346 static int ni6527_auto_attach(struct comedi_device *dev,
 347                                         unsigned long context_unused)
 348 {
 349         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 350         struct ni6527_private *devpriv;
 351         struct comedi_subdevice *s;
 352         int ret;
 353
 354         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 355         if (!devpriv)
 356                 return -ENOMEM;
 357         dev->private = devpriv;
 358
 359         dev->board_ptr = ni6527_find_boardinfo(pcidev);
 360         if (!dev->board_ptr)
 361                 return -ENODEV;
 362
 363         devpriv->mite = mite_alloc(pcidev);
 364         if (!devpriv->mite)
 365                 return -ENOMEM;
 366
 367         ret = mite_setup(devpriv->mite);
 368         if (ret < 0) {
 369                 dev_err(dev->class_dev, "error setting up mite\n");
 370                 return ret;
 371         }
 372
 373         dev->board_name = this_board->name;
 374         dev_info(dev->class_dev, "board: %s, ID=0x%02x\n", dev->board_name,
 375                  readb(devpriv->mite->daq_io_addr + ID_Register));
 376
 377         ret = comedi_alloc_subdevices(dev, 3);
 378         if (ret)
 379                 return ret;
 380
 381         s = &dev->subdevices[0];
 382         s->type = COMEDI_SUBD_DI;
 383         s->subdev_flags = SDF_READABLE;
 384         s->n_chan = 24;
 385         s->range_table = &range_digital;
 386         s->maxdata = 1;
 387         s->insn_config = ni6527_di_insn_config;
 388         s->insn_bits = ni6527_di_insn_bits;
 389
 390         s = &dev->subdevices[1];
 391         s->type = COMEDI_SUBD_DO;
 392         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
 393         s->n_chan = 24;
 394         s->range_table = &range_unknown;  /* FIXME: actually conductance */
 395         s->maxdata = 1;
 396         s->insn_bits = ni6527_do_insn_bits;
 397
 398         s = &dev->subdevices[2];
 399         dev->read_subdev = s;
 400         s->type = COMEDI_SUBD_DI;
 401         s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
 402         s->n_chan = 1;
 403         s->range_table = &range_unknown;
 404         s->maxdata = 1;
 405         s->do_cmdtest = ni6527_intr_cmdtest;
 406         s->do_cmd = ni6527_intr_cmd;
 407         s->cancel = ni6527_intr_cancel;
 408         s->insn_bits = ni6527_intr_insn_bits;
 409         s->insn_config = ni6527_intr_insn_config;
 410
 411         writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(0));
 412         writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(1));
 413         writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(2));
 414
 415         writeb(ClrEdge | ClrOverflow | ClrFilter | ClrInterval,
 416                devpriv->mite->daq_io_addr + Clear_Register);
 417         writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 418
 419         ret = request_irq(mite_irq(devpriv->mite), ni6527_interrupt,
 420                           IRQF_SHARED, DRIVER_NAME, dev);
 421         if (ret < 0)
 422                 dev_warn(dev->class_dev, "irq not available\n");
 423         else
 424                 dev->irq = mite_irq(devpriv->mite);
 425
 426         return 0;
 427 }
 428
 429 static void ni6527_detach(struct comedi_device *dev)
 430 {
 431         struct ni6527_private *devpriv = dev->private;
 432
 433         if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr)
 434                 writeb(0x00,
 435                        devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 436         if (dev->irq)
 437                 free_irq(dev->irq, dev);
 438         if (devpriv && devpriv->mite) {
 439                 mite_unsetup(devpriv->mite);
 440                 mite_free(devpriv->mite);
 441         }
 442 }
 443
 444 static struct comedi_driver ni6527_driver = {
 445         .driver_name = DRIVER_NAME,
 446         .module = THIS_MODULE,
 447         .auto_attach = ni6527_auto_attach,
 448         .detach = ni6527_detach,
 449 };
 450
 451 static int ni6527_pci_probe(struct pci_dev *dev,
 452                                       const struct pci_device_id *ent)
 453 {
 454         return comedi_pci_auto_config(dev, &ni6527_driver);
 455 }
 456
 457 static struct pci_driver ni6527_pci_driver = {
 458         .name = DRIVER_NAME,
 459         .id_table = ni6527_pci_table,
 460         .probe = ni6527_pci_probe,
 461         .remove         = comedi_pci_auto_unconfig,
 462 };
 463 module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
 464
 465 MODULE_AUTHOR("Comedi http://www.comedi.org");
 466 MODULE_DESCRIPTION("Comedi low-level driver");
 467 MODULE_LICENSE("GPL");