3 Hardware driver for NI Mite PCI interface chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
22 #include <linux/pci.h>
23 #include <linux/log2.h>
24 #include <linux/slab.h>
25 #include "../comedidev.h"
27 /* #define DEBUG_MITE */
31 #define MDPRINTK(format, args...) pr_debug(format , ## args)
33 #define MDPRINTK(format, args...) do { } while (0)
36 #define MAX_MITE_DMA_CHANNELS 8
38 struct mite_dma_descriptor {
45 struct mite_dma_descriptor_ring {
46 struct device *hw_dev;
48 struct mite_dma_descriptor *descriptors;
49 dma_addr_t descriptors_dma_addr;
53 struct mite_struct *mite;
57 struct mite_dma_descriptor_ring *ring;
61 struct pci_dev *pcidev;
62 resource_size_t mite_phys_addr;
63 void __iomem *mite_io_addr;
64 resource_size_t daq_phys_addr;
65 void __iomem *daq_io_addr;
66 struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
67 short channel_allocated[MAX_MITE_DMA_CHANNELS];
73 struct mite_struct *mite_alloc(struct pci_dev *pcidev);
75 static inline void mite_free(struct mite_struct *mite)
80 static inline unsigned int mite_irq(struct mite_struct *mite)
82 return mite->pcidev->irq;
85 static inline unsigned int mite_device_id(struct mite_struct *mite)
87 return mite->pcidev->device;
90 int mite_setup(struct mite_struct *mite);
91 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
92 void mite_unsetup(struct mite_struct *mite);
93 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite);
94 void mite_free_ring(struct mite_dma_descriptor_ring *ring);
95 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
97 mite_dma_descriptor_ring
98 *ring, unsigned min_channel,
99 unsigned max_channel);
100 static inline struct mite_channel *mite_request_channel(struct mite_struct
103 mite_dma_descriptor_ring
106 return mite_request_channel_in_range(mite, ring, 0,
107 mite->num_channels - 1);
110 void mite_release_channel(struct mite_channel *mite_chan);
112 unsigned mite_dma_tcr(struct mite_channel *mite_chan);
113 void mite_dma_arm(struct mite_channel *mite_chan);
114 void mite_dma_disarm(struct mite_channel *mite_chan);
115 int mite_sync_input_dma(struct mite_channel *mite_chan,
116 struct comedi_async *async);
117 int mite_sync_output_dma(struct mite_channel *mite_chan,
118 struct comedi_async *async);
119 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
120 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
121 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
122 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
123 u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
124 unsigned mite_get_status(struct mite_channel *mite_chan);
125 int mite_done(struct mite_channel *mite_chan);
127 void mite_prep_dma(struct mite_channel *mite_chan,
128 unsigned int num_device_bits, unsigned int num_memory_bits);
129 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
130 struct comedi_async *async);
133 void mite_print_chsr(unsigned int chsr);
134 void mite_dump_regs(struct mite_channel *mite_chan);
137 static inline int CHAN_OFFSET(int channel)
139 return 0x500 + 0x100 * channel;
142 enum mite_registers {
143 /* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
144 written and read back. The bits 0x1f always read as 1.
145 The rest always read as zero. */
146 MITE_UNKNOWN_DMA_BURST_REG = 0x28,
147 MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */
148 MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */
149 MITE_IODWCR_1 = 0xf4,
150 MITE_PCI_CONFIG_OFFSET = 0x300,
151 MITE_CSIGR = 0x460 /* chip signature */
153 static inline int MITE_CHOR(int channel)
154 { /* channel operation */
155 return CHAN_OFFSET(channel) + 0x0;
158 static inline int MITE_CHCR(int channel)
159 { /* channel control */
160 return CHAN_OFFSET(channel) + 0x4;
163 static inline int MITE_TCR(int channel)
164 { /* transfer count */
165 return CHAN_OFFSET(channel) + 0x8;
168 static inline int MITE_MCR(int channel)
169 { /* memory configuration */
170 return CHAN_OFFSET(channel) + 0xc;
173 static inline int MITE_MAR(int channel)
174 { /* memory address */
175 return CHAN_OFFSET(channel) + 0x10;
178 static inline int MITE_DCR(int channel)
179 { /* device configuration */
180 return CHAN_OFFSET(channel) + 0x14;
183 static inline int MITE_DAR(int channel)
184 { /* device address */
185 return CHAN_OFFSET(channel) + 0x18;
188 static inline int MITE_LKCR(int channel)
189 { /* link configuration */
190 return CHAN_OFFSET(channel) + 0x1c;
193 static inline int MITE_LKAR(int channel)
195 return CHAN_OFFSET(channel) + 0x20;
198 static inline int MITE_LLKAR(int channel)
199 { /* see mite section of tnt5002 manual */
200 return CHAN_OFFSET(channel) + 0x24;
203 static inline int MITE_BAR(int channel)
205 return CHAN_OFFSET(channel) + 0x28;
208 static inline int MITE_BCR(int channel)
210 return CHAN_OFFSET(channel) + 0x2c;
213 static inline int MITE_SAR(int channel)
215 return CHAN_OFFSET(channel) + 0x30;
218 static inline int MITE_WSCR(int channel)
220 return CHAN_OFFSET(channel) + 0x34;
223 static inline int MITE_WSER(int channel)
225 return CHAN_OFFSET(channel) + 0x38;
228 static inline int MITE_CHSR(int channel)
229 { /* channel status */
230 return CHAN_OFFSET(channel) + 0x3c;
233 static inline int MITE_FCR(int channel)
235 return CHAN_OFFSET(channel) + 0x40;
238 enum MITE_IODWBSR_bits {
239 WENAB = 0x80, /* window enable */
242 static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
249 return (order - 1) & 0x1f;
252 enum MITE_UNKNOWN_DMA_BURST_bits {
253 UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
256 static inline int mite_csigr_version(u32 csigr_bits)
258 return csigr_bits & 0xf;
261 static inline int mite_csigr_type(u32 csigr_bits)
262 { /* original mite = 0, minimite = 1 */
263 return (csigr_bits >> 4) & 0xf;
266 static inline int mite_csigr_mmode(u32 csigr_bits)
267 { /* mite mode, minimite = 1 */
268 return (csigr_bits >> 8) & 0x3;
271 static inline int mite_csigr_imode(u32 csigr_bits)
272 { /* cpu port interface mode, pci = 0x3 */
273 return (csigr_bits >> 12) & 0x3;
276 static inline int mite_csigr_dmac(u32 csigr_bits)
277 { /* number of dma channels */
278 return (csigr_bits >> 16) & 0xf;
281 static inline int mite_csigr_wpdep(u32 csigr_bits)
282 { /* write post fifo depth */
283 unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
287 return 1 << (wpdep_bits - 1);
290 static inline int mite_csigr_wins(u32 csigr_bits)
292 return (csigr_bits >> 24) & 0x1f;
295 static inline int mite_csigr_iowins(u32 csigr_bits)
296 { /* number of io windows */
297 return (csigr_bits >> 29) & 0x7;
305 DCR_NORMAL = (1 << 29),
309 enum MITE_CHOR_bits {
310 CHOR_DMARESET = (1 << 31),
311 CHOR_SET_SEND_TC = (1 << 11),
312 CHOR_CLR_SEND_TC = (1 << 10),
313 CHOR_SET_LPAUSE = (1 << 9),
314 CHOR_CLR_LPAUSE = (1 << 8),
315 CHOR_CLRDONE = (1 << 7),
316 CHOR_CLRRB = (1 << 6),
317 CHOR_CLRLC = (1 << 5),
318 CHOR_FRESET = (1 << 4),
319 CHOR_ABORT = (1 << 3), /* stop without emptying fifo */
320 CHOR_STOP = (1 << 2), /* stop after emptying fifo */
321 CHOR_CONT = (1 << 1),
322 CHOR_START = (1 << 0),
323 CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
326 enum MITE_CHCR_bits {
327 CHCR_SET_DMA_IE = (1 << 31),
328 CHCR_CLR_DMA_IE = (1 << 30),
329 CHCR_SET_LINKP_IE = (1 << 29),
330 CHCR_CLR_LINKP_IE = (1 << 28),
331 CHCR_SET_SAR_IE = (1 << 27),
332 CHCR_CLR_SAR_IE = (1 << 26),
333 CHCR_SET_DONE_IE = (1 << 25),
334 CHCR_CLR_DONE_IE = (1 << 24),
335 CHCR_SET_MRDY_IE = (1 << 23),
336 CHCR_CLR_MRDY_IE = (1 << 22),
337 CHCR_SET_DRDY_IE = (1 << 21),
338 CHCR_CLR_DRDY_IE = (1 << 20),
339 CHCR_SET_LC_IE = (1 << 19),
340 CHCR_CLR_LC_IE = (1 << 18),
341 CHCR_SET_CONT_RB_IE = (1 << 17),
342 CHCR_CLR_CONT_RB_IE = (1 << 16),
343 CHCR_FIFODIS = (1 << 15),
345 CHCR_BURSTEN = (1 << 14),
347 CHCR_BYTE_SWAP_DEVICE = (1 << 6),
348 CHCR_BYTE_SWAP_MEMORY = (1 << 4),
350 CHCR_DEV_TO_MEM = CHCR_DIR,
352 CHCR_NORMAL = (0 << 0),
353 CHCR_CONTINUE = (1 << 0),
354 CHCR_RINGBUFF = (2 << 0),
355 CHCR_LINKSHORT = (4 << 0),
356 CHCR_LINKLONG = (5 << 0),
358 (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
359 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
360 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
363 enum ConfigRegister_bits {
364 CR_REQS_MASK = 0x7 << 16,
365 CR_ASEQDONT = 0x0 << 10,
366 CR_ASEQUP = 0x1 << 10,
367 CR_ASEQDOWN = 0x2 << 10,
368 CR_ASEQ_MASK = 0x3 << 10,
369 CR_PSIZE8 = (1 << 8),
370 CR_PSIZE16 = (2 << 8),
371 CR_PSIZE32 = (3 << 8),
372 CR_PORTCPU = (0 << 6),
373 CR_PORTIO = (1 << 6),
374 CR_PORTVXI = (2 << 6),
375 CR_PORTMXI = (3 << 6),
376 CR_AMDEVICE = (1 << 0),
378 static inline int CR_REQS(int source)
380 return (source & 0x7) << 16;
383 static inline int CR_REQSDRQ(unsigned drq_line)
385 /* This also works on m-series when
386 using channels (drq_line) 4 or 5. */
387 return CR_REQS((drq_line & 0x3) | 0x4);
390 static inline int CR_RL(unsigned int retry_limit)
395 value = 1 + ilog2(retry_limit);
398 return (value & 0x7) << 21;
402 CHSR_INT = (1 << 31),
403 CHSR_LPAUSES = (1 << 29),
404 CHSR_SARS = (1 << 27),
405 CHSR_DONE = (1 << 25),
406 CHSR_MRDY = (1 << 23),
407 CHSR_DRDY = (1 << 21),
408 CHSR_LINKC = (1 << 19),
409 CHSR_CONTS_RB = (1 << 17),
410 CHSR_ERROR = (1 << 15),
411 CHSR_SABORT = (1 << 14),
412 CHSR_HABORT = (1 << 13),
413 CHSR_STOPS = (1 << 12),
414 CHSR_OPERR_mask = (3 << 10),
415 CHSR_OPERR_NOERROR = (0 << 10),
416 CHSR_OPERR_FIFOERROR = (1 << 10),
417 CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */
418 CHSR_XFERR = (1 << 9),
420 CHSR_DRQ1 = (1 << 7),
421 CHSR_DRQ0 = (1 << 6),
422 CHSR_LxERR_mask = (3 << 4),
423 CHSR_LBERR = (1 << 4),
424 CHSR_LRERR = (2 << 4),
425 CHSR_LOERR = (3 << 4),
426 CHSR_MxERR_mask = (3 << 2),
427 CHSR_MBERR = (1 << 2),
428 CHSR_MRERR = (2 << 2),
429 CHSR_MOERR = (3 << 2),
430 CHSR_DxERR_mask = (3 << 0),
431 CHSR_DBERR = (1 << 0),
432 CHSR_DRERR = (2 << 0),
433 CHSR_DOERR = (3 << 0),
436 static inline void mite_dma_reset(struct mite_channel *mite_chan)
438 writel(CHOR_DMARESET | CHOR_FRESET,
439 mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));