Pileus Git - ~andy/linux/blob - drivers/staging/comedi/drivers/mite.c

   1 /*
   2     comedi/drivers/mite.c
   3     Hardware driver for NI Mite PCI interface chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 /*
  25         The PCI-MIO E series driver was originally written by
  26         Tomasz Motylewski <...>, and ported to comedi by ds.
  27
  28         References for specifications:
  29
  30            321747b.pdf  Register Level Programmer Manual (obsolete)
  31            321747c.pdf  Register Level Programmer Manual (new)
  32            DAQ-STC reference manual
  33
  34         Other possibly relevant info:
  35
  36            320517c.pdf  User manual (obsolete)
  37            320517f.pdf  User manual (new)
  38            320889a.pdf  delete
  39            320906c.pdf  maximum signal ratings
  40            321066a.pdf  about 16x
  41            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  42            321808a.pdf  about at-mio-16e-10 rev P
  43            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  44            321838a.pdf  about at-mio-16de-10 rev N
  45
  46         ISSUES:
  47
  48 */
  49
  50 /* #define USE_KMALLOC */
  51
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 #include <linux/pci.h>
  55
  56 #include "../comedidev.h"
  57
  58 #include "comedi_fc.h"
  59 #include "mite.h"
  60
  61 #define PCI_MITE_SIZE           4096
  62 #define PCI_DAQ_SIZE            4096
  63 #define PCI_DAQ_SIZE_660X       8192
  64
  65 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  66
  67 struct mite_struct *mite_alloc(struct pci_dev *pcidev)
  68 {
  69         struct mite_struct *mite;
  70         unsigned int i;
  71
  72         mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  73         if (mite) {
  74                 spin_lock_init(&mite->lock);
  75                 mite->pcidev = pcidev;
  76                 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  77                         mite->channels[i].mite = mite;
  78                         mite->channels[i].channel = i;
  79                         mite->channels[i].done = 1;
  80                 }
  81         }
  82         return mite;
  83 }
  84 EXPORT_SYMBOL(mite_alloc);
  85
  86 static void dump_chip_signature(u32 csigr_bits)
  87 {
  88         pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
  89                 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
  90                 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
  91         pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
  92                 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
  93                 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
  94 }
  95
  96 static unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
  97 {
  98         unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
  99         unsigned empty_count = (fcr_bits >> 16) & 0xff;
 100         unsigned full_count = fcr_bits & 0xff;
 101         return empty_count + full_count;
 102 }
 103
 104 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
 105 {
 106         unsigned long length;
 107         resource_size_t addr;
 108         int i;
 109         u32 csigr_bits;
 110         unsigned unknown_dma_burst_bits;
 111
 112         if (comedi_pci_enable(mite->pcidev, "mite")) {
 113                 dev_err(&mite->pcidev->dev,
 114                         "error enabling mite and requesting io regions\n");
 115                 return -EIO;
 116         }
 117         pci_set_master(mite->pcidev);
 118
 119         addr = pci_resource_start(mite->pcidev, 0);
 120         mite->mite_phys_addr = addr;
 121         mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
 122         if (!mite->mite_io_addr) {
 123                 dev_err(&mite->pcidev->dev,
 124                         "Failed to remap mite io memory address\n");
 125                 return -ENOMEM;
 126         }
 127
 128         addr = pci_resource_start(mite->pcidev, 1);
 129         mite->daq_phys_addr = addr;
 130         length = pci_resource_len(mite->pcidev, 1);
 131         /*
 132          * In case of a 660x board, DAQ size is 8k instead of 4k
 133          * (see as shown by lspci output)
 134          */
 135         mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
 136         if (!mite->daq_io_addr) {
 137                 dev_err(&mite->pcidev->dev,
 138                         "Failed to remap daq io memory address\n");
 139                 return -ENOMEM;
 140         }
 141
 142         if (use_iodwbsr_1) {
 143                 writel(0, mite->mite_io_addr + MITE_IODWBSR);
 144                 dev_info(&mite->pcidev->dev,
 145                          "using I/O Window Base Size register 1\n");
 146                 writel(mite->daq_phys_addr | WENAB |
 147                        MITE_IODWBSR_1_WSIZE_bits(length),
 148                        mite->mite_io_addr + MITE_IODWBSR_1);
 149                 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
 150         } else {
 151                 writel(mite->daq_phys_addr | WENAB,
 152                        mite->mite_io_addr + MITE_IODWBSR);
 153         }
 154         /*
 155          * make sure dma bursts work. I got this from running a bus analyzer
 156          * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
 157          * of 0x61f and bursts worked. 6281 powered up with register value of
 158          * 0x1f and bursts didn't work. The NI windows driver reads the
 159          * register, then does a bitwise-or of 0x600 with it and writes it back.
 160          */
 161         unknown_dma_burst_bits =
 162             readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 163         unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
 164         writel(unknown_dma_burst_bits,
 165                mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 166
 167         csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
 168         mite->num_channels = mite_csigr_dmac(csigr_bits);
 169         if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
 170                 dev_warn(&mite->pcidev->dev,
 171                          "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
 172                          mite->num_channels, MAX_MITE_DMA_CHANNELS);
 173                 mite->num_channels = MAX_MITE_DMA_CHANNELS;
 174         }
 175         dump_chip_signature(csigr_bits);
 176         for (i = 0; i < mite->num_channels; i++) {
 177                 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
 178                 /* disable interrupts */
 179                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 180                        CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 181                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 182                        mite->mite_io_addr + MITE_CHCR(i));
 183         }
 184         mite->fifo_size = mite_fifo_size(mite, 0);
 185         dev_info(&mite->pcidev->dev, "fifo size is %i.\n", mite->fifo_size);
 186         return 0;
 187 }
 188 EXPORT_SYMBOL(mite_setup2);
 189
 190 int mite_setup(struct mite_struct *mite)
 191 {
 192         return mite_setup2(mite, 0);
 193 }
 194 EXPORT_SYMBOL(mite_setup);
 195
 196 void mite_unsetup(struct mite_struct *mite)
 197 {
 198         /* unsigned long offset, start, length; */
 199
 200         if (!mite)
 201                 return;
 202
 203         if (mite->mite_io_addr) {
 204                 iounmap(mite->mite_io_addr);
 205                 mite->mite_io_addr = NULL;
 206         }
 207         if (mite->daq_io_addr) {
 208                 iounmap(mite->daq_io_addr);
 209                 mite->daq_io_addr = NULL;
 210         }
 211         if (mite->mite_phys_addr) {
 212                 comedi_pci_disable(mite->pcidev);
 213                 mite->mite_phys_addr = 0;
 214         }
 215 }
 216 EXPORT_SYMBOL(mite_unsetup);
 217
 218 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite)
 219 {
 220         struct mite_dma_descriptor_ring *ring =
 221             kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
 222
 223         if (ring == NULL)
 224                 return ring;
 225         ring->hw_dev = get_device(&mite->pcidev->dev);
 226         if (ring->hw_dev == NULL) {
 227                 kfree(ring);
 228                 return NULL;
 229         }
 230         ring->n_links = 0;
 231         ring->descriptors = NULL;
 232         ring->descriptors_dma_addr = 0;
 233         return ring;
 234 };
 235 EXPORT_SYMBOL(mite_alloc_ring);
 236
 237 void mite_free_ring(struct mite_dma_descriptor_ring *ring)
 238 {
 239         if (ring) {
 240                 if (ring->descriptors) {
 241                         dma_free_coherent(ring->hw_dev,
 242                                           ring->n_links *
 243                                           sizeof(struct mite_dma_descriptor),
 244                                           ring->descriptors,
 245                                           ring->descriptors_dma_addr);
 246                 }
 247                 put_device(ring->hw_dev);
 248                 kfree(ring);
 249         }
 250 };
 251 EXPORT_SYMBOL(mite_free_ring);
 252
 253 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
 254                                                    struct
 255                                                    mite_dma_descriptor_ring
 256                                                    *ring, unsigned min_channel,
 257                                                    unsigned max_channel)
 258 {
 259         int i;
 260         unsigned long flags;
 261         struct mite_channel *channel = NULL;
 262
 263         /* spin lock so mite_release_channel can be called safely
 264          * from interrupts
 265          */
 266         spin_lock_irqsave(&mite->lock, flags);
 267         for (i = min_channel; i <= max_channel; ++i) {
 268                 if (mite->channel_allocated[i] == 0) {
 269                         mite->channel_allocated[i] = 1;
 270                         channel = &mite->channels[i];
 271                         channel->ring = ring;
 272                         break;
 273                 }
 274         }
 275         spin_unlock_irqrestore(&mite->lock, flags);
 276         return channel;
 277 }
 278 EXPORT_SYMBOL(mite_request_channel_in_range);
 279
 280 void mite_release_channel(struct mite_channel *mite_chan)
 281 {
 282         struct mite_struct *mite = mite_chan->mite;
 283         unsigned long flags;
 284
 285         /*  spin lock to prevent races with mite_request_channel */
 286         spin_lock_irqsave(&mite->lock, flags);
 287         if (mite->channel_allocated[mite_chan->channel]) {
 288                 mite_dma_disarm(mite_chan);
 289                 mite_dma_reset(mite_chan);
 290         /*
 291          * disable all channel's interrupts (do it after disarm/reset so
 292          * MITE_CHCR reg isn't changed while dma is still active!)
 293          */
 294                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
 295                        CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
 296                        CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 297                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 298                        mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 299                 mite->channel_allocated[mite_chan->channel] = 0;
 300                 mite_chan->ring = NULL;
 301                 mmiowb();
 302         }
 303         spin_unlock_irqrestore(&mite->lock, flags);
 304 }
 305 EXPORT_SYMBOL(mite_release_channel);
 306
 307 void mite_dma_arm(struct mite_channel *mite_chan)
 308 {
 309         struct mite_struct *mite = mite_chan->mite;
 310         int chor;
 311         unsigned long flags;
 312
 313         MDPRINTK("mite_dma_arm ch%i\n", mite_chan->channel);
 314         /*
 315          * memory barrier is intended to insure any twiddling with the buffer
 316          * is done before writing to the mite to arm dma transfer
 317          */
 318         smp_mb();
 319         /* arm */
 320         chor = CHOR_START;
 321         spin_lock_irqsave(&mite->lock, flags);
 322         mite_chan->done = 0;
 323         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 324         mmiowb();
 325         spin_unlock_irqrestore(&mite->lock, flags);
 326 /*       mite_dma_tcr(mite, channel); */
 327 }
 328 EXPORT_SYMBOL(mite_dma_arm);
 329
 330 /**************************************/
 331
 332 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 333                     struct comedi_async *async)
 334 {
 335         unsigned int n_links;
 336         int i;
 337
 338         if (ring->descriptors) {
 339                 dma_free_coherent(ring->hw_dev,
 340                                   ring->n_links *
 341                                   sizeof(struct mite_dma_descriptor),
 342                                   ring->descriptors,
 343                                   ring->descriptors_dma_addr);
 344         }
 345         ring->descriptors = NULL;
 346         ring->descriptors_dma_addr = 0;
 347         ring->n_links = 0;
 348
 349         if (async->prealloc_bufsz == 0)
 350                 return 0;
 351
 352         n_links = async->prealloc_bufsz >> PAGE_SHIFT;
 353
 354         MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
 355
 356         ring->descriptors =
 357             dma_alloc_coherent(ring->hw_dev,
 358                                n_links * sizeof(struct mite_dma_descriptor),
 359                                &ring->descriptors_dma_addr, GFP_KERNEL);
 360         if (!ring->descriptors) {
 361                 dev_err(async->subdevice->device->class_dev,
 362                         "mite: ring buffer allocation failed\n");
 363                 return -ENOMEM;
 364         }
 365         ring->n_links = n_links;
 366
 367         for (i = 0; i < n_links; i++) {
 368                 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
 369                 ring->descriptors[i].addr =
 370                     cpu_to_le32(async->buf_page_list[i].dma_addr);
 371                 ring->descriptors[i].next =
 372                     cpu_to_le32(ring->descriptors_dma_addr + (i +
 373                                                               1) *
 374                                 sizeof(struct mite_dma_descriptor));
 375         }
 376         ring->descriptors[n_links - 1].next =
 377             cpu_to_le32(ring->descriptors_dma_addr);
 378         /*
 379          * barrier is meant to insure that all the writes to the dma descriptors
 380          * have completed before the dma controller is commanded to read them
 381          */
 382         smp_wmb();
 383         return 0;
 384 }
 385 EXPORT_SYMBOL(mite_buf_change);
 386
 387 void mite_prep_dma(struct mite_channel *mite_chan,
 388                    unsigned int num_device_bits, unsigned int num_memory_bits)
 389 {
 390         unsigned int chor, chcr, mcr, dcr, lkcr;
 391         struct mite_struct *mite = mite_chan->mite;
 392
 393         MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
 394
 395         /* reset DMA and FIFO */
 396         chor = CHOR_DMARESET | CHOR_FRESET;
 397         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 398
 399         /* short link chaining mode */
 400         chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
 401             CHCR_BURSTEN;
 402         /*
 403          * Link Complete Interrupt: interrupt every time a link
 404          * in MITE_RING is completed. This can generate a lot of
 405          * extra interrupts, but right now we update the values
 406          * of buf_int_ptr and buf_int_count at each interrupt. A
 407          * better method is to poll the MITE before each user
 408          * "read()" to calculate the number of bytes available.
 409          */
 410         chcr |= CHCR_SET_LC_IE;
 411         if (num_memory_bits == 32 && num_device_bits == 16) {
 412                 /*
 413                  * Doing a combined 32 and 16 bit byteswap gets the 16 bit
 414                  * samples into the fifo in the right order. Tested doing 32 bit
 415                  * memory to 16 bit device transfers to the analog out of a
 416                  * pxi-6281, which has mite version = 1, type = 4. This also
 417                  * works for dma reads from the counters on e-series boards.
 418                  */
 419                 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
 420         }
 421         if (mite_chan->dir == COMEDI_INPUT)
 422                 chcr |= CHCR_DEV_TO_MEM;
 423
 424         writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 425
 426         /* to/from memory */
 427         mcr = CR_RL(64) | CR_ASEQUP;
 428         switch (num_memory_bits) {
 429         case 8:
 430                 mcr |= CR_PSIZE8;
 431                 break;
 432         case 16:
 433                 mcr |= CR_PSIZE16;
 434                 break;
 435         case 32:
 436                 mcr |= CR_PSIZE32;
 437                 break;
 438         default:
 439                 pr_warn("bug! invalid mem bit width for dma transfer\n");
 440                 break;
 441         }
 442         writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
 443
 444         /* from/to device */
 445         dcr = CR_RL(64) | CR_ASEQUP;
 446         dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
 447         switch (num_device_bits) {
 448         case 8:
 449                 dcr |= CR_PSIZE8;
 450                 break;
 451         case 16:
 452                 dcr |= CR_PSIZE16;
 453                 break;
 454         case 32:
 455                 dcr |= CR_PSIZE32;
 456                 break;
 457         default:
 458                 pr_warn("bug! invalid dev bit width for dma transfer\n");
 459                 break;
 460         }
 461         writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
 462
 463         /* reset the DAR */
 464         writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 465
 466         /* the link is 32bits */
 467         lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
 468         writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
 469
 470         /* starting address for link chaining */
 471         writel(mite_chan->ring->descriptors_dma_addr,
 472                mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 473
 474         MDPRINTK("exit mite_prep_dma\n");
 475 }
 476 EXPORT_SYMBOL(mite_prep_dma);
 477
 478 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
 479 {
 480         struct mite_struct *mite = mite_chan->mite;
 481         return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 482 }
 483
 484 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
 485 {
 486         struct mite_struct *mite = mite_chan->mite;
 487         return readl(mite->mite_io_addr +
 488                      MITE_FCR(mite_chan->channel)) & 0x000000FF;
 489 }
 490 EXPORT_SYMBOL(mite_bytes_in_transit);
 491
 492 /* returns lower bound for number of bytes transferred from device to memory */
 493 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
 494 {
 495         u32 device_byte_count;
 496
 497         device_byte_count = mite_device_bytes_transferred(mite_chan);
 498         return device_byte_count - mite_bytes_in_transit(mite_chan);
 499 }
 500 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
 501
 502 /* returns upper bound for number of bytes transferred from device to memory */
 503 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
 504 {
 505         u32 in_transit_count;
 506
 507         in_transit_count = mite_bytes_in_transit(mite_chan);
 508         return mite_device_bytes_transferred(mite_chan) - in_transit_count;
 509 }
 510 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
 511
 512 /* returns lower bound for number of bytes read from memory to device */
 513 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
 514 {
 515         u32 device_byte_count;
 516
 517         device_byte_count = mite_device_bytes_transferred(mite_chan);
 518         return device_byte_count + mite_bytes_in_transit(mite_chan);
 519 }
 520 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
 521
 522 /* returns upper bound for number of bytes read from memory to device */
 523 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
 524 {
 525         u32 in_transit_count;
 526
 527         in_transit_count = mite_bytes_in_transit(mite_chan);
 528         return mite_device_bytes_transferred(mite_chan) + in_transit_count;
 529 }
 530 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
 531
 532 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
 533 {
 534         struct mite_struct *mite = mite_chan->mite;
 535         int tcr;
 536         int lkar;
 537
 538         lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 539         tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
 540         MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
 541                  lkar, tcr);
 542
 543         return tcr;
 544 }
 545 EXPORT_SYMBOL(mite_dma_tcr);
 546
 547 void mite_dma_disarm(struct mite_channel *mite_chan)
 548 {
 549         struct mite_struct *mite = mite_chan->mite;
 550         unsigned chor;
 551
 552         /* disarm */
 553         chor = CHOR_ABORT;
 554         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 555 }
 556 EXPORT_SYMBOL(mite_dma_disarm);
 557
 558 int mite_sync_input_dma(struct mite_channel *mite_chan,
 559                         struct comedi_async *async)
 560 {
 561         int count;
 562         unsigned int nbytes, old_alloc_count;
 563         const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
 564
 565         old_alloc_count = async->buf_write_alloc_count;
 566         /* write alloc as much as we can */
 567         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 568
 569         nbytes = mite_bytes_written_to_memory_lb(mite_chan);
 570         if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
 571                   old_alloc_count) > 0) {
 572                 dev_warn(async->subdevice->device->class_dev,
 573                          "mite: DMA overwrite of free area\n");
 574                 async->events |= COMEDI_CB_OVERFLOW;
 575                 return -1;
 576         }
 577
 578         count = nbytes - async->buf_write_count;
 579         /* it's possible count will be negative due to
 580          * conservative value returned by mite_bytes_written_to_memory_lb */
 581         if (count <= 0)
 582                 return 0;
 583
 584         comedi_buf_write_free(async, count);
 585
 586         async->scan_progress += count;
 587         if (async->scan_progress >= bytes_per_scan) {
 588                 async->scan_progress %= bytes_per_scan;
 589                 async->events |= COMEDI_CB_EOS;
 590         }
 591         async->events |= COMEDI_CB_BLOCK;
 592         return 0;
 593 }
 594 EXPORT_SYMBOL(mite_sync_input_dma);
 595
 596 int mite_sync_output_dma(struct mite_channel *mite_chan,
 597                          struct comedi_async *async)
 598 {
 599         int count;
 600         u32 nbytes_ub, nbytes_lb;
 601         unsigned int old_alloc_count;
 602         u32 stop_count =
 603             async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
 604
 605         old_alloc_count = async->buf_read_alloc_count;
 606         /*  read alloc as much as we can */
 607         comedi_buf_read_alloc(async, async->prealloc_bufsz);
 608         nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
 609         if (async->cmd.stop_src == TRIG_COUNT &&
 610             (int)(nbytes_lb - stop_count) > 0)
 611                 nbytes_lb = stop_count;
 612         nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
 613         if (async->cmd.stop_src == TRIG_COUNT &&
 614             (int)(nbytes_ub - stop_count) > 0)
 615                 nbytes_ub = stop_count;
 616         if ((int)(nbytes_ub - old_alloc_count) > 0) {
 617                 dev_warn(async->subdevice->device->class_dev,
 618                          "mite: DMA underrun\n");
 619                 async->events |= COMEDI_CB_OVERFLOW;
 620                 return -1;
 621         }
 622         count = nbytes_lb - async->buf_read_count;
 623         if (count <= 0)
 624                 return 0;
 625
 626         if (count) {
 627                 comedi_buf_read_free(async, count);
 628                 async->events |= COMEDI_CB_BLOCK;
 629         }
 630         return 0;
 631 }
 632 EXPORT_SYMBOL(mite_sync_output_dma);
 633
 634 unsigned mite_get_status(struct mite_channel *mite_chan)
 635 {
 636         struct mite_struct *mite = mite_chan->mite;
 637         unsigned status;
 638         unsigned long flags;
 639
 640         spin_lock_irqsave(&mite->lock, flags);
 641         status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 642         if (status & CHSR_DONE) {
 643                 mite_chan->done = 1;
 644                 writel(CHOR_CLRDONE,
 645                        mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 646         }
 647         mmiowb();
 648         spin_unlock_irqrestore(&mite->lock, flags);
 649         return status;
 650 }
 651 EXPORT_SYMBOL(mite_get_status);
 652
 653 int mite_done(struct mite_channel *mite_chan)
 654 {
 655         struct mite_struct *mite = mite_chan->mite;
 656         unsigned long flags;
 657         int done;
 658
 659         mite_get_status(mite_chan);
 660         spin_lock_irqsave(&mite->lock, flags);
 661         done = mite_chan->done;
 662         spin_unlock_irqrestore(&mite->lock, flags);
 663         return done;
 664 }
 665 EXPORT_SYMBOL(mite_done);
 666
 667 #ifdef DEBUG_MITE
 668
 669 /* names of bits in mite registers */
 670
 671 static const char *const mite_CHOR_strings[] = {
 672         "start", "cont", "stop", "abort",
 673         "freset", "clrlc", "clrrb", "clrdone",
 674         "clr_lpause", "set_lpause", "clr_send_tc",
 675         "set_send_tc", "12", "13", "14",
 676         "15", "16", "17", "18",
 677         "19", "20", "21", "22",
 678         "23", "24", "25", "26",
 679         "27", "28", "29", "30",
 680         "dmareset",
 681 };
 682
 683 static const char *const mite_CHCR_strings[] = {
 684         "continue", "ringbuff", "2", "3",
 685         "4", "5", "6", "7",
 686         "8", "9", "10", "11",
 687         "12", "13", "bursten", "fifodis",
 688         "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
 689         "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
 690         "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
 691         "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
 692 };
 693
 694 static const char *const mite_MCR_strings[] = {
 695         "amdevice", "1", "2", "3",
 696         "4", "5", "portio", "portvxi",
 697         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
 698         "12", "13", "blocken", "berhand",
 699         "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
 700         "rd512", "rl1", "rl2", "rl8",
 701         "24", "25", "26", "27",
 702         "28", "29", "30", "stopen",
 703 };
 704
 705 static const char *const mite_DCR_strings[] = {
 706         "amdevice", "1", "2", "3",
 707         "4", "5", "portio", "portvxi",
 708         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
 709         "aseqxp8", "13", "blocken", "berhand",
 710         "reqsintlim", "reqs1", "reqs2", "rd32",
 711         "rd512", "rl1", "rl2", "rl8",
 712         "23", "24", "25", "27",
 713         "28", "wsdevc", "wsdevs", "rwdevpack",
 714 };
 715
 716 static const char *const mite_LKCR_strings[] = {
 717         "amdevice", "1", "2", "3",
 718         "4", "5", "portio", "portvxi",
 719         "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
 720         "12", "13", "14", "berhand",
 721         "16", "17", "18", "rd32",
 722         "rd512", "rl1", "rl2", "rl8",
 723         "24", "25", "26", "27",
 724         "28", "29", "30", "chngend",
 725 };
 726
 727 static const char *const mite_CHSR_strings[] = {
 728         "d.err0", "d.err1", "m.err0", "m.err1",
 729         "l.err0", "l.err1", "drq0", "drq1",
 730         "end", "xferr", "operr0", "operr1",
 731         "stops", "habort", "sabort", "error",
 732         "16", "conts_rb", "18", "linkc",
 733         "20", "drdy", "22", "mrdy",
 734         "24", "done", "26", "sars",
 735         "28", "lpauses", "30", "int",
 736 };
 737
 738 static void mite_decode(const char *const *bit_str, unsigned int bits)
 739 {
 740         int i;
 741
 742         for (i = 31; i >= 0; i--) {
 743                 if (bits & (1 << i))
 744                         pr_debug(" %s\n", bit_str[i]);
 745         }
 746 }
 747
 748 void mite_dump_regs(struct mite_channel *mite_chan)
 749 {
 750         void __iomem *mite_io_addr = mite_chan->mite->mite_io_addr;
 751         unsigned int offset;
 752         unsigned int value;
 753         int channel = mite_chan->channel;
 754
 755         pr_debug("mite_dump_regs ch%i\n", channel);
 756         pr_debug("mite address is  =%p\n", mite_io_addr);
 757
 758         offset = MITE_CHOR(channel);
 759         value = readl(mite_io_addr + offset);
 760         pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset, value);
 761         mite_decode(mite_CHOR_strings, value);
 762         offset = MITE_CHCR(channel);
 763         value = readl(mite_io_addr + offset);
 764         pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset, value);
 765         mite_decode(mite_CHCR_strings, value);
 766         offset = MITE_TCR(channel);
 767         value = readl(mite_io_addr + offset);
 768         pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset, value);
 769         offset = MITE_MCR(channel);
 770         value = readl(mite_io_addr + offset);
 771         pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset, value);
 772         mite_decode(mite_MCR_strings, value);
 773         offset = MITE_MAR(channel);
 774         value = readl(mite_io_addr + offset);
 775         pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset, value);
 776         offset = MITE_DCR(channel);
 777         value = readl(mite_io_addr + offset);
 778         pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset, value);
 779         mite_decode(mite_DCR_strings, value);
 780         offset = MITE_DAR(channel);
 781         value = readl(mite_io_addr + offset);
 782         pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset, value);
 783         offset = MITE_LKCR(channel);
 784         value = readl(mite_io_addr + offset);
 785         pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset, value);
 786         mite_decode(mite_LKCR_strings, value);
 787         offset = MITE_LKAR(channel);
 788         value = readl(mite_io_addr + offset);
 789         pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset, value);
 790         offset = MITE_CHSR(channel);
 791         value = readl(mite_io_addr + offset);
 792         pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset, value);
 793         mite_decode(mite_CHSR_strings, value);
 794         offset = MITE_FCR(channel);
 795         value = readl(mite_io_addr + offset);
 796         pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset, value);
 797 }
 798 EXPORT_SYMBOL(mite_dump_regs);
 799 #endif
 800
 801 static int __init mite_module_init(void)
 802 {
 803         return 0;
 804 }
 805
 806 static void __exit mite_module_exit(void)
 807 {
 808 }
 809
 810 module_init(mite_module_init);
 811 module_exit(mite_module_exit);
 812
 813 MODULE_AUTHOR("Comedi http://www.comedi.org");
 814 MODULE_DESCRIPTION("Comedi low-level driver");
 815 MODULE_LICENSE("GPL");