3 comedi/drivers/me_daq.c
5 Hardware driver for Meilhaus data acquisition cards:
7 ME-2000i, ME-2600i, ME-3000vm1
9 Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Description: Meilhaus PCI data acquisition cards
29 Author: Michael Hillmann <hillmann@syscongroup.de>
30 Devices: [Meilhaus] ME-2600i (me_daq), ME-2000i
37 Configuration options:
39 [0] - PCI bus number (optional)
40 [1] - PCI slot number (optional)
42 If bus/slot is not specified, the first available PCI
46 #include <linux/interrupt.h>
47 #include <linux/sched.h>
48 #include <linux/firmware.h>
49 #include "../comedidev.h"
51 #define ME2600_FIRMWARE "me2600_firmware.bin"
53 #define ME2000_DEVICE_ID 0x2000
54 #define ME2600_DEVICE_ID 0x2600
56 #define PLX_INTCSR 0x4C /* PLX interrupt status register */
57 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
59 #define ME_CONTROL_1 0x0000 /* - | W */
60 #define INTERRUPT_ENABLE (1<<15)
61 #define COUNTER_B_IRQ (1<<12)
62 #define COUNTER_A_IRQ (1<<11)
63 #define CHANLIST_READY_IRQ (1<<10)
64 #define EXT_IRQ (1<<9)
65 #define ADFIFO_HALFFULL_IRQ (1<<8)
66 #define SCAN_COUNT_ENABLE (1<<5)
67 #define SIMULTANEOUS_ENABLE (1<<4)
68 #define TRIGGER_FALLING_EDGE (1<<3)
69 #define CONTINUOUS_MODE (1<<2)
70 #define DISABLE_ADC (0<<0)
71 #define SOFTWARE_TRIGGERED_ADC (1<<0)
72 #define SCAN_TRIGGERED_ADC (2<<0)
73 #define EXT_TRIGGERED_ADC (3<<0)
74 #define ME_ADC_START 0x0000 /* R | - */
75 #define ME_CONTROL_2 0x0002 /* - | W */
76 #define ENABLE_ADFIFO (1<<10)
77 #define ENABLE_CHANLIST (1<<9)
78 #define ENABLE_PORT_B (1<<7)
79 #define ENABLE_PORT_A (1<<6)
80 #define ENABLE_COUNTER_B (1<<4)
81 #define ENABLE_COUNTER_A (1<<3)
82 #define ENABLE_DAC (1<<1)
83 #define BUFFERED_DAC (1<<0)
84 #define ME_DAC_UPDATE 0x0002 /* R | - */
85 #define ME_STATUS 0x0004 /* R | - */
86 #define COUNTER_B_IRQ_PENDING (1<<12)
87 #define COUNTER_A_IRQ_PENDING (1<<11)
88 #define CHANLIST_READY_IRQ_PENDING (1<<10)
89 #define EXT_IRQ_PENDING (1<<9)
90 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
91 #define ADFIFO_FULL (1<<4)
92 #define ADFIFO_HALFFULL (1<<3)
93 #define ADFIFO_EMPTY (1<<2)
94 #define CHANLIST_FULL (1<<1)
95 #define FST_ACTIVE (1<<0)
96 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
97 #define ME_DIO_PORT_A 0x0006 /* R | W */
98 #define ME_DIO_PORT_B 0x0008 /* R | W */
99 #define ME_TIMER_DATA_0 0x000A /* - | W */
100 #define ME_TIMER_DATA_1 0x000C /* - | W */
101 #define ME_TIMER_DATA_2 0x000E /* - | W */
102 #define ME_CHANNEL_LIST 0x0010 /* - | W */
103 #define ADC_UNIPOLAR (1<<6)
104 #define ADC_GAIN_0 (0<<4)
105 #define ADC_GAIN_1 (1<<4)
106 #define ADC_GAIN_2 (2<<4)
107 #define ADC_GAIN_3 (3<<4)
108 #define ME_READ_AD_FIFO 0x0010 /* R | - */
109 #define ME_DAC_CONTROL 0x0012 /* - | W */
110 #define DAC_UNIPOLAR_D (0<<4)
111 #define DAC_BIPOLAR_D (1<<4)
112 #define DAC_UNIPOLAR_C (0<<5)
113 #define DAC_BIPOLAR_C (1<<5)
114 #define DAC_UNIPOLAR_B (0<<6)
115 #define DAC_BIPOLAR_B (1<<6)
116 #define DAC_UNIPOLAR_A (0<<7)
117 #define DAC_BIPOLAR_A (1<<7)
118 #define DAC_GAIN_0_D (0<<8)
119 #define DAC_GAIN_1_D (1<<8)
120 #define DAC_GAIN_0_C (0<<9)
121 #define DAC_GAIN_1_C (1<<9)
122 #define DAC_GAIN_0_B (0<<10)
123 #define DAC_GAIN_1_B (1<<10)
124 #define DAC_GAIN_0_A (0<<11)
125 #define DAC_GAIN_1_A (1<<11)
126 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
127 #define ME_DAC_DATA_A 0x0014 /* - | W */
128 #define ME_DAC_DATA_B 0x0016 /* - | W */
129 #define ME_DAC_DATA_C 0x0018 /* - | W */
130 #define ME_DAC_DATA_D 0x001A /* - | W */
131 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
132 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
133 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
134 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
135 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
136 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
138 static const struct comedi_lrange me2000_ai_range = {
152 static const struct comedi_lrange me2600_ai_range = {
166 static const struct comedi_lrange me2600_ao_range = {
175 /* Board specification structure */
177 const char *name; /* driver name */
179 int ao_channel_nbr; /* DA config */
181 int ao_resolution_mask;
182 const struct comedi_lrange *ao_range_list;
183 int ai_channel_nbr; /* AD config */
185 int ai_resolution_mask;
186 const struct comedi_lrange *ai_range_list;
187 int dio_channel_nbr; /* DIO config */
190 static const struct me_board me_boards[] = {
193 .device_id = ME2600_DEVICE_ID,
197 .ao_resolution_mask = 0x0fff,
198 .ao_range_list = &me2600_ao_range,
199 .ai_channel_nbr = 16,
202 .ai_resolution_mask = 0x0fff,
203 .ai_range_list = &me2600_ai_range,
204 .dio_channel_nbr = 32,
208 .device_id = ME2000_DEVICE_ID,
212 .ao_resolution_mask = 0,
213 .ao_range_list = NULL,
214 .ai_channel_nbr = 16,
217 .ai_resolution_mask = 0x0fff,
218 .ai_range_list = &me2000_ai_range,
219 .dio_channel_nbr = 32,
223 /* Private data structure */
224 struct me_private_data {
225 void __iomem *plx_regbase; /* PLX configuration base address */
226 void __iomem *me_regbase; /* Base address of the Meilhaus card */
227 unsigned long plx_regbase_size; /* Size of PLX configuration space */
228 unsigned long me_regbase_size; /* Size of Meilhaus space */
230 unsigned short control_1; /* Mirror of CONTROL_1 register */
231 unsigned short control_2; /* Mirror of CONTROL_2 register */
232 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
233 int ao_readback[4]; /* Mirror of analog output data */
237 * ------------------------------------------------------------------
241 * ------------------------------------------------------------------
243 static inline void sleep(unsigned sec)
245 current->state = TASK_INTERRUPTIBLE;
246 schedule_timeout(sec * HZ);
250 * ------------------------------------------------------------------
252 * DIGITAL INPUT/OUTPUT SECTION
254 * ------------------------------------------------------------------
256 static int me_dio_insn_config(struct comedi_device *dev,
257 struct comedi_subdevice *s,
258 struct comedi_insn *insn, unsigned int *data)
260 struct me_private_data *dev_private = dev->private;
262 int mask = 1 << CR_CHAN(insn->chanspec);
265 if (mask & 0x0000ffff) { /* Port A in use */
269 dev_private->control_2 |= ENABLE_PORT_A;
270 writew(dev_private->control_2,
271 dev_private->me_regbase + ME_CONTROL_2);
272 } else { /* Port B in use */
277 dev_private->control_2 |= ENABLE_PORT_B;
278 writew(dev_private->control_2,
279 dev_private->me_regbase + ME_CONTROL_2);
283 /* Config port as output */
286 /* Config port as input */
293 /* Digital instant input/outputs */
294 static int me_dio_insn_bits(struct comedi_device *dev,
295 struct comedi_subdevice *s,
296 struct comedi_insn *insn, unsigned int *data)
298 struct me_private_data *dev_private = dev->private;
299 unsigned int mask = data[0];
302 s->state |= (mask & data[1]);
305 if (mask & 0x0000ffff) { /* Port A */
306 writew((s->state & 0xffff),
307 dev_private->me_regbase + ME_DIO_PORT_A);
309 data[1] &= ~0x0000ffff;
310 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A);
313 if (mask & 0xffff0000) { /* Port B */
314 writew(((s->state >> 16) & 0xffff),
315 dev_private->me_regbase + ME_DIO_PORT_B);
317 data[1] &= ~0xffff0000;
318 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16;
325 * ------------------------------------------------------------------
327 * ANALOG INPUT SECTION
329 * ------------------------------------------------------------------
332 /* Analog instant input */
333 static int me_ai_insn_read(struct comedi_device *dev,
334 struct comedi_subdevice *s,
335 struct comedi_insn *insn, unsigned int *data)
337 struct me_private_data *dev_private = dev->private;
338 unsigned short value;
339 int chan = CR_CHAN((&insn->chanspec)[0]);
340 int rang = CR_RANGE((&insn->chanspec)[0]);
341 int aref = CR_AREF((&insn->chanspec)[0]);
344 /* stop any running conversion */
345 dev_private->control_1 &= 0xFFFC;
346 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
348 /* clear chanlist and ad fifo */
349 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
350 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
352 /* reset any pending interrupt */
353 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
355 /* enable the chanlist and ADC fifo */
356 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
357 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
359 /* write to channel list fifo */
360 /* b3:b0 are the channel number */
362 /* b5:b4 are the channel gain */
363 value |= (rang & 0x03) << 4;
364 /* b6 channel polarity */
365 value |= (rang & 0x04) << 4;
366 /* b7 single or differential */
367 value |= ((aref & AREF_DIFF) ? 0x80 : 0);
368 writew(value & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
370 /* set ADC mode to software trigger */
371 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
372 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
374 /* start conversion by reading from ADC_START */
375 readw(dev_private->me_regbase + ME_ADC_START);
377 /* wait for ADC fifo not empty flag */
378 for (i = 100000; i > 0; i--)
379 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
382 /* get value from ADC fifo */
385 (readw(dev_private->me_regbase +
386 ME_READ_AD_FIFO) ^ 0x800) & 0x0FFF;
388 dev_err(dev->class_dev, "Cannot get single value\n");
392 /* stop any running conversion */
393 dev_private->control_1 &= 0xFFFC;
394 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
400 * ------------------------------------------------------------------
402 * HARDWARE TRIGGERED ANALOG INPUT SECTION
404 * ------------------------------------------------------------------
407 /* Cancel analog input autoscan */
408 static int me_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
410 struct me_private_data *dev_private = dev->private;
412 /* disable interrupts */
414 /* stop any running conversion */
415 dev_private->control_1 &= 0xFFFC;
416 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
421 /* Test analog input command */
422 static int me_ai_do_cmd_test(struct comedi_device *dev,
423 struct comedi_subdevice *s, struct comedi_cmd *cmd)
428 /* Analog input command */
429 static int me_ai_do_cmd(struct comedi_device *dev,
430 struct comedi_subdevice *s)
436 * ------------------------------------------------------------------
438 * ANALOG OUTPUT SECTION
440 * ------------------------------------------------------------------
443 /* Analog instant output */
444 static int me_ao_insn_write(struct comedi_device *dev,
445 struct comedi_subdevice *s,
446 struct comedi_insn *insn, unsigned int *data)
448 struct me_private_data *dev_private = dev->private;
454 dev_private->control_2 |= ENABLE_DAC;
455 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
457 /* and set DAC to "buffered" mode */
458 dev_private->control_2 |= BUFFERED_DAC;
459 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
461 /* Set dac-control register */
462 for (i = 0; i < insn->n; i++) {
463 chan = CR_CHAN((&insn->chanspec)[i]);
464 rang = CR_RANGE((&insn->chanspec)[i]);
466 /* clear bits for this channel */
467 dev_private->dac_control &= ~(0x0880 >> chan);
469 dev_private->dac_control |=
470 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
472 dev_private->dac_control |=
473 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
475 writew(dev_private->dac_control,
476 dev_private->me_regbase + ME_DAC_CONTROL);
478 /* Update dac-control register */
479 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
481 /* Set data register */
482 for (i = 0; i < insn->n; i++) {
483 chan = CR_CHAN((&insn->chanspec)[i]);
484 writew((data[0] & s->maxdata),
485 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
486 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
489 /* Update dac with data registers */
490 readw(dev_private->me_regbase + ME_DAC_UPDATE);
495 /* Analog output readback */
496 static int me_ao_insn_read(struct comedi_device *dev,
497 struct comedi_subdevice *s, struct comedi_insn *insn,
500 struct me_private_data *dev_private = dev->private;
503 for (i = 0; i < insn->n; i++) {
505 dev_private->ao_readback[CR_CHAN((&insn->chanspec)[i])];
512 * ------------------------------------------------------------------
514 * INITIALISATION SECTION
516 * ------------------------------------------------------------------
519 /* Xilinx firmware download for card: ME-2600i */
520 static int me2600_xilinx_download(struct comedi_device *dev,
521 const u8 *data, size_t size)
523 struct me_private_data *dev_private = dev->private;
525 unsigned int file_length;
528 /* disable irq's on PLX */
529 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
531 /* First, make a dummy read to reset xilinx */
532 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
534 /* Wait until reset is over */
537 /* Write a dummy value to Xilinx */
538 writeb(0x00, dev_private->me_regbase + 0x0);
542 * Format of the firmware
543 * Build longs from the byte-wise coded header
544 * Byte 1-3: length of the array
547 * Byte 12-15: reserved
552 file_length = (((unsigned int)data[0] & 0xff) << 24) +
553 (((unsigned int)data[1] & 0xff) << 16) +
554 (((unsigned int)data[2] & 0xff) << 8) +
555 ((unsigned int)data[3] & 0xff);
558 * Loop for writing firmware byte by byte to xilinx
559 * Firmware data start at offfset 16
561 for (i = 0; i < file_length; i++)
562 writeb((data[16 + i] & 0xff),
563 dev_private->me_regbase + 0x0);
565 /* Write 5 dummy values to xilinx */
566 for (i = 0; i < 5; i++)
567 writeb(0x00, dev_private->me_regbase + 0x0);
569 /* Test if there was an error during download -> INTB was thrown */
570 value = readl(dev_private->plx_regbase + PLX_INTCSR);
572 /* Disable interrupt */
573 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
574 dev_err(dev->class_dev, "Xilinx download failed\n");
578 /* Wait until the Xilinx is ready for real work */
581 /* Enable PLX-Interrupts */
582 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
587 static int me2600_upload_firmware(struct comedi_device *dev)
589 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
590 const struct firmware *fw;
593 ret = request_firmware(&fw, ME2600_FIRMWARE, &pcidev->dev);
597 ret = me2600_xilinx_download(dev, fw->data, fw->size);
598 release_firmware(fw);
604 static int me_reset(struct comedi_device *dev)
606 struct me_private_data *dev_private = dev->private;
609 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
610 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
611 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
612 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
614 /* Save values in the board context */
615 dev_private->dac_control = 0;
616 dev_private->control_1 = 0;
617 dev_private->control_2 = 0;
622 static const void *me_find_boardinfo(struct comedi_device *dev,
623 struct pci_dev *pcidev)
625 const struct me_board *board;
628 for (i = 0; i < ARRAY_SIZE(me_boards); i++) {
629 board = &me_boards[i];
630 if (board->device_id == pcidev->device)
636 static int me_attach_pci(struct comedi_device *dev, struct pci_dev *pcidev)
638 const struct me_board *board;
639 struct me_private_data *dev_private;
640 struct comedi_subdevice *s;
641 resource_size_t plx_regbase_tmp;
642 unsigned long plx_regbase_size_tmp;
643 resource_size_t me_regbase_tmp;
644 unsigned long me_regbase_size_tmp;
645 resource_size_t swap_regbase_tmp;
646 unsigned long swap_regbase_size_tmp;
647 resource_size_t regbase_tmp;
650 board = me_find_boardinfo(dev, pcidev);
653 dev->board_ptr = board;
654 dev->board_name = board->name;
656 dev_private = kzalloc(sizeof(*dev_private), GFP_KERNEL);
659 dev->private = dev_private;
661 /* Enable PCI device and request PCI regions */
662 if (comedi_pci_enable(pcidev, dev->board_name) < 0) {
663 dev_err(dev->class_dev,
664 "Failed to enable PCI device and request regions\n");
668 /* Read PLX register base address [PCI_BASE_ADDRESS #0]. */
669 plx_regbase_tmp = pci_resource_start(pcidev, 0);
670 plx_regbase_size_tmp = pci_resource_len(pcidev, 0);
671 dev_private->plx_regbase =
672 ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
673 dev_private->plx_regbase_size = plx_regbase_size_tmp;
674 if (!dev_private->plx_regbase) {
675 dev_err(dev->class_dev, "Failed to remap I/O memory\n");
679 /* Read Swap base address [PCI_BASE_ADDRESS #5]. */
681 swap_regbase_tmp = pci_resource_start(pcidev, 5);
682 swap_regbase_size_tmp = pci_resource_len(pcidev, 5);
684 if (!swap_regbase_tmp)
685 dev_err(dev->class_dev, "Swap not present\n");
687 /*---------------------------------------------- Workaround start ---*/
688 if (plx_regbase_tmp & 0x0080) {
689 dev_err(dev->class_dev, "PLX-Bug detected\n");
691 if (swap_regbase_tmp) {
692 regbase_tmp = plx_regbase_tmp;
693 plx_regbase_tmp = swap_regbase_tmp;
694 swap_regbase_tmp = regbase_tmp;
696 result = pci_write_config_dword(pcidev,
699 if (result != PCIBIOS_SUCCESSFUL)
702 result = pci_write_config_dword(pcidev,
705 if (result != PCIBIOS_SUCCESSFUL)
708 plx_regbase_tmp -= 0x80;
709 result = pci_write_config_dword(pcidev,
712 if (result != PCIBIOS_SUCCESSFUL)
716 /*--------------------------------------------- Workaround end -----*/
718 /* Read Meilhaus register base address [PCI_BASE_ADDRESS #2]. */
720 me_regbase_tmp = pci_resource_start(pcidev, 2);
721 me_regbase_size_tmp = pci_resource_len(pcidev, 2);
722 dev_private->me_regbase_size = me_regbase_size_tmp;
723 dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
724 if (!dev_private->me_regbase) {
725 dev_err(dev->class_dev, "Failed to remap I/O memory\n");
729 /* Download firmware and reset card */
730 if (board->device_id == ME2600_DEVICE_ID) {
731 result = me2600_upload_firmware(dev);
737 error = comedi_alloc_subdevices(dev, 3);
741 s = &dev->subdevices[0];
742 s->type = COMEDI_SUBD_AI;
743 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
744 s->n_chan = board->ai_channel_nbr;
745 s->maxdata = board->ai_resolution_mask;
746 s->len_chanlist = board->ai_channel_nbr;
747 s->range_table = board->ai_range_list;
748 s->cancel = me_ai_cancel;
749 s->insn_read = me_ai_insn_read;
750 s->do_cmdtest = me_ai_do_cmd_test;
751 s->do_cmd = me_ai_do_cmd;
753 s = &dev->subdevices[1];
754 s->type = COMEDI_SUBD_AO;
755 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
756 s->n_chan = board->ao_channel_nbr;
757 s->maxdata = board->ao_resolution_mask;
758 s->len_chanlist = board->ao_channel_nbr;
759 s->range_table = board->ao_range_list;
760 s->insn_read = me_ao_insn_read;
761 s->insn_write = me_ao_insn_write;
763 s = &dev->subdevices[2];
764 s->type = COMEDI_SUBD_DIO;
765 s->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
766 s->n_chan = board->dio_channel_nbr;
768 s->len_chanlist = board->dio_channel_nbr;
769 s->range_table = &range_digital;
770 s->insn_bits = me_dio_insn_bits;
771 s->insn_config = me_dio_insn_config;
774 dev_info(dev->class_dev, "%s: %s attached\n",
775 dev->driver->driver_name, dev->board_name);
780 static void me_detach(struct comedi_device *dev)
782 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
783 struct me_private_data *dev_private = dev->private;
786 if (dev_private->me_regbase) {
788 iounmap(dev_private->me_regbase);
790 if (dev_private->plx_regbase)
791 iounmap(dev_private->plx_regbase);
794 if (dev_private->plx_regbase_size)
795 comedi_pci_disable(pcidev);
800 static struct comedi_driver me_daq_driver = {
801 .driver_name = "me_daq",
802 .module = THIS_MODULE,
803 .attach_pci = me_attach_pci,
807 static int __devinit me_daq_pci_probe(struct pci_dev *dev,
808 const struct pci_device_id *ent)
810 return comedi_pci_auto_config(dev, &me_daq_driver);
813 static void __devexit me_daq_pci_remove(struct pci_dev *dev)
815 comedi_pci_auto_unconfig(dev);
818 static DEFINE_PCI_DEVICE_TABLE(me_daq_pci_table) = {
819 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID) },
820 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID) },
823 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
825 static struct pci_driver me_daq_pci_driver = {
827 .id_table = me_daq_pci_table,
828 .probe = me_daq_pci_probe,
829 .remove = __devexit_p(me_daq_pci_remove),
831 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
833 MODULE_AUTHOR("Comedi http://www.comedi.org");
834 MODULE_DESCRIPTION("Comedi low-level driver");
835 MODULE_LICENSE("GPL");
836 MODULE_FIRMWARE(ME2600_FIRMWARE);