3 comedi/drivers/me_daq.c
5 Hardware driver for Meilhaus data acquisition cards:
7 ME-2000i, ME-2600i, ME-3000vm1
9 Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Description: Meilhaus PCI data acquisition cards
29 Author: Michael Hillmann <hillmann@syscongroup.de>
30 Devices: [Meilhaus] ME-2600i (me_daq), ME-2000i
37 Configuration options:
39 [0] - PCI bus number (optional)
40 [1] - PCI slot number (optional)
42 If bus/slot is not specified, the first available PCI
46 #include <linux/interrupt.h>
47 #include <linux/sched.h>
48 #include <linux/firmware.h>
49 #include "../comedidev.h"
51 #define ME2600_FIRMWARE "me2600_firmware.bin"
53 #define PCI_VENDOR_ID_MEILHAUS 0x1402
54 #define ME2000_DEVICE_ID 0x2000
55 #define ME2600_DEVICE_ID 0x2600
57 #define PLX_INTCSR 0x4C /* PLX interrupt status register */
58 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
60 #define ME_CONTROL_1 0x0000 /* - | W */
61 #define INTERRUPT_ENABLE (1<<15)
62 #define COUNTER_B_IRQ (1<<12)
63 #define COUNTER_A_IRQ (1<<11)
64 #define CHANLIST_READY_IRQ (1<<10)
65 #define EXT_IRQ (1<<9)
66 #define ADFIFO_HALFFULL_IRQ (1<<8)
67 #define SCAN_COUNT_ENABLE (1<<5)
68 #define SIMULTANEOUS_ENABLE (1<<4)
69 #define TRIGGER_FALLING_EDGE (1<<3)
70 #define CONTINUOUS_MODE (1<<2)
71 #define DISABLE_ADC (0<<0)
72 #define SOFTWARE_TRIGGERED_ADC (1<<0)
73 #define SCAN_TRIGGERED_ADC (2<<0)
74 #define EXT_TRIGGERED_ADC (3<<0)
75 #define ME_ADC_START 0x0000 /* R | - */
76 #define ME_CONTROL_2 0x0002 /* - | W */
77 #define ENABLE_ADFIFO (1<<10)
78 #define ENABLE_CHANLIST (1<<9)
79 #define ENABLE_PORT_B (1<<7)
80 #define ENABLE_PORT_A (1<<6)
81 #define ENABLE_COUNTER_B (1<<4)
82 #define ENABLE_COUNTER_A (1<<3)
83 #define ENABLE_DAC (1<<1)
84 #define BUFFERED_DAC (1<<0)
85 #define ME_DAC_UPDATE 0x0002 /* R | - */
86 #define ME_STATUS 0x0004 /* R | - */
87 #define COUNTER_B_IRQ_PENDING (1<<12)
88 #define COUNTER_A_IRQ_PENDING (1<<11)
89 #define CHANLIST_READY_IRQ_PENDING (1<<10)
90 #define EXT_IRQ_PENDING (1<<9)
91 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
92 #define ADFIFO_FULL (1<<4)
93 #define ADFIFO_HALFFULL (1<<3)
94 #define ADFIFO_EMPTY (1<<2)
95 #define CHANLIST_FULL (1<<1)
96 #define FST_ACTIVE (1<<0)
97 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
98 #define ME_DIO_PORT_A 0x0006 /* R | W */
99 #define ME_DIO_PORT_B 0x0008 /* R | W */
100 #define ME_TIMER_DATA_0 0x000A /* - | W */
101 #define ME_TIMER_DATA_1 0x000C /* - | W */
102 #define ME_TIMER_DATA_2 0x000E /* - | W */
103 #define ME_CHANNEL_LIST 0x0010 /* - | W */
104 #define ADC_UNIPOLAR (1<<6)
105 #define ADC_GAIN_0 (0<<4)
106 #define ADC_GAIN_1 (1<<4)
107 #define ADC_GAIN_2 (2<<4)
108 #define ADC_GAIN_3 (3<<4)
109 #define ME_READ_AD_FIFO 0x0010 /* R | - */
110 #define ME_DAC_CONTROL 0x0012 /* - | W */
111 #define DAC_UNIPOLAR_D (0<<4)
112 #define DAC_BIPOLAR_D (1<<4)
113 #define DAC_UNIPOLAR_C (0<<5)
114 #define DAC_BIPOLAR_C (1<<5)
115 #define DAC_UNIPOLAR_B (0<<6)
116 #define DAC_BIPOLAR_B (1<<6)
117 #define DAC_UNIPOLAR_A (0<<7)
118 #define DAC_BIPOLAR_A (1<<7)
119 #define DAC_GAIN_0_D (0<<8)
120 #define DAC_GAIN_1_D (1<<8)
121 #define DAC_GAIN_0_C (0<<9)
122 #define DAC_GAIN_1_C (1<<9)
123 #define DAC_GAIN_0_B (0<<10)
124 #define DAC_GAIN_1_B (1<<10)
125 #define DAC_GAIN_0_A (0<<11)
126 #define DAC_GAIN_1_A (1<<11)
127 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
128 #define ME_DAC_DATA_A 0x0014 /* - | W */
129 #define ME_DAC_DATA_B 0x0016 /* - | W */
130 #define ME_DAC_DATA_C 0x0018 /* - | W */
131 #define ME_DAC_DATA_D 0x001A /* - | W */
132 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
133 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
134 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
135 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
136 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
137 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
139 static const struct comedi_lrange me2000_ai_range = {
153 static const struct comedi_lrange me2600_ai_range = {
167 static const struct comedi_lrange me2600_ao_range = {
176 /* Board specification structure */
178 const char *name; /* driver name */
180 int ao_channel_nbr; /* DA config */
182 int ao_resolution_mask;
183 const struct comedi_lrange *ao_range_list;
184 int ai_channel_nbr; /* AD config */
186 int ai_resolution_mask;
187 const struct comedi_lrange *ai_range_list;
188 int dio_channel_nbr; /* DIO config */
191 static const struct me_board me_boards[] = {
194 .device_id = ME2600_DEVICE_ID,
198 .ao_resolution_mask = 0x0fff,
199 .ao_range_list = &me2600_ao_range,
200 .ai_channel_nbr = 16,
203 .ai_resolution_mask = 0x0fff,
204 .ai_range_list = &me2600_ai_range,
205 .dio_channel_nbr = 32,
209 .device_id = ME2000_DEVICE_ID,
213 .ao_resolution_mask = 0,
214 .ao_range_list = NULL,
215 .ai_channel_nbr = 16,
218 .ai_resolution_mask = 0x0fff,
219 .ai_range_list = &me2000_ai_range,
220 .dio_channel_nbr = 32,
224 /* Private data structure */
225 struct me_private_data {
226 void __iomem *plx_regbase; /* PLX configuration base address */
227 void __iomem *me_regbase; /* Base address of the Meilhaus card */
228 unsigned long plx_regbase_size; /* Size of PLX configuration space */
229 unsigned long me_regbase_size; /* Size of Meilhaus space */
231 unsigned short control_1; /* Mirror of CONTROL_1 register */
232 unsigned short control_2; /* Mirror of CONTROL_2 register */
233 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
234 int ao_readback[4]; /* Mirror of analog output data */
238 * ------------------------------------------------------------------
242 * ------------------------------------------------------------------
244 static inline void sleep(unsigned sec)
246 current->state = TASK_INTERRUPTIBLE;
247 schedule_timeout(sec * HZ);
251 * ------------------------------------------------------------------
253 * DIGITAL INPUT/OUTPUT SECTION
255 * ------------------------------------------------------------------
257 static int me_dio_insn_config(struct comedi_device *dev,
258 struct comedi_subdevice *s,
259 struct comedi_insn *insn, unsigned int *data)
261 struct me_private_data *dev_private = dev->private;
263 int mask = 1 << CR_CHAN(insn->chanspec);
266 if (mask & 0x0000ffff) { /* Port A in use */
270 dev_private->control_2 |= ENABLE_PORT_A;
271 writew(dev_private->control_2,
272 dev_private->me_regbase + ME_CONTROL_2);
273 } else { /* Port B in use */
278 dev_private->control_2 |= ENABLE_PORT_B;
279 writew(dev_private->control_2,
280 dev_private->me_regbase + ME_CONTROL_2);
284 /* Config port as output */
287 /* Config port as input */
294 /* Digital instant input/outputs */
295 static int me_dio_insn_bits(struct comedi_device *dev,
296 struct comedi_subdevice *s,
297 struct comedi_insn *insn, unsigned int *data)
299 struct me_private_data *dev_private = dev->private;
300 unsigned int mask = data[0];
303 s->state |= (mask & data[1]);
306 if (mask & 0x0000ffff) { /* Port A */
307 writew((s->state & 0xffff),
308 dev_private->me_regbase + ME_DIO_PORT_A);
310 data[1] &= ~0x0000ffff;
311 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A);
314 if (mask & 0xffff0000) { /* Port B */
315 writew(((s->state >> 16) & 0xffff),
316 dev_private->me_regbase + ME_DIO_PORT_B);
318 data[1] &= ~0xffff0000;
319 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16;
326 * ------------------------------------------------------------------
328 * ANALOG INPUT SECTION
330 * ------------------------------------------------------------------
333 /* Analog instant input */
334 static int me_ai_insn_read(struct comedi_device *dev,
335 struct comedi_subdevice *s,
336 struct comedi_insn *insn, unsigned int *data)
338 struct me_private_data *dev_private = dev->private;
339 unsigned short value;
340 int chan = CR_CHAN((&insn->chanspec)[0]);
341 int rang = CR_RANGE((&insn->chanspec)[0]);
342 int aref = CR_AREF((&insn->chanspec)[0]);
345 /* stop any running conversion */
346 dev_private->control_1 &= 0xFFFC;
347 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
349 /* clear chanlist and ad fifo */
350 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
351 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
353 /* reset any pending interrupt */
354 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
356 /* enable the chanlist and ADC fifo */
357 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
358 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
360 /* write to channel list fifo */
361 /* b3:b0 are the channel number */
363 /* b5:b4 are the channel gain */
364 value |= (rang & 0x03) << 4;
365 /* b6 channel polarity */
366 value |= (rang & 0x04) << 4;
367 /* b7 single or differential */
368 value |= ((aref & AREF_DIFF) ? 0x80 : 0);
369 writew(value & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
371 /* set ADC mode to software trigger */
372 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
373 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
375 /* start conversion by reading from ADC_START */
376 readw(dev_private->me_regbase + ME_ADC_START);
378 /* wait for ADC fifo not empty flag */
379 for (i = 100000; i > 0; i--)
380 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
383 /* get value from ADC fifo */
386 (readw(dev_private->me_regbase +
387 ME_READ_AD_FIFO) ^ 0x800) & 0x0FFF;
389 dev_err(dev->class_dev, "Cannot get single value\n");
393 /* stop any running conversion */
394 dev_private->control_1 &= 0xFFFC;
395 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
401 * ------------------------------------------------------------------
403 * HARDWARE TRIGGERED ANALOG INPUT SECTION
405 * ------------------------------------------------------------------
408 /* Cancel analog input autoscan */
409 static int me_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
411 struct me_private_data *dev_private = dev->private;
413 /* disable interrupts */
415 /* stop any running conversion */
416 dev_private->control_1 &= 0xFFFC;
417 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
422 /* Test analog input command */
423 static int me_ai_do_cmd_test(struct comedi_device *dev,
424 struct comedi_subdevice *s, struct comedi_cmd *cmd)
429 /* Analog input command */
430 static int me_ai_do_cmd(struct comedi_device *dev,
431 struct comedi_subdevice *s)
437 * ------------------------------------------------------------------
439 * ANALOG OUTPUT SECTION
441 * ------------------------------------------------------------------
444 /* Analog instant output */
445 static int me_ao_insn_write(struct comedi_device *dev,
446 struct comedi_subdevice *s,
447 struct comedi_insn *insn, unsigned int *data)
449 struct me_private_data *dev_private = dev->private;
455 dev_private->control_2 |= ENABLE_DAC;
456 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
458 /* and set DAC to "buffered" mode */
459 dev_private->control_2 |= BUFFERED_DAC;
460 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
462 /* Set dac-control register */
463 for (i = 0; i < insn->n; i++) {
464 chan = CR_CHAN((&insn->chanspec)[i]);
465 rang = CR_RANGE((&insn->chanspec)[i]);
467 /* clear bits for this channel */
468 dev_private->dac_control &= ~(0x0880 >> chan);
470 dev_private->dac_control |=
471 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
473 dev_private->dac_control |=
474 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
476 writew(dev_private->dac_control,
477 dev_private->me_regbase + ME_DAC_CONTROL);
479 /* Update dac-control register */
480 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
482 /* Set data register */
483 for (i = 0; i < insn->n; i++) {
484 chan = CR_CHAN((&insn->chanspec)[i]);
485 writew((data[0] & s->maxdata),
486 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
487 dev_private->ao_readback[chan] = (data[0] & s->maxdata);
490 /* Update dac with data registers */
491 readw(dev_private->me_regbase + ME_DAC_UPDATE);
496 /* Analog output readback */
497 static int me_ao_insn_read(struct comedi_device *dev,
498 struct comedi_subdevice *s, struct comedi_insn *insn,
501 struct me_private_data *dev_private = dev->private;
504 for (i = 0; i < insn->n; i++) {
506 dev_private->ao_readback[CR_CHAN((&insn->chanspec)[i])];
513 * ------------------------------------------------------------------
515 * INITIALISATION SECTION
517 * ------------------------------------------------------------------
520 /* Xilinx firmware download for card: ME-2600i */
521 static int me2600_xilinx_download(struct comedi_device *dev,
522 const u8 *data, size_t size)
524 struct me_private_data *dev_private = dev->private;
526 unsigned int file_length;
529 /* disable irq's on PLX */
530 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
532 /* First, make a dummy read to reset xilinx */
533 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
535 /* Wait until reset is over */
538 /* Write a dummy value to Xilinx */
539 writeb(0x00, dev_private->me_regbase + 0x0);
543 * Format of the firmware
544 * Build longs from the byte-wise coded header
545 * Byte 1-3: length of the array
548 * Byte 12-15: reserved
553 file_length = (((unsigned int)data[0] & 0xff) << 24) +
554 (((unsigned int)data[1] & 0xff) << 16) +
555 (((unsigned int)data[2] & 0xff) << 8) +
556 ((unsigned int)data[3] & 0xff);
559 * Loop for writing firmware byte by byte to xilinx
560 * Firmware data start at offfset 16
562 for (i = 0; i < file_length; i++)
563 writeb((data[16 + i] & 0xff),
564 dev_private->me_regbase + 0x0);
566 /* Write 5 dummy values to xilinx */
567 for (i = 0; i < 5; i++)
568 writeb(0x00, dev_private->me_regbase + 0x0);
570 /* Test if there was an error during download -> INTB was thrown */
571 value = readl(dev_private->plx_regbase + PLX_INTCSR);
573 /* Disable interrupt */
574 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
575 dev_err(dev->class_dev, "Xilinx download failed\n");
579 /* Wait until the Xilinx is ready for real work */
582 /* Enable PLX-Interrupts */
583 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
588 static int me2600_upload_firmware(struct comedi_device *dev)
590 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
591 const struct firmware *fw;
594 ret = request_firmware(&fw, ME2600_FIRMWARE, &pcidev->dev);
598 ret = me2600_xilinx_download(dev, fw->data, fw->size);
599 release_firmware(fw);
605 static int me_reset(struct comedi_device *dev)
607 struct me_private_data *dev_private = dev->private;
610 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
611 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
612 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
613 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
615 /* Save values in the board context */
616 dev_private->dac_control = 0;
617 dev_private->control_1 = 0;
618 dev_private->control_2 = 0;
623 static const void *me_find_boardinfo(struct comedi_device *dev,
624 struct pci_dev *pcidev)
626 const struct me_board *board;
629 for (i = 0; i < ARRAY_SIZE(me_boards); i++) {
630 board = &me_boards[i];
631 if (board->device_id == pcidev->device)
637 static int me_attach_pci(struct comedi_device *dev, struct pci_dev *pcidev)
639 const struct me_board *board;
640 struct me_private_data *dev_private;
641 struct comedi_subdevice *s;
642 resource_size_t plx_regbase_tmp;
643 unsigned long plx_regbase_size_tmp;
644 resource_size_t me_regbase_tmp;
645 unsigned long me_regbase_size_tmp;
646 resource_size_t swap_regbase_tmp;
647 unsigned long swap_regbase_size_tmp;
648 resource_size_t regbase_tmp;
651 board = me_find_boardinfo(dev, pcidev);
654 dev->board_ptr = board;
655 dev->board_name = board->name;
657 dev_private = kzalloc(sizeof(*dev_private), GFP_KERNEL);
660 dev->private = dev_private;
662 /* Enable PCI device and request PCI regions */
663 if (comedi_pci_enable(pcidev, dev->board_name) < 0) {
664 dev_err(dev->class_dev,
665 "Failed to enable PCI device and request regions\n");
669 /* Read PLX register base address [PCI_BASE_ADDRESS #0]. */
670 plx_regbase_tmp = pci_resource_start(pcidev, 0);
671 plx_regbase_size_tmp = pci_resource_len(pcidev, 0);
672 dev_private->plx_regbase =
673 ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
674 dev_private->plx_regbase_size = plx_regbase_size_tmp;
675 if (!dev_private->plx_regbase) {
676 dev_err(dev->class_dev, "Failed to remap I/O memory\n");
680 /* Read Swap base address [PCI_BASE_ADDRESS #5]. */
682 swap_regbase_tmp = pci_resource_start(pcidev, 5);
683 swap_regbase_size_tmp = pci_resource_len(pcidev, 5);
685 if (!swap_regbase_tmp)
686 dev_err(dev->class_dev, "Swap not present\n");
688 /*---------------------------------------------- Workaround start ---*/
689 if (plx_regbase_tmp & 0x0080) {
690 dev_err(dev->class_dev, "PLX-Bug detected\n");
692 if (swap_regbase_tmp) {
693 regbase_tmp = plx_regbase_tmp;
694 plx_regbase_tmp = swap_regbase_tmp;
695 swap_regbase_tmp = regbase_tmp;
697 result = pci_write_config_dword(pcidev,
700 if (result != PCIBIOS_SUCCESSFUL)
703 result = pci_write_config_dword(pcidev,
706 if (result != PCIBIOS_SUCCESSFUL)
709 plx_regbase_tmp -= 0x80;
710 result = pci_write_config_dword(pcidev,
713 if (result != PCIBIOS_SUCCESSFUL)
717 /*--------------------------------------------- Workaround end -----*/
719 /* Read Meilhaus register base address [PCI_BASE_ADDRESS #2]. */
721 me_regbase_tmp = pci_resource_start(pcidev, 2);
722 me_regbase_size_tmp = pci_resource_len(pcidev, 2);
723 dev_private->me_regbase_size = me_regbase_size_tmp;
724 dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
725 if (!dev_private->me_regbase) {
726 dev_err(dev->class_dev, "Failed to remap I/O memory\n");
730 /* Download firmware and reset card */
731 if (board->device_id == ME2600_DEVICE_ID) {
732 result = me2600_upload_firmware(dev);
738 error = comedi_alloc_subdevices(dev, 3);
742 s = &dev->subdevices[0];
743 s->type = COMEDI_SUBD_AI;
744 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
745 s->n_chan = board->ai_channel_nbr;
746 s->maxdata = board->ai_resolution_mask;
747 s->len_chanlist = board->ai_channel_nbr;
748 s->range_table = board->ai_range_list;
749 s->cancel = me_ai_cancel;
750 s->insn_read = me_ai_insn_read;
751 s->do_cmdtest = me_ai_do_cmd_test;
752 s->do_cmd = me_ai_do_cmd;
754 s = &dev->subdevices[1];
755 s->type = COMEDI_SUBD_AO;
756 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
757 s->n_chan = board->ao_channel_nbr;
758 s->maxdata = board->ao_resolution_mask;
759 s->len_chanlist = board->ao_channel_nbr;
760 s->range_table = board->ao_range_list;
761 s->insn_read = me_ao_insn_read;
762 s->insn_write = me_ao_insn_write;
764 s = &dev->subdevices[2];
765 s->type = COMEDI_SUBD_DIO;
766 s->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
767 s->n_chan = board->dio_channel_nbr;
769 s->len_chanlist = board->dio_channel_nbr;
770 s->range_table = &range_digital;
771 s->insn_bits = me_dio_insn_bits;
772 s->insn_config = me_dio_insn_config;
775 dev_info(dev->class_dev, "%s: %s attached\n",
776 dev->driver->driver_name, dev->board_name);
781 static void me_detach(struct comedi_device *dev)
783 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
784 struct me_private_data *dev_private = dev->private;
787 if (dev_private->me_regbase) {
789 iounmap(dev_private->me_regbase);
791 if (dev_private->plx_regbase)
792 iounmap(dev_private->plx_regbase);
795 if (dev_private->plx_regbase_size)
796 comedi_pci_disable(pcidev);
801 static struct comedi_driver me_daq_driver = {
802 .driver_name = "me_daq",
803 .module = THIS_MODULE,
804 .attach_pci = me_attach_pci,
808 static int __devinit me_daq_pci_probe(struct pci_dev *dev,
809 const struct pci_device_id *ent)
811 return comedi_pci_auto_config(dev, &me_daq_driver);
814 static void __devexit me_daq_pci_remove(struct pci_dev *dev)
816 comedi_pci_auto_unconfig(dev);
819 static DEFINE_PCI_DEVICE_TABLE(me_daq_pci_table) = {
820 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID) },
821 { PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID) },
824 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
826 static struct pci_driver me_daq_pci_driver = {
828 .id_table = me_daq_pci_table,
829 .probe = me_daq_pci_probe,
830 .remove = __devexit_p(me_daq_pci_remove),
832 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
834 MODULE_AUTHOR("Comedi http://www.comedi.org");
835 MODULE_DESCRIPTION("Comedi low-level driver");
836 MODULE_LICENSE("GPL");
837 MODULE_FIRMWARE(ME2600_FIRMWARE);