2 comedi/drivers/me4000.c
3 Source code for the Meilhaus ME-4000 board family.
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Description: Meilhaus ME-4000 series boards
26 Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is
27 Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)
28 Updated: Mon, 18 Mar 2002 15:34:01 -0800
29 Status: broken (no support for loading firmware)
38 Configuration Options: not applicable, uses PCI auto config
40 The firmware required by these boards is available in the
41 comedi_nonfree_firmware tarball available from
42 http://www.comedi.org. However, the driver's support for
43 loading the firmware through comedi_config is currently
48 #include <linux/interrupt.h>
49 #include "../comedidev.h"
51 #include <linux/delay.h>
52 #include <linux/list.h>
53 #include <linux/spinlock.h>
55 #include "comedi_fc.h"
59 /* file removed due to GPL incompatibility */
60 #include "me4000_fw.h"
63 #define PCI_VENDOR_ID_MEILHAUS 0x1402
65 #define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650
66 #define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660
67 #define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661
68 #define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662
69 #define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663
70 #define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670
71 #define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671
72 #define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672
73 #define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673
74 #define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680
75 #define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681
76 #define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682
77 #define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683
80 * ME4000 Register map and bit defines
82 #define ME4000_AO_CHAN(x) ((x) * 0x18)
84 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
85 #define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
86 #define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
87 #define ME4000_AO_CTRL_MASK_MODE (3 << 0)
88 #define ME4000_AO_CTRL_BIT_STOP (1 << 2)
89 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
90 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
91 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
92 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
93 #define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
94 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
95 #define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
96 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
97 #define ME4000_AO_STATUS_BIT_FSM (1 << 0)
98 #define ME4000_AO_STATUS_BIT_FF (1 << 1)
99 #define ME4000_AO_STATUS_BIT_HF (1 << 2)
100 #define ME4000_AO_STATUS_BIT_EF (1 << 3)
101 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
102 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
103 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
104 #define ME4000_AI_CTRL_REG 0x74
105 #define ME4000_AI_STATUS_REG 0x74
106 #define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
107 #define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
108 #define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
109 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
110 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
111 #define ME4000_AI_CTRL_BIT_STOP (1 << 5)
112 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
113 #define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
114 #define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
115 #define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
116 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
117 #define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
118 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
119 #define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
120 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
121 #define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
122 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
123 #define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
124 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
125 #define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
126 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
127 #define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
128 #define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
129 #define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
130 #define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
131 #define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
132 #define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
133 #define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
134 #define ME4000_AI_STATUS_BIT_LE (1 << 28)
135 #define ME4000_AI_STATUS_BIT_FSM (1 << 29)
136 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
137 #define ME4000_AI_CHANNEL_LIST_REG 0x78
138 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED (0 << 5)
139 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL (1 << 5)
140 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 (0 << 6)
141 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 (1 << 6)
142 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 (2 << 6)
143 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 (3 << 6)
144 #define ME4000_AI_LIST_LAST_ENTRY (1 << 8)
145 #define ME4000_AI_DATA_REG 0x7c
146 #define ME4000_AI_CHAN_TIMER_REG 0x80
147 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
148 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
149 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
150 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
151 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
152 #define ME4000_AI_START_REG 0x98
153 #define ME4000_IRQ_STATUS_REG 0x9c
154 #define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
155 #define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
156 #define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
157 #define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
158 #define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
159 #define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
160 #define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
161 #define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
162 #define ME4000_DIO_PORT_0_REG 0xa0
163 #define ME4000_DIO_PORT_1_REG 0xa4
164 #define ME4000_DIO_PORT_2_REG 0xa8
165 #define ME4000_DIO_PORT_3_REG 0xac
166 #define ME4000_DIO_DIR_REG 0xb0
167 #define ME4000_AO_LOADSETREG_XX 0xb4
168 #define ME4000_DIO_CTRL_REG 0xb8
169 #define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
170 #define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
171 #define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
172 #define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
173 #define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
174 #define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
175 #define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
176 #define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
177 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
178 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
179 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
180 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
181 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
182 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
183 #define ME4000_AO_DEMUX_ADJUST_REG 0xbc
184 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
185 #define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
188 * PLX Register map and bit defines
190 #define PLX_INTCSR 0x4c
191 #define PLX_INTCSR_LOCAL_INT1_EN (1 << 0)
192 #define PLX_INTCSR_LOCAL_INT1_POL (1 << 1)
193 #define PLX_INTCSR_LOCAL_INT1_STATE (1 << 2)
194 #define PLX_INTCSR_LOCAL_INT2_EN (1 << 3)
195 #define PLX_INTCSR_LOCAL_INT2_POL (1 << 4)
196 #define PLX_INTCSR_LOCAL_INT2_STATE (1 << 5)
197 #define PLX_INTCSR_PCI_INT_EN (1 << 6)
198 #define PLX_INTCSR_SOFT_INT (1 << 7)
200 #define PLX_ICR_BIT_EEPROM_CLOCK_SET (1 << 24)
201 #define PLX_ICR_BIT_EEPROM_CHIP_SELECT (1 << 25)
202 #define PLX_ICR_BIT_EEPROM_WRITE (1 << 26)
203 #define PLX_ICR_BIT_EEPROM_READ (1 << 27)
204 #define PLX_ICR_BIT_EEPROM_VALID (1 << 28)
205 #define PLX_ICR_MASK_EEPROM (0x1f << 24)
207 #define EEPROM_DELAY 1
209 #define ME4000_AI_FIFO_COUNT 2048
211 #define ME4000_AI_MIN_TICKS 66
212 #define ME4000_AI_MIN_SAMPLE_TIME 2000
213 #define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
215 #define ME4000_AI_CHANNEL_LIST_COUNT 1024
218 unsigned long plx_regbase;
219 unsigned long timer_regbase;
221 unsigned int ao_readback[4];
224 struct me4000_board {
226 unsigned short device_id;
237 static const struct me4000_board me4000_boards[] = {
240 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4650,
245 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660,
252 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660I,
259 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660S,
267 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660IS,
275 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670,
284 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670I,
293 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670S,
303 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670IS,
313 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680,
323 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680I,
333 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680S,
344 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680IS,
356 static const struct comedi_lrange me4000_ai_range = {
366 #define FIRMWARE_NOT_AVAILABLE 1
367 #if FIRMWARE_NOT_AVAILABLE
368 extern unsigned char *xilinx_firm;
371 static int xilinx_download(struct comedi_device *dev)
373 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
374 struct me4000_info *info = dev->private;
375 unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
377 wait_queue_head_t queue;
384 init_waitqueue_head(&queue);
387 * Set PLX local interrupt 2 polarity to high.
388 * Interrupt is thrown by init pin of xilinx.
390 outl(0x10, info->plx_regbase + PLX_INTCSR);
392 /* Set /CS and /WRITE of the Xilinx */
393 value = inl(info->plx_regbase + PLX_ICR);
395 outl(value, info->plx_regbase + PLX_ICR);
397 /* Init Xilinx with CS1 */
398 inb(xilinx_iobase + 0xC8);
400 /* Wait until /INIT pin is set */
402 if (!(inl(info->plx_regbase + PLX_INTCSR) & 0x20)) {
403 dev_err(dev->class_dev, "Can't init Xilinx\n");
407 /* Reset /CS and /WRITE of the Xilinx */
408 value = inl(info->plx_regbase + PLX_ICR);
410 outl(value, info->plx_regbase + PLX_ICR);
411 if (FIRMWARE_NOT_AVAILABLE) {
412 dev_err(dev->class_dev,
413 "xilinx firmware unavailable due to licensing, aborting");
416 /* Download Xilinx firmware */
417 size = (xilinx_firm[0] << 24) + (xilinx_firm[1] << 16) +
418 (xilinx_firm[2] << 8) + xilinx_firm[3];
421 for (idx = 0; idx < size; idx++) {
422 outb(xilinx_firm[16 + idx], xilinx_iobase);
425 /* Check if BUSY flag is low */
426 if (inl(info->plx_regbase + PLX_ICR) & 0x20) {
427 dev_err(dev->class_dev,
428 "Xilinx is still busy (idx = %d)\n",
435 /* If done flag is high download was successful */
436 if (inl(info->plx_regbase + PLX_ICR) & 0x4) {
438 dev_err(dev->class_dev, "DONE flag is not set\n");
439 dev_err(dev->class_dev, "Download not successful\n");
443 /* Set /CS and /WRITE */
444 value = inl(info->plx_regbase + PLX_ICR);
446 outl(value, info->plx_regbase + PLX_ICR);
451 static void me4000_reset(struct comedi_device *dev)
453 struct me4000_info *info = dev->private;
457 /* Make a hardware reset */
458 val = inl(info->plx_regbase + PLX_ICR);
460 outl(val, info->plx_regbase + PLX_ICR);
462 outl(val , info->plx_regbase + PLX_ICR);
464 /* 0x8000 to the DACs means an output voltage of 0V */
465 for (chan = 0; chan < 4; chan++)
466 outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
468 /* Set both stop bits in the analog input control register */
469 outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
470 dev->iobase + ME4000_AI_CTRL_REG);
472 /* Set both stop bits in the analog output control register */
473 val = ME4000_AO_CTRL_BIT_IMMEDIATE_STOP | ME4000_AO_CTRL_BIT_STOP;
474 for (chan = 0; chan < 4; chan++)
475 outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
477 /* Enable interrupts on the PLX */
478 outl(0x43, info->plx_regbase + PLX_INTCSR);
480 /* Set the adustment register for AO demux */
481 outl(ME4000_AO_DEMUX_ADJUST_VALUE,
482 dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
485 * Set digital I/O direction for port 0
486 * to output on isolated versions
488 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
489 outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
492 /*=============================================================================
494 ===========================================================================*/
496 static int me4000_ai_insn_read(struct comedi_device *dev,
497 struct comedi_subdevice *subdevice,
498 struct comedi_insn *insn, unsigned int *data)
500 const struct me4000_board *thisboard = comedi_board(dev);
501 int chan = CR_CHAN(insn->chanspec);
502 int rang = CR_RANGE(insn->chanspec);
503 int aref = CR_AREF(insn->chanspec);
505 unsigned long entry = 0;
511 } else if (insn->n > 1) {
512 dev_err(dev->class_dev, "Invalid instruction length %d\n",
519 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
522 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
525 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
528 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
531 dev_err(dev->class_dev, "Invalid range specified\n");
538 if (chan >= thisboard->ai_nchan) {
539 dev_err(dev->class_dev,
540 "Analog input is not available\n");
543 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED | chan;
547 if (rang == 0 || rang == 1) {
548 dev_err(dev->class_dev,
549 "Range must be bipolar when aref = diff\n");
553 if (chan >= thisboard->ai_diff_nchan) {
554 dev_err(dev->class_dev,
555 "Analog input is not available\n");
558 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL | chan;
561 dev_err(dev->class_dev, "Invalid aref specified\n");
565 entry |= ME4000_AI_LIST_LAST_ENTRY;
567 /* Clear channel list, data fifo and both stop bits */
568 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
569 tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
570 ME4000_AI_CTRL_BIT_DATA_FIFO |
571 ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
572 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
574 /* Set the acquisition mode to single */
575 tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
576 ME4000_AI_CTRL_BIT_MODE_2);
577 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
579 /* Enable channel list and data fifo */
580 tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
581 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
583 /* Generate channel list entry */
584 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
586 /* Set the timer to maximum sample rate */
587 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
588 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
590 /* Start conversion by dummy read */
591 inl(dev->iobase + ME4000_AI_START_REG);
593 /* Wait until ready */
595 if (!(inl(dev->iobase + ME4000_AI_STATUS_REG) &
596 ME4000_AI_STATUS_BIT_EF_DATA)) {
597 dev_err(dev->class_dev, "Value not available after wait\n");
601 /* Read value from data fifo */
602 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
603 data[0] = lval ^ 0x8000;
608 static int me4000_ai_cancel(struct comedi_device *dev,
609 struct comedi_subdevice *s)
613 /* Stop any running conversion */
614 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
615 tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
616 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
618 /* Clear the control register */
619 outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
624 static int ai_check_chanlist(struct comedi_device *dev,
625 struct comedi_subdevice *s, struct comedi_cmd *cmd)
627 const struct me4000_board *thisboard = comedi_board(dev);
631 /* Check whether a channel list is available */
632 if (!cmd->chanlist_len) {
633 dev_err(dev->class_dev, "No channel list available\n");
637 /* Check the channel list size */
638 if (cmd->chanlist_len > ME4000_AI_CHANNEL_LIST_COUNT) {
639 dev_err(dev->class_dev, "Channel list is to large\n");
643 /* Check the pointer */
644 if (!cmd->chanlist) {
645 dev_err(dev->class_dev, "NULL pointer to channel list\n");
649 /* Check whether aref is equal for all entries */
650 aref = CR_AREF(cmd->chanlist[0]);
651 for (i = 0; i < cmd->chanlist_len; i++) {
652 if (CR_AREF(cmd->chanlist[i]) != aref) {
653 dev_err(dev->class_dev,
654 "Mode is not equal for all entries\n");
659 /* Check whether channels are available for this ending */
660 if (aref == SDF_DIFF) {
661 for (i = 0; i < cmd->chanlist_len; i++) {
662 if (CR_CHAN(cmd->chanlist[i]) >=
663 thisboard->ai_diff_nchan) {
664 dev_err(dev->class_dev,
665 "Channel number to high\n");
670 for (i = 0; i < cmd->chanlist_len; i++) {
671 if (CR_CHAN(cmd->chanlist[i]) >= thisboard->ai_nchan) {
672 dev_err(dev->class_dev,
673 "Channel number to high\n");
679 /* Check if bipolar is set for all entries when in differential mode */
680 if (aref == SDF_DIFF) {
681 for (i = 0; i < cmd->chanlist_len; i++) {
682 if (CR_RANGE(cmd->chanlist[i]) != 1 &&
683 CR_RANGE(cmd->chanlist[i]) != 2) {
684 dev_err(dev->class_dev,
685 "Bipolar is not selected in differential mode\n");
694 static int ai_round_cmd_args(struct comedi_device *dev,
695 struct comedi_subdevice *s,
696 struct comedi_cmd *cmd,
697 unsigned int *init_ticks,
698 unsigned int *scan_ticks, unsigned int *chan_ticks)
707 if (cmd->start_arg) {
708 *init_ticks = (cmd->start_arg * 33) / 1000;
709 rest = (cmd->start_arg * 33) % 1000;
711 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
714 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
720 if (cmd->scan_begin_arg) {
721 *scan_ticks = (cmd->scan_begin_arg * 33) / 1000;
722 rest = (cmd->scan_begin_arg * 33) % 1000;
724 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
727 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
733 if (cmd->convert_arg) {
734 *chan_ticks = (cmd->convert_arg * 33) / 1000;
735 rest = (cmd->convert_arg * 33) % 1000;
737 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
740 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
749 static void ai_write_timer(struct comedi_device *dev,
750 unsigned int init_ticks,
751 unsigned int scan_ticks, unsigned int chan_ticks)
753 outl(init_ticks - 1, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG);
754 outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);
757 outl(scan_ticks - 1, dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG);
758 outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);
761 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
762 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
765 static int ai_write_chanlist(struct comedi_device *dev,
766 struct comedi_subdevice *s, struct comedi_cmd *cmd)
774 for (i = 0; i < cmd->chanlist_len; i++) {
775 chan = CR_CHAN(cmd->chanlist[i]);
776 rang = CR_RANGE(cmd->chanlist[i]);
777 aref = CR_AREF(cmd->chanlist[i]);
782 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
784 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
786 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
788 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
790 if (aref == SDF_DIFF)
791 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
793 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED;
795 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
801 static int ai_prepare(struct comedi_device *dev,
802 struct comedi_subdevice *s,
803 struct comedi_cmd *cmd,
804 unsigned int init_ticks,
805 unsigned int scan_ticks, unsigned int chan_ticks)
808 unsigned long tmp = 0;
810 /* Write timer arguments */
811 ai_write_timer(dev, init_ticks, scan_ticks, chan_ticks);
813 /* Reset control register */
814 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
817 if ((cmd->start_src == TRIG_EXT &&
818 cmd->scan_begin_src == TRIG_TIMER &&
819 cmd->convert_src == TRIG_TIMER) ||
820 (cmd->start_src == TRIG_EXT &&
821 cmd->scan_begin_src == TRIG_FOLLOW &&
822 cmd->convert_src == TRIG_TIMER)) {
823 tmp = ME4000_AI_CTRL_BIT_MODE_1 |
824 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
825 ME4000_AI_CTRL_BIT_DATA_FIFO;
826 } else if (cmd->start_src == TRIG_EXT &&
827 cmd->scan_begin_src == TRIG_EXT &&
828 cmd->convert_src == TRIG_TIMER) {
829 tmp = ME4000_AI_CTRL_BIT_MODE_2 |
830 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
831 ME4000_AI_CTRL_BIT_DATA_FIFO;
832 } else if (cmd->start_src == TRIG_EXT &&
833 cmd->scan_begin_src == TRIG_EXT &&
834 cmd->convert_src == TRIG_EXT) {
835 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
836 ME4000_AI_CTRL_BIT_MODE_1 |
837 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
838 ME4000_AI_CTRL_BIT_DATA_FIFO;
840 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
841 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
842 ME4000_AI_CTRL_BIT_DATA_FIFO;
846 if (cmd->stop_src == TRIG_COUNT) {
847 outl(cmd->chanlist_len * cmd->stop_arg,
848 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
849 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
850 } else if (cmd->stop_src == TRIG_NONE &&
851 cmd->scan_end_src == TRIG_COUNT) {
852 outl(cmd->scan_end_arg,
853 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
854 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
856 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
859 /* Write the setup to the control register */
860 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
862 /* Write the channel list */
863 ai_write_chanlist(dev, s, cmd);
868 static int me4000_ai_do_cmd(struct comedi_device *dev,
869 struct comedi_subdevice *s)
872 unsigned int init_ticks = 0;
873 unsigned int scan_ticks = 0;
874 unsigned int chan_ticks = 0;
875 struct comedi_cmd *cmd = &s->async->cmd;
877 /* Reset the analog input */
878 err = me4000_ai_cancel(dev, s);
882 /* Round the timer arguments */
883 err = ai_round_cmd_args(dev,
884 s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
888 /* Prepare the AI for acquisition */
889 err = ai_prepare(dev, s, cmd, init_ticks, scan_ticks, chan_ticks);
893 /* Start acquistion by dummy read */
894 inl(dev->iobase + ME4000_AI_START_REG);
899 static int me4000_ai_do_cmd_test(struct comedi_device *dev,
900 struct comedi_subdevice *s,
901 struct comedi_cmd *cmd)
904 unsigned int init_ticks;
905 unsigned int chan_ticks;
906 unsigned int scan_ticks;
909 /* Only rounding flags are implemented */
910 cmd->flags &= TRIG_ROUND_NEAREST | TRIG_ROUND_UP | TRIG_ROUND_DOWN;
912 /* Round the timer arguments */
913 ai_round_cmd_args(dev, s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
915 /* Step 1 : check if triggers are trivially valid */
917 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
918 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
919 TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT);
920 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
921 err |= cfc_check_trigger_src(&cmd->scan_end_src,
922 TRIG_NONE | TRIG_COUNT);
923 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT);
928 /* Step 2a : make sure trigger sources are unique */
930 err |= cfc_check_trigger_is_unique(cmd->start_src);
931 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
932 err |= cfc_check_trigger_is_unique(cmd->convert_src);
933 err |= cfc_check_trigger_is_unique(cmd->scan_end_src);
934 err |= cfc_check_trigger_is_unique(cmd->stop_src);
936 /* Step 2b : and mutually compatible */
938 if (cmd->start_src == TRIG_NOW &&
939 cmd->scan_begin_src == TRIG_TIMER &&
940 cmd->convert_src == TRIG_TIMER) {
941 } else if (cmd->start_src == TRIG_NOW &&
942 cmd->scan_begin_src == TRIG_FOLLOW &&
943 cmd->convert_src == TRIG_TIMER) {
944 } else if (cmd->start_src == TRIG_EXT &&
945 cmd->scan_begin_src == TRIG_TIMER &&
946 cmd->convert_src == TRIG_TIMER) {
947 } else if (cmd->start_src == TRIG_EXT &&
948 cmd->scan_begin_src == TRIG_FOLLOW &&
949 cmd->convert_src == TRIG_TIMER) {
950 } else if (cmd->start_src == TRIG_EXT &&
951 cmd->scan_begin_src == TRIG_EXT &&
952 cmd->convert_src == TRIG_TIMER) {
953 } else if (cmd->start_src == TRIG_EXT &&
954 cmd->scan_begin_src == TRIG_EXT &&
955 cmd->convert_src == TRIG_EXT) {
960 if (cmd->stop_src == TRIG_NONE && cmd->scan_end_src == TRIG_NONE) {
961 } else if (cmd->stop_src == TRIG_COUNT &&
962 cmd->scan_end_src == TRIG_NONE) {
963 } else if (cmd->stop_src == TRIG_NONE &&
964 cmd->scan_end_src == TRIG_COUNT) {
965 } else if (cmd->stop_src == TRIG_COUNT &&
966 cmd->scan_end_src == TRIG_COUNT) {
975 * Stage 3. Check if arguments are generally valid.
977 if (cmd->chanlist_len < 1) {
978 dev_err(dev->class_dev, "No channel list\n");
979 cmd->chanlist_len = 1;
982 if (init_ticks < 66) {
983 dev_err(dev->class_dev, "Start arg to low\n");
984 cmd->start_arg = 2000;
987 if (scan_ticks && scan_ticks < 67) {
988 dev_err(dev->class_dev, "Scan begin arg to low\n");
989 cmd->scan_begin_arg = 2031;
992 if (chan_ticks < 66) {
993 dev_err(dev->class_dev, "Convert arg to low\n");
994 cmd->convert_arg = 2000;
1002 * Stage 4. Check for argument conflicts.
1004 if (cmd->start_src == TRIG_NOW &&
1005 cmd->scan_begin_src == TRIG_TIMER &&
1006 cmd->convert_src == TRIG_TIMER) {
1008 /* Check timer arguments */
1009 if (init_ticks < ME4000_AI_MIN_TICKS) {
1010 dev_err(dev->class_dev, "Invalid start arg\n");
1011 cmd->start_arg = 2000; /* 66 ticks at least */
1014 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1015 dev_err(dev->class_dev, "Invalid convert arg\n");
1016 cmd->convert_arg = 2000; /* 66 ticks at least */
1019 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1020 dev_err(dev->class_dev, "Invalid scan end arg\n");
1022 /* At least one tick more */
1023 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1026 } else if (cmd->start_src == TRIG_NOW &&
1027 cmd->scan_begin_src == TRIG_FOLLOW &&
1028 cmd->convert_src == TRIG_TIMER) {
1030 /* Check timer arguments */
1031 if (init_ticks < ME4000_AI_MIN_TICKS) {
1032 dev_err(dev->class_dev, "Invalid start arg\n");
1033 cmd->start_arg = 2000; /* 66 ticks at least */
1036 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1037 dev_err(dev->class_dev, "Invalid convert arg\n");
1038 cmd->convert_arg = 2000; /* 66 ticks at least */
1041 } else if (cmd->start_src == TRIG_EXT &&
1042 cmd->scan_begin_src == TRIG_TIMER &&
1043 cmd->convert_src == TRIG_TIMER) {
1045 /* Check timer arguments */
1046 if (init_ticks < ME4000_AI_MIN_TICKS) {
1047 dev_err(dev->class_dev, "Invalid start arg\n");
1048 cmd->start_arg = 2000; /* 66 ticks at least */
1051 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1052 dev_err(dev->class_dev, "Invalid convert arg\n");
1053 cmd->convert_arg = 2000; /* 66 ticks at least */
1056 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1057 dev_err(dev->class_dev, "Invalid scan end arg\n");
1059 /* At least one tick more */
1060 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1063 } else if (cmd->start_src == TRIG_EXT &&
1064 cmd->scan_begin_src == TRIG_FOLLOW &&
1065 cmd->convert_src == TRIG_TIMER) {
1067 /* Check timer arguments */
1068 if (init_ticks < ME4000_AI_MIN_TICKS) {
1069 dev_err(dev->class_dev, "Invalid start arg\n");
1070 cmd->start_arg = 2000; /* 66 ticks at least */
1073 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1074 dev_err(dev->class_dev, "Invalid convert arg\n");
1075 cmd->convert_arg = 2000; /* 66 ticks at least */
1078 } else if (cmd->start_src == TRIG_EXT &&
1079 cmd->scan_begin_src == TRIG_EXT &&
1080 cmd->convert_src == TRIG_TIMER) {
1082 /* Check timer arguments */
1083 if (init_ticks < ME4000_AI_MIN_TICKS) {
1084 dev_err(dev->class_dev, "Invalid start arg\n");
1085 cmd->start_arg = 2000; /* 66 ticks at least */
1088 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1089 dev_err(dev->class_dev, "Invalid convert arg\n");
1090 cmd->convert_arg = 2000; /* 66 ticks at least */
1093 } else if (cmd->start_src == TRIG_EXT &&
1094 cmd->scan_begin_src == TRIG_EXT &&
1095 cmd->convert_src == TRIG_EXT) {
1097 /* Check timer arguments */
1098 if (init_ticks < ME4000_AI_MIN_TICKS) {
1099 dev_err(dev->class_dev, "Invalid start arg\n");
1100 cmd->start_arg = 2000; /* 66 ticks at least */
1104 if (cmd->stop_src == TRIG_COUNT) {
1105 if (cmd->stop_arg == 0) {
1106 dev_err(dev->class_dev, "Invalid stop arg\n");
1111 if (cmd->scan_end_src == TRIG_COUNT) {
1112 if (cmd->scan_end_arg == 0) {
1113 dev_err(dev->class_dev, "Invalid scan end arg\n");
1114 cmd->scan_end_arg = 1;
1123 * Stage 5. Check the channel list.
1125 if (ai_check_chanlist(dev, s, cmd))
1131 static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
1134 struct comedi_device *dev = dev_id;
1135 struct comedi_subdevice *s = &dev->subdevices[0];
1143 /* Reset all events */
1144 s->async->events = 0;
1146 /* Check if irq number is right */
1147 if (irq != dev->irq) {
1148 dev_err(dev->class_dev, "Incorrect interrupt num: %d\n", irq);
1152 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1153 ME4000_IRQ_STATUS_BIT_AI_HF) {
1154 /* Read status register to find out what happened */
1155 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1157 if (!(tmp & ME4000_AI_STATUS_BIT_FF_DATA) &&
1158 !(tmp & ME4000_AI_STATUS_BIT_HF_DATA) &&
1159 (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1160 c = ME4000_AI_FIFO_COUNT;
1163 * FIFO overflow, so stop conversion
1164 * and disable all interrupts
1166 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1167 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1168 ME4000_AI_CTRL_BIT_SC_IRQ);
1169 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1171 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1173 dev_err(dev->class_dev, "FIFO overflow\n");
1174 } else if ((tmp & ME4000_AI_STATUS_BIT_FF_DATA)
1175 && !(tmp & ME4000_AI_STATUS_BIT_HF_DATA)
1176 && (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1177 s->async->events |= COMEDI_CB_BLOCK;
1179 c = ME4000_AI_FIFO_COUNT / 2;
1181 dev_err(dev->class_dev,
1182 "Can't determine state of fifo\n");
1186 * Undefined state, so stop conversion
1187 * and disable all interrupts
1189 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1190 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1191 ME4000_AI_CTRL_BIT_SC_IRQ);
1192 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1194 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1196 dev_err(dev->class_dev, "Undefined FIFO state\n");
1199 for (i = 0; i < c; i++) {
1200 /* Read value from data fifo */
1201 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1204 if (!comedi_buf_put(s->async, lval)) {
1206 * Buffer overflow, so stop conversion
1207 * and disable all interrupts
1209 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1210 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1211 ME4000_AI_CTRL_BIT_SC_IRQ);
1212 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1214 s->async->events |= COMEDI_CB_OVERFLOW;
1216 dev_err(dev->class_dev, "Buffer overflow\n");
1222 /* Work is done, so reset the interrupt */
1223 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1224 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1225 tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1226 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1229 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1230 ME4000_IRQ_STATUS_BIT_SC) {
1231 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOA;
1234 * Acquisition is complete, so stop
1235 * conversion and disable all interrupts
1237 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1238 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1239 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
1240 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1242 /* Poll data until fifo empty */
1243 while (inl(dev->iobase + ME4000_AI_CTRL_REG) &
1244 ME4000_AI_STATUS_BIT_EF_DATA) {
1245 /* Read value from data fifo */
1246 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1249 if (!comedi_buf_put(s->async, lval)) {
1250 dev_err(dev->class_dev, "Buffer overflow\n");
1251 s->async->events |= COMEDI_CB_OVERFLOW;
1256 /* Work is done, so reset the interrupt */
1257 tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1258 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1259 tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1260 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1263 if (s->async->events)
1264 comedi_event(dev, s);
1269 /*=============================================================================
1270 Analog output section
1271 ===========================================================================*/
1273 static int me4000_ao_insn_write(struct comedi_device *dev,
1274 struct comedi_subdevice *s,
1275 struct comedi_insn *insn, unsigned int *data)
1277 const struct me4000_board *thisboard = comedi_board(dev);
1278 struct me4000_info *info = dev->private;
1279 int chan = CR_CHAN(insn->chanspec);
1280 int rang = CR_RANGE(insn->chanspec);
1281 int aref = CR_AREF(insn->chanspec);
1286 } else if (insn->n > 1) {
1287 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1292 if (chan >= thisboard->ao_nchan) {
1293 dev_err(dev->class_dev, "Invalid channel %d\n", insn->n);
1298 dev_err(dev->class_dev, "Invalid range %d\n", insn->n);
1302 if (aref != AREF_GROUND && aref != AREF_COMMON) {
1303 dev_err(dev->class_dev, "Invalid aref %d\n", insn->n);
1307 /* Stop any running conversion */
1308 tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan));
1309 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
1310 outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan));
1312 /* Clear control register and set to single mode */
1313 outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));
1315 /* Write data value */
1316 outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));
1318 /* Store in the mirror */
1319 info->ao_readback[chan] = data[0];
1324 static int me4000_ao_insn_read(struct comedi_device *dev,
1325 struct comedi_subdevice *s,
1326 struct comedi_insn *insn, unsigned int *data)
1328 struct me4000_info *info = dev->private;
1329 int chan = CR_CHAN(insn->chanspec);
1333 } else if (insn->n > 1) {
1334 dev_err(dev->class_dev, "Invalid instruction length\n");
1338 data[0] = info->ao_readback[chan];
1343 /*=============================================================================
1345 ===========================================================================*/
1347 static int me4000_dio_insn_bits(struct comedi_device *dev,
1348 struct comedi_subdevice *s,
1349 struct comedi_insn *insn, unsigned int *data)
1352 * The insn data consists of a mask in data[0] and the new data
1353 * in data[1]. The mask defines which bits we are concerning about.
1354 * The new data must be anded with the mask.
1355 * Each channel corresponds to a bit.
1358 /* Check if requested ports are configured for output */
1359 if ((s->io_bits & data[0]) != data[0])
1362 s->state &= ~data[0];
1363 s->state |= data[0] & data[1];
1365 /* Write out the new digital output lines */
1366 outl((s->state >> 0) & 0xFF,
1367 dev->iobase + ME4000_DIO_PORT_0_REG);
1368 outl((s->state >> 8) & 0xFF,
1369 dev->iobase + ME4000_DIO_PORT_1_REG);
1370 outl((s->state >> 16) & 0xFF,
1371 dev->iobase + ME4000_DIO_PORT_2_REG);
1372 outl((s->state >> 24) & 0xFF,
1373 dev->iobase + ME4000_DIO_PORT_3_REG);
1376 /* On return, data[1] contains the value of
1377 the digital input and output lines. */
1378 data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |
1379 ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |
1380 ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |
1381 ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);
1386 static int me4000_dio_insn_config(struct comedi_device *dev,
1387 struct comedi_subdevice *s,
1388 struct comedi_insn *insn, unsigned int *data)
1391 int chan = CR_CHAN(insn->chanspec);
1396 case INSN_CONFIG_DIO_QUERY:
1398 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1400 case INSN_CONFIG_DIO_INPUT:
1401 case INSN_CONFIG_DIO_OUTPUT:
1406 * The input or output configuration of each digital line is
1407 * configured by a special insn_config instruction. chanspec
1408 * contains the channel to be changed, and data[0] contains the
1409 * value INSN_CONFIG_DIO_INPUT or INSN_CONFIG_DIO_OUTPUT.
1410 * On the ME-4000 it is only possible to switch port wise (8 bit)
1413 tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG);
1415 if (data[0] == INSN_CONFIG_DIO_OUTPUT) {
1418 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 |
1419 ME4000_DIO_CTRL_BIT_MODE_1);
1420 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1421 } else if (chan < 16) {
1423 * Chech for optoisolated ME-4000 version.
1424 * If one the first port is a fixed output
1425 * port and the second is a fixed input port.
1427 if (!inl(dev->iobase + ME4000_DIO_DIR_REG))
1430 s->io_bits |= 0xFF00;
1431 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1432 ME4000_DIO_CTRL_BIT_MODE_3);
1433 tmp |= ME4000_DIO_CTRL_BIT_MODE_2;
1434 } else if (chan < 24) {
1435 s->io_bits |= 0xFF0000;
1436 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_4 |
1437 ME4000_DIO_CTRL_BIT_MODE_5);
1438 tmp |= ME4000_DIO_CTRL_BIT_MODE_4;
1439 } else if (chan < 32) {
1440 s->io_bits |= 0xFF000000;
1441 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_6 |
1442 ME4000_DIO_CTRL_BIT_MODE_7);
1443 tmp |= ME4000_DIO_CTRL_BIT_MODE_6;
1450 * Chech for optoisolated ME-4000 version.
1451 * If one the first port is a fixed output
1452 * port and the second is a fixed input port.
1454 if (!inl(dev->iobase + ME4000_DIO_DIR_REG))
1457 s->io_bits &= ~0xFF;
1458 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 |
1459 ME4000_DIO_CTRL_BIT_MODE_1);
1460 } else if (chan < 16) {
1461 s->io_bits &= ~0xFF00;
1462 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1463 ME4000_DIO_CTRL_BIT_MODE_3);
1464 } else if (chan < 24) {
1465 s->io_bits &= ~0xFF0000;
1466 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_4 |
1467 ME4000_DIO_CTRL_BIT_MODE_5);
1468 } else if (chan < 32) {
1469 s->io_bits &= ~0xFF000000;
1470 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_6 |
1471 ME4000_DIO_CTRL_BIT_MODE_7);
1477 outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG);
1482 /*=============================================================================
1484 ===========================================================================*/
1486 static int me4000_cnt_insn_config(struct comedi_device *dev,
1487 struct comedi_subdevice *s,
1488 struct comedi_insn *insn,
1491 struct me4000_info *info = dev->private;
1499 err = i8254_load(info->timer_regbase, 0, insn->chanspec, 0,
1500 I8254_MODE0 | I8254_BINARY);
1504 case GPCT_SET_OPERATION:
1508 err = i8254_set_mode(info->timer_regbase, 0, insn->chanspec,
1509 (data[1] << 1) | I8254_BINARY);
1520 static int me4000_cnt_insn_read(struct comedi_device *dev,
1521 struct comedi_subdevice *s,
1522 struct comedi_insn *insn, unsigned int *data)
1524 struct me4000_info *info = dev->private;
1530 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1535 data[0] = i8254_read(info->timer_regbase, 0, insn->chanspec);
1540 static int me4000_cnt_insn_write(struct comedi_device *dev,
1541 struct comedi_subdevice *s,
1542 struct comedi_insn *insn, unsigned int *data)
1544 struct me4000_info *info = dev->private;
1548 } else if (insn->n > 1) {
1549 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1554 i8254_write(info->timer_regbase, 0, insn->chanspec, data[0]);
1559 static const void *me4000_find_boardinfo(struct comedi_device *dev,
1560 struct pci_dev *pcidev)
1562 const struct me4000_board *thisboard;
1565 for (i = 0; i < ARRAY_SIZE(me4000_boards); i++) {
1566 thisboard = &me4000_boards[i];
1567 if (thisboard->device_id == pcidev->device)
1573 static int me4000_attach_pci(struct comedi_device *dev,
1574 struct pci_dev *pcidev)
1576 const struct me4000_board *thisboard;
1577 struct me4000_info *info;
1578 struct comedi_subdevice *s;
1581 comedi_set_hw_dev(dev, &pcidev->dev);
1583 thisboard = me4000_find_boardinfo(dev, pcidev);
1586 dev->board_ptr = thisboard;
1587 dev->board_name = thisboard->name;
1589 info = kzalloc(sizeof(*info), GFP_KERNEL);
1592 dev->private = info;
1594 result = comedi_pci_enable(pcidev, dev->board_name);
1598 info->plx_regbase = pci_resource_start(pcidev, 1);
1599 dev->iobase = pci_resource_start(pcidev, 2);
1600 info->timer_regbase = pci_resource_start(pcidev, 3);
1601 if (!info->plx_regbase || !dev->iobase || !info->timer_regbase)
1604 result = xilinx_download(dev);
1610 result = comedi_alloc_subdevices(dev, 4);
1614 /*=========================================================================
1615 Analog input subdevice
1616 ========================================================================*/
1618 s = &dev->subdevices[0];
1620 if (thisboard->ai_nchan) {
1621 s->type = COMEDI_SUBD_AI;
1623 SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF;
1624 s->n_chan = thisboard->ai_nchan;
1625 s->maxdata = 0xFFFF; /* 16 bit ADC */
1626 s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT;
1627 s->range_table = &me4000_ai_range;
1628 s->insn_read = me4000_ai_insn_read;
1630 if (pcidev->irq > 0) {
1631 if (request_irq(pcidev->irq, me4000_ai_isr,
1632 IRQF_SHARED, dev->board_name, dev)) {
1633 dev_warn(dev->class_dev,
1634 "request_irq failed\n");
1636 dev->read_subdev = s;
1637 s->subdev_flags |= SDF_CMD_READ;
1638 s->cancel = me4000_ai_cancel;
1639 s->do_cmdtest = me4000_ai_do_cmd_test;
1640 s->do_cmd = me4000_ai_do_cmd;
1642 dev->irq = pcidev->irq;
1645 dev_warn(dev->class_dev, "No interrupt available\n");
1648 s->type = COMEDI_SUBD_UNUSED;
1651 /*=========================================================================
1652 Analog output subdevice
1653 ========================================================================*/
1655 s = &dev->subdevices[1];
1657 if (thisboard->ao_nchan) {
1658 s->type = COMEDI_SUBD_AO;
1659 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON | SDF_GROUND;
1660 s->n_chan = thisboard->ao_nchan;
1661 s->maxdata = 0xFFFF; /* 16 bit DAC */
1662 s->range_table = &range_bipolar10;
1663 s->insn_write = me4000_ao_insn_write;
1664 s->insn_read = me4000_ao_insn_read;
1666 s->type = COMEDI_SUBD_UNUSED;
1669 /*=========================================================================
1670 Digital I/O subdevice
1671 ========================================================================*/
1673 s = &dev->subdevices[2];
1675 if (thisboard->dio_nchan) {
1676 s->type = COMEDI_SUBD_DIO;
1677 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1678 s->n_chan = thisboard->dio_nchan;
1680 s->range_table = &range_digital;
1681 s->insn_bits = me4000_dio_insn_bits;
1682 s->insn_config = me4000_dio_insn_config;
1684 s->type = COMEDI_SUBD_UNUSED;
1688 * Check for optoisolated ME-4000 version. If one the first
1689 * port is a fixed output port and the second is a fixed input port.
1691 if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1693 outl(ME4000_DIO_CTRL_BIT_MODE_0,
1694 dev->iobase + ME4000_DIO_DIR_REG);
1697 /*=========================================================================
1699 ========================================================================*/
1701 s = &dev->subdevices[3];
1703 if (thisboard->has_counter) {
1704 s->type = COMEDI_SUBD_COUNTER;
1705 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1707 s->maxdata = 0xFFFF; /* 16 bit counters */
1708 s->insn_read = me4000_cnt_insn_read;
1709 s->insn_write = me4000_cnt_insn_write;
1710 s->insn_config = me4000_cnt_insn_config;
1712 s->type = COMEDI_SUBD_UNUSED;
1718 static void me4000_detach(struct comedi_device *dev)
1720 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1723 free_irq(dev->irq, dev);
1727 comedi_pci_disable(pcidev);
1732 static struct comedi_driver me4000_driver = {
1733 .driver_name = "me4000",
1734 .module = THIS_MODULE,
1735 .attach_pci = me4000_attach_pci,
1736 .detach = me4000_detach,
1739 static int __devinit me4000_pci_probe(struct pci_dev *dev,
1740 const struct pci_device_id *ent)
1742 return comedi_pci_auto_config(dev, &me4000_driver);
1745 static void __devexit me4000_pci_remove(struct pci_dev *dev)
1747 comedi_pci_auto_unconfig(dev);
1750 static DEFINE_PCI_DEVICE_TABLE(me4000_pci_table) = {
1751 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4650)},
1752 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660)},
1753 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660I)},
1754 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660S)},
1755 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660IS)},
1756 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670)},
1757 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670I)},
1758 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670S)},
1759 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670IS)},
1760 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680)},
1761 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680I)},
1762 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680S)},
1763 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680IS)},
1766 MODULE_DEVICE_TABLE(pci, me4000_pci_table);
1768 static struct pci_driver me4000_pci_driver = {
1770 .id_table = me4000_pci_table,
1771 .probe = me4000_pci_probe,
1772 .remove = __devexit_p(me4000_pci_remove),
1774 module_comedi_pci_driver(me4000_driver, me4000_pci_driver);
1776 MODULE_AUTHOR("Comedi http://www.comedi.org");
1777 MODULE_DESCRIPTION("Comedi low-level driver");
1778 MODULE_LICENSE("GPL");