Pileus Git - ~andy/linux/blob - drivers/staging/comedi/drivers/gsc_hpdi.c

   1 /*
   2     comedi/drivers/gsc_hpdi.c
   3     This is a driver for the General Standards Corporation High
   4     Speed Parallel Digital Interface rs485 boards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2003 Coherent Imaging Systems
   8
   9     COMEDI - Linux Control and Measurement Device Interface
  10     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  11
  12     This program is free software; you can redistribute it and/or modify
  13     it under the terms of the GNU General Public License as published by
  14     the Free Software Foundation; either version 2 of the License, or
  15     (at your option) any later version.
  16
  17     This program is distributed in the hope that it will be useful,
  18     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20     GNU General Public License for more details.
  21
  22     You should have received a copy of the GNU General Public License
  23     along with this program; if not, write to the Free Software
  24     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25
  26 ************************************************************************/
  27
  28 /*
  29
  30 Driver: gsc_hpdi
  31 Description: General Standards Corporation High
  32     Speed Parallel Digital Interface rs485 boards
  33 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  34 Status: only receive mode works, transmit not supported
  35 Updated: 2003-02-20
  36 Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
  37   PMC-HPDI32
  38
  39 Configuration options:
  40    [0] - PCI bus of device (optional)
  41    [1] - PCI slot of device (optional)
  42
  43 There are some additional hpdi models available from GSC for which
  44 support could be added to this driver.
  45
  46 */
  47
  48 #include <linux/interrupt.h>
  49 #include "../comedidev.h"
  50 #include <linux/delay.h>
  51
  52 #include "plx9080.h"
  53 #include "comedi_fc.h"
  54
  55 static void abort_dma(struct comedi_device *dev, unsigned int channel);
  56 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
  57 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
  58                          struct comedi_cmd *cmd);
  59 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
  60 static irqreturn_t handle_interrupt(int irq, void *d);
  61 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
  62
  63 #undef HPDI_DEBUG               /*  disable debugging messages */
  64 /* #define HPDI_DEBUG      enable debugging code */
  65
  66 #ifdef HPDI_DEBUG
  67 #define DEBUG_PRINT(format, args...)  printk(format , ## args)
  68 #else
  69 #define DEBUG_PRINT(format, args...)
  70 #endif
  71
  72 #define TIMER_BASE 50           /*  20MHz master clock */
  73 #define DMA_BUFFER_SIZE 0x10000
  74 #define NUM_DMA_BUFFERS 4
  75 #define NUM_DMA_DESCRIPTORS 256
  76
  77 /* indices of base address regions */
  78 enum base_address_regions {
  79         PLX9080_BADDRINDEX = 0,
  80         HPDI_BADDRINDEX = 2,
  81 };
  82
  83 enum hpdi_registers {
  84         FIRMWARE_REV_REG = 0x0,
  85         BOARD_CONTROL_REG = 0x4,
  86         BOARD_STATUS_REG = 0x8,
  87         TX_PROG_ALMOST_REG = 0xc,
  88         RX_PROG_ALMOST_REG = 0x10,
  89         FEATURES_REG = 0x14,
  90         FIFO_REG = 0x18,
  91         TX_STATUS_COUNT_REG = 0x1c,
  92         TX_LINE_VALID_COUNT_REG = 0x20,
  93         TX_LINE_INVALID_COUNT_REG = 0x24,
  94         RX_STATUS_COUNT_REG = 0x28,
  95         RX_LINE_COUNT_REG = 0x2c,
  96         INTERRUPT_CONTROL_REG = 0x30,
  97         INTERRUPT_STATUS_REG = 0x34,
  98         TX_CLOCK_DIVIDER_REG = 0x38,
  99         TX_FIFO_SIZE_REG = 0x40,
 100         RX_FIFO_SIZE_REG = 0x44,
 101         TX_FIFO_WORDS_REG = 0x48,
 102         RX_FIFO_WORDS_REG = 0x4c,
 103         INTERRUPT_EDGE_LEVEL_REG = 0x50,
 104         INTERRUPT_POLARITY_REG = 0x54,
 105 };
 106
 107 int command_channel_valid(unsigned int channel)
 108 {
 109         if (channel == 0 || channel > 6) {
 110                 printk(KERN_WARNING
 111                        "gsc_hpdi: bug! invalid cable command channel\n");
 112                 return 0;
 113         }
 114         return 1;
 115 }
 116
 117 /* bit definitions */
 118
 119 enum firmware_revision_bits {
 120         FEATURES_REG_PRESENT_BIT = 0x8000,
 121 };
 122 int firmware_revision(uint32_t fwr_bits)
 123 {
 124         return fwr_bits & 0xff;
 125 }
 126
 127 int pcb_revision(uint32_t fwr_bits)
 128 {
 129         return (fwr_bits >> 8) & 0xff;
 130 }
 131
 132 int hpdi_subid(uint32_t fwr_bits)
 133 {
 134         return (fwr_bits >> 16) & 0xff;
 135 }
 136
 137 enum board_control_bits {
 138         BOARD_RESET_BIT = 0x1,  /* wait 10usec before accessing fifos */
 139         TX_FIFO_RESET_BIT = 0x2,
 140         RX_FIFO_RESET_BIT = 0x4,
 141         TX_ENABLE_BIT = 0x10,
 142         RX_ENABLE_BIT = 0x20,
 143         DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
 144                 /* for ch 0, ch 1 can only transmit (when present) */
 145         LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
 146         START_TX_BIT = 0x10,
 147         CABLE_THROTTLE_ENABLE_BIT = 0x20,
 148         TEST_MODE_ENABLE_BIT = 0x80000000,
 149 };
 150 uint32_t command_discrete_output_bits(unsigned int channel, int output,
 151                                       int output_value)
 152 {
 153         uint32_t bits = 0;
 154
 155         if (command_channel_valid(channel) == 0)
 156                 return 0;
 157         if (output) {
 158                 bits |= 0x1 << (16 + channel);
 159                 if (output_value)
 160                         bits |= 0x1 << (24 + channel);
 161         } else
 162                 bits |= 0x1 << (24 + channel);
 163
 164         return bits;
 165 }
 166
 167 enum board_status_bits {
 168         COMMAND_LINE_STATUS_MASK = 0x7f,
 169         TX_IN_PROGRESS_BIT = 0x80,
 170         TX_NOT_EMPTY_BIT = 0x100,
 171         TX_NOT_ALMOST_EMPTY_BIT = 0x200,
 172         TX_NOT_ALMOST_FULL_BIT = 0x400,
 173         TX_NOT_FULL_BIT = 0x800,
 174         RX_NOT_EMPTY_BIT = 0x1000,
 175         RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
 176         RX_NOT_ALMOST_FULL_BIT = 0x4000,
 177         RX_NOT_FULL_BIT = 0x8000,
 178         BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
 179         BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
 180         TX_OVERRUN_BIT = 0x200000,
 181         RX_UNDERRUN_BIT = 0x400000,
 182         RX_OVERRUN_BIT = 0x800000,
 183 };
 184
 185 uint32_t almost_full_bits(unsigned int num_words)
 186 {
 187 /* XXX need to add or subtract one? */
 188         return (num_words << 16) & 0xff0000;
 189 }
 190
 191 uint32_t almost_empty_bits(unsigned int num_words)
 192 {
 193         return num_words & 0xffff;
 194 }
 195
 196 unsigned int almost_full_num_words(uint32_t bits)
 197 {
 198 /* XXX need to add or subtract one? */
 199         return (bits >> 16) & 0xffff;
 200 }
 201
 202 unsigned int almost_empty_num_words(uint32_t bits)
 203 {
 204         return bits & 0xffff;
 205 }
 206
 207 enum features_bits {
 208         FIFO_SIZE_PRESENT_BIT = 0x1,
 209         FIFO_WORDS_PRESENT_BIT = 0x2,
 210         LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
 211         GPIO_SUPPORTED_BIT = 0x8,
 212         PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
 213         OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
 214 };
 215
 216 enum interrupt_sources {
 217         FRAME_VALID_START_INTR = 0,
 218         FRAME_VALID_END_INTR = 1,
 219         TX_FIFO_EMPTY_INTR = 8,
 220         TX_FIFO_ALMOST_EMPTY_INTR = 9,
 221         TX_FIFO_ALMOST_FULL_INTR = 10,
 222         TX_FIFO_FULL_INTR = 11,
 223         RX_EMPTY_INTR = 12,
 224         RX_ALMOST_EMPTY_INTR = 13,
 225         RX_ALMOST_FULL_INTR = 14,
 226         RX_FULL_INTR = 15,
 227 };
 228 int command_intr_source(unsigned int channel)
 229 {
 230         if (command_channel_valid(channel) == 0)
 231                 channel = 1;
 232         return channel + 1;
 233 }
 234
 235 uint32_t intr_bit(int interrupt_source)
 236 {
 237         return 0x1 << interrupt_source;
 238 }
 239
 240 uint32_t tx_clock_divisor_bits(unsigned int divisor)
 241 {
 242         return divisor & 0xff;
 243 }
 244
 245 unsigned int fifo_size(uint32_t fifo_size_bits)
 246 {
 247         return fifo_size_bits & 0xfffff;
 248 }
 249
 250 unsigned int fifo_words(uint32_t fifo_words_bits)
 251 {
 252         return fifo_words_bits & 0xfffff;
 253 }
 254
 255 uint32_t intr_edge_bit(int interrupt_source)
 256 {
 257         return 0x1 << interrupt_source;
 258 }
 259
 260 uint32_t intr_active_high_bit(int interrupt_source)
 261 {
 262         return 0x1 << interrupt_source;
 263 }
 264
 265 struct hpdi_board {
 266
 267         char *name;
 268         int device_id;          /*  pci device id */
 269         int subdevice_id;       /*  pci subdevice id */
 270 };
 271
 272 static const struct hpdi_board hpdi_boards[] = {
 273         {
 274          .name = "pci-hpdi32",
 275          .device_id = PCI_DEVICE_ID_PLX_9080,
 276          .subdevice_id = 0x2400,
 277          },
 278 #if 0
 279         {
 280          .name = "pxi-hpdi32",
 281          .device_id = 0x9656,
 282          .subdevice_id = 0x2705,
 283          },
 284 #endif
 285 };
 286
 287 static inline struct hpdi_board *board(const struct comedi_device *dev)
 288 {
 289         return (struct hpdi_board *)dev->board_ptr;
 290 }
 291
 292 struct hpdi_private {
 293
 294         struct pci_dev *hw_dev; /*  pointer to board's pci_dev struct */
 295         /*  base addresses (physical) */
 296         resource_size_t plx9080_phys_iobase;
 297         resource_size_t hpdi_phys_iobase;
 298         /*  base addresses (ioremapped) */
 299         void __iomem *plx9080_iobase;
 300         void __iomem *hpdi_iobase;
 301         uint32_t *dio_buffer[NUM_DMA_BUFFERS];  /*  dma buffers */
 302         /* physical addresses of dma buffers */
 303         dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
 304         /* array of dma descriptors read by plx9080, allocated to get proper
 305          * alignment */
 306         struct plx_dma_desc *dma_desc;
 307         /* physical address of dma descriptor array */
 308         dma_addr_t dma_desc_phys_addr;
 309         unsigned int num_dma_descriptors;
 310         /* pointer to start of buffers indexed by descriptor */
 311         uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
 312         /* index of the dma descriptor that is currently being used */
 313         volatile unsigned int dma_desc_index;
 314         unsigned int tx_fifo_size;
 315         unsigned int rx_fifo_size;
 316         volatile unsigned long dio_count;
 317         /* software copies of values written to hpdi registers */
 318         volatile uint32_t bits[24];
 319         /* number of bytes at which to generate COMEDI_CB_BLOCK events */
 320         volatile unsigned int block_size;
 321         unsigned dio_config_output:1;
 322 };
 323
 324 static inline struct hpdi_private *priv(struct comedi_device *dev)
 325 {
 326         return dev->private;
 327 }
 328
 329 static int dio_config_insn(struct comedi_device *dev,
 330                            struct comedi_subdevice *s, struct comedi_insn *insn,
 331                            unsigned int *data)
 332 {
 333         switch (data[0]) {
 334         case INSN_CONFIG_DIO_OUTPUT:
 335                 priv(dev)->dio_config_output = 1;
 336                 return insn->n;
 337                 break;
 338         case INSN_CONFIG_DIO_INPUT:
 339                 priv(dev)->dio_config_output = 0;
 340                 return insn->n;
 341                 break;
 342         case INSN_CONFIG_DIO_QUERY:
 343                 data[1] =
 344                     priv(dev)->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
 345                 return insn->n;
 346                 break;
 347         case INSN_CONFIG_BLOCK_SIZE:
 348                 return dio_config_block_size(dev, data);
 349                 break;
 350         default:
 351                 break;
 352         }
 353
 354         return -EINVAL;
 355 }
 356
 357 static void disable_plx_interrupts(struct comedi_device *dev)
 358 {
 359         writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
 360 }
 361
 362 /* initialize plx9080 chip */
 363 static void init_plx9080(struct comedi_device *dev)
 364 {
 365         uint32_t bits;
 366         void __iomem *plx_iobase = priv(dev)->plx9080_iobase;
 367
 368         /*  plx9080 dump */
 369         DEBUG_PRINT(" plx interrupt status 0x%x\n",
 370                     readl(plx_iobase + PLX_INTRCS_REG));
 371         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
 372         DEBUG_PRINT(" plx control reg 0x%x\n",
 373                     readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
 374
 375         DEBUG_PRINT(" plx revision 0x%x\n",
 376                     readl(plx_iobase + PLX_REVISION_REG));
 377         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
 378                     readl(plx_iobase + PLX_DMA0_MODE_REG));
 379         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
 380                     readl(plx_iobase + PLX_DMA1_MODE_REG));
 381         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
 382                     readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
 383         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
 384                     readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
 385         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
 386                     readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
 387         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
 388                     readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
 389         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
 390                     readb(plx_iobase + PLX_DMA0_CS_REG));
 391         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
 392                     readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
 393         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
 394 #ifdef __BIG_ENDIAN
 395         bits = BIGEND_DMA0 | BIGEND_DMA1;
 396 #else
 397         bits = 0;
 398 #endif
 399         writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
 400
 401         disable_plx_interrupts(dev);
 402
 403         abort_dma(dev, 0);
 404         abort_dma(dev, 1);
 405
 406         /*  configure dma0 mode */
 407         bits = 0;
 408         /*  enable ready input */
 409         bits |= PLX_DMA_EN_READYIN_BIT;
 410         /*  enable dma chaining */
 411         bits |= PLX_EN_CHAIN_BIT;
 412         /*  enable interrupt on dma done
 413          *  (probably don't need this, since chain never finishes) */
 414         bits |= PLX_EN_DMA_DONE_INTR_BIT;
 415         /*  don't increment local address during transfers
 416          *  (we are transferring from a fixed fifo register) */
 417         bits |= PLX_LOCAL_ADDR_CONST_BIT;
 418         /*  route dma interrupt to pci bus */
 419         bits |= PLX_DMA_INTR_PCI_BIT;
 420         /*  enable demand mode */
 421         bits |= PLX_DEMAND_MODE_BIT;
 422         /*  enable local burst mode */
 423         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
 424         bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
 425         writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
 426 }
 427
 428 /* Allocate and initialize the subdevice structures.
 429  */
 430 static int setup_subdevices(struct comedi_device *dev)
 431 {
 432         struct comedi_subdevice *s;
 433
 434         if (alloc_subdevices(dev, 1) < 0)
 435                 return -ENOMEM;
 436
 437         s = dev->subdevices + 0;
 438         /* analog input subdevice */
 439         dev->read_subdev = s;
 440 /*      dev->write_subdev = s; */
 441         s->type = COMEDI_SUBD_DIO;
 442         s->subdev_flags =
 443             SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
 444         s->n_chan = 32;
 445         s->len_chanlist = 32;
 446         s->maxdata = 1;
 447         s->range_table = &range_digital;
 448         s->insn_config = dio_config_insn;
 449         s->do_cmd = hpdi_cmd;
 450         s->do_cmdtest = hpdi_cmd_test;
 451         s->cancel = hpdi_cancel;
 452
 453         return 0;
 454 }
 455
 456 static int init_hpdi(struct comedi_device *dev)
 457 {
 458         uint32_t plx_intcsr_bits;
 459
 460         writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG);
 461         udelay(10);
 462
 463         writel(almost_empty_bits(32) | almost_full_bits(32),
 464                priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG);
 465         writel(almost_empty_bits(32) | almost_full_bits(32),
 466                priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG);
 467
 468         priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
 469                                                   TX_FIFO_SIZE_REG));
 470         priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
 471                                                   RX_FIFO_SIZE_REG));
 472
 473         writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
 474
 475         /*  enable interrupts */
 476         plx_intcsr_bits =
 477             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
 478             ICS_DMA0_E;
 479         writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
 480
 481         return 0;
 482 }
 483
 484 /* setup dma descriptors so a link completes every 'transfer_size' bytes */
 485 static int setup_dma_descriptors(struct comedi_device *dev,
 486                                  unsigned int transfer_size)
 487 {
 488         unsigned int buffer_index, buffer_offset;
 489         uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
 490             PLX_XFER_LOCAL_TO_PCI;
 491         unsigned int i;
 492
 493         if (transfer_size > DMA_BUFFER_SIZE)
 494                 transfer_size = DMA_BUFFER_SIZE;
 495         transfer_size -= transfer_size % sizeof(uint32_t);
 496         if (transfer_size == 0)
 497                 return -1;
 498
 499         DEBUG_PRINT(" transfer_size %i\n", transfer_size);
 500         DEBUG_PRINT(" descriptors at 0x%lx\n",
 501                     (unsigned long)priv(dev)->dma_desc_phys_addr);
 502
 503         buffer_offset = 0;
 504         buffer_index = 0;
 505         for (i = 0; i < NUM_DMA_DESCRIPTORS &&
 506              buffer_index < NUM_DMA_BUFFERS; i++) {
 507                 priv(dev)->dma_desc[i].pci_start_addr =
 508                     cpu_to_le32(priv(dev)->dio_buffer_phys_addr[buffer_index] +
 509                                 buffer_offset);
 510                 priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
 511                 priv(dev)->dma_desc[i].transfer_size =
 512                     cpu_to_le32(transfer_size);
 513                 priv(dev)->dma_desc[i].next =
 514                     cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i +
 515                                                                   1) *
 516                                  sizeof(priv(dev)->dma_desc[0])) | next_bits);
 517
 518                 priv(dev)->desc_dio_buffer[i] =
 519                     priv(dev)->dio_buffer[buffer_index] +
 520                     (buffer_offset / sizeof(uint32_t));
 521
 522                 buffer_offset += transfer_size;
 523                 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
 524                         buffer_offset = 0;
 525                         buffer_index++;
 526                 }
 527
 528                 DEBUG_PRINT(" desc %i\n", i);
 529                 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
 530                             priv(dev)->desc_dio_buffer[i],
 531                             (unsigned long)priv(dev)->dma_desc[i].
 532                             pci_start_addr);
 533                 DEBUG_PRINT(" next 0x%lx\n",
 534                             (unsigned long)priv(dev)->dma_desc[i].next);
 535         }
 536         priv(dev)->num_dma_descriptors = i;
 537         /*  fix last descriptor to point back to first */
 538         priv(dev)->dma_desc[i - 1].next =
 539             cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits);
 540         DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
 541                     (unsigned long)priv(dev)->dma_desc[i - 1].next);
 542
 543         priv(dev)->block_size = transfer_size;
 544
 545         return transfer_size;
 546 }
 547
 548 static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it)
 549 {
 550         struct pci_dev *pcidev;
 551         int i;
 552         int retval;
 553
 554         printk(KERN_WARNING "comedi%d: gsc_hpdi\n", dev->minor);
 555
 556         if (alloc_private(dev, sizeof(struct hpdi_private)) < 0)
 557                 return -ENOMEM;
 558
 559         pcidev = NULL;
 560         for (i = 0; i < ARRAY_SIZE(hpdi_boards) &&
 561                     dev->board_ptr == NULL; i++) {
 562                 do {
 563                         pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX,
 564                                                 hpdi_boards[i].device_id,
 565                                                 PCI_VENDOR_ID_PLX,
 566                                                 hpdi_boards[i].subdevice_id,
 567                                                 pcidev);
 568                         /*  was a particular bus/slot requested? */
 569                         if (it->options[0] || it->options[1]) {
 570                                 /*  are we on the wrong bus/slot? */
 571                                 if (pcidev->bus->number != it->options[0] ||
 572                                     PCI_SLOT(pcidev->devfn) != it->options[1])
 573                                         continue;
 574                         }
 575                         if (pcidev) {
 576                                 priv(dev)->hw_dev = pcidev;
 577                                 dev->board_ptr = hpdi_boards + i;
 578                                 break;
 579                         }
 580                 } while (pcidev != NULL);
 581         }
 582         if (dev->board_ptr == NULL) {
 583                 printk(KERN_WARNING "gsc_hpdi: no hpdi card found\n");
 584                 return -EIO;
 585         }
 586
 587         printk(KERN_WARNING
 588                "gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name,
 589                pcidev->bus->number, PCI_SLOT(pcidev->devfn));
 590
 591         if (comedi_pci_enable(pcidev, dev->driver->driver_name)) {
 592                 printk(KERN_WARNING
 593                        " failed enable PCI device and request regions\n");
 594                 return -EIO;
 595         }
 596         pci_set_master(pcidev);
 597
 598         /* Initialize dev->board_name */
 599         dev->board_name = board(dev)->name;
 600
 601         priv(dev)->plx9080_phys_iobase =
 602             pci_resource_start(pcidev, PLX9080_BADDRINDEX);
 603         priv(dev)->hpdi_phys_iobase =
 604             pci_resource_start(pcidev, HPDI_BADDRINDEX);
 605
 606         /*  remap, won't work with 2.0 kernels but who cares */
 607         priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
 608                                             pci_resource_len(pcidev,
 609                                             PLX9080_BADDRINDEX));
 610         priv(dev)->hpdi_iobase =
 611             ioremap(priv(dev)->hpdi_phys_iobase,
 612                     pci_resource_len(pcidev, HPDI_BADDRINDEX));
 613         if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) {
 614                 printk(KERN_WARNING " failed to remap io memory\n");
 615                 return -ENOMEM;
 616         }
 617
 618         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
 619         DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase);
 620
 621         init_plx9080(dev);
 622
 623         /*  get irq */
 624         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
 625                         dev->driver->driver_name, dev)) {
 626                 printk(KERN_WARNING
 627                        " unable to allocate irq %u\n", pcidev->irq);
 628                 return -EINVAL;
 629         }
 630         dev->irq = pcidev->irq;
 631
 632         printk(KERN_WARNING " irq %u\n", dev->irq);
 633
 634         /*  allocate pci dma buffers */
 635         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
 636                 priv(dev)->dio_buffer[i] =
 637                     pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
 638                                          &priv(dev)->dio_buffer_phys_addr[i]);
 639                 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
 640                             priv(dev)->dio_buffer[i],
 641                             (unsigned long)priv(dev)->dio_buffer_phys_addr[i]);
 642         }
 643         /*  allocate dma descriptors */
 644         priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev,
 645                                                    sizeof(struct plx_dma_desc) *
 646                                                    NUM_DMA_DESCRIPTORS,
 647                                                    &priv(dev)->
 648                                                    dma_desc_phys_addr);
 649         if (priv(dev)->dma_desc_phys_addr & 0xf) {
 650                 printk(KERN_WARNING
 651                        " dma descriptors not quad-word aligned (bug)\n");
 652                 return -EIO;
 653         }
 654
 655         retval = setup_dma_descriptors(dev, 0x1000);
 656         if (retval < 0)
 657                 return retval;
 658
 659         retval = setup_subdevices(dev);
 660         if (retval < 0)
 661                 return retval;
 662
 663         return init_hpdi(dev);
 664 }
 665
 666 static void hpdi_detach(struct comedi_device *dev)
 667 {
 668         unsigned int i;
 669
 670         if (dev->irq)
 671                 free_irq(dev->irq, dev);
 672         if ((priv(dev)) && (priv(dev)->hw_dev)) {
 673                 if (priv(dev)->plx9080_iobase) {
 674                         disable_plx_interrupts(dev);
 675                         iounmap(priv(dev)->plx9080_iobase);
 676                 }
 677                 if (priv(dev)->hpdi_iobase)
 678                         iounmap(priv(dev)->hpdi_iobase);
 679                 /*  free pci dma buffers */
 680                 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
 681                         if (priv(dev)->dio_buffer[i])
 682                                 pci_free_consistent(priv(dev)->hw_dev,
 683                                                     DMA_BUFFER_SIZE,
 684                                                     priv(dev)->
 685                                                     dio_buffer[i],
 686                                                     priv
 687                                                     (dev)->dio_buffer_phys_addr
 688                                                     [i]);
 689                 }
 690                 /*  free dma descriptors */
 691                 if (priv(dev)->dma_desc)
 692                         pci_free_consistent(priv(dev)->hw_dev,
 693                                             sizeof(struct plx_dma_desc)
 694                                             * NUM_DMA_DESCRIPTORS,
 695                                             priv(dev)->dma_desc,
 696                                             priv(dev)->
 697                                             dma_desc_phys_addr);
 698                 if (priv(dev)->hpdi_phys_iobase)
 699                         comedi_pci_disable(priv(dev)->hw_dev);
 700                 pci_dev_put(priv(dev)->hw_dev);
 701         }
 702 }
 703
 704 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
 705 {
 706         unsigned int requested_block_size;
 707         int retval;
 708
 709         requested_block_size = data[1];
 710
 711         retval = setup_dma_descriptors(dev, requested_block_size);
 712         if (retval < 0)
 713                 return retval;
 714
 715         data[1] = retval;
 716
 717         return 2;
 718 }
 719
 720 static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
 721                        struct comedi_cmd *cmd)
 722 {
 723         int err = 0;
 724         int tmp;
 725         int i;
 726
 727         /* step 1: make sure trigger sources are trivially valid */
 728
 729         tmp = cmd->start_src;
 730         cmd->start_src &= TRIG_NOW;
 731         if (!cmd->start_src || tmp != cmd->start_src)
 732                 err++;
 733
 734         tmp = cmd->scan_begin_src;
 735         cmd->scan_begin_src &= TRIG_EXT;
 736         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
 737                 err++;
 738
 739         tmp = cmd->convert_src;
 740         cmd->convert_src &= TRIG_NOW;
 741         if (!cmd->convert_src || tmp != cmd->convert_src)
 742                 err++;
 743
 744         tmp = cmd->scan_end_src;
 745         cmd->scan_end_src &= TRIG_COUNT;
 746         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
 747                 err++;
 748
 749         tmp = cmd->stop_src;
 750         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
 751         if (!cmd->stop_src || tmp != cmd->stop_src)
 752                 err++;
 753
 754         if (err)
 755                 return 1;
 756
 757         /* step 2: make sure trigger sources are unique and mutually
 758          * compatible */
 759
 760         /*  uniqueness check */
 761         if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
 762                 err++;
 763
 764         if (err)
 765                 return 2;
 766
 767         /* step 3: make sure arguments are trivially compatible */
 768
 769         if (!cmd->chanlist_len) {
 770                 cmd->chanlist_len = 32;
 771                 err++;
 772         }
 773         if (cmd->scan_end_arg != cmd->chanlist_len) {
 774                 cmd->scan_end_arg = cmd->chanlist_len;
 775                 err++;
 776         }
 777
 778         switch (cmd->stop_src) {
 779         case TRIG_COUNT:
 780                 if (!cmd->stop_arg) {
 781                         cmd->stop_arg = 1;
 782                         err++;
 783                 }
 784                 break;
 785         case TRIG_NONE:
 786                 if (cmd->stop_arg != 0) {
 787                         cmd->stop_arg = 0;
 788                         err++;
 789                 }
 790                 break;
 791         default:
 792                 break;
 793         }
 794
 795         if (err)
 796                 return 3;
 797
 798         /* step 4: fix up any arguments */
 799
 800         if (err)
 801                 return 4;
 802
 803         if (!cmd->chanlist)
 804                 return 0;
 805
 806         for (i = 1; i < cmd->chanlist_len; i++) {
 807                 if (CR_CHAN(cmd->chanlist[i]) != i) {
 808                         /*  XXX could support 8 or 16 channels */
 809                         comedi_error(dev,
 810                                      "chanlist must be ch 0 to 31 in order");
 811                         err++;
 812                         break;
 813                 }
 814         }
 815
 816         if (err)
 817                 return 5;
 818
 819         return 0;
 820 }
 821
 822 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
 823                          struct comedi_cmd *cmd)
 824 {
 825         if (priv(dev)->dio_config_output)
 826                 return -EINVAL;
 827         else
 828                 return di_cmd_test(dev, s, cmd);
 829 }
 830
 831 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
 832                                unsigned int offset)
 833 {
 834         writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)],
 835                priv(dev)->hpdi_iobase + offset);
 836 }
 837
 838 static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 839 {
 840         uint32_t bits;
 841         unsigned long flags;
 842         struct comedi_async *async = s->async;
 843         struct comedi_cmd *cmd = &async->cmd;
 844
 845         hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
 846
 847         DEBUG_PRINT("hpdi: in di_cmd\n");
 848
 849         abort_dma(dev, 0);
 850
 851         priv(dev)->dma_desc_index = 0;
 852
 853         /* These register are supposedly unused during chained dma,
 854          * but I have found that left over values from last operation
 855          * occasionally cause problems with transfer of first dma
 856          * block.  Initializing them to zero seems to fix the problem. */
 857         writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
 858         writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
 859         writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
 860         /*  give location of first dma descriptor */
 861         bits =
 862             priv(dev)->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
 863             PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
 864         writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
 865
 866         /*  spinlock for plx dma control/status reg */
 867         spin_lock_irqsave(&dev->spinlock, flags);
 868         /*  enable dma transfer */
 869         writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
 870                priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
 871         spin_unlock_irqrestore(&dev->spinlock, flags);
 872
 873         if (cmd->stop_src == TRIG_COUNT)
 874                 priv(dev)->dio_count = cmd->stop_arg;
 875         else
 876                 priv(dev)->dio_count = 1;
 877
 878         /*  clear over/under run status flags */
 879         writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
 880                priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
 881         /*  enable interrupts */
 882         writel(intr_bit(RX_FULL_INTR),
 883                priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
 884
 885         DEBUG_PRINT("hpdi: starting rx\n");
 886         hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
 887
 888         return 0;
 889 }
 890
 891 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 892 {
 893         if (priv(dev)->dio_config_output)
 894                 return -EINVAL;
 895         else
 896                 return di_cmd(dev, s);
 897 }
 898
 899 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
 900 {
 901         struct comedi_async *async = dev->read_subdev->async;
 902         uint32_t next_transfer_addr;
 903         int j;
 904         int num_samples = 0;
 905         void __iomem *pci_addr_reg;
 906
 907         if (channel)
 908                 pci_addr_reg =
 909                     priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
 910         else
 911                 pci_addr_reg =
 912                     priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
 913
 914         /*  loop until we have read all the full buffers */
 915         j = 0;
 916         for (next_transfer_addr = readl(pci_addr_reg);
 917              (next_transfer_addr <
 918               le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
 919                           pci_start_addr)
 920               || next_transfer_addr >=
 921               le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
 922                           pci_start_addr) + priv(dev)->block_size)
 923              && j < priv(dev)->num_dma_descriptors; j++) {
 924                 /*  transfer data from dma buffer to comedi buffer */
 925                 num_samples = priv(dev)->block_size / sizeof(uint32_t);
 926                 if (async->cmd.stop_src == TRIG_COUNT) {
 927                         if (num_samples > priv(dev)->dio_count)
 928                                 num_samples = priv(dev)->dio_count;
 929                         priv(dev)->dio_count -= num_samples;
 930                 }
 931                 cfc_write_array_to_buffer(dev->read_subdev,
 932                                           priv(dev)->desc_dio_buffer[priv(dev)->
 933                                                                      dma_desc_index],
 934                                           num_samples * sizeof(uint32_t));
 935                 priv(dev)->dma_desc_index++;
 936                 priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors;
 937
 938                 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
 939                             priv(dev)->dma_desc[priv(dev)->dma_desc_index].
 940                             next);
 941                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
 942         }
 943         /*  XXX check for buffer overrun somehow */
 944 }
 945
 946 static irqreturn_t handle_interrupt(int irq, void *d)
 947 {
 948         struct comedi_device *dev = d;
 949         struct comedi_subdevice *s = dev->read_subdev;
 950         struct comedi_async *async = s->async;
 951         uint32_t hpdi_intr_status, hpdi_board_status;
 952         uint32_t plx_status;
 953         uint32_t plx_bits;
 954         uint8_t dma0_status, dma1_status;
 955         unsigned long flags;
 956
 957         if (!dev->attached)
 958                 return IRQ_NONE;
 959
 960         plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
 961         if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
 962                 return IRQ_NONE;
 963
 964         hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
 965         hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
 966
 967         async->events = 0;
 968
 969         if (hpdi_intr_status) {
 970                 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
 971                 writel(hpdi_intr_status,
 972                        priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
 973         }
 974         /*  spin lock makes sure no one else changes plx dma control reg */
 975         spin_lock_irqsave(&dev->spinlock, flags);
 976         dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
 977         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
 978                 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
 979                        priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
 980
 981                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
 982                 if (dma0_status & PLX_DMA_EN_BIT)
 983                         drain_dma_buffers(dev, 0);
 984                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
 985         }
 986         spin_unlock_irqrestore(&dev->spinlock, flags);
 987
 988         /*  spin lock makes sure no one else changes plx dma control reg */
 989         spin_lock_irqsave(&dev->spinlock, flags);
 990         dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
 991         if (plx_status & ICS_DMA1_A) {  /*  XXX *//*  dma chan 1 interrupt */
 992                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
 993                        priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
 994                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
 995
 996                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
 997         }
 998         spin_unlock_irqrestore(&dev->spinlock, flags);
 999
1000         /*  clear possible plx9080 interrupt sources */
1001         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
1002                 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1003                 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1004                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
1005         }
1006
1007         if (hpdi_board_status & RX_OVERRUN_BIT) {
1008                 comedi_error(dev, "rx fifo overrun");
1009                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1010                 DEBUG_PRINT("dma0_status 0x%x\n",
1011                             (int)readb(priv(dev)->plx9080_iobase +
1012                                        PLX_DMA0_CS_REG));
1013         }
1014
1015         if (hpdi_board_status & RX_UNDERRUN_BIT) {
1016                 comedi_error(dev, "rx fifo underrun");
1017                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1018         }
1019
1020         if (priv(dev)->dio_count == 0)
1021                 async->events |= COMEDI_CB_EOA;
1022
1023         DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
1024         DEBUG_PRINT("plx status 0x%x\n", plx_status);
1025         if (async->events)
1026                 DEBUG_PRINT(" events 0x%x\n", async->events);
1027
1028         cfc_handle_events(dev, s);
1029
1030         return IRQ_HANDLED;
1031 }
1032
1033 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1034 {
1035         unsigned long flags;
1036
1037         /*  spinlock for plx dma control/status reg */
1038         spin_lock_irqsave(&dev->spinlock, flags);
1039
1040         plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
1041
1042         spin_unlock_irqrestore(&dev->spinlock, flags);
1043 }
1044
1045 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1046 {
1047         hpdi_writel(dev, 0, BOARD_CONTROL_REG);
1048
1049         writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
1050
1051         abort_dma(dev, 0);
1052
1053         return 0;
1054 }
1055
1056 static struct comedi_driver gsc_hpdi_driver = {
1057         .driver_name    = "gsc_hpdi",
1058         .module         = THIS_MODULE,
1059         .attach         = hpdi_attach,
1060         .detach         = hpdi_detach,
1061 };
1062
1063 static int __devinit gsc_hpdi_pci_probe(struct pci_dev *dev,
1064                                         const struct pci_device_id *ent)
1065 {
1066         return comedi_pci_auto_config(dev, &gsc_hpdi_driver);
1067 }
1068
1069 static void __devexit gsc_hpdi_pci_remove(struct pci_dev *dev)
1070 {
1071         comedi_pci_auto_unconfig(dev);
1072 }
1073
1074 static DEFINE_PCI_DEVICE_TABLE(gsc_hpdi_pci_table) = {
1075         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
1076                     0x2400, 0, 0, 0},
1077         { 0 }
1078 };
1079 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
1080
1081 static struct pci_driver gsc_hpdi_pci_driver = {
1082         .name           = "gsc_hpdi",
1083         .id_table       = gsc_hpdi_pci_table,
1084         .probe          = gsc_hpdi_pci_probe,
1085         .remove         = __devexit_p(gsc_hpdi_pci_remove)
1086 };
1087 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
1088
1089 MODULE_AUTHOR("Comedi http://www.comedi.org");
1090 MODULE_DESCRIPTION("Comedi low-level driver");
1091 MODULE_LICENSE("GPL");