2 comedi/drivers/dmm32at.c
3 Diamond Systems mm32at code for a Comedi driver
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Description: Diamond Systems mm32at driver.
27 Author: Perry J. Piplani <perry.j.piplani@nasa.gov>
28 Updated: Fri Jun 4 09:13:24 CDT 2004
31 This driver is for the Diamond Systems MM-32-AT board
32 http://www.diamondsystems.com/products/diamondmm32at It is being used
33 on serveral projects inside NASA, without problems so far. For analog
34 input commands, TRIG_EXT is not yet supported at all..
36 Configuration Options:
37 comedi_config /dev/comedi0 dmm32at baseaddr,irq
40 #include <linux/interrupt.h>
41 #include "../comedidev.h"
42 #include <linux/ioport.h>
44 #include "comedi_fc.h"
46 /* Board register addresses */
48 #define DMM32AT_MEMSIZE 0x10
50 #define DMM32AT_CONV 0x00
51 #define DMM32AT_AILSB 0x00
52 #define DMM32AT_AUXDOUT 0x01
53 #define DMM32AT_AIMSB 0x01
54 #define DMM32AT_AILOW 0x02
55 #define DMM32AT_AIHIGH 0x03
57 #define DMM32AT_DACLSB 0x04
58 #define DMM32AT_DACSTAT 0x04
59 #define DMM32AT_DACMSB 0x05
61 #define DMM32AT_FIFOCNTRL 0x07
62 #define DMM32AT_FIFOSTAT 0x07
64 #define DMM32AT_CNTRL 0x08
65 #define DMM32AT_AISTAT 0x08
67 #define DMM32AT_INTCLOCK 0x09
69 #define DMM32AT_CNTRDIO 0x0a
71 #define DMM32AT_AICONF 0x0b
72 #define DMM32AT_AIRBACK 0x0b
74 #define DMM32AT_CLK1 0x0d
75 #define DMM32AT_CLK2 0x0e
76 #define DMM32AT_CLKCT 0x0f
78 #define DMM32AT_DIOA 0x0c
79 #define DMM32AT_DIOB 0x0d
80 #define DMM32AT_DIOC 0x0e
81 #define DMM32AT_DIOCONF 0x0f
83 /* Board register values. */
85 /* DMM32AT_DACSTAT 0x04 */
86 #define DMM32AT_DACBUSY 0x80
88 /* DMM32AT_FIFOCNTRL 0x07 */
89 #define DMM32AT_FIFORESET 0x02
90 #define DMM32AT_SCANENABLE 0x04
92 /* DMM32AT_CNTRL 0x08 */
93 #define DMM32AT_RESET 0x20
94 #define DMM32AT_INTRESET 0x08
95 #define DMM32AT_CLKACC 0x00
96 #define DMM32AT_DIOACC 0x01
98 /* DMM32AT_AISTAT 0x08 */
99 #define DMM32AT_STATUS 0x80
101 /* DMM32AT_INTCLOCK 0x09 */
102 #define DMM32AT_ADINT 0x80
103 #define DMM32AT_CLKSEL 0x03
105 /* DMM32AT_CNTRDIO 0x0a */
106 #define DMM32AT_FREQ12 0x80
108 /* DMM32AT_AICONF 0x0b */
109 #define DMM32AT_RANGE_U10 0x0c
110 #define DMM32AT_RANGE_U5 0x0d
111 #define DMM32AT_RANGE_B10 0x08
112 #define DMM32AT_RANGE_B5 0x00
113 #define DMM32AT_SCINT_20 0x00
114 #define DMM32AT_SCINT_15 0x10
115 #define DMM32AT_SCINT_10 0x20
116 #define DMM32AT_SCINT_5 0x30
118 /* DMM32AT_CLKCT 0x0f */
119 #define DMM32AT_CLKCT1 0x56 /* mode3 counter 1 - write low byte only */
120 #define DMM32AT_CLKCT2 0xb6 /* mode3 counter 2 - write high and low byte */
122 /* DMM32AT_DIOCONF 0x0f */
123 #define DMM32AT_DIENABLE 0x80
124 #define DMM32AT_DIRA 0x10
125 #define DMM32AT_DIRB 0x02
126 #define DMM32AT_DIRCL 0x01
127 #define DMM32AT_DIRCH 0x08
129 /* board AI ranges in comedi structure */
130 static const struct comedi_lrange dmm32at_airanges = {
140 /* register values for above ranges */
141 static const unsigned char dmm32at_rangebits[] = {
148 /* only one of these ranges is valid, as set by a jumper on the
149 * board. The application should only use the range set by the jumper
151 static const struct comedi_lrange dmm32at_aoranges = {
161 struct dmm32at_board {
165 struct dmm32at_private {
169 unsigned int ai_scans_left;
171 /* Used for AO readback */
172 unsigned int ao_readback[4];
173 unsigned char dio_config;
177 static int dmm32at_ai_rinsn(struct comedi_device *dev,
178 struct comedi_subdevice *s,
179 struct comedi_insn *insn, unsigned int *data)
183 unsigned char status;
184 unsigned short msb, lsb;
188 /* get the channel and range number */
190 chan = CR_CHAN(insn->chanspec) & (s->n_chan - 1);
191 range = CR_RANGE(insn->chanspec);
193 /* printk("channel=0x%02x, range=%d\n",chan,range); */
195 /* zero scan and fifo control and reset fifo */
196 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL);
198 /* write the ai channel range regs */
199 outb(chan, dev->iobase + DMM32AT_AILOW);
200 outb(chan, dev->iobase + DMM32AT_AIHIGH);
201 /* set the range bits */
202 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF);
204 /* wait for circuit to settle */
205 for (i = 0; i < 40000; i++) {
206 status = inb(dev->iobase + DMM32AT_AIRBACK);
207 if ((status & DMM32AT_STATUS) == 0)
211 printk(KERN_WARNING "dmm32at: timeout\n");
215 /* convert n samples */
216 for (n = 0; n < insn->n; n++) {
217 /* trigger conversion */
218 outb(0xff, dev->iobase + DMM32AT_CONV);
219 /* wait for conversion to end */
220 for (i = 0; i < 40000; i++) {
221 status = inb(dev->iobase + DMM32AT_AISTAT);
222 if ((status & DMM32AT_STATUS) == 0)
226 printk(KERN_WARNING "dmm32at: timeout\n");
231 lsb = inb(dev->iobase + DMM32AT_AILSB);
232 msb = inb(dev->iobase + DMM32AT_AIMSB);
234 /* invert sign bit to make range unsigned, this is an
235 idiosyncrasy of the diamond board, it return
236 conversions as a signed value, i.e. -32768 to
237 32767, flipping the bit and interpreting it as
238 signed gives you a range of 0 to 65535 which is
240 d = ((msb ^ 0x0080) << 8) + lsb;
245 /* return the number of samples read/written */
249 static int dmm32at_ns_to_timer(unsigned int *ns, int round)
255 static int dmm32at_ai_cmdtest(struct comedi_device *dev,
256 struct comedi_subdevice *s,
257 struct comedi_cmd *cmd)
261 int start_chan, gain, i;
263 /* Step 1 : check if triggers are trivially valid */
265 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
266 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
267 TRIG_TIMER /*| TRIG_EXT */);
268 err |= cfc_check_trigger_src(&cmd->convert_src,
269 TRIG_TIMER /*| TRIG_EXT */);
270 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
271 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
276 /* Step 2a : make sure trigger sources are unique */
278 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
279 err |= cfc_check_trigger_is_unique(cmd->convert_src);
280 err |= cfc_check_trigger_is_unique(cmd->stop_src);
282 /* Step 2b : and mutually compatible */
287 /* step 3: make sure arguments are trivially compatible */
289 if (cmd->start_arg != 0) {
293 #define MAX_SCAN_SPEED 1000000 /* in nanoseconds */
294 #define MIN_SCAN_SPEED 1000000000 /* in nanoseconds */
296 if (cmd->scan_begin_src == TRIG_TIMER) {
297 if (cmd->scan_begin_arg < MAX_SCAN_SPEED) {
298 cmd->scan_begin_arg = MAX_SCAN_SPEED;
301 if (cmd->scan_begin_arg > MIN_SCAN_SPEED) {
302 cmd->scan_begin_arg = MIN_SCAN_SPEED;
306 /* external trigger */
307 /* should be level/edge, hi/lo specification here */
308 /* should specify multiple external triggers */
309 if (cmd->scan_begin_arg > 9) {
310 cmd->scan_begin_arg = 9;
314 if (cmd->convert_src == TRIG_TIMER) {
315 if (cmd->convert_arg >= 17500)
316 cmd->convert_arg = 20000;
317 else if (cmd->convert_arg >= 12500)
318 cmd->convert_arg = 15000;
319 else if (cmd->convert_arg >= 7500)
320 cmd->convert_arg = 10000;
322 cmd->convert_arg = 5000;
325 /* external trigger */
327 if (cmd->convert_arg > 9) {
328 cmd->convert_arg = 9;
333 if (cmd->scan_end_arg != cmd->chanlist_len) {
334 cmd->scan_end_arg = cmd->chanlist_len;
337 if (cmd->stop_src == TRIG_COUNT) {
338 if (cmd->stop_arg > 0xfffffff0) {
339 cmd->stop_arg = 0xfffffff0;
342 if (cmd->stop_arg == 0) {
348 if (cmd->stop_arg != 0) {
357 /* step 4: fix up any arguments */
359 if (cmd->scan_begin_src == TRIG_TIMER) {
360 tmp = cmd->scan_begin_arg;
361 dmm32at_ns_to_timer(&cmd->scan_begin_arg,
362 cmd->flags & TRIG_ROUND_MASK);
363 if (tmp != cmd->scan_begin_arg)
366 if (cmd->convert_src == TRIG_TIMER) {
367 tmp = cmd->convert_arg;
368 dmm32at_ns_to_timer(&cmd->convert_arg,
369 cmd->flags & TRIG_ROUND_MASK);
370 if (tmp != cmd->convert_arg)
372 if (cmd->scan_begin_src == TRIG_TIMER &&
373 cmd->scan_begin_arg <
374 cmd->convert_arg * cmd->scan_end_arg) {
375 cmd->scan_begin_arg =
376 cmd->convert_arg * cmd->scan_end_arg;
384 /* step 5 check the channel list, the channel list for this
385 board must be consecutive and gains must be the same */
388 gain = CR_RANGE(cmd->chanlist[0]);
389 start_chan = CR_CHAN(cmd->chanlist[0]);
390 for (i = 1; i < cmd->chanlist_len; i++) {
391 if (CR_CHAN(cmd->chanlist[i]) !=
392 (start_chan + i) % s->n_chan) {
394 "entries in chanlist must be consecutive channels, counting upwards\n");
397 if (CR_RANGE(cmd->chanlist[i]) != gain) {
399 "entries in chanlist must all have the same gain\n");
411 static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec)
413 unsigned char lo1, lo2, hi2;
414 unsigned short both2;
416 /* based on 10mhz clock */
418 both2 = nansec / 20000;
419 hi2 = (both2 & 0xff00) >> 8;
420 lo2 = both2 & 0x00ff;
422 /* set the counter frequency to 10mhz */
423 outb(0, dev->iobase + DMM32AT_CNTRDIO);
425 /* get access to the clock regs */
426 outb(DMM32AT_CLKACC, dev->iobase + DMM32AT_CNTRL);
428 /* write the counter 1 control word and low byte to counter */
429 outb(DMM32AT_CLKCT1, dev->iobase + DMM32AT_CLKCT);
430 outb(lo1, dev->iobase + DMM32AT_CLK1);
432 /* write the counter 2 control word and low byte then to counter */
433 outb(DMM32AT_CLKCT2, dev->iobase + DMM32AT_CLKCT);
434 outb(lo2, dev->iobase + DMM32AT_CLK2);
435 outb(hi2, dev->iobase + DMM32AT_CLK2);
437 /* enable the ai conversion interrupt and the clock to start scans */
438 outb(DMM32AT_ADINT | DMM32AT_CLKSEL, dev->iobase + DMM32AT_INTCLOCK);
441 static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
443 struct dmm32at_private *devpriv = dev->private;
444 struct comedi_cmd *cmd = &s->async->cmd;
446 unsigned char chanlo, chanhi, status;
451 /* get the channel list and range */
452 chanlo = CR_CHAN(cmd->chanlist[0]) & (s->n_chan - 1);
453 chanhi = chanlo + cmd->chanlist_len - 1;
454 if (chanhi >= s->n_chan)
456 range = CR_RANGE(cmd->chanlist[0]);
459 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL);
461 /* set scan enable */
462 outb(DMM32AT_SCANENABLE, dev->iobase + DMM32AT_FIFOCNTRL);
464 /* write the ai channel range regs */
465 outb(chanlo, dev->iobase + DMM32AT_AILOW);
466 outb(chanhi, dev->iobase + DMM32AT_AIHIGH);
468 /* set the range bits */
469 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF);
471 /* reset the interrupt just in case */
472 outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL);
474 if (cmd->stop_src == TRIG_COUNT)
475 devpriv->ai_scans_left = cmd->stop_arg;
476 else { /* TRIG_NONE */
477 devpriv->ai_scans_left = 0xffffffff; /* indicates TRIG_NONE to
481 /* wait for circuit to settle */
482 for (i = 0; i < 40000; i++) {
483 status = inb(dev->iobase + DMM32AT_AIRBACK);
484 if ((status & DMM32AT_STATUS) == 0)
488 printk(KERN_WARNING "dmm32at: timeout\n");
492 if (devpriv->ai_scans_left > 1) {
493 /* start the clock and enable the interrupts */
494 dmm32at_setaitimer(dev, cmd->scan_begin_arg);
496 /* start the interrups and initiate a single scan */
497 outb(DMM32AT_ADINT, dev->iobase + DMM32AT_INTCLOCK);
498 outb(0xff, dev->iobase + DMM32AT_CONV);
501 /* printk("dmmat32 in command\n"); */
503 /* for(i=0;i<cmd->chanlist_len;i++) */
504 /* comedi_buf_put(s->async,i*100); */
506 /* s->async->events |= COMEDI_CB_EOA; */
507 /* comedi_event(dev, s); */
513 static int dmm32at_ai_cancel(struct comedi_device *dev,
514 struct comedi_subdevice *s)
516 struct dmm32at_private *devpriv = dev->private;
518 devpriv->ai_scans_left = 1;
522 static irqreturn_t dmm32at_isr(int irq, void *d)
524 struct comedi_device *dev = d;
525 struct dmm32at_private *devpriv = dev->private;
526 unsigned char intstat;
528 unsigned short msb, lsb;
531 if (!dev->attached) {
532 comedi_error(dev, "spurious interrupt");
536 intstat = inb(dev->iobase + DMM32AT_INTCLOCK);
538 if (intstat & DMM32AT_ADINT) {
539 struct comedi_subdevice *s = dev->read_subdev;
540 struct comedi_cmd *cmd = &s->async->cmd;
542 for (i = 0; i < cmd->chanlist_len; i++) {
544 lsb = inb(dev->iobase + DMM32AT_AILSB);
545 msb = inb(dev->iobase + DMM32AT_AIMSB);
547 /* invert sign bit to make range unsigned */
548 samp = ((msb ^ 0x0080) << 8) + lsb;
549 comedi_buf_put(s->async, samp);
552 if (devpriv->ai_scans_left != 0xffffffff) { /* TRIG_COUNT */
553 devpriv->ai_scans_left--;
554 if (devpriv->ai_scans_left == 0) {
555 /* disable further interrupts and clocks */
556 outb(0x0, dev->iobase + DMM32AT_INTCLOCK);
557 /* set the buffer to be flushed with an EOF */
558 s->async->events |= COMEDI_CB_EOA;
562 /* flush the buffer */
563 comedi_event(dev, s);
566 /* reset the interrupt */
567 outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL);
571 static int dmm32at_ao_winsn(struct comedi_device *dev,
572 struct comedi_subdevice *s,
573 struct comedi_insn *insn, unsigned int *data)
575 struct dmm32at_private *devpriv = dev->private;
577 int chan = CR_CHAN(insn->chanspec);
578 unsigned char hi, lo, status;
580 /* Writing a list of values to an AO channel is probably not
581 * very useful, but that's how the interface is defined. */
582 for (i = 0; i < insn->n; i++) {
584 devpriv->ao_readback[chan] = data[i];
586 /* get the low byte */
587 lo = data[i] & 0x00ff;
588 /* high byte also contains channel number */
589 hi = (data[i] >> 8) + chan * (1 << 6);
590 /* printk("writing 0x%02x 0x%02x\n",hi,lo); */
591 /* write the low and high values to the board */
592 outb(lo, dev->iobase + DMM32AT_DACLSB);
593 outb(hi, dev->iobase + DMM32AT_DACMSB);
595 /* wait for circuit to settle */
596 for (i = 0; i < 40000; i++) {
597 status = inb(dev->iobase + DMM32AT_DACSTAT);
598 if ((status & DMM32AT_DACBUSY) == 0)
602 printk(KERN_WARNING "dmm32at: timeout\n");
605 /* dummy read to update trigger the output */
606 status = inb(dev->iobase + DMM32AT_DACMSB);
610 /* return the number of samples read/written */
614 static int dmm32at_ao_rinsn(struct comedi_device *dev,
615 struct comedi_subdevice *s,
616 struct comedi_insn *insn, unsigned int *data)
618 struct dmm32at_private *devpriv = dev->private;
620 int chan = CR_CHAN(insn->chanspec);
622 for (i = 0; i < insn->n; i++)
623 data[i] = devpriv->ao_readback[chan];
628 static int dmm32at_dio_insn_bits(struct comedi_device *dev,
629 struct comedi_subdevice *s,
630 struct comedi_insn *insn, unsigned int *data)
632 struct dmm32at_private *devpriv = dev->private;
633 unsigned char diobits;
635 /* The insn data is a mask in data[0] and the new data
636 * in data[1], each channel cooresponding to a bit. */
638 s->state &= ~data[0];
639 s->state |= data[0] & data[1];
640 /* Write out the new digital output lines */
641 /* outw(s->state,dev->iobase + DMM32AT_DIO); */
644 /* get access to the DIO regs */
645 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
647 /* if either part of dio is set for output */
648 if (((devpriv->dio_config & DMM32AT_DIRCL) == 0) ||
649 ((devpriv->dio_config & DMM32AT_DIRCH) == 0)) {
650 diobits = (s->state & 0x00ff0000) >> 16;
651 outb(diobits, dev->iobase + DMM32AT_DIOC);
653 if ((devpriv->dio_config & DMM32AT_DIRB) == 0) {
654 diobits = (s->state & 0x0000ff00) >> 8;
655 outb(diobits, dev->iobase + DMM32AT_DIOB);
657 if ((devpriv->dio_config & DMM32AT_DIRA) == 0) {
658 diobits = (s->state & 0x000000ff);
659 outb(diobits, dev->iobase + DMM32AT_DIOA);
662 /* now read the state back in */
663 s->state = inb(dev->iobase + DMM32AT_DIOC);
665 s->state |= inb(dev->iobase + DMM32AT_DIOB);
667 s->state |= inb(dev->iobase + DMM32AT_DIOA);
670 /* on return, data[1] contains the value of the digital
671 * input and output lines. */
672 /* data[1]=inw(dev->iobase + DMM32AT_DIO); */
673 /* or we could just return the software copy of the output values if
674 * it was a purely digital output subdevice */
675 /* data[1]=s->state; */
680 static int dmm32at_dio_insn_config(struct comedi_device *dev,
681 struct comedi_subdevice *s,
682 struct comedi_insn *insn, unsigned int *data)
684 struct dmm32at_private *devpriv = dev->private;
685 unsigned char chanbit;
686 int chan = CR_CHAN(insn->chanspec);
692 chanbit = DMM32AT_DIRA;
694 chanbit = DMM32AT_DIRB;
696 chanbit = DMM32AT_DIRCL;
698 chanbit = DMM32AT_DIRCH;
700 /* The input or output configuration of each digital line is
701 * configured by a special insn_config instruction. chanspec
702 * contains the channel to be changed, and data[0] contains the
703 * value COMEDI_INPUT or COMEDI_OUTPUT. */
705 /* if output clear the bit, otherwise set it */
706 if (data[0] == COMEDI_OUTPUT)
707 devpriv->dio_config &= ~chanbit;
709 devpriv->dio_config |= chanbit;
710 /* get access to the DIO regs */
711 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
712 /* set the DIO's to the new configuration setting */
713 outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF);
718 static int dmm32at_attach(struct comedi_device *dev,
719 struct comedi_devconfig *it)
721 const struct dmm32at_board *board = comedi_board(dev);
722 struct dmm32at_private *devpriv;
724 struct comedi_subdevice *s;
725 unsigned char aihi, ailo, fifostat, aistat, intstat, airback;
726 unsigned long iobase;
729 iobase = it->options[0];
730 irq = it->options[1];
732 printk(KERN_INFO "comedi%d: dmm32at: attaching\n", dev->minor);
733 printk(KERN_DEBUG "dmm32at: probing at address 0x%04lx, irq %u\n",
736 /* register address space */
737 if (!request_region(iobase, DMM32AT_MEMSIZE, board->name)) {
738 printk(KERN_ERR "comedi%d: dmm32at: I/O port conflict\n",
742 dev->iobase = iobase;
744 /* the following just makes sure the board is there and gets
745 it to a known state */
747 /* reset the board */
748 outb(DMM32AT_RESET, dev->iobase + DMM32AT_CNTRL);
750 /* allow a millisecond to reset */
753 /* zero scan and fifo control */
754 outb(0x0, dev->iobase + DMM32AT_FIFOCNTRL);
756 /* zero interrupt and clock control */
757 outb(0x0, dev->iobase + DMM32AT_INTCLOCK);
759 /* write a test channel range, the high 3 bits should drop */
760 outb(0x80, dev->iobase + DMM32AT_AILOW);
761 outb(0xff, dev->iobase + DMM32AT_AIHIGH);
763 /* set the range at 10v unipolar */
764 outb(DMM32AT_RANGE_U10, dev->iobase + DMM32AT_AICONF);
766 /* should take 10 us to settle, here's a hundred */
769 /* read back the values */
770 ailo = inb(dev->iobase + DMM32AT_AILOW);
771 aihi = inb(dev->iobase + DMM32AT_AIHIGH);
772 fifostat = inb(dev->iobase + DMM32AT_FIFOSTAT);
773 aistat = inb(dev->iobase + DMM32AT_AISTAT);
774 intstat = inb(dev->iobase + DMM32AT_INTCLOCK);
775 airback = inb(dev->iobase + DMM32AT_AIRBACK);
777 printk(KERN_DEBUG "dmm32at: lo=0x%02x hi=0x%02x fifostat=0x%02x\n",
778 ailo, aihi, fifostat);
780 "dmm32at: aistat=0x%02x intstat=0x%02x airback=0x%02x\n",
781 aistat, intstat, airback);
783 if ((ailo != 0x00) || (aihi != 0x1f) || (fifostat != 0x80) ||
784 (aistat != 0x60 || (intstat != 0x00) || airback != 0x0c)) {
785 printk(KERN_ERR "dmmat32: board detection failed\n");
789 /* board is there, register interrupt */
791 ret = request_irq(irq, dmm32at_isr, 0, board->name, dev);
793 printk(KERN_ERR "dmm32at: irq conflict\n");
799 dev->board_name = board->name;
801 if (alloc_private(dev, sizeof(*devpriv)) < 0)
803 devpriv = dev->private;
805 ret = comedi_alloc_subdevices(dev, 3);
809 s = &dev->subdevices[0];
810 dev->read_subdev = s;
811 /* analog input subdevice */
812 s->type = COMEDI_SUBD_AI;
813 /* we support single-ended (ground) and differential */
814 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ;
817 s->range_table = &dmm32at_airanges;
818 s->len_chanlist = 32; /* This is the maximum chanlist length that
819 the board can handle */
820 s->insn_read = dmm32at_ai_rinsn;
821 s->do_cmd = dmm32at_ai_cmd;
822 s->do_cmdtest = dmm32at_ai_cmdtest;
823 s->cancel = dmm32at_ai_cancel;
825 s = &dev->subdevices[1];
826 /* analog output subdevice */
827 s->type = COMEDI_SUBD_AO;
828 s->subdev_flags = SDF_WRITABLE;
831 s->range_table = &dmm32at_aoranges;
832 s->insn_write = dmm32at_ao_winsn;
833 s->insn_read = dmm32at_ao_rinsn;
835 s = &dev->subdevices[2];
836 /* digital i/o subdevice */
838 /* get access to the DIO regs */
839 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
840 /* set the DIO's to the defualt input setting */
841 devpriv->dio_config = DMM32AT_DIRA | DMM32AT_DIRB |
842 DMM32AT_DIRCL | DMM32AT_DIRCH | DMM32AT_DIENABLE;
843 outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF);
845 /* set up the subdevice */
846 s->type = COMEDI_SUBD_DIO;
847 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
851 s->range_table = &range_digital;
852 s->insn_bits = dmm32at_dio_insn_bits;
853 s->insn_config = dmm32at_dio_insn_config;
856 printk(KERN_INFO "comedi%d: dmm32at: attached\n", dev->minor);
862 static void dmm32at_detach(struct comedi_device *dev)
865 free_irq(dev->irq, dev);
867 release_region(dev->iobase, DMM32AT_MEMSIZE);
870 static const struct dmm32at_board dmm32at_boards[] = {
876 static struct comedi_driver dmm32at_driver = {
877 .driver_name = "dmm32at",
878 .module = THIS_MODULE,
879 .attach = dmm32at_attach,
880 .detach = dmm32at_detach,
881 .board_name = &dmm32at_boards[0].name,
882 .offset = sizeof(struct dmm32at_board),
883 .num_names = ARRAY_SIZE(dmm32at_boards),
885 module_comedi_driver(dmm32at_driver);
887 MODULE_AUTHOR("Comedi http://www.comedi.org");
888 MODULE_DESCRIPTION("Comedi low-level driver");
889 MODULE_LICENSE("GPL");