Pileus Git - ~andy/linux/blob - drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31
  32     You should have received a copy of the GNU General Public License
  33     along with this program; if not, write to the Free Software
  34     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  35
  36 ************************************************************************/
  37
  38 /*
  39
  40 Driver: cb_pcidas64
  41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
  42 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  43 Status: works
  44 Updated: 2002-10-09
  45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  46   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  47   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  48   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  49   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  50   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  51   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  52   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  53   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  54
  55 Configuration options:
  56    [0] - PCI bus of device (optional)
  57    [1] - PCI slot of device (optional)
  58
  59 These boards may be autocalibrated with the comedi_calibrate utility.
  60
  61 To select the bnc trigger input on the 4020 (instead of the dio input),
  62 specify a nonzero channel in the chanspec.  If you wish to use an external
  63 master clock on the 4020, you may do so by setting the scan_begin_src
  64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  65 to configure the divisor to use for the external clock.
  66
  67 Some devices are not identified because the PCI device IDs are not yet
  68 known. If you have such a board, please file a bug report at
  69 https://bugs.comedi.org.
  70
  71 */
  72
  73 /*
  74
  75 TODO:
  76         make it return error if user attempts an ai command that uses the
  77                 external queue, and an ao command simultaneously
  78         user counter subdevice
  79         there are a number of boards this driver will support when they are
  80                 fully released, but does not yet since the pci device id numbers
  81                 are not yet available.
  82         support prescaled 100khz clock for slow pacing (not available on 6000 series?)
  83         make ao fifo size adjustable like ai fifo
  84 */
  85
  86 #include "../comedidev.h"
  87 #include <linux/delay.h>
  88 #include <linux/interrupt.h>
  89
  90 #include "8253.h"
  91 #include "8255.h"
  92 #include "plx9080.h"
  93 #include "comedi_fc.h"
  94
  95 #undef PCIDAS64_DEBUG           /*  disable debugging code */
  96 /* #define PCIDAS64_DEBUG         enable debugging code */
  97
  98 #ifdef PCIDAS64_DEBUG
  99 #define DEBUG_PRINT(format, args...)  printk(format , ## args)
 100 #else
 101 #define DEBUG_PRINT(format, args...)
 102 #endif
 103
 104 #define TIMER_BASE 25           /*  40MHz master clock */
 105 #define PRESCALED_TIMER_BASE    10000   /*  100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */
 106 #define DMA_BUFFER_SIZE 0x1000
 107
 108 /* maximum value that can be loaded into board's 24-bit counters*/
 109 static const int max_counter_value = 0xffffff;
 110
 111 /* PCI-DAS64xxx base addresses */
 112
 113 /* indices of base address regions */
 114 enum base_address_regions {
 115         PLX9080_BADDRINDEX = 0,
 116         MAIN_BADDRINDEX = 2,
 117         DIO_COUNTER_BADDRINDEX = 3,
 118 };
 119
 120 /* devpriv->main_iobase registers */
 121 enum write_only_registers {
 122         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 123         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 124         DAQ_SYNC_REG = 0xc,
 125         DAQ_ATRIG_LOW_4020_REG = 0xc,
 126         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 127         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 128         CALIBRATION_REG = 0x14,
 129         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,   /*  lower 16 bits of adc sample interval counter */
 130         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,   /*  upper 8 bits of adc sample interval counter */
 131         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,    /*  lower 16 bits of delay interval counter */
 132         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,    /*  upper 8 bits of delay interval counter */
 133         ADC_COUNT_LOWER_REG = 0x1e,     /*  lower 16 bits of hardware conversion/scan counter */
 134         ADC_COUNT_UPPER_REG = 0x20,     /*  upper 8 bits of hardware conversion/scan counter */
 135         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 136         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 137         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 138         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 139         ADC_BUFFER_CLEAR_REG = 0x2a,
 140         ADC_QUEUE_HIGH_REG = 0x2c,      /*  high channel for internal queue, use adc_chan_bits() inline above */
 141         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 142         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 143         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,   /*  lower 16 bits of dac sample interval counter */
 144         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,   /*  upper 8 bits of dac sample interval counter */
 145         DAC_SELECT_REG = 0x60,
 146         DAC_START_REG = 0x64,
 147         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 148 };
 149 static inline unsigned int dac_convert_reg(unsigned int channel)
 150 {
 151         return 0x70 + (2 * (channel & 0x1));
 152 }
 153
 154 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 155 {
 156         return 0x70 + (4 * (channel & 0x1));
 157 }
 158
 159 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 160 {
 161         return 0x72 + (4 * (channel & 0x1));
 162 }
 163
 164 enum read_only_registers {
 165         HW_STATUS_REG = 0x0,    /*  hardware status register, reading this apparently clears pending interrupts as well */
 166         PIPE1_READ_REG = 0x4,
 167         ADC_READ_PNTR_REG = 0x8,
 168         LOWER_XFER_REG = 0x10,
 169         ADC_WRITE_PNTR_REG = 0xc,
 170         PREPOST_REG = 0x14,
 171 };
 172
 173 enum read_write_registers {
 174         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 175         ADC_QUEUE_FIFO_REG = 0x100,     /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 176         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 177         DAC_FIFO_REG = 0x300,   /* dac data fifo, has weird interactions with external channel queue */
 178 };
 179
 180 /* devpriv->dio_counter_iobase registers */
 181 enum dio_counter_registers {
 182         DIO_8255_OFFSET = 0x0,
 183         DO_REG = 0x20,
 184         DI_REG = 0x28,
 185         DIO_DIRECTION_60XX_REG = 0x40,
 186         DIO_DATA_60XX_REG = 0x48,
 187 };
 188
 189 /* bit definitions for write-only registers */
 190
 191 enum intr_enable_contents {
 192         ADC_INTR_SRC_MASK = 0x3,        /*  bits that set adc interrupt source */
 193         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quater full */
 194         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 195         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 196         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence (probably wont use this it's pretty fancy) */
 197         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 198         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done interrupt */
 199         DAC_INTR_SRC_MASK = 0x30,
 200         DAC_INTR_QEMPTY_BITS = 0x0,
 201         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 202         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 203         EN_DAC_DONE_INTR_BIT = 0x80,
 204         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 205         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 206         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 207         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 208         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 209 };
 210
 211 enum hw_config_contents {
 212         MASTER_CLOCK_4020_MASK = 0x3,   /*  bits that specify master clock source for 4020 */
 213         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock for 4020 */
 214         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 215         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 216         EXT_QUEUE_BIT = 0x200,  /*  use external channel/gain queue (more versatile than internal queue) */
 217         SLOW_DAC_BIT = 0x400,   /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 218         HW_CONFIG_DUMMY_BITS = 0x2000,  /*  bit with unknown function yet given as default value in pci-das64 manual */
 219         DMA_CH_SELECT_BIT = 0x8000,     /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 220         FIFO_SIZE_REG = 0x4,    /*  allows adjustment of fifo sizes */
 221         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 222         DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
 223 };
 224 #define DAC_FIFO_SIZE 0x2000
 225
 226 enum daq_atrig_low_4020_contents {
 227         EXT_AGATE_BNC_BIT = 0x8000,     /*  use trig/ext clk bnc input for analog gate signal */
 228         EXT_STOP_TRIG_BNC_BIT = 0x4000, /*  use trig/ext clk bnc input for external stop trigger signal */
 229         EXT_START_TRIG_BNC_BIT = 0x2000,        /*  use trig/ext clk bnc input for external start trigger signal */
 230 };
 231 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 232 {
 233         return threshold & 0xfff;
 234 }
 235
 236 enum adc_control0_contents {
 237         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 238         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 239         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 240         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 241         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 242         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 243         ADC_START_TRIG_SOFT_BITS = 0x10,
 244         ADC_START_TRIG_EXT_BITS = 0x20,
 245         ADC_START_TRIG_ANALOG_BITS = 0x30,
 246         ADC_START_TRIG_MASK = 0x30,
 247         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 248         ADC_EXT_CONV_FALLING_BIT = 0x800,       /*  external pacing uses falling edge */
 249         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,     /*  enable hardware scan counter */
 250         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 251         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 252 };
 253
 254 enum adc_control1_contents {
 255         ADC_QUEUE_CONFIG_BIT = 0x1,     /*  should be set for boards with > 16 channels */
 256         CONVERT_POLARITY_BIT = 0x10,
 257         EOC_POLARITY_BIT = 0x20,
 258         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 259         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 260         RETRIGGER_BIT = 0x800,
 261         ADC_LO_CHANNEL_4020_MASK = 0x300,
 262         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 263         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 264         FOUR_CHANNEL_4020_BITS = 0x2000,        /*  four channel mode for 4020 */
 265         CHANNEL_MODE_4020_MASK = 0x3000,
 266         ADC_MODE_MASK = 0xf000,
 267 };
 268 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 269 {
 270         return (channel & 0x3) << 8;
 271 };
 272
 273 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 274 {
 275         return (channel & 0x3) << 10;
 276 };
 277
 278 static inline uint16_t adc_mode_bits(unsigned int mode)
 279 {
 280         return (mode & 0xf) << 12;
 281 };
 282
 283 enum calibration_contents {
 284         SELECT_8800_BIT = 0x1,
 285         SELECT_8402_64XX_BIT = 0x2,
 286         SELECT_1590_60XX_BIT = 0x2,
 287         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 288         SERIAL_DATA_IN_BIT = 0x80,
 289         SERIAL_CLOCK_BIT = 0x100,
 290         CAL_EN_60XX_BIT = 0x200,        /*  calibration enable for 60xx series */
 291         CAL_GAIN_BIT = 0x800,
 292 };
 293 /* calibration sources for 6025 are:
 294  *  0 : ground
 295  *  1 : 10V
 296  *  2 : 5V
 297  *  3 : 0.5V
 298  *  4 : 0.05V
 299  *  5 : ground
 300  *  6 : dac channel 0
 301  *  7 : dac channel 1
 302  */
 303 static inline uint16_t adc_src_bits(unsigned int source)
 304 {
 305         return (source & 0xf) << 3;
 306 };
 307
 308 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 309 {
 310         return (channel & 0x3) << 8;
 311 };
 312
 313 enum adc_queue_load_contents {
 314         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 315         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 316         ADC_COMMON_BIT = 0x2000,        /*  non-referenced single-ended (common-mode input) */
 317         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 318         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 319 };
 320 static inline uint16_t adc_chan_bits(unsigned int channel)
 321 {
 322         return channel & 0x3f;
 323 };
 324
 325 enum dac_control0_contents {
 326         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 327         DAC_CYCLIC_STOP_BIT = 0x4000,
 328         DAC_WAVEFORM_MODE_BIT = 0x100,
 329         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 330         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 331         WAVEFORM_TRIG_MASK = 0x30,
 332         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 333         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 334         WAVEFORM_TRIG_EXT_BITS = 0x20,
 335         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 336         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 337         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 338         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 339         WAVEFORM_GATE_SELECT_BIT = 0x1,
 340 };
 341
 342 enum dac_control1_contents {
 343         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 344         DAC1_EXT_REF_BIT = 0x200,
 345         DAC0_EXT_REF_BIT = 0x100,
 346         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 347         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 348         DAC_SW_GATE_BIT = 0x20,
 349         DAC1_UNIPOLAR_BIT = 0x8,
 350         DAC0_UNIPOLAR_BIT = 0x2,
 351 };
 352
 353 /* bit definitions for read-only registers */
 354 enum hw_status_contents {
 355         DAC_UNDERRUN_BIT = 0x1,
 356         ADC_OVERRUN_BIT = 0x2,
 357         DAC_ACTIVE_BIT = 0x4,
 358         ADC_ACTIVE_BIT = 0x8,
 359         DAC_INTR_PENDING_BIT = 0x10,
 360         ADC_INTR_PENDING_BIT = 0x20,
 361         DAC_DONE_BIT = 0x40,
 362         ADC_DONE_BIT = 0x80,
 363         EXT_INTR_PENDING_BIT = 0x100,
 364         ADC_STOP_BIT = 0x200,
 365 };
 366 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 367 {
 368         return (hw_status_bits >> 10) & 0x3;
 369 };
 370
 371 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 372 {
 373         return (prepost_bits >> 6) & 0x3;
 374 }
 375
 376 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 377 {
 378         return (prepost_bits >> 12) & 0x3;
 379 }
 380
 381 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 382 {
 383         return (prepost_bits >> 14) & 0x3;
 384 }
 385
 386 /* I2C addresses for 4020 */
 387 enum i2c_addresses {
 388         RANGE_CAL_I2C_ADDR = 0x20,
 389         CALDAC0_I2C_ADDR = 0xc,
 390         CALDAC1_I2C_ADDR = 0xd,
 391 };
 392
 393 enum range_cal_i2c_contents {
 394         ADC_SRC_4020_MASK = 0x70,       /*  bits that set what source the adc converter measures */
 395         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,       /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 396 };
 397 static inline uint8_t adc_src_4020_bits(unsigned int source)
 398 {
 399         return (source << 4) & ADC_SRC_4020_MASK;
 400 };
 401
 402 static inline uint8_t attenuate_bit(unsigned int channel)
 403 {
 404         /*  attenuate channel (+-5V input range) */
 405         return 1 << (channel & 0x3);
 406 };
 407
 408 /* analog input ranges for 64xx boards */
 409 static const struct comedi_lrange ai_ranges_64xx = {
 410         8,
 411         {
 412          BIP_RANGE(10),
 413          BIP_RANGE(5),
 414          BIP_RANGE(2.5),
 415          BIP_RANGE(1.25),
 416          UNI_RANGE(10),
 417          UNI_RANGE(5),
 418          UNI_RANGE(2.5),
 419          UNI_RANGE(1.25)
 420          }
 421 };
 422
 423 /* analog input ranges for 60xx boards */
 424 static const struct comedi_lrange ai_ranges_60xx = {
 425         4,
 426         {
 427          BIP_RANGE(10),
 428          BIP_RANGE(5),
 429          BIP_RANGE(0.5),
 430          BIP_RANGE(0.05),
 431          }
 432 };
 433
 434 /* analog input ranges for 6030, etc boards */
 435 static const struct comedi_lrange ai_ranges_6030 = {
 436         14,
 437         {
 438          BIP_RANGE(10),
 439          BIP_RANGE(5),
 440          BIP_RANGE(2),
 441          BIP_RANGE(1),
 442          BIP_RANGE(0.5),
 443          BIP_RANGE(0.2),
 444          BIP_RANGE(0.1),
 445          UNI_RANGE(10),
 446          UNI_RANGE(5),
 447          UNI_RANGE(2),
 448          UNI_RANGE(1),
 449          UNI_RANGE(0.5),
 450          UNI_RANGE(0.2),
 451          UNI_RANGE(0.1),
 452          }
 453 };
 454
 455 /* analog input ranges for 6052, etc boards */
 456 static const struct comedi_lrange ai_ranges_6052 = {
 457         15,
 458         {
 459          BIP_RANGE(10),
 460          BIP_RANGE(5),
 461          BIP_RANGE(2.5),
 462          BIP_RANGE(1),
 463          BIP_RANGE(0.5),
 464          BIP_RANGE(0.25),
 465          BIP_RANGE(0.1),
 466          BIP_RANGE(0.05),
 467          UNI_RANGE(10),
 468          UNI_RANGE(5),
 469          UNI_RANGE(2),
 470          UNI_RANGE(1),
 471          UNI_RANGE(0.5),
 472          UNI_RANGE(0.2),
 473          UNI_RANGE(0.1),
 474          }
 475 };
 476
 477 /* analog input ranges for 4020 board */
 478 static const struct comedi_lrange ai_ranges_4020 = {
 479         2,
 480         {
 481          BIP_RANGE(5),
 482          BIP_RANGE(1),
 483          }
 484 };
 485
 486 /* analog output ranges */
 487 static const struct comedi_lrange ao_ranges_64xx = {
 488         4,
 489         {
 490          BIP_RANGE(5),
 491          BIP_RANGE(10),
 492          UNI_RANGE(5),
 493          UNI_RANGE(10),
 494          }
 495 };
 496
 497 static const int ao_range_code_64xx[] = {
 498         0x0,
 499         0x1,
 500         0x2,
 501         0x3,
 502 };
 503
 504 static const struct comedi_lrange ao_ranges_60xx = {
 505         1,
 506         {
 507          BIP_RANGE(10),
 508          }
 509 };
 510
 511 static const int ao_range_code_60xx[] = {
 512         0x0,
 513 };
 514
 515 static const struct comedi_lrange ao_ranges_6030 = {
 516         2,
 517         {
 518          BIP_RANGE(10),
 519          UNI_RANGE(10),
 520          }
 521 };
 522
 523 static const int ao_range_code_6030[] = {
 524         0x0,
 525         0x2,
 526 };
 527
 528 static const struct comedi_lrange ao_ranges_4020 = {
 529         2,
 530         {
 531          BIP_RANGE(5),
 532          BIP_RANGE(10),
 533          }
 534 };
 535
 536 static const int ao_range_code_4020[] = {
 537         0x1,
 538         0x0,
 539 };
 540
 541 enum register_layout {
 542         LAYOUT_60XX,
 543         LAYOUT_64XX,
 544         LAYOUT_4020,
 545 };
 546
 547 struct hw_fifo_info {
 548         unsigned int num_segments;
 549         unsigned int max_segment_length;
 550         unsigned int sample_packing_ratio;
 551         uint16_t fifo_size_reg_mask;
 552 };
 553
 554 struct pcidas64_board {
 555         const char *name;
 556         int device_id;          /*  pci device id */
 557         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 558         int ai_bits;            /*  analog input resolution */
 559         int ai_speed;           /*  fastest conversion period in ns */
 560         const struct comedi_lrange *ai_range_table;
 561         int ao_nchan;           /*  number of analog out channels */
 562         int ao_bits;            /*  analog output resolution */
 563         int ao_scan_speed;      /*  analog output speed (for a scan, not conversion) */
 564         const struct comedi_lrange *ao_range_table;
 565         const int *ao_range_code;
 566         const struct hw_fifo_info *const ai_fifo;
 567         enum register_layout layout;    /*  different board families have slightly different registers */
 568         unsigned has_8255:1;
 569 };
 570
 571 static const struct hw_fifo_info ai_fifo_4020 = {
 572         .num_segments = 2,
 573         .max_segment_length = 0x8000,
 574         .sample_packing_ratio = 2,
 575         .fifo_size_reg_mask = 0x7f,
 576 };
 577
 578 static const struct hw_fifo_info ai_fifo_64xx = {
 579         .num_segments = 4,
 580         .max_segment_length = 0x800,
 581         .sample_packing_ratio = 1,
 582         .fifo_size_reg_mask = 0x3f,
 583 };
 584
 585 static const struct hw_fifo_info ai_fifo_60xx = {
 586         .num_segments = 4,
 587         .max_segment_length = 0x800,
 588         .sample_packing_ratio = 1,
 589         .fifo_size_reg_mask = 0x7f,
 590 };
 591
 592 /* maximum number of dma transfers we will chain together into a ring
 593  * (and the maximum number of dma buffers we maintain) */
 594 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 595 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 596 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 597 static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board)
 598 {
 599         if (board->layout == LAYOUT_4020)
 600                 return MAX_AI_DMA_RING_COUNT;
 601         else
 602                 return MIN_AI_DMA_RING_COUNT;
 603 }
 604
 605 static const int bytes_in_sample = 2;
 606
 607 static const struct pcidas64_board pcidas64_boards[] = {
 608         {
 609          .name = "pci-das6402/16",
 610          .device_id = 0x1d,
 611          .ai_se_chans = 64,
 612          .ai_bits = 16,
 613          .ai_speed = 5000,
 614          .ao_nchan = 2,
 615          .ao_bits = 16,
 616          .ao_scan_speed = 10000,
 617          .layout = LAYOUT_64XX,
 618          .ai_range_table = &ai_ranges_64xx,
 619          .ao_range_table = &ao_ranges_64xx,
 620          .ao_range_code = ao_range_code_64xx,
 621          .ai_fifo = &ai_fifo_64xx,
 622          .has_8255 = 1,
 623          },
 624         {
 625          .name = "pci-das6402/12",      /*  XXX check */
 626          .device_id = 0x1e,
 627          .ai_se_chans = 64,
 628          .ai_bits = 12,
 629          .ai_speed = 5000,
 630          .ao_nchan = 2,
 631          .ao_bits = 12,
 632          .ao_scan_speed = 10000,
 633          .layout = LAYOUT_64XX,
 634          .ai_range_table = &ai_ranges_64xx,
 635          .ao_range_table = &ao_ranges_64xx,
 636          .ao_range_code = ao_range_code_64xx,
 637          .ai_fifo = &ai_fifo_64xx,
 638          .has_8255 = 1,
 639          },
 640         {
 641          .name = "pci-das64/m1/16",
 642          .device_id = 0x35,
 643          .ai_se_chans = 64,
 644          .ai_bits = 16,
 645          .ai_speed = 1000,
 646          .ao_nchan = 2,
 647          .ao_bits = 16,
 648          .ao_scan_speed = 10000,
 649          .layout = LAYOUT_64XX,
 650          .ai_range_table = &ai_ranges_64xx,
 651          .ao_range_table = &ao_ranges_64xx,
 652          .ao_range_code = ao_range_code_64xx,
 653          .ai_fifo = &ai_fifo_64xx,
 654          .has_8255 = 1,
 655          },
 656         {
 657          .name = "pci-das64/m2/16",
 658          .device_id = 0x36,
 659          .ai_se_chans = 64,
 660          .ai_bits = 16,
 661          .ai_speed = 500,
 662          .ao_nchan = 2,
 663          .ao_bits = 16,
 664          .ao_scan_speed = 10000,
 665          .layout = LAYOUT_64XX,
 666          .ai_range_table = &ai_ranges_64xx,
 667          .ao_range_table = &ao_ranges_64xx,
 668          .ao_range_code = ao_range_code_64xx,
 669          .ai_fifo = &ai_fifo_64xx,
 670          .has_8255 = 1,
 671          },
 672         {
 673          .name = "pci-das64/m3/16",
 674          .device_id = 0x37,
 675          .ai_se_chans = 64,
 676          .ai_bits = 16,
 677          .ai_speed = 333,
 678          .ao_nchan = 2,
 679          .ao_bits = 16,
 680          .ao_scan_speed = 10000,
 681          .layout = LAYOUT_64XX,
 682          .ai_range_table = &ai_ranges_64xx,
 683          .ao_range_table = &ao_ranges_64xx,
 684          .ao_range_code = ao_range_code_64xx,
 685          .ai_fifo = &ai_fifo_64xx,
 686          .has_8255 = 1,
 687          },
 688         {
 689          .name = "pci-das6013",
 690          .device_id = 0x78,
 691          .ai_se_chans = 16,
 692          .ai_bits = 16,
 693          .ai_speed = 5000,
 694          .ao_nchan = 0,
 695          .ao_bits = 16,
 696          .layout = LAYOUT_60XX,
 697          .ai_range_table = &ai_ranges_60xx,
 698          .ao_range_table = &ao_ranges_60xx,
 699          .ao_range_code = ao_range_code_60xx,
 700          .ai_fifo = &ai_fifo_60xx,
 701          .has_8255 = 0,
 702          },
 703         {
 704          .name = "pci-das6014",
 705          .device_id = 0x79,
 706          .ai_se_chans = 16,
 707          .ai_bits = 16,
 708          .ai_speed = 5000,
 709          .ao_nchan = 2,
 710          .ao_bits = 16,
 711          .ao_scan_speed = 100000,
 712          .layout = LAYOUT_60XX,
 713          .ai_range_table = &ai_ranges_60xx,
 714          .ao_range_table = &ao_ranges_60xx,
 715          .ao_range_code = ao_range_code_60xx,
 716          .ai_fifo = &ai_fifo_60xx,
 717          .has_8255 = 0,
 718          },
 719         {
 720          .name = "pci-das6023",
 721          .device_id = 0x5d,
 722          .ai_se_chans = 16,
 723          .ai_bits = 12,
 724          .ai_speed = 5000,
 725          .ao_nchan = 0,
 726          .ao_scan_speed = 100000,
 727          .layout = LAYOUT_60XX,
 728          .ai_range_table = &ai_ranges_60xx,
 729          .ao_range_table = &ao_ranges_60xx,
 730          .ao_range_code = ao_range_code_60xx,
 731          .ai_fifo = &ai_fifo_60xx,
 732          .has_8255 = 1,
 733          },
 734         {
 735          .name = "pci-das6025",
 736          .device_id = 0x5e,
 737          .ai_se_chans = 16,
 738          .ai_bits = 12,
 739          .ai_speed = 5000,
 740          .ao_nchan = 2,
 741          .ao_bits = 12,
 742          .ao_scan_speed = 100000,
 743          .layout = LAYOUT_60XX,
 744          .ai_range_table = &ai_ranges_60xx,
 745          .ao_range_table = &ao_ranges_60xx,
 746          .ao_range_code = ao_range_code_60xx,
 747          .ai_fifo = &ai_fifo_60xx,
 748          .has_8255 = 1,
 749          },
 750         {
 751          .name = "pci-das6030",
 752          .device_id = 0x5f,
 753          .ai_se_chans = 16,
 754          .ai_bits = 16,
 755          .ai_speed = 10000,
 756          .ao_nchan = 2,
 757          .ao_bits = 16,
 758          .ao_scan_speed = 10000,
 759          .layout = LAYOUT_60XX,
 760          .ai_range_table = &ai_ranges_6030,
 761          .ao_range_table = &ao_ranges_6030,
 762          .ao_range_code = ao_range_code_6030,
 763          .ai_fifo = &ai_fifo_60xx,
 764          .has_8255 = 0,
 765          },
 766         {
 767          .name = "pci-das6031",
 768          .device_id = 0x60,
 769          .ai_se_chans = 64,
 770          .ai_bits = 16,
 771          .ai_speed = 10000,
 772          .ao_nchan = 2,
 773          .ao_bits = 16,
 774          .ao_scan_speed = 10000,
 775          .layout = LAYOUT_60XX,
 776          .ai_range_table = &ai_ranges_6030,
 777          .ao_range_table = &ao_ranges_6030,
 778          .ao_range_code = ao_range_code_6030,
 779          .ai_fifo = &ai_fifo_60xx,
 780          .has_8255 = 0,
 781          },
 782         {
 783          .name = "pci-das6032",
 784          .device_id = 0x61,
 785          .ai_se_chans = 16,
 786          .ai_bits = 16,
 787          .ai_speed = 10000,
 788          .ao_nchan = 0,
 789          .layout = LAYOUT_60XX,
 790          .ai_range_table = &ai_ranges_6030,
 791          .ai_fifo = &ai_fifo_60xx,
 792          .has_8255 = 0,
 793          },
 794         {
 795          .name = "pci-das6033",
 796          .device_id = 0x62,
 797          .ai_se_chans = 64,
 798          .ai_bits = 16,
 799          .ai_speed = 10000,
 800          .ao_nchan = 0,
 801          .layout = LAYOUT_60XX,
 802          .ai_range_table = &ai_ranges_6030,
 803          .ai_fifo = &ai_fifo_60xx,
 804          .has_8255 = 0,
 805          },
 806         {
 807          .name = "pci-das6034",
 808          .device_id = 0x63,
 809          .ai_se_chans = 16,
 810          .ai_bits = 16,
 811          .ai_speed = 5000,
 812          .ao_nchan = 0,
 813          .ao_scan_speed = 0,
 814          .layout = LAYOUT_60XX,
 815          .ai_range_table = &ai_ranges_60xx,
 816          .ai_fifo = &ai_fifo_60xx,
 817          .has_8255 = 0,
 818          },
 819         {
 820          .name = "pci-das6035",
 821          .device_id = 0x64,
 822          .ai_se_chans = 16,
 823          .ai_bits = 16,
 824          .ai_speed = 5000,
 825          .ao_nchan = 2,
 826          .ao_bits = 12,
 827          .ao_scan_speed = 100000,
 828          .layout = LAYOUT_60XX,
 829          .ai_range_table = &ai_ranges_60xx,
 830          .ao_range_table = &ao_ranges_60xx,
 831          .ao_range_code = ao_range_code_60xx,
 832          .ai_fifo = &ai_fifo_60xx,
 833          .has_8255 = 0,
 834          },
 835         {
 836          .name = "pci-das6036",
 837          .device_id = 0x6f,
 838          .ai_se_chans = 16,
 839          .ai_bits = 16,
 840          .ai_speed = 5000,
 841          .ao_nchan = 2,
 842          .ao_bits = 16,
 843          .ao_scan_speed = 100000,
 844          .layout = LAYOUT_60XX,
 845          .ai_range_table = &ai_ranges_60xx,
 846          .ao_range_table = &ao_ranges_60xx,
 847          .ao_range_code = ao_range_code_60xx,
 848          .ai_fifo = &ai_fifo_60xx,
 849          .has_8255 = 0,
 850          },
 851         {
 852          .name = "pci-das6040",
 853          .device_id = 0x65,
 854          .ai_se_chans = 16,
 855          .ai_bits = 12,
 856          .ai_speed = 2000,
 857          .ao_nchan = 2,
 858          .ao_bits = 12,
 859          .ao_scan_speed = 1000,
 860          .layout = LAYOUT_60XX,
 861          .ai_range_table = &ai_ranges_6052,
 862          .ao_range_table = &ao_ranges_6030,
 863          .ao_range_code = ao_range_code_6030,
 864          .ai_fifo = &ai_fifo_60xx,
 865          .has_8255 = 0,
 866          },
 867         {
 868          .name = "pci-das6052",
 869          .device_id = 0x66,
 870          .ai_se_chans = 16,
 871          .ai_bits = 16,
 872          .ai_speed = 3333,
 873          .ao_nchan = 2,
 874          .ao_bits = 16,
 875          .ao_scan_speed = 3333,
 876          .layout = LAYOUT_60XX,
 877          .ai_range_table = &ai_ranges_6052,
 878          .ao_range_table = &ao_ranges_6030,
 879          .ao_range_code = ao_range_code_6030,
 880          .ai_fifo = &ai_fifo_60xx,
 881          .has_8255 = 0,
 882          },
 883         {
 884          .name = "pci-das6070",
 885          .device_id = 0x67,
 886          .ai_se_chans = 16,
 887          .ai_bits = 12,
 888          .ai_speed = 800,
 889          .ao_nchan = 2,
 890          .ao_bits = 12,
 891          .ao_scan_speed = 1000,
 892          .layout = LAYOUT_60XX,
 893          .ai_range_table = &ai_ranges_6052,
 894          .ao_range_table = &ao_ranges_6030,
 895          .ao_range_code = ao_range_code_6030,
 896          .ai_fifo = &ai_fifo_60xx,
 897          .has_8255 = 0,
 898          },
 899         {
 900          .name = "pci-das6071",
 901          .device_id = 0x68,
 902          .ai_se_chans = 64,
 903          .ai_bits = 12,
 904          .ai_speed = 800,
 905          .ao_nchan = 2,
 906          .ao_bits = 12,
 907          .ao_scan_speed = 1000,
 908          .layout = LAYOUT_60XX,
 909          .ai_range_table = &ai_ranges_6052,
 910          .ao_range_table = &ao_ranges_6030,
 911          .ao_range_code = ao_range_code_6030,
 912          .ai_fifo = &ai_fifo_60xx,
 913          .has_8255 = 0,
 914          },
 915         {
 916          .name = "pci-das4020/12",
 917          .device_id = 0x52,
 918          .ai_se_chans = 4,
 919          .ai_bits = 12,
 920          .ai_speed = 50,
 921          .ao_bits = 12,
 922          .ao_nchan = 2,
 923          .ao_scan_speed = 0,    /*  no hardware pacing on ao */
 924          .layout = LAYOUT_4020,
 925          .ai_range_table = &ai_ranges_4020,
 926          .ao_range_table = &ao_ranges_4020,
 927          .ao_range_code = ao_range_code_4020,
 928          .ai_fifo = &ai_fifo_4020,
 929          .has_8255 = 1,
 930          },
 931 #if 0
 932         {
 933          .name = "pci-das6402/16/jr",
 934          .device_id = 0         /*  XXX, */
 935          .ai_se_chans = 64,
 936          .ai_bits = 16,
 937          .ai_speed = 5000,
 938          .ao_nchan = 0,
 939          .ao_scan_speed = 10000,
 940          .layout = LAYOUT_64XX,
 941          .ai_range_table = &ai_ranges_64xx,
 942          .ai_fifo = ai_fifo_64xx,
 943          .has_8255 = 1,
 944          },
 945         {
 946          .name = "pci-das64/m1/16/jr",
 947          .device_id = 0         /*  XXX, */
 948          .ai_se_chans = 64,
 949          .ai_bits = 16,
 950          .ai_speed = 1000,
 951          .ao_nchan = 0,
 952          .ao_scan_speed = 10000,
 953          .layout = LAYOUT_64XX,
 954          .ai_range_table = &ai_ranges_64xx,
 955          .ai_fifo = ai_fifo_64xx,
 956          .has_8255 = 1,
 957          },
 958         {
 959          .name = "pci-das64/m2/16/jr",
 960          .device_id = 0         /*  XXX, */
 961          .ai_se_chans = 64,
 962          .ai_bits = 16,
 963          .ai_speed = 500,
 964          .ao_nchan = 0,
 965          .ao_scan_speed = 10000,
 966          .layout = LAYOUT_64XX,
 967          .ai_range_table = &ai_ranges_64xx,
 968          .ai_fifo = ai_fifo_64xx,
 969          .has_8255 = 1,
 970          },
 971         {
 972          .name = "pci-das64/m3/16/jr",
 973          .device_id = 0         /*  XXX, */
 974          .ai_se_chans = 64,
 975          .ai_bits = 16,
 976          .ai_speed = 333,
 977          .ao_nchan = 0,
 978          .ao_scan_speed = 10000,
 979          .layout = LAYOUT_64XX,
 980          .ai_range_table = &ai_ranges_64xx,
 981          .ai_fifo = ai_fifo_64xx,
 982          .has_8255 = 1,
 983          },
 984         {
 985          .name = "pci-das64/m1/14",
 986          .device_id = 0,        /*  XXX */
 987          .ai_se_chans = 64,
 988          .ai_bits = 14,
 989          .ai_speed = 1000,
 990          .ao_nchan = 2,
 991          .ao_scan_speed = 10000,
 992          .layout = LAYOUT_64XX,
 993          .ai_range_table = &ai_ranges_64xx,
 994          .ai_fifo = ai_fifo_64xx,
 995          .has_8255 = 1,
 996          },
 997         {
 998          .name = "pci-das64/m2/14",
 999          .device_id = 0,        /*  XXX */
1000          .ai_se_chans = 64,
1001          .ai_bits = 14,
1002          .ai_speed = 500,
1003          .ao_nchan = 2,
1004          .ao_scan_speed = 10000,
1005          .layout = LAYOUT_64XX,
1006          .ai_range_table = &ai_ranges_64xx,
1007          .ai_fifo = ai_fifo_64xx,
1008          .has_8255 = 1,
1009          },
1010         {
1011          .name = "pci-das64/m3/14",
1012          .device_id = 0,        /*  XXX */
1013          .ai_se_chans = 64,
1014          .ai_bits = 14,
1015          .ai_speed = 333,
1016          .ao_nchan = 2,
1017          .ao_scan_speed = 10000,
1018          .layout = LAYOUT_64XX,
1019          .ai_range_table = &ai_ranges_64xx,
1020          .ai_fifo = ai_fifo_64xx,
1021          .has_8255 = 1,
1022          },
1023 #endif
1024 };
1025
1026 static inline struct pcidas64_board *board(const struct comedi_device *dev)
1027 {
1028         return (struct pcidas64_board *)dev->board_ptr;
1029 }
1030
1031 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1032                                               int use_differential)
1033 {
1034         if ((board(dev)->layout == LAYOUT_64XX && !use_differential) ||
1035             (board(dev)->layout == LAYOUT_60XX && use_differential))
1036                 return ADC_SE_DIFF_BIT;
1037         else
1038                 return 0;
1039 };
1040
1041 struct ext_clock_info {
1042         unsigned int divisor;   /*  master clock divisor to use for scans with external master clock */
1043         unsigned int chanspec;  /*  chanspec for master clock input when used as scan begin src */
1044 };
1045
1046 /* this structure is for data unique to this hardware driver. */
1047 struct pcidas64_private {
1048         /*  base addresses (physical) */
1049         resource_size_t plx9080_phys_iobase;
1050         resource_size_t main_phys_iobase;
1051         resource_size_t dio_counter_phys_iobase;
1052         /*  base addresses (ioremapped) */
1053         void __iomem *plx9080_iobase;
1054         void __iomem *main_iobase;
1055         void __iomem *dio_counter_iobase;
1056         /*  local address (used by dma controller) */
1057         uint32_t local0_iobase;
1058         uint32_t local1_iobase;
1059         volatile unsigned int ai_count; /*  number of analog input samples remaining */
1060         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];     /*  dma buffers for analog input */
1061         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];   /*  physical addresses of ai dma buffers */
1062         struct plx_dma_desc *ai_dma_desc;       /*  array of ai dma descriptors read by plx9080, allocated to get proper alignment */
1063         dma_addr_t ai_dma_desc_bus_addr;        /*  physical address of ai dma descriptor array */
1064         volatile unsigned int ai_dma_index;     /*  index of the ai dma descriptor/buffer that is currently being used */
1065         uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /*  dma buffers for analog output */
1066         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];       /*  physical addresses of ao dma buffers */
1067         struct plx_dma_desc *ao_dma_desc;
1068         dma_addr_t ao_dma_desc_bus_addr;
1069         volatile unsigned int ao_dma_index;     /*  keeps track of buffer where the next ao sample should go */
1070         volatile unsigned long ao_count;        /*  number of analog output samples remaining */
1071         volatile unsigned int ao_value[2];      /*  remember what the analog outputs are set to, to allow readback */
1072         unsigned int hw_revision;       /*  stc chip hardware revision number */
1073         volatile unsigned int intr_enable_bits; /*  last bits sent to INTR_ENABLE_REG register */
1074         volatile uint16_t adc_control1_bits;    /*  last bits sent to ADC_CONTROL1_REG register */
1075         volatile uint16_t fifo_size_bits;       /*  last bits sent to FIFO_SIZE_REG register */
1076         volatile uint16_t hw_config_bits;       /*  last bits sent to HW_CONFIG_REG register */
1077         volatile uint16_t dac_control1_bits;
1078         volatile uint32_t plx_control_bits;     /*  last bits written to plx9080 control register */
1079         volatile uint32_t plx_intcsr_bits;      /*  last bits written to plx interrupt control and status register */
1080         volatile int calibration_source;        /*  index of calibration source readable through ai ch0 */
1081         volatile uint8_t i2c_cal_range_bits;    /*  bits written to i2c calibration/range register */
1082         volatile unsigned int ext_trig_falling; /*  configure digital triggers to trigger on falling edge */
1083         /*  states of various devices stored to enable read-back */
1084         unsigned int ad8402_state[2];
1085         unsigned int caldac_state[8];
1086         volatile short ai_cmd_running;
1087         unsigned int ai_fifo_segment_length;
1088         struct ext_clock_info ext_clock;
1089         short ao_bounce_buffer[DAC_FIFO_SIZE];
1090 };
1091
1092 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1093                     struct comedi_insn *insn, unsigned int *data);
1094 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1095                           struct comedi_insn *insn, unsigned int *data);
1096 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1097                     struct comedi_insn *insn, unsigned int *data);
1098 static int ao_readback_insn(struct comedi_device *dev,
1099                             struct comedi_subdevice *s,
1100                             struct comedi_insn *insn, unsigned int *data);
1101 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1102 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1103                       struct comedi_cmd *cmd);
1104 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1105 static int ao_inttrig(struct comedi_device *dev,
1106                       struct comedi_subdevice *subdev, unsigned int trig_num);
1107 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1108                       struct comedi_cmd *cmd);
1109 static irqreturn_t handle_interrupt(int irq, void *d);
1110 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1111 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1112 static int dio_callback(int dir, int port, int data, unsigned long arg);
1113 static int dio_callback_4020(int dir, int port, int data, unsigned long arg);
1114 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
1115                     struct comedi_insn *insn, unsigned int *data);
1116 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1117                     struct comedi_insn *insn, unsigned int *data);
1118 static int dio_60xx_config_insn(struct comedi_device *dev,
1119                                 struct comedi_subdevice *s,
1120                                 struct comedi_insn *insn, unsigned int *data);
1121 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1122                           struct comedi_insn *insn, unsigned int *data);
1123 static int calib_read_insn(struct comedi_device *dev,
1124                            struct comedi_subdevice *s, struct comedi_insn *insn,
1125                            unsigned int *data);
1126 static int calib_write_insn(struct comedi_device *dev,
1127                             struct comedi_subdevice *s,
1128                             struct comedi_insn *insn, unsigned int *data);
1129 static int ad8402_read_insn(struct comedi_device *dev,
1130                             struct comedi_subdevice *s,
1131                             struct comedi_insn *insn, unsigned int *data);
1132 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
1133                          unsigned int value);
1134 static int ad8402_write_insn(struct comedi_device *dev,
1135                              struct comedi_subdevice *s,
1136                              struct comedi_insn *insn, unsigned int *data);
1137 static int eeprom_read_insn(struct comedi_device *dev,
1138                             struct comedi_subdevice *s,
1139                             struct comedi_insn *insn, unsigned int *data);
1140 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
1141 static unsigned int get_divisor(unsigned int ns, unsigned int flags);
1142 static void i2c_write(struct comedi_device *dev, unsigned int address,
1143                       const uint8_t *data, unsigned int length);
1144 static void caldac_write(struct comedi_device *dev, unsigned int channel,
1145                          unsigned int value);
1146 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
1147                              uint8_t value);
1148 /* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */
1149 static int caldac_i2c_write(struct comedi_device *dev,
1150                             unsigned int caldac_channel, unsigned int value);
1151 static void abort_dma(struct comedi_device *dev, unsigned int channel);
1152 static void disable_plx_interrupts(struct comedi_device *dev);
1153 static int set_ai_fifo_size(struct comedi_device *dev,
1154                             unsigned int num_samples);
1155 static unsigned int ai_fifo_size(struct comedi_device *dev);
1156 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1157                                       unsigned int num_entries);
1158 static void disable_ai_pacing(struct comedi_device *dev);
1159 static void disable_ai_interrupts(struct comedi_device *dev);
1160 static void enable_ai_interrupts(struct comedi_device *dev,
1161                                  const struct comedi_cmd *cmd);
1162 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags);
1163 static void load_ao_dma(struct comedi_device *dev,
1164                         const struct comedi_cmd *cmd);
1165
1166 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1167                                        unsigned int range_index)
1168 {
1169         const struct comedi_krange *range =
1170             &board(dev)->ai_range_table->range[range_index];
1171         unsigned int bits = 0;
1172
1173         switch (range->max) {
1174         case 10000000:
1175                 bits = 0x000;
1176                 break;
1177         case 5000000:
1178                 bits = 0x100;
1179                 break;
1180         case 2000000:
1181         case 2500000:
1182                 bits = 0x200;
1183                 break;
1184         case 1000000:
1185         case 1250000:
1186                 bits = 0x300;
1187                 break;
1188         case 500000:
1189                 bits = 0x400;
1190                 break;
1191         case 200000:
1192         case 250000:
1193                 bits = 0x500;
1194                 break;
1195         case 100000:
1196                 bits = 0x600;
1197                 break;
1198         case 50000:
1199                 bits = 0x700;
1200                 break;
1201         default:
1202                 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1203                 break;
1204         }
1205         if (range->min == 0)
1206                 bits += 0x900;
1207         return bits;
1208 }
1209
1210 static unsigned int hw_revision(const struct comedi_device *dev,
1211                                 uint16_t hw_status_bits)
1212 {
1213         if (board(dev)->layout == LAYOUT_4020)
1214                 return (hw_status_bits >> 13) & 0x7;
1215
1216         return (hw_status_bits >> 12) & 0xf;
1217 }
1218
1219 static void set_dac_range_bits(struct comedi_device *dev,
1220                                volatile uint16_t *bits, unsigned int channel,
1221                                unsigned int range)
1222 {
1223         unsigned int code = board(dev)->ao_range_code[range];
1224
1225         if (channel > 1)
1226                 comedi_error(dev, "bug! bad channel?");
1227         if (code & ~0x3)
1228                 comedi_error(dev, "bug! bad range code?");
1229
1230         *bits &= ~(0x3 << (2 * channel));
1231         *bits |= code << (2 * channel);
1232 };
1233
1234 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1235 {
1236         return board->ao_nchan && board->layout != LAYOUT_4020;
1237 }
1238
1239 /* initialize plx9080 chip */
1240 static void init_plx9080(struct comedi_device *dev)
1241 {
1242         struct pcidas64_private *devpriv = dev->private;
1243         uint32_t bits;
1244         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1245
1246         devpriv->plx_control_bits =
1247             readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1248
1249         /*  plx9080 dump */
1250         DEBUG_PRINT(" plx interrupt status 0x%x\n",
1251                     readl(plx_iobase + PLX_INTRCS_REG));
1252         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1253         DEBUG_PRINT(" plx control reg 0x%x\n", devpriv->plx_control_bits);
1254         DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1255                     readl(plx_iobase + PLX_MARB_REG));
1256         DEBUG_PRINT(" plx region0 reg 0x%x\n",
1257                     readl(plx_iobase + PLX_REGION0_REG));
1258         DEBUG_PRINT(" plx region1 reg 0x%x\n",
1259                     readl(plx_iobase + PLX_REGION1_REG));
1260
1261         DEBUG_PRINT(" plx revision 0x%x\n",
1262                     readl(plx_iobase + PLX_REVISION_REG));
1263         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1264                     readl(plx_iobase + PLX_DMA0_MODE_REG));
1265         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1266                     readl(plx_iobase + PLX_DMA1_MODE_REG));
1267         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1268                     readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1269         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1270                     readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1271         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1272                     readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1273         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1274                     readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1275         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1276                     readb(plx_iobase + PLX_DMA0_CS_REG));
1277         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1278                     readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1279         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1280
1281 #ifdef __BIG_ENDIAN
1282         bits = BIGEND_DMA0 | BIGEND_DMA1;
1283 #else
1284         bits = 0;
1285 #endif
1286         writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1287
1288         disable_plx_interrupts(dev);
1289
1290         abort_dma(dev, 0);
1291         abort_dma(dev, 1);
1292
1293         /*  configure dma0 mode */
1294         bits = 0;
1295         /*  enable ready input, not sure if this is necessary */
1296         bits |= PLX_DMA_EN_READYIN_BIT;
1297         /*  enable bterm, not sure if this is necessary */
1298         bits |= PLX_EN_BTERM_BIT;
1299         /*  enable dma chaining */
1300         bits |= PLX_EN_CHAIN_BIT;
1301         /*  enable interrupt on dma done (probably don't need this, since chain never finishes) */
1302         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1303         /*  don't increment local address during transfers (we are transferring from a fixed fifo register) */
1304         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1305         /*  route dma interrupt to pci bus */
1306         bits |= PLX_DMA_INTR_PCI_BIT;
1307         /*  enable demand mode */
1308         bits |= PLX_DEMAND_MODE_BIT;
1309         /*  enable local burst mode */
1310         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1311         /*  4020 uses 32 bit dma */
1312         if (board(dev)->layout == LAYOUT_4020) {
1313                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1314         } else {                /*  localspace0 bus is 16 bits wide */
1315                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1316         }
1317         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1318         if (ao_cmd_is_supported(board(dev)))
1319                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1320
1321         /*  enable interrupts on plx 9080 */
1322         devpriv->plx_intcsr_bits |=
1323             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1324             ICS_DMA0_E | ICS_DMA1_E;
1325         writel(devpriv->plx_intcsr_bits,
1326                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1327 }
1328
1329 /* Allocate and initialize the subdevice structures.
1330  */
1331 static int setup_subdevices(struct comedi_device *dev)
1332 {
1333         struct pcidas64_private *devpriv = dev->private;
1334         struct comedi_subdevice *s;
1335         void __iomem *dio_8255_iobase;
1336         int i;
1337         int ret;
1338
1339         ret = comedi_alloc_subdevices(dev, 10);
1340         if (ret)
1341                 return ret;
1342
1343         s = &dev->subdevices[0];
1344         /* analog input subdevice */
1345         dev->read_subdev = s;
1346         s->type = COMEDI_SUBD_AI;
1347         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
1348         if (board(dev)->layout == LAYOUT_60XX)
1349                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
1350         else if (board(dev)->layout == LAYOUT_64XX)
1351                 s->subdev_flags |= SDF_DIFF;
1352         /* XXX Number of inputs in differential mode is ignored */
1353         s->n_chan = board(dev)->ai_se_chans;
1354         s->len_chanlist = 0x2000;
1355         s->maxdata = (1 << board(dev)->ai_bits) - 1;
1356         s->range_table = board(dev)->ai_range_table;
1357         s->insn_read = ai_rinsn;
1358         s->insn_config = ai_config_insn;
1359         s->do_cmd = ai_cmd;
1360         s->do_cmdtest = ai_cmdtest;
1361         s->cancel = ai_cancel;
1362         if (board(dev)->layout == LAYOUT_4020) {
1363                 uint8_t data;
1364                 /*  set adc to read from inputs (not internal calibration sources) */
1365                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
1366                 /*  set channels to +-5 volt input ranges */
1367                 for (i = 0; i < s->n_chan; i++)
1368                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
1369                 data = devpriv->i2c_cal_range_bits;
1370                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
1371         }
1372
1373         /* analog output subdevice */
1374         s = &dev->subdevices[1];
1375         if (board(dev)->ao_nchan) {
1376                 s->type = COMEDI_SUBD_AO;
1377                 s->subdev_flags =
1378                     SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE;
1379                 s->n_chan = board(dev)->ao_nchan;
1380                 s->maxdata = (1 << board(dev)->ao_bits) - 1;
1381                 s->range_table = board(dev)->ao_range_table;
1382                 s->insn_read = ao_readback_insn;
1383                 s->insn_write = ao_winsn;
1384                 if (ao_cmd_is_supported(board(dev))) {
1385                         dev->write_subdev = s;
1386                         s->do_cmdtest = ao_cmdtest;
1387                         s->do_cmd = ao_cmd;
1388                         s->len_chanlist = board(dev)->ao_nchan;
1389                         s->cancel = ao_cancel;
1390                 }
1391         } else {
1392                 s->type = COMEDI_SUBD_UNUSED;
1393         }
1394
1395         /*  digital input */
1396         s = &dev->subdevices[2];
1397         if (board(dev)->layout == LAYOUT_64XX) {
1398                 s->type = COMEDI_SUBD_DI;
1399                 s->subdev_flags = SDF_READABLE;
1400                 s->n_chan = 4;
1401                 s->maxdata = 1;
1402                 s->range_table = &range_digital;
1403                 s->insn_bits = di_rbits;
1404         } else
1405                 s->type = COMEDI_SUBD_UNUSED;
1406
1407         /*  digital output */
1408         if (board(dev)->layout == LAYOUT_64XX) {
1409                 s = &dev->subdevices[3];
1410                 s->type = COMEDI_SUBD_DO;
1411                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1412                 s->n_chan = 4;
1413                 s->maxdata = 1;
1414                 s->range_table = &range_digital;
1415                 s->insn_bits = do_wbits;
1416         } else
1417                 s->type = COMEDI_SUBD_UNUSED;
1418
1419         /* 8255 */
1420         s = &dev->subdevices[4];
1421         if (board(dev)->has_8255) {
1422                 if (board(dev)->layout == LAYOUT_4020) {
1423                         dio_8255_iobase =
1424                             devpriv->main_iobase + I8255_4020_REG;
1425                         subdev_8255_init(dev, s, dio_callback_4020,
1426                                          (unsigned long)dio_8255_iobase);
1427                 } else {
1428                         dio_8255_iobase =
1429                             devpriv->dio_counter_iobase + DIO_8255_OFFSET;
1430                         subdev_8255_init(dev, s, dio_callback,
1431                                          (unsigned long)dio_8255_iobase);
1432                 }
1433         } else
1434                 s->type = COMEDI_SUBD_UNUSED;
1435
1436         /*  8 channel dio for 60xx */
1437         s = &dev->subdevices[5];
1438         if (board(dev)->layout == LAYOUT_60XX) {
1439                 s->type = COMEDI_SUBD_DIO;
1440                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1441                 s->n_chan = 8;
1442                 s->maxdata = 1;
1443                 s->range_table = &range_digital;
1444                 s->insn_config = dio_60xx_config_insn;
1445                 s->insn_bits = dio_60xx_wbits;
1446         } else
1447                 s->type = COMEDI_SUBD_UNUSED;
1448
1449         /*  caldac */
1450         s = &dev->subdevices[6];
1451         s->type = COMEDI_SUBD_CALIB;
1452         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1453         s->n_chan = 8;
1454         if (board(dev)->layout == LAYOUT_4020)
1455                 s->maxdata = 0xfff;
1456         else
1457                 s->maxdata = 0xff;
1458         s->insn_read = calib_read_insn;
1459         s->insn_write = calib_write_insn;
1460         for (i = 0; i < s->n_chan; i++)
1461                 caldac_write(dev, i, s->maxdata / 2);
1462
1463         /*  2 channel ad8402 potentiometer */
1464         s = &dev->subdevices[7];
1465         if (board(dev)->layout == LAYOUT_64XX) {
1466                 s->type = COMEDI_SUBD_CALIB;
1467                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1468                 s->n_chan = 2;
1469                 s->insn_read = ad8402_read_insn;
1470                 s->insn_write = ad8402_write_insn;
1471                 s->maxdata = 0xff;
1472                 for (i = 0; i < s->n_chan; i++)
1473                         ad8402_write(dev, i, s->maxdata / 2);
1474         } else
1475                 s->type = COMEDI_SUBD_UNUSED;
1476
1477         /* serial EEPROM, if present */
1478         s = &dev->subdevices[8];
1479         if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
1480                 s->type = COMEDI_SUBD_MEMORY;
1481                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
1482                 s->n_chan = 128;
1483                 s->maxdata = 0xffff;
1484                 s->insn_read = eeprom_read_insn;
1485         } else
1486                 s->type = COMEDI_SUBD_UNUSED;
1487
1488         /*  user counter subd XXX */
1489         s = &dev->subdevices[9];
1490         s->type = COMEDI_SUBD_UNUSED;
1491
1492         return 0;
1493 }
1494
1495 static void disable_plx_interrupts(struct comedi_device *dev)
1496 {
1497         struct pcidas64_private *devpriv = dev->private;
1498
1499         devpriv->plx_intcsr_bits = 0;
1500         writel(devpriv->plx_intcsr_bits,
1501                devpriv->plx9080_iobase + PLX_INTRCS_REG);
1502 }
1503
1504 static void init_stc_registers(struct comedi_device *dev)
1505 {
1506         struct pcidas64_private *devpriv = dev->private;
1507         uint16_t bits;
1508         unsigned long flags;
1509
1510         spin_lock_irqsave(&dev->spinlock, flags);
1511
1512         /*  bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */
1513         if (1)
1514                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1515         writew(devpriv->adc_control1_bits,
1516                devpriv->main_iobase + ADC_CONTROL1_REG);
1517
1518         /*  6402/16 manual says this register must be initialized to 0xff? */
1519         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1520
1521         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1522         if (board(dev)->layout == LAYOUT_4020)
1523                 bits |= INTERNAL_CLOCK_4020_BITS;
1524         devpriv->hw_config_bits |= bits;
1525         writew(devpriv->hw_config_bits,
1526                devpriv->main_iobase + HW_CONFIG_REG);
1527
1528         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1529         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1530
1531         spin_unlock_irqrestore(&dev->spinlock, flags);
1532
1533         /*  set fifos to maximum size */
1534         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1535         set_ai_fifo_segment_length(dev,
1536                                    board(dev)->ai_fifo->max_segment_length);
1537
1538         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1539         devpriv->intr_enable_bits =     /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1540             EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1541         writew(devpriv->intr_enable_bits,
1542                devpriv->main_iobase + INTR_ENABLE_REG);
1543
1544         disable_ai_pacing(dev);
1545 };
1546
1547 static int alloc_and_init_dma_members(struct comedi_device *dev)
1548 {
1549         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1550         struct pcidas64_private *devpriv = dev->private;
1551         int i;
1552
1553         /*  alocate pci dma buffers */
1554         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1555                 devpriv->ai_buffer[i] =
1556                     pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1557                                          &devpriv->ai_buffer_bus_addr[i]);
1558                 if (devpriv->ai_buffer[i] == NULL)
1559                         return -ENOMEM;
1560
1561         }
1562         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1563                 if (ao_cmd_is_supported(board(dev))) {
1564                         devpriv->ao_buffer[i] =
1565                             pci_alloc_consistent(pcidev,
1566                                                  DMA_BUFFER_SIZE,
1567                                                  &devpriv->
1568                                                  ao_buffer_bus_addr[i]);
1569                         if (devpriv->ao_buffer[i] == NULL)
1570                                 return -ENOMEM;
1571
1572                 }
1573         }
1574         /*  allocate dma descriptors */
1575         devpriv->ai_dma_desc =
1576             pci_alloc_consistent(pcidev,
1577                                  sizeof(struct plx_dma_desc) *
1578                                  ai_dma_ring_count(board(dev)),
1579                                  &devpriv->ai_dma_desc_bus_addr);
1580         if (devpriv->ai_dma_desc == NULL)
1581                 return -ENOMEM;
1582
1583         DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1584                     devpriv->ai_dma_desc_bus_addr);
1585         if (ao_cmd_is_supported(board(dev))) {
1586                 devpriv->ao_dma_desc =
1587                     pci_alloc_consistent(pcidev,
1588                                          sizeof(struct plx_dma_desc) *
1589                                          AO_DMA_RING_COUNT,
1590                                          &devpriv->ao_dma_desc_bus_addr);
1591                 if (devpriv->ao_dma_desc == NULL)
1592                         return -ENOMEM;
1593
1594                 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1595                             devpriv->ao_dma_desc_bus_addr);
1596         }
1597         /*  initialize dma descriptors */
1598         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1599                 devpriv->ai_dma_desc[i].pci_start_addr =
1600                     cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1601                 if (board(dev)->layout == LAYOUT_4020)
1602                         devpriv->ai_dma_desc[i].local_start_addr =
1603                             cpu_to_le32(devpriv->local1_iobase +
1604                                         ADC_FIFO_REG);
1605                 else
1606                         devpriv->ai_dma_desc[i].local_start_addr =
1607                             cpu_to_le32(devpriv->local0_iobase +
1608                                         ADC_FIFO_REG);
1609                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1610                 devpriv->ai_dma_desc[i].next =
1611                     cpu_to_le32((devpriv->ai_dma_desc_bus_addr + ((i +
1612                                                                      1) %
1613                                                                     ai_dma_ring_count
1614                                                                     (board
1615                                                                      (dev))) *
1616                                  sizeof(devpriv->ai_dma_desc[0])) |
1617                                 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1618                                 PLX_XFER_LOCAL_TO_PCI);
1619         }
1620         if (ao_cmd_is_supported(board(dev))) {
1621                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1622                         devpriv->ao_dma_desc[i].pci_start_addr =
1623                             cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1624                         devpriv->ao_dma_desc[i].local_start_addr =
1625                             cpu_to_le32(devpriv->local0_iobase +
1626                                         DAC_FIFO_REG);
1627                         devpriv->ao_dma_desc[i].transfer_size =
1628                             cpu_to_le32(0);
1629                         devpriv->ao_dma_desc[i].next =
1630                             cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1631                                          ((i + 1) % (AO_DMA_RING_COUNT)) *
1632                                          sizeof(devpriv->ao_dma_desc[0])) |
1633                                         PLX_DESC_IN_PCI_BIT |
1634                                         PLX_INTR_TERM_COUNT);
1635                 }
1636         }
1637         return 0;
1638 }
1639
1640 static inline void warn_external_queue(struct comedi_device *dev)
1641 {
1642         comedi_error(dev,
1643                      "AO command and AI external channel queue cannot be used simultaneously.");
1644         comedi_error(dev,
1645                      "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1646 }
1647
1648 static struct pci_dev *cb_pcidas64_find_pci_dev(struct comedi_device *dev,
1649                                                 struct comedi_devconfig *it)
1650 {
1651         struct pci_dev *pcidev = NULL;
1652         int bus = it->options[0];
1653         int slot = it->options[1];
1654         int i;
1655
1656         for_each_pci_dev(pcidev) {
1657                 if (bus || slot) {
1658                         if (bus != pcidev->bus->number ||
1659                             slot != PCI_SLOT(pcidev->devfn))
1660                                 continue;
1661                 }
1662                 if (pcidev->vendor != PCI_VENDOR_ID_CB)
1663                         continue;
1664
1665                 for (i = 0; i < ARRAY_SIZE(pcidas64_boards); i++) {
1666                         if (pcidas64_boards[i].device_id != pcidev->device)
1667                                 continue;
1668                         dev->board_ptr = pcidas64_boards + i;
1669                         return pcidev;
1670                 }
1671         }
1672         dev_err(dev->class_dev,
1673                 "No supported board found! (req. bus %d, slot %d)\n",
1674                 bus, slot);
1675         return NULL;
1676 }
1677
1678 /*
1679  * Attach is called by the Comedi core to configure the driver
1680  * for a particular board.
1681  */
1682 static int attach(struct comedi_device *dev, struct comedi_devconfig *it)
1683 {
1684         struct pcidas64_private *devpriv;
1685         struct pci_dev *pcidev;
1686         uint32_t local_range, local_decode;
1687         int retval;
1688
1689         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1690         if (!devpriv)
1691                 return -ENOMEM;
1692         dev->private = devpriv;
1693
1694         pcidev = cb_pcidas64_find_pci_dev(dev, it);
1695         if (!pcidev)
1696                 return -EIO;
1697         comedi_set_hw_dev(dev, &pcidev->dev);
1698
1699         if (comedi_pci_enable(pcidev, dev->driver->driver_name)) {
1700                 dev_warn(dev->class_dev,
1701                          "failed to enable PCI device and request regions\n");
1702                 return -EIO;
1703         }
1704         pci_set_master(pcidev);
1705
1706         /* Initialize dev->board_name */
1707         dev->board_name = board(dev)->name;
1708
1709         dev->iobase = pci_resource_start(pcidev, MAIN_BADDRINDEX);
1710
1711         devpriv->plx9080_phys_iobase =
1712             pci_resource_start(pcidev, PLX9080_BADDRINDEX);
1713         devpriv->main_phys_iobase = dev->iobase;
1714         devpriv->dio_counter_phys_iobase =
1715             pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
1716
1717         /*  remap, won't work with 2.0 kernels but who cares */
1718         devpriv->plx9080_iobase = ioremap(devpriv->plx9080_phys_iobase,
1719                                             pci_resource_len(pcidev,
1720                                                              PLX9080_BADDRINDEX));
1721         devpriv->main_iobase =
1722             ioremap(devpriv->main_phys_iobase,
1723                     pci_resource_len(pcidev, MAIN_BADDRINDEX));
1724         devpriv->dio_counter_iobase =
1725             ioremap(devpriv->dio_counter_phys_iobase,
1726                     pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
1727
1728         if (!devpriv->plx9080_iobase || !devpriv->main_iobase
1729             || !devpriv->dio_counter_iobase) {
1730                 dev_warn(dev->class_dev, "failed to remap io memory\n");
1731                 return -ENOMEM;
1732         }
1733
1734         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
1735         DEBUG_PRINT(" main remapped to 0x%p\n", devpriv->main_iobase);
1736         DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1737                     devpriv->dio_counter_iobase);
1738
1739         /*  figure out what local addresses are */
1740         local_range =
1741             readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) & LRNG_MEM_MASK;
1742         local_decode =
1743             readl(devpriv->plx9080_iobase +
1744                   PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK;
1745         devpriv->local0_iobase =
1746             ((uint32_t) devpriv->main_phys_iobase & ~local_range) |
1747             local_decode;
1748         local_range =
1749             readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) & LRNG_MEM_MASK;
1750         local_decode =
1751             readl(devpriv->plx9080_iobase +
1752                   PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK;
1753         devpriv->local1_iobase =
1754             ((uint32_t) devpriv->dio_counter_phys_iobase & ~local_range) |
1755             local_decode;
1756
1757         DEBUG_PRINT(" local 0 io addr 0x%x\n", devpriv->local0_iobase);
1758         DEBUG_PRINT(" local 1 io addr 0x%x\n", devpriv->local1_iobase);
1759
1760         retval = alloc_and_init_dma_members(dev);
1761         if (retval < 0)
1762                 return retval;
1763
1764         devpriv->hw_revision =
1765             hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
1766         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
1767                 devpriv->hw_revision);
1768         init_plx9080(dev);
1769         init_stc_registers(dev);
1770         /*  get irq */
1771         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
1772                         "cb_pcidas64", dev)) {
1773                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
1774                         pcidev->irq);
1775                 return -EINVAL;
1776         }
1777         dev->irq = pcidev->irq;
1778         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
1779
1780         retval = setup_subdevices(dev);
1781         if (retval < 0)
1782                 return retval;
1783
1784
1785         return 0;
1786 }
1787
1788 static void detach(struct comedi_device *dev)
1789 {
1790         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1791         struct pcidas64_private *devpriv = dev->private;
1792         unsigned int i;
1793
1794         if (dev->irq)
1795                 free_irq(dev->irq, dev);
1796         if (devpriv) {
1797                 if (pcidev) {
1798                         if (devpriv->plx9080_iobase) {
1799                                 disable_plx_interrupts(dev);
1800                                 iounmap(devpriv->plx9080_iobase);
1801                         }
1802                         if (devpriv->main_iobase)
1803                                 iounmap(devpriv->main_iobase);
1804                         if (devpriv->dio_counter_iobase)
1805                                 iounmap(devpriv->dio_counter_iobase);
1806                         /*  free pci dma buffers */
1807                         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1808                                 if (devpriv->ai_buffer[i])
1809                                         pci_free_consistent(pcidev,
1810                                                 DMA_BUFFER_SIZE,
1811                                                 devpriv->ai_buffer[i],
1812                                                 devpriv->ai_buffer_bus_addr[i]);
1813                         }
1814                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1815                                 if (devpriv->ao_buffer[i])
1816                                         pci_free_consistent(pcidev,
1817                                                 DMA_BUFFER_SIZE,
1818                                                 devpriv->ao_buffer[i],
1819                                                 devpriv->ao_buffer_bus_addr[i]);
1820                         }
1821                         /*  free dma descriptors */
1822                         if (devpriv->ai_dma_desc)
1823                                 pci_free_consistent(pcidev,
1824                                         sizeof(struct plx_dma_desc) *
1825                                         ai_dma_ring_count(board(dev)),
1826                                         devpriv->ai_dma_desc,
1827                                         devpriv->ai_dma_desc_bus_addr);
1828                         if (devpriv->ao_dma_desc)
1829                                 pci_free_consistent(pcidev,
1830                                         sizeof(struct plx_dma_desc) *
1831                                         AO_DMA_RING_COUNT,
1832                                         devpriv->ao_dma_desc,
1833                                         devpriv->ao_dma_desc_bus_addr);
1834                 }
1835         }
1836         if (dev->subdevices)
1837                 subdev_8255_cleanup(dev, &dev->subdevices[4]);
1838         if (pcidev) {
1839                 if (dev->iobase)
1840                         comedi_pci_disable(pcidev);
1841
1842                 pci_dev_put(pcidev);
1843         }
1844 }
1845
1846 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1847                     struct comedi_insn *insn, unsigned int *data)
1848 {
1849         struct pcidas64_private *devpriv = dev->private;
1850         unsigned int bits = 0, n, i;
1851         unsigned int channel, range, aref;
1852         unsigned long flags;
1853         static const int timeout = 100;
1854
1855         DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1856         channel = CR_CHAN(insn->chanspec);
1857         range = CR_RANGE(insn->chanspec);
1858         aref = CR_AREF(insn->chanspec);
1859
1860         /*  disable card's analog input interrupt sources and pacing */
1861         /*  4020 generates dac done interrupts even though they are disabled */
1862         disable_ai_pacing(dev);
1863
1864         spin_lock_irqsave(&dev->spinlock, flags);
1865         if (insn->chanspec & CR_ALT_FILTER)
1866                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1867         else
1868                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1869         writew(devpriv->adc_control1_bits,
1870                devpriv->main_iobase + ADC_CONTROL1_REG);
1871         spin_unlock_irqrestore(&dev->spinlock, flags);
1872
1873         if (board(dev)->layout != LAYOUT_4020) {
1874                 /*  use internal queue */
1875                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1876                 writew(devpriv->hw_config_bits,
1877                        devpriv->main_iobase + HW_CONFIG_REG);
1878
1879                 /*  ALT_SOURCE is internal calibration reference */
1880                 if (insn->chanspec & CR_ALT_SOURCE) {
1881                         unsigned int cal_en_bit;
1882
1883                         DEBUG_PRINT("reading calibration source\n");
1884                         if (board(dev)->layout == LAYOUT_60XX)
1885                                 cal_en_bit = CAL_EN_60XX_BIT;
1886                         else
1887                                 cal_en_bit = CAL_EN_64XX_BIT;
1888                         /*  select internal reference source to connect to channel 0 */
1889                         writew(cal_en_bit |
1890                                adc_src_bits(devpriv->calibration_source),
1891                                devpriv->main_iobase + CALIBRATION_REG);
1892                 } else {
1893                         /*  make sure internal calibration source is turned off */
1894                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1895                 }
1896                 /*  load internal queue */
1897                 bits = 0;
1898                 /*  set gain */
1899                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1900                 /*  set single-ended / differential */
1901                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1902                 if (aref == AREF_COMMON)
1903                         bits |= ADC_COMMON_BIT;
1904                 bits |= adc_chan_bits(channel);
1905                 /*  set stop channel */
1906                 writew(adc_chan_bits(channel),
1907                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1908                 /*  set start channel, and rest of settings */
1909                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1910         } else {
1911                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1912
1913                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1914                 if (insn->chanspec & CR_ALT_SOURCE) {
1915                         DEBUG_PRINT("reading calibration source\n");
1916                         devpriv->i2c_cal_range_bits |=
1917                             adc_src_4020_bits(devpriv->calibration_source);
1918                 } else {        /* select BNC inputs */
1919                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1920                 }
1921                 /*  select range */
1922                 if (range == 0)
1923                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1924                 else
1925                         devpriv->i2c_cal_range_bits &=
1926                             ~attenuate_bit(channel);
1927                 /*  update calibration/range i2c register only if necessary, as it is very slow */
1928                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1929                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1930                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1931                                   sizeof(i2c_data));
1932                 }
1933
1934                 /* 4020 manual asks that sample interval register to be set before writing to convert register.
1935                  * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
1936                 writew(0,
1937                        devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1938                 writew(2,
1939                        devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1940         }
1941
1942         for (n = 0; n < insn->n; n++) {
1943
1944                 /*  clear adc buffer (inside loop for 4020 sake) */
1945                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1946
1947                 /* trigger conversion, bits sent only matter for 4020 */
1948                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1949                        devpriv->main_iobase + ADC_CONVERT_REG);
1950
1951                 /*  wait for data */
1952                 for (i = 0; i < timeout; i++) {
1953                         bits = readw(devpriv->main_iobase + HW_STATUS_REG);
1954                         DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1955                         if (board(dev)->layout == LAYOUT_4020) {
1956                                 if (readw(devpriv->main_iobase +
1957                                           ADC_WRITE_PNTR_REG))
1958                                         break;
1959                         } else {
1960                                 if (pipe_full_bits(bits))
1961                                         break;
1962                         }
1963                         udelay(1);
1964                 }
1965                 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1966                 if (i == timeout) {
1967                         comedi_error(dev, " analog input read insn timed out");
1968                         printk(" status 0x%x\n", bits);
1969                         return -ETIME;
1970                 }
1971                 if (board(dev)->layout == LAYOUT_4020)
1972                         data[n] =
1973                             readl(devpriv->dio_counter_iobase +
1974                                   ADC_FIFO_REG) & 0xffff;
1975                 else
1976                         data[n] =
1977                             readw(devpriv->main_iobase + PIPE1_READ_REG);
1978         }
1979
1980         return n;
1981 }
1982
1983 static int ai_config_calibration_source(struct comedi_device *dev,
1984                                         unsigned int *data)
1985 {
1986         struct pcidas64_private *devpriv = dev->private;
1987         unsigned int source = data[1];
1988         int num_calibration_sources;
1989
1990         if (board(dev)->layout == LAYOUT_60XX)
1991                 num_calibration_sources = 16;
1992         else
1993                 num_calibration_sources = 8;
1994         if (source >= num_calibration_sources) {
1995                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1996                         source);
1997                 return -EINVAL;
1998         }
1999
2000         DEBUG_PRINT("setting calibration source to %i\n", source);
2001         devpriv->calibration_source = source;
2002
2003         return 2;
2004 }
2005
2006 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
2007 {
2008         int fifo_size;
2009         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
2010         unsigned int block_size, requested_block_size;
2011         int retval;
2012
2013         requested_block_size = data[1];
2014
2015         if (requested_block_size) {
2016                 fifo_size =
2017                     requested_block_size * fifo->num_segments / bytes_in_sample;
2018
2019                 retval = set_ai_fifo_size(dev, fifo_size);
2020                 if (retval < 0)
2021                         return retval;
2022
2023         }
2024
2025         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
2026
2027         data[1] = block_size;
2028
2029         return 2;
2030 }
2031
2032 static int ai_config_master_clock_4020(struct comedi_device *dev,
2033                                        unsigned int *data)
2034 {
2035         struct pcidas64_private *devpriv = dev->private;
2036         unsigned int divisor = data[4];
2037         int retval = 0;
2038
2039         if (divisor < 2) {
2040                 divisor = 2;
2041                 retval = -EAGAIN;
2042         }
2043
2044         switch (data[1]) {
2045         case COMEDI_EV_SCAN_BEGIN:
2046                 devpriv->ext_clock.divisor = divisor;
2047                 devpriv->ext_clock.chanspec = data[2];
2048                 break;
2049         default:
2050                 return -EINVAL;
2051                 break;
2052         }
2053
2054         data[4] = divisor;
2055
2056         return retval ? retval : 5;
2057 }
2058
2059 /* XXX could add support for 60xx series */
2060 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
2061 {
2062
2063         switch (board(dev)->layout) {
2064         case LAYOUT_4020:
2065                 return ai_config_master_clock_4020(dev, data);
2066                 break;
2067         default:
2068                 return -EINVAL;
2069                 break;
2070         }
2071
2072         return -EINVAL;
2073 }
2074
2075 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
2076                           struct comedi_insn *insn, unsigned int *data)
2077 {
2078         int id = data[0];
2079
2080         switch (id) {
2081         case INSN_CONFIG_ALT_SOURCE:
2082                 return ai_config_calibration_source(dev, data);
2083                 break;
2084         case INSN_CONFIG_BLOCK_SIZE:
2085                 return ai_config_block_size(dev, data);
2086                 break;
2087         case INSN_CONFIG_TIMER_1:
2088                 return ai_config_master_clock(dev, data);
2089                 break;
2090         default:
2091                 return -EINVAL;
2092                 break;
2093         }
2094         return -EINVAL;
2095 }
2096
2097 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2098                       struct comedi_cmd *cmd)
2099 {
2100         int err = 0;
2101         unsigned int tmp_arg, tmp_arg2;
2102         int i;
2103         int aref;
2104         unsigned int triggers;
2105
2106         /* Step 1 : check if triggers are trivially valid */
2107
2108         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2109
2110         triggers = TRIG_TIMER;
2111         if (board(dev)->layout == LAYOUT_4020)
2112                 triggers |= TRIG_OTHER;
2113         else
2114                 triggers |= TRIG_FOLLOW;
2115         err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2116
2117         triggers = TRIG_TIMER;
2118         if (board(dev)->layout == LAYOUT_4020)
2119                 triggers |= TRIG_NOW;
2120         else
2121                 triggers |= TRIG_EXT;
2122         err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2123
2124         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2125         err |= cfc_check_trigger_src(&cmd->stop_src,
2126                                         TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2127
2128         if (err)
2129                 return 1;
2130
2131         /* Step 2a : make sure trigger sources are unique */
2132
2133         err |= cfc_check_trigger_is_unique(cmd->start_src);
2134         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2135         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2136         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2137
2138         /* Step 2b : and mutually compatible */
2139
2140         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2141                 err |= -EINVAL;
2142         if (cmd->stop_src != TRIG_COUNT &&
2143             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2144                 err |= -EINVAL;
2145
2146         if (err)
2147                 return 2;
2148
2149         /* step 3: make sure arguments are trivially compatible */
2150
2151         if (cmd->convert_src == TRIG_TIMER) {
2152                 if (board(dev)->layout == LAYOUT_4020) {
2153                         if (cmd->convert_arg) {
2154                                 cmd->convert_arg = 0;
2155                                 err++;
2156                         }
2157                 } else {
2158                         if (cmd->convert_arg < board(dev)->ai_speed) {
2159                                 cmd->convert_arg = board(dev)->ai_speed;
2160                                 err++;
2161                         }
2162                         if (cmd->scan_begin_src == TRIG_TIMER) {
2163                                 /*  if scans are timed faster than conversion rate allows */
2164                                 if (cmd->convert_arg * cmd->chanlist_len >
2165                                     cmd->scan_begin_arg) {
2166                                         cmd->scan_begin_arg =
2167                                             cmd->convert_arg *
2168                                             cmd->chanlist_len;
2169                                         err++;
2170                                 }
2171                         }
2172                 }
2173         }
2174
2175         if (!cmd->chanlist_len) {
2176                 cmd->chanlist_len = 1;
2177                 err++;
2178         }
2179         if (cmd->scan_end_arg != cmd->chanlist_len) {
2180                 cmd->scan_end_arg = cmd->chanlist_len;
2181                 err++;
2182         }
2183
2184         switch (cmd->stop_src) {
2185         case TRIG_EXT:
2186                 break;
2187         case TRIG_COUNT:
2188                 if (!cmd->stop_arg) {
2189                         cmd->stop_arg = 1;
2190                         err++;
2191                 }
2192                 break;
2193         case TRIG_NONE:
2194                 if (cmd->stop_arg != 0) {
2195                         cmd->stop_arg = 0;
2196                         err++;
2197                 }
2198                 break;
2199         default:
2200                 break;
2201         }
2202
2203         if (err)
2204                 return 3;
2205
2206         /* step 4: fix up any arguments */
2207
2208         if (cmd->convert_src == TRIG_TIMER) {
2209                 tmp_arg = cmd->convert_arg;
2210                 tmp_arg2 = cmd->scan_begin_arg;
2211                 check_adc_timing(dev, cmd);
2212                 if (tmp_arg != cmd->convert_arg)
2213                         err++;
2214                 if (tmp_arg2 != cmd->scan_begin_arg)
2215                         err++;
2216         }
2217
2218         if (err)
2219                 return 4;
2220
2221         /*  make sure user is doesn't change analog reference mid chanlist */
2222         if (cmd->chanlist) {
2223                 aref = CR_AREF(cmd->chanlist[0]);
2224                 for (i = 1; i < cmd->chanlist_len; i++) {
2225                         if (aref != CR_AREF(cmd->chanlist[i])) {
2226                                 comedi_error(dev,
2227                                              "all elements in chanlist must use the same analog reference");
2228                                 err++;
2229                                 break;
2230                         }
2231                 }
2232                 /*  check 4020 chanlist */
2233                 if (board(dev)->layout == LAYOUT_4020) {
2234                         unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2235                         for (i = 1; i < cmd->chanlist_len; i++) {
2236                                 if (CR_CHAN(cmd->chanlist[i]) !=
2237                                     first_channel + i) {
2238                                         comedi_error(dev,
2239                                                      "chanlist must use consecutive channels");
2240                                         err++;
2241                                         break;
2242                                 }
2243                         }
2244                         if (cmd->chanlist_len == 3) {
2245                                 comedi_error(dev,
2246                                              "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2247                                 err++;
2248                         }
2249                 }
2250         }
2251
2252         if (err)
2253                 return 5;
2254
2255         return 0;
2256 }
2257
2258 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2259 {
2260 /* disable for now until I work out a race */
2261         return 0;
2262
2263         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2264                 return 1;
2265         else
2266                 return 0;
2267 }
2268
2269 static void setup_sample_counters(struct comedi_device *dev,
2270                                   struct comedi_cmd *cmd)
2271 {
2272         struct pcidas64_private *devpriv = dev->private;
2273
2274         if (cmd->stop_src == TRIG_COUNT) {
2275                 /*  set software count */
2276                 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
2277         }
2278         /*  load hardware conversion counter */
2279         if (use_hw_sample_counter(cmd)) {
2280                 writew(cmd->stop_arg & 0xffff,
2281                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2282                 writew((cmd->stop_arg >> 16) & 0xff,
2283                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2284         } else {
2285                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2286         }
2287 }
2288
2289 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2290 {
2291         struct pcidas64_private *devpriv = dev->private;
2292         unsigned int num_samples;
2293
2294         num_samples =
2295             devpriv->ai_fifo_segment_length *
2296             board(dev)->ai_fifo->sample_packing_ratio;
2297         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2298                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2299
2300         return num_samples;
2301 }
2302
2303 static void disable_ai_pacing(struct comedi_device *dev)
2304 {
2305         struct pcidas64_private *devpriv = dev->private;
2306         unsigned long flags;
2307
2308         disable_ai_interrupts(dev);
2309
2310         spin_lock_irqsave(&dev->spinlock, flags);
2311         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
2312         writew(devpriv->adc_control1_bits,
2313                devpriv->main_iobase + ADC_CONTROL1_REG);
2314         spin_unlock_irqrestore(&dev->spinlock, flags);
2315
2316         /* disable pacing, triggering, etc */
2317         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
2318                devpriv->main_iobase + ADC_CONTROL0_REG);
2319 }
2320
2321 static void disable_ai_interrupts(struct comedi_device *dev)
2322 {
2323         struct pcidas64_private *devpriv = dev->private;
2324         unsigned long flags;
2325
2326         spin_lock_irqsave(&dev->spinlock, flags);
2327         devpriv->intr_enable_bits &=
2328             ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
2329             ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
2330             ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
2331         writew(devpriv->intr_enable_bits,
2332                devpriv->main_iobase + INTR_ENABLE_REG);
2333         spin_unlock_irqrestore(&dev->spinlock, flags);
2334
2335         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
2336 }
2337
2338 static void enable_ai_interrupts(struct comedi_device *dev,
2339                                  const struct comedi_cmd *cmd)
2340 {
2341         struct pcidas64_private *devpriv = dev->private;
2342         uint32_t bits;
2343         unsigned long flags;
2344
2345         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
2346             EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
2347         /*  Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */
2348         if (cmd->flags & TRIG_WAKE_EOS) {
2349                 /*  4020 doesn't support pio transfers except for fifo dregs */
2350                 if (board(dev)->layout != LAYOUT_4020)
2351                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
2352         }
2353         spin_lock_irqsave(&dev->spinlock, flags);
2354         devpriv->intr_enable_bits |= bits;
2355         writew(devpriv->intr_enable_bits,
2356                devpriv->main_iobase + INTR_ENABLE_REG);
2357         DEBUG_PRINT("intr enable bits 0x%x\n", devpriv->intr_enable_bits);
2358         spin_unlock_irqrestore(&dev->spinlock, flags);
2359 }
2360
2361 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2362                                         const struct comedi_cmd *cmd)
2363 {
2364         /*  supposed to load counter with desired divisor minus 3 */
2365         return cmd->convert_arg / TIMER_BASE - 3;
2366 }
2367
2368 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2369                                      struct comedi_cmd *cmd)
2370 {
2371         uint32_t count;
2372         /*  figure out how long we need to delay at end of scan */
2373         switch (cmd->scan_begin_src) {
2374         case TRIG_TIMER:
2375                 count = (cmd->scan_begin_arg -
2376                          (cmd->convert_arg * (cmd->chanlist_len - 1)))
2377                     / TIMER_BASE;
2378                 break;
2379         case TRIG_FOLLOW:
2380                 count = cmd->convert_arg / TIMER_BASE;
2381                 break;
2382         default:
2383                 return 0;
2384                 break;
2385         }
2386         return count - 3;
2387 }
2388
2389 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2390                                         struct comedi_cmd *cmd)
2391 {
2392         struct pcidas64_private *devpriv = dev->private;
2393         unsigned int divisor;
2394
2395         switch (cmd->scan_begin_src) {
2396         case TRIG_TIMER:
2397                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2398                 break;
2399         case TRIG_OTHER:
2400                 divisor = devpriv->ext_clock.divisor;
2401                 break;
2402         default:                /*  should never happen */
2403                 comedi_error(dev, "bug! failed to set ai pacing!");
2404                 divisor = 1000;
2405                 break;
2406         }
2407
2408         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2409         return divisor - 2;
2410 }
2411
2412 static void select_master_clock_4020(struct comedi_device *dev,
2413                                      const struct comedi_cmd *cmd)
2414 {
2415         struct pcidas64_private *devpriv = dev->private;
2416
2417         /*  select internal/external master clock */
2418         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2419         if (cmd->scan_begin_src == TRIG_OTHER) {
2420                 int chanspec = devpriv->ext_clock.chanspec;
2421
2422                 if (CR_CHAN(chanspec))
2423                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2424                 else
2425                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2426         } else {
2427                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2428         }
2429         writew(devpriv->hw_config_bits,
2430                devpriv->main_iobase + HW_CONFIG_REG);
2431 }
2432
2433 static void select_master_clock(struct comedi_device *dev,
2434                                 const struct comedi_cmd *cmd)
2435 {
2436         switch (board(dev)->layout) {
2437         case LAYOUT_4020:
2438                 select_master_clock_4020(dev, cmd);
2439                 break;
2440         default:
2441                 break;
2442         }
2443 }
2444
2445 static inline void dma_start_sync(struct comedi_device *dev,
2446                                   unsigned int channel)
2447 {
2448         struct pcidas64_private *devpriv = dev->private;
2449         unsigned long flags;
2450
2451         /*  spinlock for plx dma control/status reg */
2452         spin_lock_irqsave(&dev->spinlock, flags);
2453         if (channel)
2454                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2455                        PLX_CLEAR_DMA_INTR_BIT,
2456                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2457         else
2458                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2459                        PLX_CLEAR_DMA_INTR_BIT,
2460                        devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2461         spin_unlock_irqrestore(&dev->spinlock, flags);
2462 }
2463
2464 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2465 {
2466         struct pcidas64_private *devpriv = dev->private;
2467         uint32_t convert_counter = 0, scan_counter = 0;
2468
2469         check_adc_timing(dev, cmd);
2470
2471         select_master_clock(dev, cmd);
2472
2473         if (board(dev)->layout == LAYOUT_4020) {
2474                 convert_counter = ai_convert_counter_4020(dev, cmd);
2475         } else {
2476                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2477                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2478         }
2479
2480         /*  load lower 16 bits of convert interval */
2481         writew(convert_counter & 0xffff,
2482                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2483         DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2484         /*  load upper 8 bits of convert interval */
2485         writew((convert_counter >> 16) & 0xff,
2486                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2487         /*  load lower 16 bits of scan delay */
2488         writew(scan_counter & 0xffff,
2489                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2490         /*  load upper 8 bits of scan delay */
2491         writew((scan_counter >> 16) & 0xff,
2492                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2493         DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2494 }
2495
2496 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2497 {
2498         int i;
2499         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2500                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2501                     CR_CHAN(cmd->chanlist[i]) + 1)
2502                         return 0;
2503                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2504                     CR_RANGE(cmd->chanlist[i]))
2505                         return 0;
2506                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2507                         return 0;
2508         }
2509         return 1;
2510 }
2511
2512 static int setup_channel_queue(struct comedi_device *dev,
2513                                const struct comedi_cmd *cmd)
2514 {
2515         struct pcidas64_private *devpriv = dev->private;
2516         unsigned short bits;
2517         int i;
2518
2519         if (board(dev)->layout != LAYOUT_4020) {
2520                 if (use_internal_queue_6xxx(cmd)) {
2521                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2522                         writew(devpriv->hw_config_bits,
2523                                devpriv->main_iobase + HW_CONFIG_REG);
2524                         bits = 0;
2525                         /*  set channel */
2526                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2527                         /*  set gain */
2528                         bits |= ai_range_bits_6xxx(dev,
2529                                                    CR_RANGE(cmd->chanlist[0]));
2530                         /*  set single-ended / differential */
2531                         bits |= se_diff_bit_6xxx(dev,
2532                                                  CR_AREF(cmd->chanlist[0]) ==
2533                                                  AREF_DIFF);
2534                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2535                                 bits |= ADC_COMMON_BIT;
2536                         /*  set stop channel */
2537                         writew(adc_chan_bits
2538                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2539                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2540                         /*  set start channel, and rest of settings */
2541                         writew(bits,
2542                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2543                 } else {
2544                         /*  use external queue */
2545                         if (dev->write_subdev && dev->write_subdev->busy) {
2546                                 warn_external_queue(dev);
2547                                 return -EBUSY;
2548                         }
2549                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2550                         writew(devpriv->hw_config_bits,
2551                                devpriv->main_iobase + HW_CONFIG_REG);
2552                         /*  clear DAC buffer to prevent weird interactions */
2553                         writew(0,
2554                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2555                         /*  clear queue pointer */
2556                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2557                         /*  load external queue */
2558                         for (i = 0; i < cmd->chanlist_len; i++) {
2559                                 bits = 0;
2560                                 /*  set channel */
2561                                 bits |=
2562                                     adc_chan_bits(CR_CHAN(cmd->chanlist[i]));
2563                                 /*  set gain */
2564                                 bits |= ai_range_bits_6xxx(dev,
2565                                                            CR_RANGE(cmd->
2566                                                                     chanlist
2567                                                                     [i]));
2568                                 /*  set single-ended / differential */
2569                                 bits |= se_diff_bit_6xxx(dev,
2570                                                          CR_AREF(cmd->
2571                                                                  chanlist[i]) ==
2572                                                          AREF_DIFF);
2573                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2574                                         bits |= ADC_COMMON_BIT;
2575                                 /*  mark end of queue */
2576                                 if (i == cmd->chanlist_len - 1)
2577                                         bits |= QUEUE_EOSCAN_BIT |
2578                                             QUEUE_EOSEQ_BIT;
2579                                 writew(bits,
2580                                        devpriv->main_iobase +
2581                                        ADC_QUEUE_FIFO_REG);
2582                                 DEBUG_PRINT
2583                                     ("wrote 0x%x to external channel queue\n",
2584                                      bits);
2585                         }
2586                         /* doing a queue clear is not specified in board docs,
2587                          * but required for reliable operation */
2588                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2589                         /*  prime queue holding register */
2590                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2591                 }
2592         } else {
2593                 unsigned short old_cal_range_bits =
2594                     devpriv->i2c_cal_range_bits;
2595
2596                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2597                 /* select BNC inputs */
2598                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2599                 /*  select ranges */
2600                 for (i = 0; i < cmd->chanlist_len; i++) {
2601                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2602                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2603
2604                         if (range == 0)
2605                                 devpriv->i2c_cal_range_bits |=
2606                                     attenuate_bit(channel);
2607                         else
2608                                 devpriv->i2c_cal_range_bits &=
2609                                     ~attenuate_bit(channel);
2610                 }
2611                 /*  update calibration/range i2c register only if necessary, as it is very slow */
2612                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2613                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2614                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2615                                   sizeof(i2c_data));
2616                 }
2617         }
2618         return 0;
2619 }
2620
2621 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2622                                              unsigned int dma_channel,
2623                                              unsigned int descriptor_bits)
2624 {
2625         struct pcidas64_private *devpriv = dev->private;
2626
2627         /* The transfer size, pci address, and local address registers
2628          * are supposedly unused during chained dma,
2629          * but I have found that left over values from last operation
2630          * occasionally cause problems with transfer of first dma
2631          * block.  Initializing them to zero seems to fix the problem. */
2632         if (dma_channel) {
2633                 writel(0,
2634                        devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2635                 writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2636                 writel(0,
2637                        devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2638                 writel(descriptor_bits,
2639                        devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2640         } else {
2641                 writel(0,
2642                        devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2643                 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2644                 writel(0,
2645                        devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2646                 writel(descriptor_bits,
2647                        devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2648         }
2649 }
2650
2651 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2652 {
2653         struct pcidas64_private *devpriv = dev->private;
2654         struct comedi_async *async = s->async;
2655         struct comedi_cmd *cmd = &async->cmd;
2656         uint32_t bits;
2657         unsigned int i;
2658         unsigned long flags;
2659         int retval;
2660
2661         disable_ai_pacing(dev);
2662         abort_dma(dev, 1);
2663
2664         retval = setup_channel_queue(dev, cmd);
2665         if (retval < 0)
2666                 return retval;
2667
2668         /*  make sure internal calibration source is turned off */
2669         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2670
2671         set_ai_pacing(dev, cmd);
2672
2673         setup_sample_counters(dev, cmd);
2674
2675         enable_ai_interrupts(dev, cmd);
2676
2677         spin_lock_irqsave(&dev->spinlock, flags);
2678         /* set mode, allow conversions through software gate */
2679         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2680         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2681         if (board(dev)->layout != LAYOUT_4020) {
2682                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2683                 if (cmd->convert_src == TRIG_EXT)
2684                         devpriv->adc_control1_bits |= adc_mode_bits(13);        /*  good old mode 13 */
2685                 else
2686                         devpriv->adc_control1_bits |= adc_mode_bits(8); /*  mode 8.  What else could you need? */
2687         } else {
2688                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2689                 if (cmd->chanlist_len == 4)
2690                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2691                 else if (cmd->chanlist_len == 2)
2692                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2693                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2694                 devpriv->adc_control1_bits |=
2695                     adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2696                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2697                 devpriv->adc_control1_bits |=
2698                     adc_hi_chan_4020_bits(CR_CHAN
2699                                           (cmd->
2700                                            chanlist[cmd->chanlist_len - 1]));
2701         }
2702         writew(devpriv->adc_control1_bits,
2703                devpriv->main_iobase + ADC_CONTROL1_REG);
2704         DEBUG_PRINT("control1 bits 0x%x\n", devpriv->adc_control1_bits);
2705         spin_unlock_irqrestore(&dev->spinlock, flags);
2706
2707         /*  clear adc buffer */
2708         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2709
2710         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2711             board(dev)->layout == LAYOUT_4020) {
2712                 devpriv->ai_dma_index = 0;
2713
2714                 /*  set dma transfer size */
2715                 for (i = 0; i < ai_dma_ring_count(board(dev)); i++)
2716                         devpriv->ai_dma_desc[i].transfer_size =
2717                             cpu_to_le32(dma_transfer_size(dev) *
2718                                         sizeof(uint16_t));
2719
2720                 /*  give location of first dma descriptor */
2721                 load_first_dma_descriptor(dev, 1,
2722                                           devpriv->ai_dma_desc_bus_addr |
2723                                           PLX_DESC_IN_PCI_BIT |
2724                                           PLX_INTR_TERM_COUNT |
2725                                           PLX_XFER_LOCAL_TO_PCI);
2726
2727                 dma_start_sync(dev, 1);
2728         }
2729
2730         if (board(dev)->layout == LAYOUT_4020) {
2731                 /* set source for external triggers */
2732                 bits = 0;
2733                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2734                         bits |= EXT_START_TRIG_BNC_BIT;
2735                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2736                         bits |= EXT_STOP_TRIG_BNC_BIT;
2737                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2738         }
2739
2740         spin_lock_irqsave(&dev->spinlock, flags);
2741
2742         /* enable pacing, triggering, etc */
2743         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2744         if (cmd->flags & TRIG_WAKE_EOS)
2745                 bits |= ADC_DMA_DISABLE_BIT;
2746         /*  set start trigger */
2747         if (cmd->start_src == TRIG_EXT) {
2748                 bits |= ADC_START_TRIG_EXT_BITS;
2749                 if (cmd->start_arg & CR_INVERT)
2750                         bits |= ADC_START_TRIG_FALLING_BIT;
2751         } else if (cmd->start_src == TRIG_NOW)
2752                 bits |= ADC_START_TRIG_SOFT_BITS;
2753         if (use_hw_sample_counter(cmd))
2754                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2755         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2756         DEBUG_PRINT("control0 bits 0x%x\n", bits);
2757
2758         devpriv->ai_cmd_running = 1;
2759
2760         spin_unlock_irqrestore(&dev->spinlock, flags);
2761
2762         /*  start acquisition */
2763         if (cmd->start_src == TRIG_NOW) {
2764                 writew(0, devpriv->main_iobase + ADC_START_REG);
2765                 DEBUG_PRINT("soft trig\n");
2766         }
2767
2768         return 0;
2769 }
2770
2771 /* read num_samples from 16 bit wide ai fifo */
2772 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2773 {
2774         struct pcidas64_private *devpriv = dev->private;
2775         struct comedi_subdevice *s = dev->read_subdev;
2776         struct comedi_async *async = s->async;
2777         struct comedi_cmd *cmd = &async->cmd;
2778         unsigned int i;
2779         uint16_t prepost_bits;
2780         int read_segment, read_index, write_segment, write_index;
2781         int num_samples;
2782
2783         do {
2784                 /*  get least significant 15 bits */
2785                 read_index =
2786                     readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2787                 write_index =
2788                     readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2789                 /* Get most significant bits (grey code).  Different boards use different code
2790                  * so use a scheme that doesn't depend on encoding.  This read must
2791                  * occur after reading least significant 15 bits to avoid race
2792                  * with fifo switching to next segment. */
2793                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2794
2795                 /* if read and write pointers are not on the same fifo segment, read to the
2796                  * end of the read segment */
2797                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2798                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2799
2800                 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2801                             read_segment, write_segment, read_index,
2802                             write_index);
2803
2804                 if (read_segment != write_segment)
2805                         num_samples =
2806                             devpriv->ai_fifo_segment_length - read_index;
2807                 else
2808                         num_samples = write_index - read_index;
2809
2810                 if (cmd->stop_src == TRIG_COUNT) {
2811                         if (devpriv->ai_count == 0)
2812                                 break;
2813                         if (num_samples > devpriv->ai_count)
2814                                 num_samples = devpriv->ai_count;
2815
2816                         devpriv->ai_count -= num_samples;
2817                 }
2818
2819                 if (num_samples < 0) {
2820                         dev_err(dev->class_dev,
2821                                 "cb_pcidas64: bug! num_samples < 0\n");
2822                         break;
2823                 }
2824
2825                 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2826
2827                 for (i = 0; i < num_samples; i++) {
2828                         cfc_write_to_buffer(s,
2829                                             readw(devpriv->main_iobase +
2830                                                   ADC_FIFO_REG));
2831                 }
2832
2833         } while (read_segment != write_segment);
2834 }
2835
2836 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2837  * The pci-4020 hardware only supports
2838  * dma transfers (it only supports the use of pio for draining the last remaining
2839  * points from the fifo when a data acquisition operation has completed).
2840  */
2841 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2842 {
2843         struct pcidas64_private *devpriv = dev->private;
2844         struct comedi_subdevice *s = dev->read_subdev;
2845         struct comedi_async *async = s->async;
2846         struct comedi_cmd *cmd = &async->cmd;
2847         unsigned int i;
2848         unsigned int max_transfer = 100000;
2849         uint32_t fifo_data;
2850         int write_code =
2851             readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2852         int read_code =
2853             readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2854
2855         if (cmd->stop_src == TRIG_COUNT) {
2856                 if (max_transfer > devpriv->ai_count)
2857                         max_transfer = devpriv->ai_count;
2858
2859         }
2860         for (i = 0; read_code != write_code && i < max_transfer;) {
2861                 fifo_data = readl(devpriv->dio_counter_iobase + ADC_FIFO_REG);
2862                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2863                 i++;
2864                 if (i < max_transfer) {
2865                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2866                         i++;
2867                 }
2868                 read_code =
2869                     readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2870         }
2871         devpriv->ai_count -= i;
2872 }
2873
2874 /* empty fifo */
2875 static void pio_drain_ai_fifo(struct comedi_device *dev)
2876 {
2877         if (board(dev)->layout == LAYOUT_4020)
2878                 pio_drain_ai_fifo_32(dev);
2879         else
2880                 pio_drain_ai_fifo_16(dev);
2881 }
2882
2883 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2884 {
2885         struct pcidas64_private *devpriv = dev->private;
2886         struct comedi_async *async = dev->read_subdev->async;
2887         uint32_t next_transfer_addr;
2888         int j;
2889         int num_samples = 0;
2890         void __iomem *pci_addr_reg;
2891
2892         if (channel)
2893                 pci_addr_reg =
2894                     devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2895         else
2896                 pci_addr_reg =
2897                     devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2898
2899         /*  loop until we have read all the full buffers */
2900         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2901              (next_transfer_addr <
2902               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index]
2903               || next_transfer_addr >=
2904               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2905               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev)); j++) {
2906                 /*  transfer data from dma buffer to comedi buffer */
2907                 num_samples = dma_transfer_size(dev);
2908                 if (async->cmd.stop_src == TRIG_COUNT) {
2909                         if (num_samples > devpriv->ai_count)
2910                                 num_samples = devpriv->ai_count;
2911                         devpriv->ai_count -= num_samples;
2912                 }
2913                 cfc_write_array_to_buffer(dev->read_subdev,
2914                                           devpriv->ai_buffer[devpriv->
2915                                                                ai_dma_index],
2916                                           num_samples * sizeof(uint16_t));
2917                 devpriv->ai_dma_index =
2918                     (devpriv->ai_dma_index +
2919                      1) % ai_dma_ring_count(board(dev));
2920
2921                 DEBUG_PRINT("next buffer addr 0x%lx\n",
2922                             (unsigned long)devpriv->
2923                             ai_buffer_bus_addr[devpriv->ai_dma_index]);
2924                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2925         }
2926         /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
2927          * unused buffer) */
2928 }
2929
2930 static void handle_ai_interrupt(struct comedi_device *dev,
2931                                 unsigned short status,
2932                                 unsigned int plx_status)
2933 {
2934         struct pcidas64_private *devpriv = dev->private;
2935         struct comedi_subdevice *s = dev->read_subdev;
2936         struct comedi_async *async = s->async;
2937         struct comedi_cmd *cmd = &async->cmd;
2938         uint8_t dma1_status;
2939         unsigned long flags;
2940
2941         /*  check for fifo overrun */
2942         if (status & ADC_OVERRUN_BIT) {
2943                 comedi_error(dev, "fifo overrun");
2944                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2945         }
2946         /*  spin lock makes sure no one else changes plx dma control reg */
2947         spin_lock_irqsave(&dev->spinlock, flags);
2948         dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2949         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2950                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2951                        devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2952                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2953
2954                 if (dma1_status & PLX_DMA_EN_BIT)
2955                         drain_dma_buffers(dev, 1);
2956
2957                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2958         }
2959         spin_unlock_irqrestore(&dev->spinlock, flags);
2960
2961         if (status & ADC_DONE_BIT)
2962                 DEBUG_PRINT("adc done interrupt\n");
2963
2964         /*  drain fifo with pio */
2965         if ((status & ADC_DONE_BIT) ||
2966             ((cmd->flags & TRIG_WAKE_EOS) &&
2967              (status & ADC_INTR_PENDING_BIT) &&
2968              (board(dev)->layout != LAYOUT_4020))) {
2969                 DEBUG_PRINT("pio fifo drain\n");
2970                 spin_lock_irqsave(&dev->spinlock, flags);
2971                 if (devpriv->ai_cmd_running) {
2972                         spin_unlock_irqrestore(&dev->spinlock, flags);
2973                         pio_drain_ai_fifo(dev);
2974                 } else
2975                         spin_unlock_irqrestore(&dev->spinlock, flags);
2976         }
2977         /*  if we are have all the data, then quit */
2978         if ((cmd->stop_src == TRIG_COUNT && (int)devpriv->ai_count <= 0) ||
2979             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2980                 async->events |= COMEDI_CB_EOA;
2981         }
2982
2983         cfc_handle_events(dev, s);
2984 }
2985
2986 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2987 {
2988         struct pcidas64_private *devpriv = dev->private;
2989         unsigned int buffer_index;
2990
2991         if (devpriv->ao_dma_index == 0)
2992                 buffer_index = AO_DMA_RING_COUNT - 1;
2993         else
2994                 buffer_index = devpriv->ao_dma_index - 1;
2995         return buffer_index;
2996 }
2997
2998 static int last_ao_dma_load_completed(struct comedi_device *dev)
2999 {
3000         struct pcidas64_private *devpriv = dev->private;
3001         unsigned int buffer_index;
3002         unsigned int transfer_address;
3003         unsigned short dma_status;
3004
3005         buffer_index = prev_ao_dma_index(dev);
3006         dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3007         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
3008                 return 0;
3009
3010         transfer_address =
3011             readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
3012         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
3013                 return 0;
3014
3015         return 1;
3016 }
3017
3018 static int ao_stopped_by_error(struct comedi_device *dev,
3019                                const struct comedi_cmd *cmd)
3020 {
3021         struct pcidas64_private *devpriv = dev->private;
3022
3023         if (cmd->stop_src == TRIG_NONE)
3024                 return 1;
3025         if (cmd->stop_src == TRIG_COUNT) {
3026                 if (devpriv->ao_count)
3027                         return 1;
3028                 if (last_ao_dma_load_completed(dev) == 0)
3029                         return 1;
3030         }
3031         return 0;
3032 }
3033
3034 static inline int ao_dma_needs_restart(struct comedi_device *dev,
3035                                        unsigned short dma_status)
3036 {
3037         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
3038             (dma_status & PLX_DMA_EN_BIT) == 0)
3039                 return 0;
3040         if (last_ao_dma_load_completed(dev))
3041                 return 0;
3042
3043         return 1;
3044 }
3045
3046 static void restart_ao_dma(struct comedi_device *dev)
3047 {
3048         struct pcidas64_private *devpriv = dev->private;
3049         unsigned int dma_desc_bits;
3050
3051         dma_desc_bits =
3052             readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
3053         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
3054         DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
3055         load_first_dma_descriptor(dev, 0, dma_desc_bits);
3056
3057         dma_start_sync(dev, 0);
3058 }
3059
3060 static void handle_ao_interrupt(struct comedi_device *dev,
3061                                 unsigned short status, unsigned int plx_status)
3062 {
3063         struct pcidas64_private *devpriv = dev->private;
3064         struct comedi_subdevice *s = dev->write_subdev;
3065         struct comedi_async *async;
3066         struct comedi_cmd *cmd;
3067         uint8_t dma0_status;
3068         unsigned long flags;
3069
3070         /* board might not support ao, in which case write_subdev is NULL */
3071         if (s == NULL)
3072                 return;
3073         async = s->async;
3074         cmd = &async->cmd;
3075
3076         /*  spin lock makes sure no one else changes plx dma control reg */
3077         spin_lock_irqsave(&dev->spinlock, flags);
3078         dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3079         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3080                 if ((dma0_status & PLX_DMA_EN_BIT)
3081                     && !(dma0_status & PLX_DMA_DONE_BIT))
3082                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3083                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3084                 else
3085                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3086                                devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
3087                 spin_unlock_irqrestore(&dev->spinlock, flags);
3088                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3089                 if (dma0_status & PLX_DMA_EN_BIT) {
3090                         load_ao_dma(dev, cmd);
3091                         /* try to recover from dma end-of-chain event */
3092                         if (ao_dma_needs_restart(dev, dma0_status))
3093                                 restart_ao_dma(dev);
3094                 }
3095                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3096         } else
3097                 spin_unlock_irqrestore(&dev->spinlock, flags);
3098
3099         if ((status & DAC_DONE_BIT)) {
3100                 async->events |= COMEDI_CB_EOA;
3101                 if (ao_stopped_by_error(dev, cmd))
3102                         async->events |= COMEDI_CB_ERROR;
3103                 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3104                             readl(devpriv->plx9080_iobase +
3105                                   PLX_DMA0_DESCRIPTOR_REG));
3106                 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3107                             readl(devpriv->plx9080_iobase +
3108                                   PLX_DMA0_PCI_ADDRESS_REG));
3109         }
3110         cfc_handle_events(dev, s);
3111 }
3112
3113 static irqreturn_t handle_interrupt(int irq, void *d)
3114 {
3115         struct comedi_device *dev = d;
3116         struct pcidas64_private *devpriv = dev->private;
3117         unsigned short status;
3118         uint32_t plx_status;
3119         uint32_t plx_bits;
3120
3121         plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3122         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3123
3124         DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status);
3125         DEBUG_PRINT("plx status 0x%x\n", plx_status);
3126
3127         /* an interrupt before all the postconfig stuff gets done could
3128          * cause a NULL dereference if we continue through the
3129          * interrupt handler */
3130         if (dev->attached == 0) {
3131                 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3132                             status);
3133                 return IRQ_HANDLED;
3134         }
3135         handle_ai_interrupt(dev, status, plx_status);
3136         handle_ao_interrupt(dev, status, plx_status);
3137
3138         /*  clear possible plx9080 interrupt sources */
3139         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3140                 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3141                 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3142                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3143         }
3144
3145         DEBUG_PRINT("exiting handler\n");
3146
3147         return IRQ_HANDLED;
3148 }
3149
3150 static void abort_dma(struct comedi_device *dev, unsigned int channel)
3151 {
3152         struct pcidas64_private *devpriv = dev->private;
3153         unsigned long flags;
3154
3155         /*  spinlock for plx dma control/status reg */
3156         spin_lock_irqsave(&dev->spinlock, flags);
3157
3158         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
3159
3160         spin_unlock_irqrestore(&dev->spinlock, flags);
3161 }
3162
3163 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3164 {
3165         struct pcidas64_private *devpriv = dev->private;
3166         unsigned long flags;
3167
3168         spin_lock_irqsave(&dev->spinlock, flags);
3169         if (devpriv->ai_cmd_running == 0) {
3170                 spin_unlock_irqrestore(&dev->spinlock, flags);
3171                 return 0;
3172         }
3173         devpriv->ai_cmd_running = 0;
3174         spin_unlock_irqrestore(&dev->spinlock, flags);
3175
3176         disable_ai_pacing(dev);
3177
3178         abort_dma(dev, 1);
3179
3180         DEBUG_PRINT("ai canceled\n");
3181         return 0;
3182 }
3183
3184 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3185                     struct comedi_insn *insn, unsigned int *data)
3186 {
3187         struct pcidas64_private *devpriv = dev->private;
3188         int chan = CR_CHAN(insn->chanspec);
3189         int range = CR_RANGE(insn->chanspec);
3190
3191         /*  do some initializing */
3192         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3193
3194         /*  set range */
3195         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3196         writew(devpriv->dac_control1_bits,
3197                devpriv->main_iobase + DAC_CONTROL1_REG);
3198
3199         /*  write to channel */
3200         if (board(dev)->layout == LAYOUT_4020) {
3201                 writew(data[0] & 0xff,
3202                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3203                 writew((data[0] >> 8) & 0xf,
3204                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3205         } else {
3206                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3207         }
3208
3209         /*  remember output value */
3210         devpriv->ao_value[chan] = data[0];
3211
3212         return 1;
3213 }
3214
3215 static int ao_readback_insn(struct comedi_device *dev,
3216                             struct comedi_subdevice *s,
3217                             struct comedi_insn *insn, unsigned int *data)
3218 {
3219         struct pcidas64_private *devpriv = dev->private;
3220
3221         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
3222
3223         return 1;
3224 }
3225
3226 static void set_dac_control0_reg(struct comedi_device *dev,
3227                                  const struct comedi_cmd *cmd)
3228 {
3229         struct pcidas64_private *devpriv = dev->private;
3230         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3231             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3232
3233         if (cmd->start_src == TRIG_EXT) {
3234                 bits |= WAVEFORM_TRIG_EXT_BITS;
3235                 if (cmd->start_arg & CR_INVERT)
3236                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3237         } else {
3238                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3239         }
3240         if (cmd->scan_begin_src == TRIG_EXT) {
3241                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3242                 if (cmd->scan_begin_arg & CR_INVERT)
3243                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3244         }
3245         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3246 }
3247
3248 static void set_dac_control1_reg(struct comedi_device *dev,
3249                                  const struct comedi_cmd *cmd)
3250 {
3251         struct pcidas64_private *devpriv = dev->private;
3252         int i;
3253
3254         for (i = 0; i < cmd->chanlist_len; i++) {
3255                 int channel, range;
3256
3257                 channel = CR_CHAN(cmd->chanlist[i]);
3258                 range = CR_RANGE(cmd->chanlist[i]);
3259                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3260                                    range);
3261         }
3262         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3263         writew(devpriv->dac_control1_bits,
3264                devpriv->main_iobase + DAC_CONTROL1_REG);
3265 }
3266
3267 static void set_dac_select_reg(struct comedi_device *dev,
3268                                const struct comedi_cmd *cmd)
3269 {
3270         struct pcidas64_private *devpriv = dev->private;
3271         uint16_t bits;
3272         unsigned int first_channel, last_channel;
3273
3274         first_channel = CR_CHAN(cmd->chanlist[0]);
3275         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3276         if (last_channel < first_channel)
3277                 comedi_error(dev, "bug! last ao channel < first ao channel");
3278
3279         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3280
3281         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3282 }
3283
3284 static void set_dac_interval_regs(struct comedi_device *dev,
3285                                   const struct comedi_cmd *cmd)
3286 {
3287         struct pcidas64_private *devpriv = dev->private;
3288         unsigned int divisor;
3289
3290         if (cmd->scan_begin_src != TRIG_TIMER)
3291                 return;
3292
3293         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3294         if (divisor > max_counter_value) {
3295                 comedi_error(dev, "bug! ao divisor too big");
3296                 divisor = max_counter_value;
3297         }
3298         writew(divisor & 0xffff,
3299                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3300         writew((divisor >> 16) & 0xff,
3301                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3302 }
3303
3304 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
3305                                        const struct comedi_cmd *cmd)
3306 {
3307         struct pcidas64_private *devpriv = dev->private;
3308         unsigned int num_bytes, buffer_index, prev_buffer_index;
3309         unsigned int next_bits;
3310
3311         buffer_index = devpriv->ao_dma_index;
3312         prev_buffer_index = prev_ao_dma_index(dev);
3313
3314         DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index,
3315                     devpriv->ao_buffer_bus_addr[buffer_index]);
3316
3317         num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3318         if (num_bytes > DMA_BUFFER_SIZE)
3319                 num_bytes = DMA_BUFFER_SIZE;
3320         if (cmd->stop_src == TRIG_COUNT && num_bytes > devpriv->ao_count)
3321                 num_bytes = devpriv->ao_count;
3322         num_bytes -= num_bytes % bytes_in_sample;
3323
3324         if (num_bytes == 0)
3325                 return 0;
3326
3327         DEBUG_PRINT("loading %i bytes\n", num_bytes);
3328
3329         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3330                                                devpriv->
3331                                                ao_buffer[buffer_index],
3332                                                num_bytes);
3333         devpriv->ao_dma_desc[buffer_index].transfer_size =
3334             cpu_to_le32(num_bytes);
3335         /* set end of chain bit so we catch underruns */
3336         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
3337         next_bits |= PLX_END_OF_CHAIN_BIT;
3338         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3339         /* clear end of chain bit on previous buffer now that we have set it
3340          * for the last buffer */
3341         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
3342         next_bits &= ~PLX_END_OF_CHAIN_BIT;
3343         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3344
3345         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3346         devpriv->ao_count -= num_bytes;
3347
3348         return num_bytes;
3349 }
3350
3351 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3352 {
3353         struct pcidas64_private *devpriv = dev->private;
3354         unsigned int num_bytes;
3355         unsigned int next_transfer_addr;
3356         void __iomem *pci_addr_reg =
3357             devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3358         unsigned int buffer_index;
3359
3360         do {
3361                 buffer_index = devpriv->ao_dma_index;
3362                 /* don't overwrite data that hasn't been transferred yet */
3363                 next_transfer_addr = readl(pci_addr_reg);
3364                 if (next_transfer_addr >=
3365                     devpriv->ao_buffer_bus_addr[buffer_index]
3366                     && next_transfer_addr <
3367                     devpriv->ao_buffer_bus_addr[buffer_index] +
3368                     DMA_BUFFER_SIZE)
3369                         return;
3370                 num_bytes = load_ao_dma_buffer(dev, cmd);
3371         } while (num_bytes >= DMA_BUFFER_SIZE);
3372 }
3373
3374 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3375 {
3376         struct pcidas64_private *devpriv = dev->private;
3377         unsigned int num_bytes;
3378         int i;
3379
3380         /* clear queue pointer too, since external queue has
3381          * weird interactions with ao fifo */
3382         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3383         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3384
3385         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3386         if (cmd->stop_src == TRIG_COUNT &&
3387             num_bytes / bytes_in_sample > devpriv->ao_count)
3388                 num_bytes = devpriv->ao_count * bytes_in_sample;
3389         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3390                                                devpriv->ao_bounce_buffer,
3391                                                num_bytes);
3392         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3393                 writew(devpriv->ao_bounce_buffer[i],
3394                        devpriv->main_iobase + DAC_FIFO_REG);
3395         }
3396         devpriv->ao_count -= num_bytes / bytes_in_sample;
3397         if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count == 0)
3398                 return 0;
3399         num_bytes = load_ao_dma_buffer(dev, cmd);
3400         if (num_bytes == 0)
3401                 return -1;
3402         if (num_bytes >= DMA_BUFFER_SIZE) ;
3403         load_ao_dma(dev, cmd);
3404
3405         dma_start_sync(dev, 0);
3406
3407         return 0;
3408 }
3409
3410 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3411 {
3412         if (dev->read_subdev->busy)
3413                 return 0;
3414         if (board(dev)->layout == LAYOUT_4020)
3415                 return 0;
3416         else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3417                 return 0;
3418         return 1;
3419 }
3420
3421 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3422 {
3423         struct pcidas64_private *devpriv = dev->private;
3424         struct comedi_cmd *cmd = &s->async->cmd;
3425
3426         if (external_ai_queue_in_use(dev)) {
3427                 warn_external_queue(dev);
3428                 return -EBUSY;
3429         }
3430         /* disable analog output system during setup */
3431         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3432
3433         devpriv->ao_dma_index = 0;
3434         devpriv->ao_count = cmd->stop_arg * cmd->chanlist_len;
3435
3436         set_dac_select_reg(dev, cmd);
3437         set_dac_interval_regs(dev, cmd);
3438         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3439                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3440
3441         set_dac_control1_reg(dev, cmd);
3442         s->async->inttrig = ao_inttrig;
3443
3444         return 0;
3445 }
3446
3447 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3448                       unsigned int trig_num)
3449 {
3450         struct pcidas64_private *devpriv = dev->private;
3451         struct comedi_cmd *cmd = &s->async->cmd;
3452         int retval;
3453
3454         if (trig_num != 0)
3455                 return -EINVAL;
3456
3457         retval = prep_ao_dma(dev, cmd);
3458         if (retval < 0)
3459                 return -EPIPE;
3460
3461         set_dac_control0_reg(dev, cmd);
3462
3463         if (cmd->start_src == TRIG_INT)
3464                 writew(0, devpriv->main_iobase + DAC_START_REG);
3465
3466         s->async->inttrig = NULL;
3467
3468         return 0;
3469 }
3470
3471 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3472                       struct comedi_cmd *cmd)
3473 {
3474         int err = 0;
3475         unsigned int tmp_arg;
3476         int i;
3477
3478         /* Step 1 : check if triggers are trivially valid */
3479
3480         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3481         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3482                                         TRIG_TIMER | TRIG_EXT);
3483         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3484         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3485         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3486
3487         if (err)
3488                 return 1;
3489
3490         /* Step 2a : make sure trigger sources are unique */
3491
3492         err |= cfc_check_trigger_is_unique(cmd->start_src);
3493         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3494
3495         /* Step 2b : and mutually compatible */
3496
3497         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3498                 err |= -EINVAL;
3499         if (cmd->stop_src != TRIG_COUNT &&
3500             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3501                 err |= -EINVAL;
3502
3503         if (err)
3504                 return 2;
3505
3506         /* step 3: make sure arguments are trivially compatible */
3507
3508         if (cmd->scan_begin_src == TRIG_TIMER) {
3509                 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) {
3510                         cmd->scan_begin_arg = board(dev)->ao_scan_speed;
3511                         err++;
3512                 }
3513                 if (get_ao_divisor(cmd->scan_begin_arg,
3514                                    cmd->flags) > max_counter_value) {
3515                         cmd->scan_begin_arg =
3516                             (max_counter_value + 2) * TIMER_BASE;
3517                         err++;
3518                 }
3519         }
3520
3521         if (!cmd->chanlist_len) {
3522                 cmd->chanlist_len = 1;
3523                 err++;
3524         }
3525         if (cmd->scan_end_arg != cmd->chanlist_len) {
3526                 cmd->scan_end_arg = cmd->chanlist_len;
3527                 err++;
3528         }
3529
3530         if (err)
3531                 return 3;
3532
3533         /* step 4: fix up any arguments */
3534
3535         if (cmd->scan_begin_src == TRIG_TIMER) {
3536                 tmp_arg = cmd->scan_begin_arg;
3537                 cmd->scan_begin_arg =
3538                     get_divisor(cmd->scan_begin_arg, cmd->flags) * TIMER_BASE;
3539                 if (tmp_arg != cmd->scan_begin_arg)
3540                         err++;
3541         }
3542
3543         if (err)
3544                 return 4;
3545
3546         if (cmd->chanlist) {
3547                 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3548                 for (i = 1; i < cmd->chanlist_len; i++) {
3549                         if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3550                                 comedi_error(dev,
3551                                              "chanlist must use consecutive channels");
3552                                 err++;
3553                                 break;
3554                         }
3555                 }
3556         }
3557
3558         if (err)
3559                 return 5;
3560
3561         return 0;
3562 }
3563
3564 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3565 {
3566         struct pcidas64_private *devpriv = dev->private;
3567
3568         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3569         abort_dma(dev, 0);
3570         return 0;
3571 }
3572
3573 static int dio_callback(int dir, int port, int data, unsigned long arg)
3574 {
3575         void __iomem *iobase = (void __iomem *)arg;
3576         if (dir) {
3577                 writeb(data, iobase + port);
3578                 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3579                 return 0;
3580         } else {
3581                 return readb(iobase + port);
3582         }
3583 }
3584
3585 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3586 {
3587         void __iomem *iobase = (void __iomem *)arg;
3588         if (dir) {
3589                 writew(data, iobase + 2 * port);
3590                 return 0;
3591         } else {
3592                 return readw(iobase + 2 * port);
3593         }
3594 }
3595
3596 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3597                     struct comedi_insn *insn, unsigned int *data)
3598 {
3599         struct pcidas64_private *devpriv = dev->private;
3600         unsigned int bits;
3601
3602         bits = readb(devpriv->dio_counter_iobase + DI_REG);
3603         bits &= 0xf;
3604         data[1] = bits;
3605         data[0] = 0;
3606
3607         return insn->n;
3608 }
3609
3610 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3611                     struct comedi_insn *insn, unsigned int *data)
3612 {
3613         struct pcidas64_private *devpriv = dev->private;
3614
3615         data[0] &= 0xf;
3616         /*  zero bits we are going to change */
3617         s->state &= ~data[0];
3618         /*  set new bits */
3619         s->state |= data[0] & data[1];
3620
3621         writeb(s->state, devpriv->dio_counter_iobase + DO_REG);
3622
3623         data[1] = s->state;
3624
3625         return insn->n;
3626 }
3627
3628 static int dio_60xx_config_insn(struct comedi_device *dev,
3629                                 struct comedi_subdevice *s,
3630                                 struct comedi_insn *insn, unsigned int *data)
3631 {
3632         struct pcidas64_private *devpriv = dev->private;
3633         unsigned int mask;
3634
3635         mask = 1 << CR_CHAN(insn->chanspec);
3636
3637         switch (data[0]) {
3638         case INSN_CONFIG_DIO_INPUT:
3639                 s->io_bits &= ~mask;
3640                 break;
3641         case INSN_CONFIG_DIO_OUTPUT:
3642                 s->io_bits |= mask;
3643                 break;
3644         case INSN_CONFIG_DIO_QUERY:
3645                 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3646                 return 2;
3647         default:
3648                 return -EINVAL;
3649         }
3650
3651         writeb(s->io_bits,
3652                devpriv->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3653
3654         return 1;
3655 }
3656
3657 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3658                           struct comedi_insn *insn, unsigned int *data)
3659 {
3660         struct pcidas64_private *devpriv = dev->private;
3661
3662         if (data[0]) {
3663                 s->state &= ~data[0];
3664                 s->state |= (data[0] & data[1]);
3665                 writeb(s->state,
3666                        devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3667         }
3668
3669         data[1] = readb(devpriv->dio_counter_iobase + DIO_DATA_60XX_REG);
3670
3671         return insn->n;
3672 }
3673
3674 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3675                          unsigned int value)
3676 {
3677         struct pcidas64_private *devpriv = dev->private;
3678
3679         devpriv->caldac_state[channel] = value;
3680
3681         switch (board(dev)->layout) {
3682         case LAYOUT_60XX:
3683         case LAYOUT_64XX:
3684                 caldac_8800_write(dev, channel, value);
3685                 break;
3686         case LAYOUT_4020:
3687                 caldac_i2c_write(dev, channel, value);
3688                 break;
3689         default:
3690                 break;
3691         }
3692 }
3693
3694 static int calib_write_insn(struct comedi_device *dev,
3695                             struct comedi_subdevice *s,
3696                             struct comedi_insn *insn, unsigned int *data)
3697 {
3698         struct pcidas64_private *devpriv = dev->private;
3699         int channel = CR_CHAN(insn->chanspec);
3700
3701         /* return immediately if setting hasn't changed, since
3702          * programming these things is slow */
3703         if (devpriv->caldac_state[channel] == data[0])
3704                 return 1;
3705
3706         caldac_write(dev, channel, data[0]);
3707
3708         return 1;
3709 }
3710
3711 static int calib_read_insn(struct comedi_device *dev,
3712                            struct comedi_subdevice *s, struct comedi_insn *insn,
3713                            unsigned int *data)
3714 {
3715         struct pcidas64_private *devpriv = dev->private;
3716         unsigned int channel = CR_CHAN(insn->chanspec);
3717
3718         data[0] = devpriv->caldac_state[channel];
3719
3720         return 1;
3721 }
3722
3723 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3724                          unsigned int value)
3725 {
3726         struct pcidas64_private *devpriv = dev->private;
3727         static const int bitstream_length = 10;
3728         unsigned int bit, register_bits;
3729         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3730         static const int ad8402_udelay = 1;
3731
3732         devpriv->ad8402_state[channel] = value;
3733
3734         register_bits = SELECT_8402_64XX_BIT;
3735         udelay(ad8402_udelay);
3736         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3737
3738         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3739                 if (bitstream & bit)
3740                         register_bits |= SERIAL_DATA_IN_BIT;
3741                 else
3742                         register_bits &= ~SERIAL_DATA_IN_BIT;
3743                 udelay(ad8402_udelay);
3744                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3745                 udelay(ad8402_udelay);
3746                 writew(register_bits | SERIAL_CLOCK_BIT,
3747                        devpriv->main_iobase + CALIBRATION_REG);
3748         }
3749
3750         udelay(ad8402_udelay);
3751         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3752 }
3753
3754 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3755 static int ad8402_write_insn(struct comedi_device *dev,
3756                              struct comedi_subdevice *s,
3757                              struct comedi_insn *insn, unsigned int *data)
3758 {
3759         struct pcidas64_private *devpriv = dev->private;
3760         int channel = CR_CHAN(insn->chanspec);
3761
3762         /* return immediately if setting hasn't changed, since
3763          * programming these things is slow */
3764         if (devpriv->ad8402_state[channel] == data[0])
3765                 return 1;
3766
3767         devpriv->ad8402_state[channel] = data[0];
3768
3769         ad8402_write(dev, channel, data[0]);
3770
3771         return 1;
3772 }
3773
3774 static int ad8402_read_insn(struct comedi_device *dev,
3775                             struct comedi_subdevice *s,
3776                             struct comedi_insn *insn, unsigned int *data)
3777 {
3778         struct pcidas64_private *devpriv = dev->private;
3779         unsigned int channel = CR_CHAN(insn->chanspec);
3780
3781         data[0] = devpriv->ad8402_state[channel];
3782
3783         return 1;
3784 }
3785
3786 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3787 {
3788         struct pcidas64_private *devpriv = dev->private;
3789         static const int bitstream_length = 11;
3790         static const int read_command = 0x6;
3791         unsigned int bitstream = (read_command << 8) | address;
3792         unsigned int bit;
3793         void __iomem * const plx_control_addr =
3794             devpriv->plx9080_iobase + PLX_CONTROL_REG;
3795         uint16_t value;
3796         static const int value_length = 16;
3797         static const int eeprom_udelay = 1;
3798
3799         udelay(eeprom_udelay);
3800         devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3801         /*  make sure we don't send anything to the i2c bus on 4020 */
3802         devpriv->plx_control_bits |= CTL_USERO;
3803         writel(devpriv->plx_control_bits, plx_control_addr);
3804         /*  activate serial eeprom */
3805         udelay(eeprom_udelay);
3806         devpriv->plx_control_bits |= CTL_EE_CS;
3807         writel(devpriv->plx_control_bits, plx_control_addr);
3808
3809         /*  write read command and desired memory address */
3810         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3811                 /*  set bit to be written */
3812                 udelay(eeprom_udelay);
3813                 if (bitstream & bit)
3814                         devpriv->plx_control_bits |= CTL_EE_W;
3815                 else
3816                         devpriv->plx_control_bits &= ~CTL_EE_W;
3817                 writel(devpriv->plx_control_bits, plx_control_addr);
3818                 /*  clock in bit */
3819                 udelay(eeprom_udelay);
3820                 devpriv->plx_control_bits |= CTL_EE_CLK;
3821                 writel(devpriv->plx_control_bits, plx_control_addr);
3822                 udelay(eeprom_udelay);
3823                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3824                 writel(devpriv->plx_control_bits, plx_control_addr);
3825         }
3826         /*  read back value from eeprom memory location */
3827         value = 0;
3828         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3829                 /*  clock out bit */
3830                 udelay(eeprom_udelay);
3831                 devpriv->plx_control_bits |= CTL_EE_CLK;
3832                 writel(devpriv->plx_control_bits, plx_control_addr);
3833                 udelay(eeprom_udelay);
3834                 devpriv->plx_control_bits &= ~CTL_EE_CLK;
3835                 writel(devpriv->plx_control_bits, plx_control_addr);
3836                 udelay(eeprom_udelay);
3837                 if (readl(plx_control_addr) & CTL_EE_R)
3838                         value |= bit;
3839         }
3840
3841         /*  deactivate eeprom serial input */
3842         udelay(eeprom_udelay);
3843         devpriv->plx_control_bits &= ~CTL_EE_CS;
3844         writel(devpriv->plx_control_bits, plx_control_addr);
3845
3846         return value;
3847 }
3848
3849 static int eeprom_read_insn(struct comedi_device *dev,
3850                             struct comedi_subdevice *s,
3851                             struct comedi_insn *insn, unsigned int *data)
3852 {
3853         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3854
3855         return 1;
3856 }
3857
3858 /* utility function that rounds desired timing to an achievable time, and
3859  * sets cmd members appropriately.
3860  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3861  */
3862 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
3863 {
3864         unsigned int convert_divisor = 0, scan_divisor;
3865         static const int min_convert_divisor = 3;
3866         static const int max_convert_divisor =
3867             max_counter_value + min_convert_divisor;
3868         static const int min_scan_divisor_4020 = 2;
3869         unsigned long long max_scan_divisor, min_scan_divisor;
3870
3871         if (cmd->convert_src == TRIG_TIMER) {
3872                 if (board(dev)->layout == LAYOUT_4020) {
3873                         cmd->convert_arg = 0;
3874                 } else {
3875                         convert_divisor =
3876                             get_divisor(cmd->convert_arg, cmd->flags);
3877                         if (convert_divisor > max_convert_divisor)
3878                                 convert_divisor = max_convert_divisor;
3879                         if (convert_divisor < min_convert_divisor)
3880                                 convert_divisor = min_convert_divisor;
3881                         cmd->convert_arg = convert_divisor * TIMER_BASE;
3882                 }
3883         } else if (cmd->convert_src == TRIG_NOW)
3884                 cmd->convert_arg = 0;
3885
3886         if (cmd->scan_begin_src == TRIG_TIMER) {
3887                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
3888                 if (cmd->convert_src == TRIG_TIMER) {
3889                         /*  XXX check for integer overflows */
3890                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
3891                         max_scan_divisor =
3892                             (convert_divisor * cmd->chanlist_len - 1) +
3893                             max_counter_value;
3894                 } else {
3895                         min_scan_divisor = min_scan_divisor_4020;
3896                         max_scan_divisor = max_counter_value + min_scan_divisor;
3897                 }
3898                 if (scan_divisor > max_scan_divisor)
3899                         scan_divisor = max_scan_divisor;
3900                 if (scan_divisor < min_scan_divisor)
3901                         scan_divisor = min_scan_divisor;
3902                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
3903         }
3904
3905         return;
3906 }
3907
3908 /* Gets nearest achievable timing given master clock speed, does not
3909  * take into account possible minimum/maximum divisor values.  Used
3910  * by other timing checking functions. */
3911 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
3912 {
3913         unsigned int divisor;
3914
3915         switch (flags & TRIG_ROUND_MASK) {
3916         case TRIG_ROUND_UP:
3917                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
3918                 break;
3919         case TRIG_ROUND_DOWN:
3920                 divisor = ns / TIMER_BASE;
3921                 break;
3922         case TRIG_ROUND_NEAREST:
3923         default:
3924                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
3925                 break;
3926         }
3927         return divisor;
3928 }
3929
3930 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3931 {
3932         return get_divisor(ns, flags) - 2;
3933 }
3934
3935 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
3936 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
3937 {
3938         unsigned int num_fifo_entries;
3939         int retval;
3940         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3941
3942         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
3943
3944         retval = set_ai_fifo_segment_length(dev,
3945                                             num_fifo_entries /
3946                                             fifo->num_segments);
3947         if (retval < 0)
3948                 return retval;
3949
3950         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
3951
3952         DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
3953
3954         return num_samples;
3955 }
3956
3957 /* query length of fifo */
3958 static unsigned int ai_fifo_size(struct comedi_device *dev)
3959 {
3960         struct pcidas64_private *devpriv = dev->private;
3961
3962         return devpriv->ai_fifo_segment_length *
3963             board(dev)->ai_fifo->num_segments *
3964             board(dev)->ai_fifo->sample_packing_ratio;
3965 }
3966
3967 static int set_ai_fifo_segment_length(struct comedi_device *dev,
3968                                       unsigned int num_entries)
3969 {
3970         struct pcidas64_private *devpriv = dev->private;
3971         static const int increment_size = 0x100;
3972         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3973         unsigned int num_increments;
3974         uint16_t bits;
3975
3976         if (num_entries < increment_size)
3977                 num_entries = increment_size;
3978         if (num_entries > fifo->max_segment_length)
3979                 num_entries = fifo->max_segment_length;
3980
3981         /*  1 == 256 entries, 2 == 512 entries, etc */
3982         num_increments = (num_entries + increment_size / 2) / increment_size;
3983
3984         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
3985         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
3986         devpriv->fifo_size_bits |= bits;
3987         writew(devpriv->fifo_size_bits,
3988                devpriv->main_iobase + FIFO_SIZE_REG);
3989
3990         devpriv->ai_fifo_segment_length = num_increments * increment_size;
3991
3992         DEBUG_PRINT("set hardware fifo segment length to %i\n",
3993                     devpriv->ai_fifo_segment_length);
3994
3995         return devpriv->ai_fifo_segment_length;
3996 }
3997
3998 /* pci-6025 8800 caldac:
3999  * address 0 == dac channel 0 offset
4000  * address 1 == dac channel 0 gain
4001  * address 2 == dac channel 1 offset
4002  * address 3 == dac channel 1 gain
4003  * address 4 == fine adc offset
4004  * address 5 == coarse adc offset
4005  * address 6 == coarse adc gain
4006  * address 7 == fine adc gain
4007  */
4008 /* pci-6402/16 uses all 8 channels for dac:
4009  * address 0 == dac channel 0 fine gain
4010  * address 1 == dac channel 0 coarse gain
4011  * address 2 == dac channel 0 coarse offset
4012  * address 3 == dac channel 1 coarse offset
4013  * address 4 == dac channel 1 fine gain
4014  * address 5 == dac channel 1 coarse gain
4015  * address 6 == dac channel 0 fine offset
4016  * address 7 == dac channel 1 fine offset
4017 */
4018
4019 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
4020                              uint8_t value)
4021 {
4022         struct pcidas64_private *devpriv = dev->private;
4023         static const int num_caldac_channels = 8;
4024         static const int bitstream_length = 11;
4025         unsigned int bitstream = ((address & 0x7) << 8) | value;
4026         unsigned int bit, register_bits;
4027         static const int caldac_8800_udelay = 1;
4028
4029         if (address >= num_caldac_channels) {
4030                 comedi_error(dev, "illegal caldac channel");
4031                 return -1;
4032         }
4033         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
4034                 register_bits = 0;
4035                 if (bitstream & bit)
4036                         register_bits |= SERIAL_DATA_IN_BIT;
4037                 udelay(caldac_8800_udelay);
4038                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
4039                 register_bits |= SERIAL_CLOCK_BIT;
4040                 udelay(caldac_8800_udelay);
4041                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
4042         }
4043         udelay(caldac_8800_udelay);
4044         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
4045         udelay(caldac_8800_udelay);
4046         writew(0, devpriv->main_iobase + CALIBRATION_REG);
4047         udelay(caldac_8800_udelay);
4048         return 0;
4049 }
4050
4051 /* 4020 caldacs */
4052 static int caldac_i2c_write(struct comedi_device *dev,
4053                             unsigned int caldac_channel, unsigned int value)
4054 {
4055         uint8_t serial_bytes[3];
4056         uint8_t i2c_addr;
4057         enum pointer_bits {
4058                 /*  manual has gain and offset bits switched */
4059                 OFFSET_0_2 = 0x1,
4060                 GAIN_0_2 = 0x2,
4061                 OFFSET_1_3 = 0x4,
4062                 GAIN_1_3 = 0x8,
4063         };
4064         enum data_bits {
4065                 NOT_CLEAR_REGISTERS = 0x20,
4066         };
4067
4068         switch (caldac_channel) {
4069         case 0:         /*  chan 0 offset */
4070                 i2c_addr = CALDAC0_I2C_ADDR;
4071                 serial_bytes[0] = OFFSET_0_2;
4072                 break;
4073         case 1:         /*  chan 1 offset */
4074                 i2c_addr = CALDAC0_I2C_ADDR;
4075                 serial_bytes[0] = OFFSET_1_3;
4076                 break;
4077         case 2:         /*  chan 2 offset */
4078                 i2c_addr = CALDAC1_I2C_ADDR;
4079                 serial_bytes[0] = OFFSET_0_2;
4080                 break;
4081         case 3:         /*  chan 3 offset */
4082                 i2c_addr = CALDAC1_I2C_ADDR;
4083                 serial_bytes[0] = OFFSET_1_3;
4084                 break;
4085         case 4:         /*  chan 0 gain */
4086                 i2c_addr = CALDAC0_I2C_ADDR;
4087                 serial_bytes[0] = GAIN_0_2;
4088                 break;
4089         case 5:         /*  chan 1 gain */
4090                 i2c_addr = CALDAC0_I2C_ADDR;
4091                 serial_bytes[0] = GAIN_1_3;
4092                 break;
4093         case 6:         /*  chan 2 gain */
4094                 i2c_addr = CALDAC1_I2C_ADDR;
4095                 serial_bytes[0] = GAIN_0_2;
4096                 break;
4097         case 7:         /*  chan 3 gain */
4098                 i2c_addr = CALDAC1_I2C_ADDR;
4099                 serial_bytes[0] = GAIN_1_3;
4100                 break;
4101         default:
4102                 comedi_error(dev, "invalid caldac channel\n");
4103                 return -1;
4104                 break;
4105         }
4106         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
4107         serial_bytes[2] = value & 0xff;
4108         i2c_write(dev, i2c_addr, serial_bytes, 3);
4109         return 0;
4110 }
4111
4112 /* Their i2c requires a huge delay on setting clock or data high for some reason */
4113 static const int i2c_high_udelay = 1000;
4114 static const int i2c_low_udelay = 10;
4115
4116 /* set i2c data line high or low */
4117 static void i2c_set_sda(struct comedi_device *dev, int state)
4118 {
4119         struct pcidas64_private *devpriv = dev->private;
4120         static const int data_bit = CTL_EE_W;
4121         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
4122                                          PLX_CONTROL_REG;
4123
4124         if (state) {
4125                 /*  set data line high */
4126                 devpriv->plx_control_bits &= ~data_bit;
4127                 writel(devpriv->plx_control_bits, plx_control_addr);
4128                 udelay(i2c_high_udelay);
4129         } else {                /*  set data line low */
4130
4131                 devpriv->plx_control_bits |= data_bit;
4132                 writel(devpriv->plx_control_bits, plx_control_addr);
4133                 udelay(i2c_low_udelay);
4134         }
4135 }
4136
4137 /* set i2c clock line high or low */
4138 static void i2c_set_scl(struct comedi_device *dev, int state)
4139 {
4140         struct pcidas64_private *devpriv = dev->private;
4141         static const int clock_bit = CTL_USERO;
4142         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
4143                                          PLX_CONTROL_REG;
4144
4145         if (state) {
4146                 /*  set clock line high */
4147                 devpriv->plx_control_bits &= ~clock_bit;
4148                 writel(devpriv->plx_control_bits, plx_control_addr);
4149                 udelay(i2c_high_udelay);
4150         } else {                /*  set clock line low */
4151
4152                 devpriv->plx_control_bits |= clock_bit;
4153                 writel(devpriv->plx_control_bits, plx_control_addr);
4154                 udelay(i2c_low_udelay);
4155         }
4156 }
4157
4158 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
4159 {
4160         uint8_t bit;
4161         unsigned int num_bits = 8;
4162
4163         DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
4164
4165         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
4166                 i2c_set_scl(dev, 0);
4167                 if ((byte & bit))
4168                         i2c_set_sda(dev, 1);
4169                 else
4170                         i2c_set_sda(dev, 0);
4171                 i2c_set_scl(dev, 1);
4172         }
4173 }
4174
4175 /* we can't really read the lines, so fake it */
4176 static int i2c_read_ack(struct comedi_device *dev)
4177 {
4178         i2c_set_scl(dev, 0);
4179         i2c_set_sda(dev, 1);
4180         i2c_set_scl(dev, 1);
4181
4182         return 0;               /*  return fake acknowledge bit */
4183 }
4184
4185 /* send start bit */
4186 static void i2c_start(struct comedi_device *dev)
4187 {
4188         i2c_set_scl(dev, 1);
4189         i2c_set_sda(dev, 1);
4190         i2c_set_sda(dev, 0);
4191 }
4192
4193 /* send stop bit */
4194 static void i2c_stop(struct comedi_device *dev)
4195 {
4196         i2c_set_scl(dev, 0);
4197         i2c_set_sda(dev, 0);
4198         i2c_set_scl(dev, 1);
4199         i2c_set_sda(dev, 1);
4200 }
4201
4202 static void i2c_write(struct comedi_device *dev, unsigned int address,
4203                       const uint8_t *data, unsigned int length)
4204 {
4205         struct pcidas64_private *devpriv = dev->private;
4206         unsigned int i;
4207         uint8_t bitstream;
4208         static const int read_bit = 0x1;
4209
4210 /* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */
4211
4212         /*  make sure we dont send anything to eeprom */
4213         devpriv->plx_control_bits &= ~CTL_EE_CS;
4214
4215         i2c_stop(dev);
4216         i2c_start(dev);
4217
4218         /*  send address and write bit */
4219         bitstream = (address << 1) & ~read_bit;
4220         i2c_write_byte(dev, bitstream);
4221
4222         /*  get acknowledge */
4223         if (i2c_read_ack(dev) != 0) {
4224                 comedi_error(dev, "i2c write failed: no acknowledge");
4225                 i2c_stop(dev);
4226                 return;
4227         }
4228         /*  write data bytes */
4229         for (i = 0; i < length; i++) {
4230                 i2c_write_byte(dev, data[i]);
4231                 if (i2c_read_ack(dev) != 0) {
4232                         comedi_error(dev, "i2c write failed: no acknowledge");
4233                         i2c_stop(dev);
4234                         return;
4235                 }
4236         }
4237         i2c_stop(dev);
4238 }
4239
4240 static struct comedi_driver cb_pcidas64_driver = {
4241         .driver_name    = "cb_pcidas64",
4242         .module         = THIS_MODULE,
4243         .attach         = attach,
4244         .detach         = detach,
4245 };
4246
4247 static int __devinit cb_pcidas64_pci_probe(struct pci_dev *dev,
4248                                            const struct pci_device_id *ent)
4249 {
4250         return comedi_pci_auto_config(dev, &cb_pcidas64_driver);
4251 }
4252
4253 static void __devexit cb_pcidas64_pci_remove(struct pci_dev *dev)
4254 {
4255         comedi_pci_auto_unconfig(dev);
4256 }
4257
4258 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4259         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001d) },
4260         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x001e) },
4261         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0035) },
4262         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0036) },
4263         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0037) },
4264         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0052) },
4265         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005d) },
4266         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005e) },
4267         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x005f) },
4268         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0061) },
4269         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0062) },
4270         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0063) },
4271         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0064) },
4272         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0066) },
4273         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0067) },
4274         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0068) },
4275         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x006f) },
4276         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0078) },
4277         { PCI_DEVICE(PCI_VENDOR_ID_CB, 0x0079) },
4278         { 0 }
4279 };
4280 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4281
4282 static struct pci_driver cb_pcidas64_pci_driver = {
4283         .name           = "cb_pcidas64",
4284         .id_table       = cb_pcidas64_pci_table,
4285         .probe          = cb_pcidas64_pci_probe,
4286         .remove         = __devexit_p(cb_pcidas64_pci_remove),
4287 };
4288 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4289
4290 MODULE_AUTHOR("Comedi http://www.comedi.org");
4291 MODULE_DESCRIPTION("Comedi low-level driver");
4292 MODULE_LICENSE("GPL");