2 comedi/drivers/amplc_dio200.c
3 Driver for Amplicon PC272E and PCI272 DIO boards.
4 (Support for other boards in Amplicon 200 series may be added at
5 a later date, e.g. PCI215.)
7 Copyright (C) 2005 MEV Ltd. <http://www.mev.co.uk/>
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Driver: amplc_dio200
29 * Description: Amplicon 200 Series Digital I/O
30 * Author: Ian Abbott <abbotti@mev.co.uk>
31 * Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e),
32 * PCI215 (pci215), PCIe215 (pcie215), PC218E (pc218e), PCIe236 (pcie236),
33 * PC272E (pc272e), PCI272 (pci272), PCIe296 (pcie296)
34 * Updated: Wed, 24 Oct 2012 16:22:34 +0100
37 * Configuration options - PC212E, PC214E, PC215E, PC218E, PC272E:
38 * [0] - I/O port base address
39 * [1] - IRQ (optional, but commands won't work without it)
41 * Manual configuration of PCI(e) cards is not supported; they are configured
44 * Passing a zero for an option is the same as leaving it unspecified.
48 * PC212E PC214E PC215E/PCI215
49 * ------------- ------------- -------------
52 * 1 CTR-Y1 PPI-Y PPI-Y
53 * 2 CTR-Y2 CTR-Z1* CTR-Z1
54 * 3 CTR-Z1 INTERRUPT* CTR-Z2
58 * PCIe215 PC218E PCIe236
59 * ------------- ------------- -------------
61 * 0 PPI-X CTR-X1 PPI-X
62 * 1 UNUSED CTR-X2 UNUSED
63 * 2 PPI-Y CTR-Y1 UNUSED
64 * 3 UNUSED CTR-Y2 UNUSED
65 * 4 CTR-Z1 CTR-Z1 CTR-Z1
66 * 5 CTR-Z2 CTR-Z2 CTR-Z2
67 * 6 TIMER INTERRUPT TIMER
68 * 7 INTERRUPT INTERRUPT
70 * PC272E/PCI272 PCIe296
71 * ------------- -------------
82 * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
83 * are configurable as inputs or outputs in four groups:
85 * Port A - channels 0 to 7
86 * Port B - channels 8 to 15
87 * Port CL - channels 16 to 19
88 * Port CH - channels 20 to 23
90 * Only mode 0 of the 8255 chips is supported.
92 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
93 * channel is configured individually with INSN_CONFIG instructions. The
94 * specific type of configuration instruction is specified in data[0].
95 * Some configuration instructions expect an additional parameter in
96 * data[1]; others return a value in data[1]. The following configuration
97 * instructions are supported:
99 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
100 * BCD/binary setting specified in data[1].
102 * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
103 * counter channel into data[1].
105 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
106 * specified in data[1] (this is a hardware-specific value). Not
107 * supported on PC214E. For the other boards, valid clock sources are
110 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
111 * connector. (N.B. for other values, the counter channel's CLKn
112 * pin on the SK1 connector is an output!)
113 * 1. Internal 10 MHz clock.
114 * 2. Internal 1 MHz clock.
115 * 3. Internal 100 kHz clock.
116 * 4. Internal 10 kHz clock.
117 * 5. Internal 1 kHz clock.
118 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
119 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
120 * the SK1 connector. This pin is shared by all three counter
121 * channels on the chip.
123 * For the PCIe boards, clock sources in the range 0 to 31 are allowed
124 * and the following additional clock sources are defined:
126 * 8. HIGH logic level.
127 * 9. LOW logic level.
128 * 10. "Pattern present" signal.
129 * 11. Internal 20 MHz clock.
131 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
132 * clock source in data[1]. For internal clock sources, data[2] is set
133 * to the period in ns.
135 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
136 * specified in data[2] (this is a hardware-specific value). Not
137 * supported on PC214E. For the other boards, valid gate sources are 0
140 * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
141 * 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
142 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
143 * connector. (N.B. for other values, the counter channel's GATn
144 * pin on the SK1 connector is an output!)
145 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
152 * For the PCIe boards, gate sources in the range 0 to 31 are allowed;
153 * the following additional clock sources and clock sources 6 and 7 are
156 * 6. /GAT n, negated version of the counter channel's dedicated
157 * GAT input (negated version of gate source 2).
158 * 7. OUT n-2, the non-inverted output of counter channel n-2
159 * (negated version of gate source 3).
160 * 8. "Pattern present" signal, HIGH while pattern present.
161 * 9. "Pattern occurred" latched signal, latches HIGH when pattern
163 * 10. "Pattern gone away" latched signal, latches LOW when pattern
164 * goes away after it occurred.
165 * 11. Negated "pattern present" signal, LOW while pattern present
166 * (negated version of gate source 8).
167 * 12. Negated "pattern occurred" latched signal, latches LOW when
168 * pattern occurs (negated version of gate source 9).
169 * 13. Negated "pattern gone away" latched signal, latches LOW when
170 * pattern goes away after it occurred (negated version of gate
173 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
176 * Clock and gate interconnection notes:
178 * 1. Clock source OUT n-1 is the output of the preceding channel on the
179 * same counter subdevice if n > 0, or the output of channel 2 on the
180 * preceding counter subdevice (see note 3) if n = 0.
182 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
183 * same counter subdevice if n = 2, or the inverted output of channel n+1
184 * on the preceding counter subdevice (see note 3) if n < 2.
186 * 3. The counter subdevices are connected in a ring, so the highest
187 * counter subdevice precedes the lowest.
189 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
191 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
192 * digital inputs come from the interrupt status register. The number of
193 * channels matches the number of interrupt sources. The PC214E does not
194 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
199 * PC212E PC214E PC215E/PCI215
200 * ------------- ------------- -------------
202 * 0 PPI-X-C0 JUMPER-J5 PPI-X-C0
203 * 1 PPI-X-C3 PPI-X-C3
204 * 2 CTR-Y1-OUT1 PPI-Y-C0
205 * 3 CTR-Y2-OUT1 PPI-Y-C3
206 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1
207 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1
209 * PCIe215 PC218E PCIe236
210 * ------------- ------------- -------------
212 * 0 PPI-X-C0 CTR-X1-OUT1 PPI-X-C0
213 * 1 PPI-X-C3 CTR-X2-OUT1 PPI-X-C3
214 * 2 PPI-Y-C0 CTR-Y1-OUT1 unused
215 * 3 PPI-Y-C3 CTR-Y2-OUT1 unused
216 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
217 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
219 * PC272E/PCI272 PCIe296
220 * ------------- -------------
222 * 0 PPI-X-C0 PPI-X1-C0
223 * 1 PPI-X-C3 PPI-X1-C3
224 * 2 PPI-Y-C0 PPI-Y1-C0
225 * 3 PPI-Y-C3 PPI-Y1-C3
226 * 4 PPI-Z-C0 CTR-Z1-OUT1
227 * 5 PPI-Z-C3 CTR-Z2-OUT1
229 * When an interrupt source is enabled in the interrupt source enable
230 * register, a rising edge on the source signal latches the corresponding
231 * bit to 1 in the interrupt status register.
233 * When the interrupt status register value as a whole (actually, just the
234 * 6 least significant bits) goes from zero to non-zero, the board will
235 * generate an interrupt. For level-triggered hardware interrupts (PCI
236 * card), the interrupt will remain asserted until the interrupt status
237 * register is cleared to zero. For edge-triggered hardware interrupts
238 * (ISA card), no further interrupts will occur until the interrupt status
239 * register is cleared to zero. To clear a bit to zero in the interrupt
240 * status register, the corresponding interrupt source must be disabled
241 * in the interrupt source enable register (there is no separate interrupt
244 * The PC214E does not have an interrupt source enable register or an
245 * interrupt status register; its 'INTERRUPT' subdevice has a single
246 * channel and its interrupt source is selected by the position of jumper
251 * The driver supports a read streaming acquisition command on the
252 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
253 * to be enabled. All channels will be sampled together (convert_src ==
254 * TRIG_NOW). The scan begins a short time after the hardware interrupt
255 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
256 * scan_begin_arg == 0). The value read from the interrupt status register
257 * is packed into a short value, one bit per requested channel, in the
258 * order they appear in the channel list.
261 #include <linux/pci.h>
262 #include <linux/interrupt.h>
263 #include <linux/slab.h>
265 #include "../comedidev.h"
267 #include "comedi_fc.h"
270 #define DIO200_DRIVER_NAME "amplc_dio200"
272 #define DO_ISA IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_ISA)
273 #define DO_PCI IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_PCI)
276 #define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a
277 #define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b
278 #define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011
279 #define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012
280 #define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014
282 /* 8255 control register bits */
283 #define CR_C_LO_IO 0x01
285 #define CR_B_MODE 0x04
286 #define CR_C_HI_IO 0x08
288 #define CR_A_MODE(a) ((a)<<5)
291 /* 200 series registers */
292 #define DIO200_IO_SIZE 0x20
293 #define DIO200_PCIE_IO_SIZE 0x4000
294 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
295 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
296 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
297 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
298 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
299 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
300 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
301 /* Extra registers for new PCIe boards */
302 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
303 #define DIO200_VERSION 0x24 /* Hardware version register */
304 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
305 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
308 * Functions for constructing value for DIO_200_?CLK_SCE and
309 * DIO_200_?GAT_SCE registers:
311 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
312 * 'chan' is the channel: 0, 1 or 2.
313 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
315 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
318 return (which << 5) | (chan << 3) |
319 ((source & 030) << 3) | (source & 007);
322 static unsigned char clk_sce(unsigned int which, unsigned int chan,
325 return clk_gat_sce(which, chan, source);
328 static unsigned char gat_sce(unsigned int which, unsigned int chan,
331 return clk_gat_sce(which, chan, source);
335 * Periods of the internal clock sources in nanoseconds.
337 static const unsigned int clock_period[32] = {
338 [1] = 100, /* 10 MHz */
339 [2] = 1000, /* 1 MHz */
340 [3] = 10000, /* 100 kHz */
341 [4] = 100000, /* 10 kHz */
342 [5] = 1000000, /* 1 kHz */
343 [11] = 50, /* 20 MHz (enhanced boards) */
344 /* clock sources 12 and later reserved for enhanced boards */
348 * Timestamp timer configuration register (for new PCIe boards).
350 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
351 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
352 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
355 * Periods of the timestamp timer clock sources in nanoseconds.
357 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
358 1, /* 1 nanosecond (but with 20 ns granularity). */
359 1000, /* 1 microsecond. */
360 1000000, /* 1 millisecond. */
366 enum dio200_regtype { no_regtype = 0, io_regtype, mmio_regtype };
367 struct dio200_region {
369 unsigned long iobase; /* I/O base address */
370 unsigned char __iomem *membase; /* mapped MMIO base address */
372 enum dio200_regtype regtype;
376 * Board descriptions.
379 enum dio200_bustype { isa_bustype, pci_bustype };
384 pc215e_model, pci215_model, pcie215_model,
387 pc272e_model, pci272_model,
391 enum dio200_layout_idx {
408 struct dio200_board {
410 unsigned short devid;
411 enum dio200_bustype bustype;
412 enum dio200_model model;
413 enum dio200_layout_idx layout;
414 unsigned char mainbar;
415 unsigned char mainshift;
416 unsigned int mainsize;
419 static const struct dio200_board dio200_boards[] = {
423 .bustype = isa_bustype,
424 .model = pc212e_model,
425 .layout = pc212_layout,
426 .mainsize = DIO200_IO_SIZE,
430 .bustype = isa_bustype,
431 .model = pc214e_model,
432 .layout = pc214_layout,
433 .mainsize = DIO200_IO_SIZE,
437 .bustype = isa_bustype,
438 .model = pc215e_model,
439 .layout = pc215_layout,
440 .mainsize = DIO200_IO_SIZE,
444 .bustype = isa_bustype,
445 .model = pc218e_model,
446 .layout = pc218_layout,
447 .mainsize = DIO200_IO_SIZE,
451 .bustype = isa_bustype,
452 .model = pc272e_model,
453 .layout = pc272_layout,
454 .mainsize = DIO200_IO_SIZE,
460 .devid = PCI_DEVICE_ID_AMPLICON_PCI215,
461 .bustype = pci_bustype,
462 .model = pci215_model,
463 .layout = pc215_layout,
465 .mainsize = DIO200_IO_SIZE,
469 .devid = PCI_DEVICE_ID_AMPLICON_PCI272,
470 .bustype = pci_bustype,
471 .model = pci272_model,
472 .layout = pc272_layout,
474 .mainsize = DIO200_IO_SIZE,
478 .devid = PCI_DEVICE_ID_AMPLICON_PCIE215,
479 .bustype = pci_bustype,
480 .model = pcie215_model,
481 .layout = pcie215_layout,
484 .mainsize = DIO200_PCIE_IO_SIZE,
488 .devid = PCI_DEVICE_ID_AMPLICON_PCIE236,
489 .bustype = pci_bustype,
490 .model = pcie236_model,
491 .layout = pcie236_layout,
494 .mainsize = DIO200_PCIE_IO_SIZE,
498 .devid = PCI_DEVICE_ID_AMPLICON_PCIE296,
499 .bustype = pci_bustype,
500 .model = pcie296_model,
501 .layout = pcie296_layout,
504 .mainsize = DIO200_PCIE_IO_SIZE,
510 * Layout descriptions - some ISA and PCI board descriptions share the same
514 enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer };
516 #define DIO200_MAX_SUBDEVS 8
517 #define DIO200_MAX_ISNS 6
519 struct dio200_layout {
520 unsigned short n_subdevs; /* number of subdevices */
521 unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */
522 unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */
523 char has_int_sce; /* has interrupt enable/status register */
524 char has_clk_gat_sce; /* has clock/gate selection registers */
525 char has_enhancements; /* has enhanced features */
528 static const struct dio200_layout dio200_layouts[] = {
532 .sdtype = {sd_8255, sd_8254, sd_8254, sd_8254,
535 .sdinfo = {0x00, 0x08, 0x0C, 0x10, 0x14,
538 .has_clk_gat_sce = 1,
542 .sdtype = {sd_8255, sd_8255, sd_8254,
544 .sdinfo = {0x00, 0x08, 0x10, 0x01},
546 .has_clk_gat_sce = 0,
551 .sdtype = {sd_8255, sd_8255, sd_8254,
554 .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
556 .has_clk_gat_sce = 1,
561 .sdtype = {sd_8254, sd_8254, sd_8255, sd_8254,
564 .sdinfo = {0x00, 0x04, 0x08, 0x0C, 0x10,
568 .has_clk_gat_sce = 1,
573 .sdtype = {sd_8255, sd_8255, sd_8255,
575 .sdinfo = {0x00, 0x08, 0x10, 0x3F},
577 .has_clk_gat_sce = 0,
582 .sdtype = {sd_8255, sd_none, sd_8255, sd_none,
583 sd_8254, sd_8254, sd_timer, sd_intr},
584 .sdinfo = {0x00, 0x00, 0x08, 0x00,
585 0x10, 0x14, 0x00, 0x3F},
587 .has_clk_gat_sce = 1,
588 .has_enhancements = 1,
592 .sdtype = {sd_8255, sd_none, sd_none, sd_none,
593 sd_8254, sd_8254, sd_timer, sd_intr},
594 .sdinfo = {0x00, 0x00, 0x00, 0x00,
595 0x10, 0x14, 0x00, 0x3F},
597 .has_clk_gat_sce = 1,
598 .has_enhancements = 1,
602 .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
603 sd_8254, sd_8254, sd_timer, sd_intr},
604 .sdinfo = {0x00, 0x04, 0x08, 0x0C,
605 0x10, 0x14, 0x00, 0x3F},
607 .has_clk_gat_sce = 1,
608 .has_enhancements = 1,
613 /* this structure is for data unique to this hardware driver. If
614 several hardware drivers keep similar information in this structure,
615 feel free to suggest moving the variable to the struct comedi_device struct.
617 struct dio200_private {
618 struct dio200_region io; /* Register region */
622 struct dio200_subdev_8254 {
623 unsigned int ofs; /* Counter base offset */
624 unsigned int clk_sce_ofs; /* CLK_SCE base address */
625 unsigned int gat_sce_ofs; /* GAT_SCE base address */
626 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
627 unsigned int clock_src[3]; /* Current clock sources */
628 unsigned int gate_src[3]; /* Current gate sources */
632 struct dio200_subdev_8255 {
633 unsigned int ofs; /* DIO base offset */
636 struct dio200_subdev_intr {
640 unsigned int valid_isns;
641 unsigned int enabled_isns;
642 unsigned int stopcount;
646 static inline const struct dio200_layout *
647 dio200_board_layout(const struct dio200_board *board)
649 return &dio200_layouts[board->layout];
652 static inline const struct dio200_layout *
653 dio200_dev_layout(struct comedi_device *dev)
655 return dio200_board_layout(comedi_board(dev));
658 static inline bool is_pci_board(const struct dio200_board *board)
660 return DO_PCI && board->bustype == pci_bustype;
663 static inline bool is_isa_board(const struct dio200_board *board)
665 return DO_ISA && board->bustype == isa_bustype;
669 * Read 8-bit register.
671 static unsigned char dio200_read8(struct comedi_device *dev,
674 const struct dio200_board *thisboard = comedi_board(dev);
675 struct dio200_private *devpriv = dev->private;
677 offset <<= thisboard->mainshift;
678 if (devpriv->io.regtype == io_regtype)
679 return inb(devpriv->io.u.iobase + offset);
681 return readb(devpriv->io.u.membase + offset);
685 * Write 8-bit register.
687 static void dio200_write8(struct comedi_device *dev, unsigned int offset,
690 const struct dio200_board *thisboard = comedi_board(dev);
691 struct dio200_private *devpriv = dev->private;
693 offset <<= thisboard->mainshift;
694 if (devpriv->io.regtype == io_regtype)
695 outb(val, devpriv->io.u.iobase + offset);
697 writeb(val, devpriv->io.u.membase + offset);
701 * Read 32-bit register.
703 static unsigned int dio200_read32(struct comedi_device *dev,
706 const struct dio200_board *thisboard = comedi_board(dev);
707 struct dio200_private *devpriv = dev->private;
709 offset <<= thisboard->mainshift;
710 if (devpriv->io.regtype == io_regtype)
711 return inl(devpriv->io.u.iobase + offset);
713 return readl(devpriv->io.u.membase + offset);
717 * Write 32-bit register.
719 static void dio200_write32(struct comedi_device *dev, unsigned int offset,
722 const struct dio200_board *thisboard = comedi_board(dev);
723 struct dio200_private *devpriv = dev->private;
725 offset <<= thisboard->mainshift;
726 if (devpriv->io.regtype == io_regtype)
727 outl(val, devpriv->io.u.iobase + offset);
729 writel(val, devpriv->io.u.membase + offset);
733 * This function looks for a board matching the supplied PCI device.
735 static const struct dio200_board *
736 dio200_find_pci_board(struct pci_dev *pci_dev)
740 for (i = 0; i < ARRAY_SIZE(dio200_boards); i++)
741 if (is_pci_board(&dio200_boards[i]) &&
742 pci_dev->device == dio200_boards[i].devid)
743 return &dio200_boards[i];
748 * This function checks and requests an I/O region, reporting an error
749 * if there is a conflict.
752 dio200_request_region(struct comedi_device *dev,
753 unsigned long from, unsigned long extent)
755 if (!from || !request_region(from, extent, DIO200_DRIVER_NAME)) {
756 dev_err(dev->class_dev, "I/O port conflict (%#lx,%lu)!\n",
764 * 'insn_bits' function for an 'INTERRUPT' subdevice.
767 dio200_subdev_intr_insn_bits(struct comedi_device *dev,
768 struct comedi_subdevice *s,
769 struct comedi_insn *insn, unsigned int *data)
771 const struct dio200_layout *layout = dio200_dev_layout(dev);
772 struct dio200_subdev_intr *subpriv = s->private;
774 if (layout->has_int_sce) {
775 /* Just read the interrupt status register. */
776 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
778 /* No interrupt status register. */
786 * Called to stop acquisition for an 'INTERRUPT' subdevice.
788 static void dio200_stop_intr(struct comedi_device *dev,
789 struct comedi_subdevice *s)
791 const struct dio200_layout *layout = dio200_dev_layout(dev);
792 struct dio200_subdev_intr *subpriv = s->private;
795 subpriv->enabled_isns = 0;
796 if (layout->has_int_sce)
797 dio200_write8(dev, subpriv->ofs, 0);
801 * Called to start acquisition for an 'INTERRUPT' subdevice.
803 static int dio200_start_intr(struct comedi_device *dev,
804 struct comedi_subdevice *s)
808 const struct dio200_layout *layout = dio200_dev_layout(dev);
809 struct dio200_subdev_intr *subpriv = s->private;
810 struct comedi_cmd *cmd = &s->async->cmd;
813 if (!subpriv->continuous && subpriv->stopcount == 0) {
814 /* An empty acquisition! */
815 s->async->events |= COMEDI_CB_EOA;
819 /* Determine interrupt sources to enable. */
822 for (n = 0; n < cmd->chanlist_len; n++)
823 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
825 isn_bits &= subpriv->valid_isns;
826 /* Enable interrupt sources. */
827 subpriv->enabled_isns = isn_bits;
828 if (layout->has_int_sce)
829 dio200_write8(dev, subpriv->ofs, isn_bits);
836 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
839 dio200_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
840 unsigned int trignum)
842 struct dio200_subdev_intr *subpriv;
849 subpriv = s->private;
851 spin_lock_irqsave(&subpriv->spinlock, flags);
852 s->async->inttrig = NULL;
854 event = dio200_start_intr(dev, s);
856 spin_unlock_irqrestore(&subpriv->spinlock, flags);
859 comedi_event(dev, s);
865 * This is called from the interrupt service routine to handle a read
866 * scan on an 'INTERRUPT' subdevice.
868 static int dio200_handle_read_intr(struct comedi_device *dev,
869 struct comedi_subdevice *s)
871 const struct dio200_layout *layout = dio200_dev_layout(dev);
872 struct dio200_subdev_intr *subpriv = s->private;
875 unsigned cur_enabled;
876 unsigned int oldevents;
881 spin_lock_irqsave(&subpriv->spinlock, flags);
882 oldevents = s->async->events;
883 if (layout->has_int_sce) {
885 * Collect interrupt sources that have triggered and disable
886 * them temporarily. Loop around until no extra interrupt
887 * sources have triggered, at which point, the valid part of
888 * the interrupt status register will read zero, clearing the
889 * cause of the interrupt.
891 * Mask off interrupt sources already seen to avoid infinite
892 * loop in case of misconfiguration.
894 cur_enabled = subpriv->enabled_isns;
895 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
896 subpriv->valid_isns & ~triggered)) != 0) {
897 triggered |= intstat;
898 cur_enabled &= ~triggered;
899 dio200_write8(dev, subpriv->ofs, cur_enabled);
903 * No interrupt status register. Assume the single interrupt
904 * source has triggered.
906 triggered = subpriv->enabled_isns;
911 * Some interrupt sources have triggered and have been
912 * temporarily disabled to clear the cause of the interrupt.
914 * Reenable them NOW to minimize the time they are disabled.
916 cur_enabled = subpriv->enabled_isns;
917 if (layout->has_int_sce)
918 dio200_write8(dev, subpriv->ofs, cur_enabled);
920 if (subpriv->active) {
922 * The command is still active.
924 * Ignore interrupt sources that the command isn't
925 * interested in (just in case there's a race
928 if (triggered & subpriv->enabled_isns) {
929 /* Collect scan data. */
931 unsigned int n, ch, len;
934 len = s->async->cmd.chanlist_len;
935 for (n = 0; n < len; n++) {
936 ch = CR_CHAN(s->async->cmd.chanlist[n]);
937 if (triggered & (1U << ch))
940 /* Write the scan to the buffer. */
941 if (comedi_buf_put(s->async, val)) {
942 s->async->events |= (COMEDI_CB_BLOCK |
945 /* Error! Stop acquisition. */
946 dio200_stop_intr(dev, s);
947 s->async->events |= COMEDI_CB_ERROR
948 | COMEDI_CB_OVERFLOW;
949 comedi_error(dev, "buffer overflow");
952 /* Check for end of acquisition. */
953 if (!subpriv->continuous) {
954 /* stop_src == TRIG_COUNT */
955 if (subpriv->stopcount > 0) {
956 subpriv->stopcount--;
957 if (subpriv->stopcount == 0) {
960 dio200_stop_intr(dev,
968 spin_unlock_irqrestore(&subpriv->spinlock, flags);
970 if (oldevents != s->async->events)
971 comedi_event(dev, s);
973 return (triggered != 0);
977 * 'cancel' function for an 'INTERRUPT' subdevice.
979 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
980 struct comedi_subdevice *s)
982 struct dio200_subdev_intr *subpriv = s->private;
985 spin_lock_irqsave(&subpriv->spinlock, flags);
987 dio200_stop_intr(dev, s);
989 spin_unlock_irqrestore(&subpriv->spinlock, flags);
995 * 'do_cmdtest' function for an 'INTERRUPT' subdevice.
998 dio200_subdev_intr_cmdtest(struct comedi_device *dev,
999 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1003 /* Step 1 : check if triggers are trivially valid */
1005 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
1006 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
1007 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
1008 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1009 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
1014 /* Step 2a : make sure trigger sources are unique */
1016 err |= cfc_check_trigger_is_unique(cmd->start_src);
1017 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1019 /* Step 2b : and mutually compatible */
1024 /* Step 3: check if arguments are trivially valid */
1026 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1027 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
1028 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
1029 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1031 switch (cmd->stop_src) {
1033 /* any count allowed */
1036 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1045 /* step 4: fix up any arguments */
1047 /* if (err) return 4; */
1053 * 'do_cmd' function for an 'INTERRUPT' subdevice.
1055 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
1056 struct comedi_subdevice *s)
1058 struct comedi_cmd *cmd = &s->async->cmd;
1059 struct dio200_subdev_intr *subpriv = s->private;
1060 unsigned long flags;
1063 spin_lock_irqsave(&subpriv->spinlock, flags);
1064 subpriv->active = 1;
1066 /* Set up end of acquisition. */
1067 switch (cmd->stop_src) {
1069 subpriv->continuous = 0;
1070 subpriv->stopcount = cmd->stop_arg;
1074 subpriv->continuous = 1;
1075 subpriv->stopcount = 0;
1079 /* Set up start of acquisition. */
1080 switch (cmd->start_src) {
1082 s->async->inttrig = dio200_inttrig_start_intr;
1086 event = dio200_start_intr(dev, s);
1089 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1092 comedi_event(dev, s);
1098 * This function initializes an 'INTERRUPT' subdevice.
1101 dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s,
1102 unsigned int offset, unsigned valid_isns)
1104 const struct dio200_layout *layout = dio200_dev_layout(dev);
1105 struct dio200_subdev_intr *subpriv;
1107 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1109 dev_err(dev->class_dev, "error! out of memory!\n");
1112 subpriv->ofs = offset;
1113 subpriv->valid_isns = valid_isns;
1114 spin_lock_init(&subpriv->spinlock);
1116 if (layout->has_int_sce)
1117 /* Disable interrupt sources. */
1118 dio200_write8(dev, subpriv->ofs, 0);
1120 s->private = subpriv;
1121 s->type = COMEDI_SUBD_DI;
1122 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
1123 if (layout->has_int_sce) {
1124 s->n_chan = DIO200_MAX_ISNS;
1125 s->len_chanlist = DIO200_MAX_ISNS;
1127 /* No interrupt source register. Support single channel. */
1129 s->len_chanlist = 1;
1131 s->range_table = &range_digital;
1133 s->insn_bits = dio200_subdev_intr_insn_bits;
1134 s->do_cmdtest = dio200_subdev_intr_cmdtest;
1135 s->do_cmd = dio200_subdev_intr_cmd;
1136 s->cancel = dio200_subdev_intr_cancel;
1142 * This function cleans up an 'INTERRUPT' subdevice.
1145 dio200_subdev_intr_cleanup(struct comedi_device *dev,
1146 struct comedi_subdevice *s)
1148 struct dio200_subdev_intr *subpriv = s->private;
1153 * Interrupt service routine.
1155 static irqreturn_t dio200_interrupt(int irq, void *d)
1157 struct comedi_device *dev = d;
1158 struct dio200_private *devpriv = dev->private;
1159 struct comedi_subdevice *s;
1165 if (devpriv->intr_sd >= 0) {
1166 s = &dev->subdevices[devpriv->intr_sd];
1167 handled = dio200_handle_read_intr(dev, s);
1172 return IRQ_RETVAL(handled);
1176 * Read an '8254' counter subdevice channel.
1179 dio200_subdev_8254_read_chan(struct comedi_device *dev,
1180 struct comedi_subdevice *s, unsigned int chan)
1182 struct dio200_subdev_8254 *subpriv = s->private;
1187 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
1189 val = dio200_read8(dev, subpriv->ofs + chan);
1190 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
1195 * Write an '8254' subdevice channel.
1198 dio200_subdev_8254_write_chan(struct comedi_device *dev,
1199 struct comedi_subdevice *s, unsigned int chan,
1202 struct dio200_subdev_8254 *subpriv = s->private;
1204 /* write lsb, msb */
1205 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
1206 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
1210 * Set mode of an '8254' subdevice channel.
1213 dio200_subdev_8254_set_mode(struct comedi_device *dev,
1214 struct comedi_subdevice *s, unsigned int chan,
1217 struct dio200_subdev_8254 *subpriv = s->private;
1221 byte |= 0x30; /* access order: lsb, msb */
1222 byte |= (mode & 0xf); /* counter mode and BCD|binary */
1223 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
1227 * Read status byte of an '8254' counter subdevice channel.
1230 dio200_subdev_8254_status(struct comedi_device *dev,
1231 struct comedi_subdevice *s, unsigned int chan)
1233 struct dio200_subdev_8254 *subpriv = s->private;
1236 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
1237 0xe0 | (2 << chan));
1239 return dio200_read8(dev, subpriv->ofs + chan);
1243 * Handle 'insn_read' for an '8254' counter subdevice.
1246 dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s,
1247 struct comedi_insn *insn, unsigned int *data)
1249 struct dio200_subdev_8254 *subpriv = s->private;
1250 int chan = CR_CHAN(insn->chanspec);
1252 unsigned long flags;
1254 for (n = 0; n < insn->n; n++) {
1255 spin_lock_irqsave(&subpriv->spinlock, flags);
1256 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
1257 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1263 * Handle 'insn_write' for an '8254' counter subdevice.
1266 dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s,
1267 struct comedi_insn *insn, unsigned int *data)
1269 struct dio200_subdev_8254 *subpriv = s->private;
1270 int chan = CR_CHAN(insn->chanspec);
1272 unsigned long flags;
1274 for (n = 0; n < insn->n; n++) {
1275 spin_lock_irqsave(&subpriv->spinlock, flags);
1276 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
1277 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1283 * Set gate source for an '8254' counter subdevice channel.
1286 dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
1287 struct comedi_subdevice *s,
1288 unsigned int counter_number,
1289 unsigned int gate_src)
1291 const struct dio200_layout *layout = dio200_dev_layout(dev);
1292 struct dio200_subdev_8254 *subpriv = s->private;
1295 if (!layout->has_clk_gat_sce)
1297 if (counter_number > 2)
1299 if (gate_src > (layout->has_enhancements ? 31 : 7))
1302 subpriv->gate_src[counter_number] = gate_src;
1303 byte = gat_sce(subpriv->which, counter_number, gate_src);
1304 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
1310 * Get gate source for an '8254' counter subdevice channel.
1313 dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
1314 struct comedi_subdevice *s,
1315 unsigned int counter_number)
1317 const struct dio200_layout *layout = dio200_dev_layout(dev);
1318 struct dio200_subdev_8254 *subpriv = s->private;
1320 if (!layout->has_clk_gat_sce)
1322 if (counter_number > 2)
1325 return subpriv->gate_src[counter_number];
1329 * Set clock source for an '8254' counter subdevice channel.
1332 dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
1333 struct comedi_subdevice *s,
1334 unsigned int counter_number,
1335 unsigned int clock_src)
1337 const struct dio200_layout *layout = dio200_dev_layout(dev);
1338 struct dio200_subdev_8254 *subpriv = s->private;
1341 if (!layout->has_clk_gat_sce)
1343 if (counter_number > 2)
1345 if (clock_src > (layout->has_enhancements ? 31 : 7))
1348 subpriv->clock_src[counter_number] = clock_src;
1349 byte = clk_sce(subpriv->which, counter_number, clock_src);
1350 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
1356 * Get clock source for an '8254' counter subdevice channel.
1359 dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
1360 struct comedi_subdevice *s,
1361 unsigned int counter_number,
1362 unsigned int *period_ns)
1364 const struct dio200_layout *layout = dio200_dev_layout(dev);
1365 struct dio200_subdev_8254 *subpriv = s->private;
1368 if (!layout->has_clk_gat_sce)
1370 if (counter_number > 2)
1373 clock_src = subpriv->clock_src[counter_number];
1374 *period_ns = clock_period[clock_src];
1379 * Handle 'insn_config' for an '8254' counter subdevice.
1382 dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s,
1383 struct comedi_insn *insn, unsigned int *data)
1385 struct dio200_subdev_8254 *subpriv = s->private;
1387 int chan = CR_CHAN(insn->chanspec);
1388 unsigned long flags;
1390 spin_lock_irqsave(&subpriv->spinlock, flags);
1392 case INSN_CONFIG_SET_COUNTER_MODE:
1393 if (data[1] > (I8254_MODE5 | I8254_BINARY))
1396 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
1398 case INSN_CONFIG_8254_READ_STATUS:
1399 data[1] = dio200_subdev_8254_status(dev, s, chan);
1401 case INSN_CONFIG_SET_GATE_SRC:
1402 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
1406 case INSN_CONFIG_GET_GATE_SRC:
1407 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
1414 case INSN_CONFIG_SET_CLOCK_SRC:
1415 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
1419 case INSN_CONFIG_GET_CLOCK_SRC:
1420 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
1431 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1432 return ret < 0 ? ret : insn->n;
1436 * This function initializes an '8254' counter subdevice.
1439 dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s,
1440 unsigned int offset)
1442 const struct dio200_layout *layout = dio200_dev_layout(dev);
1443 struct dio200_subdev_8254 *subpriv;
1446 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1448 dev_err(dev->class_dev, "error! out of memory!\n");
1452 s->private = subpriv;
1453 s->type = COMEDI_SUBD_COUNTER;
1454 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1456 s->maxdata = 0xFFFF;
1457 s->insn_read = dio200_subdev_8254_read;
1458 s->insn_write = dio200_subdev_8254_write;
1459 s->insn_config = dio200_subdev_8254_config;
1461 spin_lock_init(&subpriv->spinlock);
1462 subpriv->ofs = offset;
1463 if (layout->has_clk_gat_sce) {
1464 /* Derive CLK_SCE and GAT_SCE register offsets from
1466 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
1467 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
1468 subpriv->which = (offset >> 2) & 1;
1471 /* Initialize channels. */
1472 for (chan = 0; chan < 3; chan++) {
1473 dio200_subdev_8254_set_mode(dev, s, chan,
1474 I8254_MODE0 | I8254_BINARY);
1475 if (layout->has_clk_gat_sce) {
1476 /* Gate source 0 is VCC (logic 1). */
1477 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
1478 /* Clock source 0 is the dedicated clock input. */
1479 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
1487 * This function cleans up an '8254' counter subdevice.
1490 dio200_subdev_8254_cleanup(struct comedi_device *dev,
1491 struct comedi_subdevice *s)
1493 struct dio200_subdev_intr *subpriv = s->private;
1498 * This function sets I/O directions for an '8255' DIO subdevice.
1500 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
1501 struct comedi_subdevice *s)
1503 struct dio200_subdev_8255 *subpriv = s->private;
1507 /* 1 in io_bits indicates output, 1 in config indicates input */
1508 if (!(s->io_bits & 0x0000ff))
1510 if (!(s->io_bits & 0x00ff00))
1512 if (!(s->io_bits & 0x0f0000))
1513 config |= CR_C_LO_IO;
1514 if (!(s->io_bits & 0xf00000))
1515 config |= CR_C_HI_IO;
1516 dio200_write8(dev, subpriv->ofs + 3, config);
1520 * Handle 'insn_bits' for an '8255' DIO subdevice.
1522 static int dio200_subdev_8255_bits(struct comedi_device *dev,
1523 struct comedi_subdevice *s,
1524 struct comedi_insn *insn, unsigned int *data)
1526 struct dio200_subdev_8255 *subpriv = s->private;
1529 s->state &= ~data[0];
1530 s->state |= (data[0] & data[1]);
1532 dio200_write8(dev, subpriv->ofs, s->state & 0xff);
1533 if (data[0] & 0xff00)
1534 dio200_write8(dev, subpriv->ofs + 1,
1535 (s->state >> 8) & 0xff);
1536 if (data[0] & 0xff0000)
1537 dio200_write8(dev, subpriv->ofs + 2,
1538 (s->state >> 16) & 0xff);
1540 data[1] = dio200_read8(dev, subpriv->ofs);
1541 data[1] |= dio200_read8(dev, subpriv->ofs + 1) << 8;
1542 data[1] |= dio200_read8(dev, subpriv->ofs + 2) << 16;
1547 * Handle 'insn_config' for an '8255' DIO subdevice.
1549 static int dio200_subdev_8255_config(struct comedi_device *dev,
1550 struct comedi_subdevice *s,
1551 struct comedi_insn *insn,
1557 mask = 1 << CR_CHAN(insn->chanspec);
1558 if (mask & 0x0000ff)
1560 else if (mask & 0x00ff00)
1562 else if (mask & 0x0f0000)
1567 case INSN_CONFIG_DIO_INPUT:
1568 s->io_bits &= ~bits;
1570 case INSN_CONFIG_DIO_OUTPUT:
1573 case INSN_CONFIG_DIO_QUERY:
1574 data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT;
1580 dio200_subdev_8255_set_dir(dev, s);
1585 * This function initializes an '8255' DIO subdevice.
1587 * offset is the offset to the 8255 chip.
1589 static int dio200_subdev_8255_init(struct comedi_device *dev,
1590 struct comedi_subdevice *s,
1591 unsigned int offset)
1593 struct dio200_subdev_8255 *subpriv;
1595 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1598 subpriv->ofs = offset;
1599 s->private = subpriv;
1600 s->type = COMEDI_SUBD_DIO;
1601 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1603 s->range_table = &range_digital;
1605 s->insn_bits = dio200_subdev_8255_bits;
1606 s->insn_config = dio200_subdev_8255_config;
1609 dio200_subdev_8255_set_dir(dev, s);
1614 * This function cleans up an '8255' DIO subdevice.
1616 static void dio200_subdev_8255_cleanup(struct comedi_device *dev,
1617 struct comedi_subdevice *s)
1619 struct dio200_subdev_8255 *subpriv = s->private;
1625 * Handle 'insn_read' for a timer subdevice.
1627 static int dio200_subdev_timer_read(struct comedi_device *dev,
1628 struct comedi_subdevice *s,
1629 struct comedi_insn *insn,
1634 for (n = 0; n < insn->n; n++)
1635 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
1640 * Reset timer subdevice.
1642 static void dio200_subdev_timer_reset(struct comedi_device *dev,
1643 struct comedi_subdevice *s)
1647 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1648 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
1649 dio200_write32(dev, DIO200_TS_CONFIG, clock);
1653 * Get timer subdevice clock source and period.
1655 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
1656 struct comedi_subdevice *s,
1658 unsigned int *period)
1662 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1664 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
1665 ts_clock_period[clk] : 0;
1669 * Set timer subdevice clock source.
1671 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
1672 struct comedi_subdevice *s,
1675 if (src > TS_CONFIG_MAX_CLK_SRC)
1677 dio200_write32(dev, DIO200_TS_CONFIG, src);
1682 * Handle 'insn_config' for a timer subdevice.
1684 static int dio200_subdev_timer_config(struct comedi_device *dev,
1685 struct comedi_subdevice *s,
1686 struct comedi_insn *insn,
1692 case INSN_CONFIG_RESET:
1693 dio200_subdev_timer_reset(dev, s);
1695 case INSN_CONFIG_SET_CLOCK_SRC:
1696 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
1700 case INSN_CONFIG_GET_CLOCK_SRC:
1701 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
1707 return ret < 0 ? ret : insn->n;
1711 * This function initializes a timer subdevice.
1713 * Uses the timestamp timer registers. There is only one timestamp timer.
1715 static int dio200_subdev_timer_init(struct comedi_device *dev,
1716 struct comedi_subdevice *s)
1718 s->type = COMEDI_SUBD_TIMER;
1719 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
1721 s->maxdata = 0xFFFFFFFF;
1722 s->insn_read = dio200_subdev_timer_read;
1723 s->insn_config = dio200_subdev_timer_config;
1728 * This function cleans up a timer subdevice.
1730 static void dio200_subdev_timer_cleanup(struct comedi_device *dev,
1731 struct comedi_subdevice *s)
1733 /* Nothing to do. */
1737 * This function does some special set-up for the PCIe boards
1738 * PCIe215, PCIe236, PCIe296.
1740 static int dio200_pcie_board_setup(struct comedi_device *dev)
1742 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1743 void __iomem *brbase;
1744 resource_size_t brlen;
1747 * The board uses Altera Cyclone IV with PCI-Express hard IP.
1748 * The FPGA configuration has the PCI-Express Avalon-MM Bridge
1749 * Control registers in PCI BAR 0, offset 0, and the length of
1750 * these registers is 0x4000.
1752 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
1753 * Enable" register at offset 0x50 to allow generation of PCIe
1754 * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
1756 brlen = pci_resource_len(pcidev, 0);
1757 if (brlen < 0x4000 ||
1758 !(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM)) {
1759 dev_err(dev->class_dev, "error! bad PCI region!\n");
1762 brbase = ioremap_nocache(pci_resource_start(pcidev, 0), brlen);
1764 dev_err(dev->class_dev, "error! failed to map registers!\n");
1767 writel(0x80, brbase + 0x50);
1769 /* Enable "enhanced" features of board. */
1770 dio200_write8(dev, DIO200_ENHANCE, 1);
1774 static void dio200_report_attach(struct comedi_device *dev, unsigned int irq)
1776 const struct dio200_board *thisboard = comedi_board(dev);
1777 struct dio200_private *devpriv = dev->private;
1778 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1782 if (is_isa_board(thisboard))
1783 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1784 "(base %#lx) ", devpriv->io.u.iobase);
1785 else if (is_pci_board(thisboard))
1786 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1787 "(pci %s) ", pci_name(pcidev));
1791 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1793 (dev->irq ? "" : " UNAVAILABLE"));
1795 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1797 dev_info(dev->class_dev, "%s %sattached\n", dev->board_name, tmpbuf);
1800 static int dio200_common_attach(struct comedi_device *dev, unsigned int irq,
1801 unsigned long req_irq_flags)
1803 const struct dio200_board *thisboard = comedi_board(dev);
1804 struct dio200_private *devpriv = dev->private;
1805 const struct dio200_layout *layout = dio200_board_layout(thisboard);
1806 struct comedi_subdevice *s;
1811 devpriv->intr_sd = -1;
1812 dev->board_name = thisboard->name;
1814 ret = comedi_alloc_subdevices(dev, layout->n_subdevs);
1818 for (n = 0; n < dev->n_subdevices; n++) {
1819 s = &dev->subdevices[n];
1820 switch (layout->sdtype[n]) {
1822 /* counter subdevice (8254) */
1823 ret = dio200_subdev_8254_init(dev, s,
1829 /* digital i/o subdevice (8255) */
1830 ret = dio200_subdev_8255_init(dev, s,
1836 /* 'INTERRUPT' subdevice */
1838 ret = dio200_subdev_intr_init(dev, s,
1844 devpriv->intr_sd = n;
1846 s->type = COMEDI_SUBD_UNUSED;
1850 /* Only on PCIe boards. */
1852 ret = dio200_subdev_timer_init(dev, s);
1856 s->type = COMEDI_SUBD_UNUSED;
1860 s->type = COMEDI_SUBD_UNUSED;
1864 sdx = devpriv->intr_sd;
1865 if (sdx >= 0 && sdx < dev->n_subdevices)
1866 dev->read_subdev = &dev->subdevices[sdx];
1868 if (request_irq(irq, dio200_interrupt, req_irq_flags,
1869 DIO200_DRIVER_NAME, dev) >= 0) {
1872 dev_warn(dev->class_dev,
1873 "warning! irq %u unavailable!\n", irq);
1876 dio200_report_attach(dev, irq);
1881 * Attach is called by the Comedi core to configure the driver
1882 * for a particular board. If you specified a board_name array
1883 * in the driver structure, dev->board_ptr contains that
1886 static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1888 const struct dio200_board *thisboard = comedi_board(dev);
1889 struct dio200_private *devpriv;
1892 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach\n");
1894 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1897 dev->private = devpriv;
1899 /* Process options and reserve resources according to bus type. */
1900 if (is_isa_board(thisboard)) {
1901 unsigned long iobase;
1904 iobase = it->options[0];
1905 irq = it->options[1];
1906 ret = dio200_request_region(dev, iobase, thisboard->mainsize);
1909 devpriv->io.u.iobase = iobase;
1910 devpriv->io.regtype = io_regtype;
1911 return dio200_common_attach(dev, irq, 0);
1912 } else if (is_pci_board(thisboard)) {
1913 dev_err(dev->class_dev,
1914 "Manual configuration of PCI board '%s' is not supported\n",
1918 dev_err(dev->class_dev, DIO200_DRIVER_NAME
1919 ": BUG! cannot determine board type!\n");
1925 * The auto_attach hook is called at PCI probe time via
1926 * comedi_pci_auto_config(). dev->board_ptr is NULL on entry.
1927 * There should be a board entry matching the supplied PCI device.
1929 static int dio200_auto_attach(struct comedi_device *dev,
1930 unsigned long context_unused)
1932 struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
1933 const struct dio200_board *thisboard;
1934 struct dio200_private *devpriv;
1935 resource_size_t base, len;
1942 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach pci %s\n",
1945 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1948 dev->private = devpriv;
1950 dev->board_ptr = dio200_find_pci_board(pci_dev);
1951 if (dev->board_ptr == NULL) {
1952 dev_err(dev->class_dev, "BUG! cannot determine board type!\n");
1955 thisboard = comedi_board(dev);
1956 ret = comedi_pci_enable(pci_dev, DIO200_DRIVER_NAME);
1958 dev_err(dev->class_dev,
1959 "error! cannot enable PCI device and request regions!\n");
1962 bar = thisboard->mainbar;
1963 base = pci_resource_start(pci_dev, bar);
1964 len = pci_resource_len(pci_dev, bar);
1965 if (len < thisboard->mainsize) {
1966 dev_err(dev->class_dev, "error! PCI region size too small!\n");
1969 if ((pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) != 0) {
1970 devpriv->io.u.membase = ioremap_nocache(base, len);
1971 if (!devpriv->io.u.membase) {
1972 dev_err(dev->class_dev,
1973 "error! cannot remap registers\n");
1976 devpriv->io.regtype = mmio_regtype;
1978 devpriv->io.u.iobase = (unsigned long)base;
1979 devpriv->io.regtype = io_regtype;
1981 switch (thisboard->model) {
1985 ret = dio200_pcie_board_setup(dev);
1992 return dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
1995 static void dio200_detach(struct comedi_device *dev)
1997 const struct dio200_board *thisboard = comedi_board(dev);
1998 struct dio200_private *devpriv = dev->private;
1999 const struct dio200_layout *layout;
2002 if (!thisboard || !devpriv)
2005 free_irq(dev->irq, dev);
2006 if (dev->subdevices) {
2007 layout = dio200_board_layout(thisboard);
2008 for (n = 0; n < dev->n_subdevices; n++) {
2009 struct comedi_subdevice *s = &dev->subdevices[n];
2010 switch (layout->sdtype[n]) {
2012 dio200_subdev_8254_cleanup(dev, s);
2015 dio200_subdev_8255_cleanup(dev, s);
2018 dio200_subdev_intr_cleanup(dev, s);
2021 /* Only on PCIe boards. */
2023 dio200_subdev_timer_cleanup(dev, s);
2030 if (is_isa_board(thisboard)) {
2031 if (devpriv->io.regtype == io_regtype)
2032 release_region(devpriv->io.u.iobase,
2033 thisboard->mainsize);
2034 } else if (is_pci_board(thisboard)) {
2035 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2037 if (devpriv->io.regtype != no_regtype) {
2038 if (devpriv->io.regtype == mmio_regtype)
2039 iounmap(devpriv->io.u.membase);
2040 comedi_pci_disable(pcidev);
2047 * The struct comedi_driver structure tells the Comedi core module
2048 * which functions to call to configure/deconfigure (attach/detach)
2049 * the board, and also about the kernel module that contains
2052 static struct comedi_driver amplc_dio200_driver = {
2053 .driver_name = DIO200_DRIVER_NAME,
2054 .module = THIS_MODULE,
2055 .attach = dio200_attach,
2056 .auto_attach = dio200_auto_attach,
2057 .detach = dio200_detach,
2058 .board_name = &dio200_boards[0].name,
2059 .offset = sizeof(struct dio200_board),
2060 .num_names = ARRAY_SIZE(dio200_boards),
2064 static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = {
2065 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215) },
2066 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272) },
2067 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236) },
2068 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215) },
2069 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296) },
2073 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
2075 static int amplc_dio200_pci_probe(struct pci_dev *dev,
2076 const struct pci_device_id
2079 return comedi_pci_auto_config(dev, &lc_dio200_driver);
2082 static struct pci_driver amplc_dio200_pci_driver = {
2083 .name = DIO200_DRIVER_NAME,
2084 .id_table = dio200_pci_table,
2085 .probe = &lc_dio200_pci_probe,
2086 .remove = comedi_pci_auto_unconfig,
2088 module_comedi_pci_driver(amplc_dio200_driver, amplc_dio200_pci_driver);
2090 module_comedi_driver(amplc_dio200_driver);
2093 MODULE_AUTHOR("Comedi http://www.comedi.org");
2094 MODULE_DESCRIPTION("Comedi low-level driver");
2095 MODULE_LICENSE("GPL");