2 comedi/drivers/amplc_dio200.c
3 Driver for Amplicon PC272E and PCI272 DIO boards.
4 (Support for other boards in Amplicon 200 series may be added at
5 a later date, e.g. PCI215.)
7 Copyright (C) 2005 MEV Ltd. <http://www.mev.co.uk/>
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Driver: amplc_dio200
29 * Description: Amplicon 200 Series Digital I/O
30 * Author: Ian Abbott <abbotti@mev.co.uk>
31 * Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e),
32 * PCI215 (pci215), PCIe215 (pcie215), PC218E (pc218e), PCIe236 (pcie236),
33 * PC272E (pc272e), PCI272 (pci272), PCIe296 (pcie296)
34 * Updated: Wed, 24 Oct 2012 16:22:34 +0100
37 * Configuration options - PC212E, PC214E, PC215E, PC218E, PC272E:
38 * [0] - I/O port base address
39 * [1] - IRQ (optional, but commands won't work without it)
41 * Manual configuration of PCI(e) cards is not supported; they are configured
44 * Passing a zero for an option is the same as leaving it unspecified.
48 * PC212E PC214E PC215E/PCI215
49 * ------------- ------------- -------------
52 * 1 CTR-Y1 PPI-Y PPI-Y
53 * 2 CTR-Y2 CTR-Z1* CTR-Z1
54 * 3 CTR-Z1 INTERRUPT* CTR-Z2
58 * PCIe215 PC218E PCIe236
59 * ------------- ------------- -------------
61 * 0 PPI-X CTR-X1 PPI-X
62 * 1 UNUSED CTR-X2 UNUSED
63 * 2 PPI-Y CTR-Y1 UNUSED
64 * 3 UNUSED CTR-Y2 UNUSED
65 * 4 CTR-Z1 CTR-Z1 CTR-Z1
66 * 5 CTR-Z2 CTR-Z2 CTR-Z2
67 * 6 TIMER INTERRUPT TIMER
68 * 7 INTERRUPT INTERRUPT
70 * PC272E/PCI272 PCIe296
71 * ------------- -------------
82 * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
83 * are configurable as inputs or outputs in four groups:
85 * Port A - channels 0 to 7
86 * Port B - channels 8 to 15
87 * Port CL - channels 16 to 19
88 * Port CH - channels 20 to 23
90 * Only mode 0 of the 8255 chips is supported.
92 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
93 * channel is configured individually with INSN_CONFIG instructions. The
94 * specific type of configuration instruction is specified in data[0].
95 * Some configuration instructions expect an additional parameter in
96 * data[1]; others return a value in data[1]. The following configuration
97 * instructions are supported:
99 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
100 * BCD/binary setting specified in data[1].
102 * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
103 * counter channel into data[1].
105 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
106 * specified in data[1] (this is a hardware-specific value). Not
107 * supported on PC214E. For the other boards, valid clock sources are
110 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
111 * connector. (N.B. for other values, the counter channel's CLKn
112 * pin on the SK1 connector is an output!)
113 * 1. Internal 10 MHz clock.
114 * 2. Internal 1 MHz clock.
115 * 3. Internal 100 kHz clock.
116 * 4. Internal 10 kHz clock.
117 * 5. Internal 1 kHz clock.
118 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
119 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
120 * the SK1 connector. This pin is shared by all three counter
121 * channels on the chip.
123 * For the PCIe boards, clock sources in the range 0 to 31 are allowed
124 * and the following additional clock sources are defined:
126 * 8. HIGH logic level.
127 * 9. LOW logic level.
128 * 10. "Pattern present" signal.
129 * 11. Internal 20 MHz clock.
131 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
132 * clock source in data[1]. For internal clock sources, data[2] is set
133 * to the period in ns.
135 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
136 * specified in data[2] (this is a hardware-specific value). Not
137 * supported on PC214E. For the other boards, valid gate sources are 0
140 * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
141 * 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
142 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
143 * connector. (N.B. for other values, the counter channel's GATn
144 * pin on the SK1 connector is an output!)
145 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
152 * For the PCIe boards, gate sources in the range 0 to 31 are allowed;
153 * the following additional clock sources and clock sources 6 and 7 are
156 * 6. /GAT n, negated version of the counter channel's dedicated
157 * GAT input (negated version of gate source 2).
158 * 7. OUT n-2, the non-inverted output of counter channel n-2
159 * (negated version of gate source 3).
160 * 8. "Pattern present" signal, HIGH while pattern present.
161 * 9. "Pattern occurred" latched signal, latches HIGH when pattern
163 * 10. "Pattern gone away" latched signal, latches LOW when pattern
164 * goes away after it occurred.
165 * 11. Negated "pattern present" signal, LOW while pattern present
166 * (negated version of gate source 8).
167 * 12. Negated "pattern occurred" latched signal, latches LOW when
168 * pattern occurs (negated version of gate source 9).
169 * 13. Negated "pattern gone away" latched signal, latches LOW when
170 * pattern goes away after it occurred (negated version of gate
173 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
176 * Clock and gate interconnection notes:
178 * 1. Clock source OUT n-1 is the output of the preceding channel on the
179 * same counter subdevice if n > 0, or the output of channel 2 on the
180 * preceding counter subdevice (see note 3) if n = 0.
182 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
183 * same counter subdevice if n = 2, or the inverted output of channel n+1
184 * on the preceding counter subdevice (see note 3) if n < 2.
186 * 3. The counter subdevices are connected in a ring, so the highest
187 * counter subdevice precedes the lowest.
189 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
191 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
192 * digital inputs come from the interrupt status register. The number of
193 * channels matches the number of interrupt sources. The PC214E does not
194 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
199 * PC212E PC214E PC215E/PCI215
200 * ------------- ------------- -------------
202 * 0 PPI-X-C0 JUMPER-J5 PPI-X-C0
203 * 1 PPI-X-C3 PPI-X-C3
204 * 2 CTR-Y1-OUT1 PPI-Y-C0
205 * 3 CTR-Y2-OUT1 PPI-Y-C3
206 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1
207 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1
209 * PCIe215 PC218E PCIe236
210 * ------------- ------------- -------------
212 * 0 PPI-X-C0 CTR-X1-OUT1 PPI-X-C0
213 * 1 PPI-X-C3 CTR-X2-OUT1 PPI-X-C3
214 * 2 PPI-Y-C0 CTR-Y1-OUT1 unused
215 * 3 PPI-Y-C3 CTR-Y2-OUT1 unused
216 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
217 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
219 * PC272E/PCI272 PCIe296
220 * ------------- -------------
222 * 0 PPI-X-C0 PPI-X1-C0
223 * 1 PPI-X-C3 PPI-X1-C3
224 * 2 PPI-Y-C0 PPI-Y1-C0
225 * 3 PPI-Y-C3 PPI-Y1-C3
226 * 4 PPI-Z-C0 CTR-Z1-OUT1
227 * 5 PPI-Z-C3 CTR-Z2-OUT1
229 * When an interrupt source is enabled in the interrupt source enable
230 * register, a rising edge on the source signal latches the corresponding
231 * bit to 1 in the interrupt status register.
233 * When the interrupt status register value as a whole (actually, just the
234 * 6 least significant bits) goes from zero to non-zero, the board will
235 * generate an interrupt. For level-triggered hardware interrupts (PCI
236 * card), the interrupt will remain asserted until the interrupt status
237 * register is cleared to zero. For edge-triggered hardware interrupts
238 * (ISA card), no further interrupts will occur until the interrupt status
239 * register is cleared to zero. To clear a bit to zero in the interrupt
240 * status register, the corresponding interrupt source must be disabled
241 * in the interrupt source enable register (there is no separate interrupt
244 * The PC214E does not have an interrupt source enable register or an
245 * interrupt status register; its 'INTERRUPT' subdevice has a single
246 * channel and its interrupt source is selected by the position of jumper
251 * The driver supports a read streaming acquisition command on the
252 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
253 * to be enabled. All channels will be sampled together (convert_src ==
254 * TRIG_NOW). The scan begins a short time after the hardware interrupt
255 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
256 * scan_begin_arg == 0). The value read from the interrupt status register
257 * is packed into a short value, one bit per requested channel, in the
258 * order they appear in the channel list.
261 #include <linux/interrupt.h>
262 #include <linux/slab.h>
264 #include "../comedidev.h"
266 #include "comedi_fc.h"
269 #define DIO200_DRIVER_NAME "amplc_dio200"
271 #define DO_ISA IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_ISA)
272 #define DO_PCI IS_ENABLED(CONFIG_COMEDI_AMPLC_DIO200_PCI)
275 #define PCI_VENDOR_ID_AMPLICON 0x14dc
276 #define PCI_DEVICE_ID_AMPLICON_PCI272 0x000a
277 #define PCI_DEVICE_ID_AMPLICON_PCI215 0x000b
278 #define PCI_DEVICE_ID_AMPLICON_PCIE236 0x0011
279 #define PCI_DEVICE_ID_AMPLICON_PCIE215 0x0012
280 #define PCI_DEVICE_ID_AMPLICON_PCIE296 0x0014
282 /* 8255 control register bits */
283 #define CR_C_LO_IO 0x01
285 #define CR_B_MODE 0x04
286 #define CR_C_HI_IO 0x08
288 #define CR_A_MODE(a) ((a)<<5)
291 /* 200 series registers */
292 #define DIO200_IO_SIZE 0x20
293 #define DIO200_PCIE_IO_SIZE 0x4000
294 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
295 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
296 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
297 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
298 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
299 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
300 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
301 /* Extra registers for new PCIe boards */
302 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
303 #define DIO200_VERSION 0x24 /* Hardware version register */
304 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
305 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
308 * Functions for constructing value for DIO_200_?CLK_SCE and
309 * DIO_200_?GAT_SCE registers:
311 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
312 * 'chan' is the channel: 0, 1 or 2.
313 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
315 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
318 return (which << 5) | (chan << 3) |
319 ((source & 030) << 3) | (source & 007);
322 static unsigned char clk_sce(unsigned int which, unsigned int chan,
325 return clk_gat_sce(which, chan, source);
328 static unsigned char gat_sce(unsigned int which, unsigned int chan,
331 return clk_gat_sce(which, chan, source);
335 * Periods of the internal clock sources in nanoseconds.
337 static const unsigned int clock_period[32] = {
338 [1] = 100, /* 10 MHz */
339 [2] = 1000, /* 1 MHz */
340 [3] = 10000, /* 100 kHz */
341 [4] = 100000, /* 10 kHz */
342 [5] = 1000000, /* 1 kHz */
343 [11] = 50, /* 20 MHz (enhanced boards) */
344 /* clock sources 12 and later reserved for enhanced boards */
348 * Timestamp timer configuration register (for new PCIe boards).
350 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
351 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
352 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
355 * Periods of the timestamp timer clock sources in nanoseconds.
357 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
358 1, /* 1 nanosecond (but with 20 ns granularity). */
359 1000, /* 1 microsecond. */
360 1000000, /* 1 millisecond. */
366 enum dio200_regtype { no_regtype = 0, io_regtype, mmio_regtype };
367 struct dio200_region {
369 unsigned long iobase; /* I/O base address */
370 unsigned char __iomem *membase; /* mapped MMIO base address */
372 enum dio200_regtype regtype;
376 * Board descriptions.
379 enum dio200_bustype { isa_bustype, pci_bustype };
384 pc215e_model, pci215_model, pcie215_model,
387 pc272e_model, pci272_model,
391 enum dio200_layout_idx {
408 struct dio200_board {
410 unsigned short devid;
411 enum dio200_bustype bustype;
412 enum dio200_model model;
413 enum dio200_layout_idx layout;
414 unsigned char mainbar;
415 unsigned char mainshift;
416 unsigned int mainsize;
419 static const struct dio200_board dio200_boards[] = {
423 .bustype = isa_bustype,
424 .model = pc212e_model,
425 .layout = pc212_layout,
426 .mainsize = DIO200_IO_SIZE,
430 .bustype = isa_bustype,
431 .model = pc214e_model,
432 .layout = pc214_layout,
433 .mainsize = DIO200_IO_SIZE,
437 .bustype = isa_bustype,
438 .model = pc215e_model,
439 .layout = pc215_layout,
440 .mainsize = DIO200_IO_SIZE,
444 .bustype = isa_bustype,
445 .model = pc218e_model,
446 .layout = pc218_layout,
447 .mainsize = DIO200_IO_SIZE,
451 .bustype = isa_bustype,
452 .model = pc272e_model,
453 .layout = pc272_layout,
454 .mainsize = DIO200_IO_SIZE,
460 .devid = PCI_DEVICE_ID_AMPLICON_PCI215,
461 .bustype = pci_bustype,
462 .model = pci215_model,
463 .layout = pc215_layout,
465 .mainsize = DIO200_IO_SIZE,
469 .devid = PCI_DEVICE_ID_AMPLICON_PCI272,
470 .bustype = pci_bustype,
471 .model = pci272_model,
472 .layout = pc272_layout,
474 .mainsize = DIO200_IO_SIZE,
478 .devid = PCI_DEVICE_ID_AMPLICON_PCIE215,
479 .bustype = pci_bustype,
480 .model = pcie215_model,
481 .layout = pcie215_layout,
484 .mainsize = DIO200_PCIE_IO_SIZE,
488 .devid = PCI_DEVICE_ID_AMPLICON_PCIE236,
489 .bustype = pci_bustype,
490 .model = pcie236_model,
491 .layout = pcie236_layout,
494 .mainsize = DIO200_PCIE_IO_SIZE,
498 .devid = PCI_DEVICE_ID_AMPLICON_PCIE296,
499 .bustype = pci_bustype,
500 .model = pcie296_model,
501 .layout = pcie296_layout,
504 .mainsize = DIO200_PCIE_IO_SIZE,
510 * Layout descriptions - some ISA and PCI board descriptions share the same
514 enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer };
516 #define DIO200_MAX_SUBDEVS 8
517 #define DIO200_MAX_ISNS 6
519 struct dio200_layout {
520 unsigned short n_subdevs; /* number of subdevices */
521 unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */
522 unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */
523 char has_int_sce; /* has interrupt enable/status register */
524 char has_clk_gat_sce; /* has clock/gate selection registers */
525 char has_enhancements; /* has enhanced features */
528 static const struct dio200_layout dio200_layouts[] = {
532 .sdtype = {sd_8255, sd_8254, sd_8254, sd_8254,
535 .sdinfo = {0x00, 0x08, 0x0C, 0x10, 0x14,
538 .has_clk_gat_sce = 1,
542 .sdtype = {sd_8255, sd_8255, sd_8254,
544 .sdinfo = {0x00, 0x08, 0x10, 0x01},
546 .has_clk_gat_sce = 0,
551 .sdtype = {sd_8255, sd_8255, sd_8254,
554 .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
556 .has_clk_gat_sce = 1,
561 .sdtype = {sd_8254, sd_8254, sd_8255, sd_8254,
564 .sdinfo = {0x00, 0x04, 0x08, 0x0C, 0x10,
568 .has_clk_gat_sce = 1,
573 .sdtype = {sd_8255, sd_8255, sd_8255,
575 .sdinfo = {0x00, 0x08, 0x10, 0x3F},
577 .has_clk_gat_sce = 0,
582 .sdtype = {sd_8255, sd_none, sd_8255, sd_none,
583 sd_8254, sd_8254, sd_timer, sd_intr},
584 .sdinfo = {0x00, 0x00, 0x08, 0x00,
585 0x10, 0x14, 0x00, 0x3F},
587 .has_clk_gat_sce = 1,
588 .has_enhancements = 1,
592 .sdtype = {sd_8255, sd_none, sd_none, sd_none,
593 sd_8254, sd_8254, sd_timer, sd_intr},
594 .sdinfo = {0x00, 0x00, 0x00, 0x00,
595 0x10, 0x14, 0x00, 0x3F},
597 .has_clk_gat_sce = 1,
598 .has_enhancements = 1,
602 .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
603 sd_8254, sd_8254, sd_timer, sd_intr},
604 .sdinfo = {0x00, 0x04, 0x08, 0x0C,
605 0x10, 0x14, 0x00, 0x3F},
607 .has_clk_gat_sce = 1,
608 .has_enhancements = 1,
613 /* this structure is for data unique to this hardware driver. If
614 several hardware drivers keep similar information in this structure,
615 feel free to suggest moving the variable to the struct comedi_device struct.
617 struct dio200_private {
618 struct dio200_region io; /* Register region */
622 struct dio200_subdev_8254 {
623 unsigned int ofs; /* Counter base offset */
624 unsigned int clk_sce_ofs; /* CLK_SCE base address */
625 unsigned int gat_sce_ofs; /* GAT_SCE base address */
626 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
627 unsigned int clock_src[3]; /* Current clock sources */
628 unsigned int gate_src[3]; /* Current gate sources */
632 struct dio200_subdev_8255 {
633 unsigned int ofs; /* DIO base offset */
636 struct dio200_subdev_intr {
640 unsigned int valid_isns;
641 unsigned int enabled_isns;
642 unsigned int stopcount;
646 static inline const struct dio200_layout *
647 dio200_board_layout(const struct dio200_board *board)
649 return &dio200_layouts[board->layout];
652 static inline const struct dio200_layout *
653 dio200_dev_layout(struct comedi_device *dev)
655 return dio200_board_layout(comedi_board(dev));
658 static inline bool is_pci_board(const struct dio200_board *board)
660 return DO_PCI && board->bustype == pci_bustype;
663 static inline bool is_isa_board(const struct dio200_board *board)
665 return DO_ISA && board->bustype == isa_bustype;
669 * Read 8-bit register.
671 static unsigned char dio200_read8(struct comedi_device *dev,
674 const struct dio200_board *thisboard = comedi_board(dev);
675 struct dio200_private *devpriv = dev->private;
677 offset <<= thisboard->mainshift;
678 if (devpriv->io.regtype == io_regtype)
679 return inb(devpriv->io.u.iobase + offset);
681 return readb(devpriv->io.u.membase + offset);
685 * Write 8-bit register.
687 static void dio200_write8(struct comedi_device *dev, unsigned int offset,
690 const struct dio200_board *thisboard = comedi_board(dev);
691 struct dio200_private *devpriv = dev->private;
693 offset <<= thisboard->mainshift;
694 if (devpriv->io.regtype == io_regtype)
695 outb(val, devpriv->io.u.iobase + offset);
697 writeb(val, devpriv->io.u.membase + offset);
701 * Read 32-bit register.
703 static unsigned int dio200_read32(struct comedi_device *dev,
706 const struct dio200_board *thisboard = comedi_board(dev);
707 struct dio200_private *devpriv = dev->private;
709 offset <<= thisboard->mainshift;
710 if (devpriv->io.regtype == io_regtype)
711 return inl(devpriv->io.u.iobase + offset);
713 return readl(devpriv->io.u.membase + offset);
717 * Write 32-bit register.
719 static void dio200_write32(struct comedi_device *dev, unsigned int offset,
722 const struct dio200_board *thisboard = comedi_board(dev);
723 struct dio200_private *devpriv = dev->private;
725 offset <<= thisboard->mainshift;
726 if (devpriv->io.regtype == io_regtype)
727 outl(val, devpriv->io.u.iobase + offset);
729 writel(val, devpriv->io.u.membase + offset);
733 * This function looks for a board matching the supplied PCI device.
735 static const struct dio200_board *
736 dio200_find_pci_board(struct pci_dev *pci_dev)
740 for (i = 0; i < ARRAY_SIZE(dio200_boards); i++)
741 if (is_pci_board(&dio200_boards[i]) &&
742 pci_dev->device == dio200_boards[i].devid)
743 return &dio200_boards[i];
748 * This function checks and requests an I/O region, reporting an error
749 * if there is a conflict.
752 dio200_request_region(struct comedi_device *dev,
753 unsigned long from, unsigned long extent)
755 if (!from || !request_region(from, extent, DIO200_DRIVER_NAME)) {
756 dev_err(dev->class_dev, "I/O port conflict (%#lx,%lu)!\n",
764 * 'insn_bits' function for an 'INTERRUPT' subdevice.
767 dio200_subdev_intr_insn_bits(struct comedi_device *dev,
768 struct comedi_subdevice *s,
769 struct comedi_insn *insn, unsigned int *data)
771 const struct dio200_layout *layout = dio200_dev_layout(dev);
772 struct dio200_subdev_intr *subpriv = s->private;
774 if (layout->has_int_sce) {
775 /* Just read the interrupt status register. */
776 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
778 /* No interrupt status register. */
786 * Called to stop acquisition for an 'INTERRUPT' subdevice.
788 static void dio200_stop_intr(struct comedi_device *dev,
789 struct comedi_subdevice *s)
791 const struct dio200_layout *layout = dio200_dev_layout(dev);
792 struct dio200_subdev_intr *subpriv = s->private;
795 subpriv->enabled_isns = 0;
796 if (layout->has_int_sce)
797 dio200_write8(dev, subpriv->ofs, 0);
801 * Called to start acquisition for an 'INTERRUPT' subdevice.
803 static int dio200_start_intr(struct comedi_device *dev,
804 struct comedi_subdevice *s)
808 const struct dio200_layout *layout = dio200_dev_layout(dev);
809 struct dio200_subdev_intr *subpriv = s->private;
810 struct comedi_cmd *cmd = &s->async->cmd;
813 if (!subpriv->continuous && subpriv->stopcount == 0) {
814 /* An empty acquisition! */
815 s->async->events |= COMEDI_CB_EOA;
819 /* Determine interrupt sources to enable. */
822 for (n = 0; n < cmd->chanlist_len; n++)
823 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
825 isn_bits &= subpriv->valid_isns;
826 /* Enable interrupt sources. */
827 subpriv->enabled_isns = isn_bits;
828 if (layout->has_int_sce)
829 dio200_write8(dev, subpriv->ofs, isn_bits);
836 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice.
839 dio200_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s,
840 unsigned int trignum)
842 struct dio200_subdev_intr *subpriv;
849 subpriv = s->private;
851 spin_lock_irqsave(&subpriv->spinlock, flags);
852 s->async->inttrig = NULL;
854 event = dio200_start_intr(dev, s);
856 spin_unlock_irqrestore(&subpriv->spinlock, flags);
859 comedi_event(dev, s);
865 * This is called from the interrupt service routine to handle a read
866 * scan on an 'INTERRUPT' subdevice.
868 static int dio200_handle_read_intr(struct comedi_device *dev,
869 struct comedi_subdevice *s)
871 const struct dio200_layout *layout = dio200_dev_layout(dev);
872 struct dio200_subdev_intr *subpriv = s->private;
875 unsigned cur_enabled;
876 unsigned int oldevents;
881 spin_lock_irqsave(&subpriv->spinlock, flags);
882 oldevents = s->async->events;
883 if (layout->has_int_sce) {
885 * Collect interrupt sources that have triggered and disable
886 * them temporarily. Loop around until no extra interrupt
887 * sources have triggered, at which point, the valid part of
888 * the interrupt status register will read zero, clearing the
889 * cause of the interrupt.
891 * Mask off interrupt sources already seen to avoid infinite
892 * loop in case of misconfiguration.
894 cur_enabled = subpriv->enabled_isns;
895 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
896 subpriv->valid_isns & ~triggered)) != 0) {
897 triggered |= intstat;
898 cur_enabled &= ~triggered;
899 dio200_write8(dev, subpriv->ofs, cur_enabled);
903 * No interrupt status register. Assume the single interrupt
904 * source has triggered.
906 triggered = subpriv->enabled_isns;
911 * Some interrupt sources have triggered and have been
912 * temporarily disabled to clear the cause of the interrupt.
914 * Reenable them NOW to minimize the time they are disabled.
916 cur_enabled = subpriv->enabled_isns;
917 if (layout->has_int_sce)
918 dio200_write8(dev, subpriv->ofs, cur_enabled);
920 if (subpriv->active) {
922 * The command is still active.
924 * Ignore interrupt sources that the command isn't
925 * interested in (just in case there's a race
928 if (triggered & subpriv->enabled_isns) {
929 /* Collect scan data. */
931 unsigned int n, ch, len;
934 len = s->async->cmd.chanlist_len;
935 for (n = 0; n < len; n++) {
936 ch = CR_CHAN(s->async->cmd.chanlist[n]);
937 if (triggered & (1U << ch))
940 /* Write the scan to the buffer. */
941 if (comedi_buf_put(s->async, val)) {
942 s->async->events |= (COMEDI_CB_BLOCK |
945 /* Error! Stop acquisition. */
946 dio200_stop_intr(dev, s);
947 s->async->events |= COMEDI_CB_ERROR
948 | COMEDI_CB_OVERFLOW;
949 comedi_error(dev, "buffer overflow");
952 /* Check for end of acquisition. */
953 if (!subpriv->continuous) {
954 /* stop_src == TRIG_COUNT */
955 if (subpriv->stopcount > 0) {
956 subpriv->stopcount--;
957 if (subpriv->stopcount == 0) {
960 dio200_stop_intr(dev,
968 spin_unlock_irqrestore(&subpriv->spinlock, flags);
970 if (oldevents != s->async->events)
971 comedi_event(dev, s);
973 return (triggered != 0);
977 * 'cancel' function for an 'INTERRUPT' subdevice.
979 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
980 struct comedi_subdevice *s)
982 struct dio200_subdev_intr *subpriv = s->private;
985 spin_lock_irqsave(&subpriv->spinlock, flags);
987 dio200_stop_intr(dev, s);
989 spin_unlock_irqrestore(&subpriv->spinlock, flags);
995 * 'do_cmdtest' function for an 'INTERRUPT' subdevice.
998 dio200_subdev_intr_cmdtest(struct comedi_device *dev,
999 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1003 /* Step 1 : check if triggers are trivially valid */
1005 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
1006 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
1007 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
1008 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1009 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
1014 /* Step 2a : make sure trigger sources are unique */
1016 err |= cfc_check_trigger_is_unique(cmd->start_src);
1017 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1019 /* Step 2b : and mutually compatible */
1024 /* step 3: make sure arguments are trivially compatible */
1026 /* cmd->start_src == TRIG_NOW || cmd->start_src == TRIG_INT */
1027 if (cmd->start_arg != 0) {
1032 /* cmd->scan_begin_src == TRIG_EXT */
1033 if (cmd->scan_begin_arg != 0) {
1034 cmd->scan_begin_arg = 0;
1038 /* cmd->convert_src == TRIG_NOW */
1039 if (cmd->convert_arg != 0) {
1040 cmd->convert_arg = 0;
1044 /* cmd->scan_end_src == TRIG_COUNT */
1045 if (cmd->scan_end_arg != cmd->chanlist_len) {
1046 cmd->scan_end_arg = cmd->chanlist_len;
1050 switch (cmd->stop_src) {
1052 /* any count allowed */
1055 if (cmd->stop_arg != 0) {
1067 /* step 4: fix up any arguments */
1069 /* if (err) return 4; */
1075 * 'do_cmd' function for an 'INTERRUPT' subdevice.
1077 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
1078 struct comedi_subdevice *s)
1080 struct comedi_cmd *cmd = &s->async->cmd;
1081 struct dio200_subdev_intr *subpriv = s->private;
1082 unsigned long flags;
1085 spin_lock_irqsave(&subpriv->spinlock, flags);
1086 subpriv->active = 1;
1088 /* Set up end of acquisition. */
1089 switch (cmd->stop_src) {
1091 subpriv->continuous = 0;
1092 subpriv->stopcount = cmd->stop_arg;
1096 subpriv->continuous = 1;
1097 subpriv->stopcount = 0;
1101 /* Set up start of acquisition. */
1102 switch (cmd->start_src) {
1104 s->async->inttrig = dio200_inttrig_start_intr;
1108 event = dio200_start_intr(dev, s);
1111 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1114 comedi_event(dev, s);
1120 * This function initializes an 'INTERRUPT' subdevice.
1123 dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s,
1124 unsigned int offset, unsigned valid_isns)
1126 const struct dio200_layout *layout = dio200_dev_layout(dev);
1127 struct dio200_subdev_intr *subpriv;
1129 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1131 dev_err(dev->class_dev, "error! out of memory!\n");
1134 subpriv->ofs = offset;
1135 subpriv->valid_isns = valid_isns;
1136 spin_lock_init(&subpriv->spinlock);
1138 if (layout->has_int_sce)
1139 /* Disable interrupt sources. */
1140 dio200_write8(dev, subpriv->ofs, 0);
1142 s->private = subpriv;
1143 s->type = COMEDI_SUBD_DI;
1144 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
1145 if (layout->has_int_sce) {
1146 s->n_chan = DIO200_MAX_ISNS;
1147 s->len_chanlist = DIO200_MAX_ISNS;
1149 /* No interrupt source register. Support single channel. */
1151 s->len_chanlist = 1;
1153 s->range_table = &range_digital;
1155 s->insn_bits = dio200_subdev_intr_insn_bits;
1156 s->do_cmdtest = dio200_subdev_intr_cmdtest;
1157 s->do_cmd = dio200_subdev_intr_cmd;
1158 s->cancel = dio200_subdev_intr_cancel;
1164 * This function cleans up an 'INTERRUPT' subdevice.
1167 dio200_subdev_intr_cleanup(struct comedi_device *dev,
1168 struct comedi_subdevice *s)
1170 struct dio200_subdev_intr *subpriv = s->private;
1175 * Interrupt service routine.
1177 static irqreturn_t dio200_interrupt(int irq, void *d)
1179 struct comedi_device *dev = d;
1180 struct dio200_private *devpriv = dev->private;
1181 struct comedi_subdevice *s;
1187 if (devpriv->intr_sd >= 0) {
1188 s = &dev->subdevices[devpriv->intr_sd];
1189 handled = dio200_handle_read_intr(dev, s);
1194 return IRQ_RETVAL(handled);
1198 * Read an '8254' counter subdevice channel.
1201 dio200_subdev_8254_read_chan(struct comedi_device *dev,
1202 struct comedi_subdevice *s, unsigned int chan)
1204 struct dio200_subdev_8254 *subpriv = s->private;
1209 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
1211 val = dio200_read8(dev, subpriv->ofs + chan);
1212 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
1217 * Write an '8254' subdevice channel.
1220 dio200_subdev_8254_write_chan(struct comedi_device *dev,
1221 struct comedi_subdevice *s, unsigned int chan,
1224 struct dio200_subdev_8254 *subpriv = s->private;
1226 /* write lsb, msb */
1227 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
1228 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
1232 * Set mode of an '8254' subdevice channel.
1235 dio200_subdev_8254_set_mode(struct comedi_device *dev,
1236 struct comedi_subdevice *s, unsigned int chan,
1239 struct dio200_subdev_8254 *subpriv = s->private;
1243 byte |= 0x30; /* access order: lsb, msb */
1244 byte |= (mode & 0xf); /* counter mode and BCD|binary */
1245 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
1249 * Read status byte of an '8254' counter subdevice channel.
1252 dio200_subdev_8254_status(struct comedi_device *dev,
1253 struct comedi_subdevice *s, unsigned int chan)
1255 struct dio200_subdev_8254 *subpriv = s->private;
1258 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
1259 0xe0 | (2 << chan));
1261 return dio200_read8(dev, subpriv->ofs + chan);
1265 * Handle 'insn_read' for an '8254' counter subdevice.
1268 dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s,
1269 struct comedi_insn *insn, unsigned int *data)
1271 struct dio200_subdev_8254 *subpriv = s->private;
1272 int chan = CR_CHAN(insn->chanspec);
1274 unsigned long flags;
1276 for (n = 0; n < insn->n; n++) {
1277 spin_lock_irqsave(&subpriv->spinlock, flags);
1278 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
1279 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1285 * Handle 'insn_write' for an '8254' counter subdevice.
1288 dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s,
1289 struct comedi_insn *insn, unsigned int *data)
1291 struct dio200_subdev_8254 *subpriv = s->private;
1292 int chan = CR_CHAN(insn->chanspec);
1294 unsigned long flags;
1296 for (n = 0; n < insn->n; n++) {
1297 spin_lock_irqsave(&subpriv->spinlock, flags);
1298 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
1299 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1305 * Set gate source for an '8254' counter subdevice channel.
1308 dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
1309 struct comedi_subdevice *s,
1310 unsigned int counter_number,
1311 unsigned int gate_src)
1313 const struct dio200_layout *layout = dio200_dev_layout(dev);
1314 struct dio200_subdev_8254 *subpriv = s->private;
1317 if (!layout->has_clk_gat_sce)
1319 if (counter_number > 2)
1321 if (gate_src > (layout->has_enhancements ? 31 : 7))
1324 subpriv->gate_src[counter_number] = gate_src;
1325 byte = gat_sce(subpriv->which, counter_number, gate_src);
1326 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
1332 * Get gate source for an '8254' counter subdevice channel.
1335 dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
1336 struct comedi_subdevice *s,
1337 unsigned int counter_number)
1339 const struct dio200_layout *layout = dio200_dev_layout(dev);
1340 struct dio200_subdev_8254 *subpriv = s->private;
1342 if (!layout->has_clk_gat_sce)
1344 if (counter_number > 2)
1347 return subpriv->gate_src[counter_number];
1351 * Set clock source for an '8254' counter subdevice channel.
1354 dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
1355 struct comedi_subdevice *s,
1356 unsigned int counter_number,
1357 unsigned int clock_src)
1359 const struct dio200_layout *layout = dio200_dev_layout(dev);
1360 struct dio200_subdev_8254 *subpriv = s->private;
1363 if (!layout->has_clk_gat_sce)
1365 if (counter_number > 2)
1367 if (clock_src > (layout->has_enhancements ? 31 : 7))
1370 subpriv->clock_src[counter_number] = clock_src;
1371 byte = clk_sce(subpriv->which, counter_number, clock_src);
1372 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
1378 * Get clock source for an '8254' counter subdevice channel.
1381 dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
1382 struct comedi_subdevice *s,
1383 unsigned int counter_number,
1384 unsigned int *period_ns)
1386 const struct dio200_layout *layout = dio200_dev_layout(dev);
1387 struct dio200_subdev_8254 *subpriv = s->private;
1390 if (!layout->has_clk_gat_sce)
1392 if (counter_number > 2)
1395 clock_src = subpriv->clock_src[counter_number];
1396 *period_ns = clock_period[clock_src];
1401 * Handle 'insn_config' for an '8254' counter subdevice.
1404 dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s,
1405 struct comedi_insn *insn, unsigned int *data)
1407 struct dio200_subdev_8254 *subpriv = s->private;
1409 int chan = CR_CHAN(insn->chanspec);
1410 unsigned long flags;
1412 spin_lock_irqsave(&subpriv->spinlock, flags);
1414 case INSN_CONFIG_SET_COUNTER_MODE:
1415 if (data[1] > (I8254_MODE5 | I8254_BINARY))
1418 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
1420 case INSN_CONFIG_8254_READ_STATUS:
1421 data[1] = dio200_subdev_8254_status(dev, s, chan);
1423 case INSN_CONFIG_SET_GATE_SRC:
1424 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
1428 case INSN_CONFIG_GET_GATE_SRC:
1429 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
1436 case INSN_CONFIG_SET_CLOCK_SRC:
1437 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
1441 case INSN_CONFIG_GET_CLOCK_SRC:
1442 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
1453 spin_unlock_irqrestore(&subpriv->spinlock, flags);
1454 return ret < 0 ? ret : insn->n;
1458 * This function initializes an '8254' counter subdevice.
1461 dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s,
1462 unsigned int offset)
1464 const struct dio200_layout *layout = dio200_dev_layout(dev);
1465 struct dio200_subdev_8254 *subpriv;
1468 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1470 dev_err(dev->class_dev, "error! out of memory!\n");
1474 s->private = subpriv;
1475 s->type = COMEDI_SUBD_COUNTER;
1476 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1478 s->maxdata = 0xFFFF;
1479 s->insn_read = dio200_subdev_8254_read;
1480 s->insn_write = dio200_subdev_8254_write;
1481 s->insn_config = dio200_subdev_8254_config;
1483 spin_lock_init(&subpriv->spinlock);
1484 subpriv->ofs = offset;
1485 if (layout->has_clk_gat_sce) {
1486 /* Derive CLK_SCE and GAT_SCE register offsets from
1488 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
1489 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
1490 subpriv->which = (offset >> 2) & 1;
1493 /* Initialize channels. */
1494 for (chan = 0; chan < 3; chan++) {
1495 dio200_subdev_8254_set_mode(dev, s, chan,
1496 I8254_MODE0 | I8254_BINARY);
1497 if (layout->has_clk_gat_sce) {
1498 /* Gate source 0 is VCC (logic 1). */
1499 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
1500 /* Clock source 0 is the dedicated clock input. */
1501 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
1509 * This function cleans up an '8254' counter subdevice.
1512 dio200_subdev_8254_cleanup(struct comedi_device *dev,
1513 struct comedi_subdevice *s)
1515 struct dio200_subdev_intr *subpriv = s->private;
1520 * This function sets I/O directions for an '8255' DIO subdevice.
1522 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
1523 struct comedi_subdevice *s)
1525 struct dio200_subdev_8255 *subpriv = s->private;
1529 /* 1 in io_bits indicates output, 1 in config indicates input */
1530 if (!(s->io_bits & 0x0000ff))
1532 if (!(s->io_bits & 0x00ff00))
1534 if (!(s->io_bits & 0x0f0000))
1535 config |= CR_C_LO_IO;
1536 if (!(s->io_bits & 0xf00000))
1537 config |= CR_C_HI_IO;
1538 dio200_write8(dev, subpriv->ofs + 3, config);
1542 * Handle 'insn_bits' for an '8255' DIO subdevice.
1544 static int dio200_subdev_8255_bits(struct comedi_device *dev,
1545 struct comedi_subdevice *s,
1546 struct comedi_insn *insn, unsigned int *data)
1548 struct dio200_subdev_8255 *subpriv = s->private;
1551 s->state &= ~data[0];
1552 s->state |= (data[0] & data[1]);
1554 dio200_write8(dev, subpriv->ofs, s->state & 0xff);
1555 if (data[0] & 0xff00)
1556 dio200_write8(dev, subpriv->ofs + 1,
1557 (s->state >> 8) & 0xff);
1558 if (data[0] & 0xff0000)
1559 dio200_write8(dev, subpriv->ofs + 2,
1560 (s->state >> 16) & 0xff);
1562 data[1] = dio200_read8(dev, subpriv->ofs);
1563 data[1] |= dio200_read8(dev, subpriv->ofs + 1) << 8;
1564 data[1] |= dio200_read8(dev, subpriv->ofs + 2) << 16;
1569 * Handle 'insn_config' for an '8255' DIO subdevice.
1571 static int dio200_subdev_8255_config(struct comedi_device *dev,
1572 struct comedi_subdevice *s,
1573 struct comedi_insn *insn,
1579 mask = 1 << CR_CHAN(insn->chanspec);
1580 if (mask & 0x0000ff)
1582 else if (mask & 0x00ff00)
1584 else if (mask & 0x0f0000)
1589 case INSN_CONFIG_DIO_INPUT:
1590 s->io_bits &= ~bits;
1592 case INSN_CONFIG_DIO_OUTPUT:
1595 case INSN_CONFIG_DIO_QUERY:
1596 data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT;
1602 dio200_subdev_8255_set_dir(dev, s);
1607 * This function initializes an '8255' DIO subdevice.
1609 * offset is the offset to the 8255 chip.
1611 static int dio200_subdev_8255_init(struct comedi_device *dev,
1612 struct comedi_subdevice *s,
1613 unsigned int offset)
1615 struct dio200_subdev_8255 *subpriv;
1617 subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
1620 subpriv->ofs = offset;
1621 s->private = subpriv;
1622 s->type = COMEDI_SUBD_DIO;
1623 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1625 s->range_table = &range_digital;
1627 s->insn_bits = dio200_subdev_8255_bits;
1628 s->insn_config = dio200_subdev_8255_config;
1631 dio200_subdev_8255_set_dir(dev, s);
1636 * This function cleans up an '8255' DIO subdevice.
1638 static void dio200_subdev_8255_cleanup(struct comedi_device *dev,
1639 struct comedi_subdevice *s)
1641 struct dio200_subdev_8255 *subpriv = s->private;
1647 * Handle 'insn_read' for a timer subdevice.
1649 static int dio200_subdev_timer_read(struct comedi_device *dev,
1650 struct comedi_subdevice *s,
1651 struct comedi_insn *insn,
1656 for (n = 0; n < insn->n; n++)
1657 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
1662 * Reset timer subdevice.
1664 static void dio200_subdev_timer_reset(struct comedi_device *dev,
1665 struct comedi_subdevice *s)
1669 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1670 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
1671 dio200_write32(dev, DIO200_TS_CONFIG, clock);
1675 * Get timer subdevice clock source and period.
1677 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
1678 struct comedi_subdevice *s,
1680 unsigned int *period)
1684 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1686 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
1687 ts_clock_period[clk] : 0;
1691 * Set timer subdevice clock source.
1693 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
1694 struct comedi_subdevice *s,
1697 if (src > TS_CONFIG_MAX_CLK_SRC)
1699 dio200_write32(dev, DIO200_TS_CONFIG, src);
1704 * Handle 'insn_config' for a timer subdevice.
1706 static int dio200_subdev_timer_config(struct comedi_device *dev,
1707 struct comedi_subdevice *s,
1708 struct comedi_insn *insn,
1714 case INSN_CONFIG_RESET:
1715 dio200_subdev_timer_reset(dev, s);
1717 case INSN_CONFIG_SET_CLOCK_SRC:
1718 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
1722 case INSN_CONFIG_GET_CLOCK_SRC:
1723 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
1729 return ret < 0 ? ret : insn->n;
1733 * This function initializes a timer subdevice.
1735 * Uses the timestamp timer registers. There is only one timestamp timer.
1737 static int dio200_subdev_timer_init(struct comedi_device *dev,
1738 struct comedi_subdevice *s)
1740 s->type = COMEDI_SUBD_TIMER;
1741 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
1743 s->maxdata = 0xFFFFFFFF;
1744 s->insn_read = dio200_subdev_timer_read;
1745 s->insn_config = dio200_subdev_timer_config;
1750 * This function cleans up a timer subdevice.
1752 static void dio200_subdev_timer_cleanup(struct comedi_device *dev,
1753 struct comedi_subdevice *s)
1755 /* Nothing to do. */
1759 * This function does some special set-up for the PCIe boards
1760 * PCIe215, PCIe236, PCIe296.
1762 static int dio200_pcie_board_setup(struct comedi_device *dev)
1764 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1765 void __iomem *brbase;
1766 resource_size_t brlen;
1769 * The board uses Altera Cyclone IV with PCI-Express hard IP.
1770 * The FPGA configuration has the PCI-Express Avalon-MM Bridge
1771 * Control registers in PCI BAR 0, offset 0, and the length of
1772 * these registers is 0x4000.
1774 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
1775 * Enable" register at offset 0x50 to allow generation of PCIe
1776 * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
1778 brlen = pci_resource_len(pcidev, 0);
1779 if (brlen < 0x4000 ||
1780 !(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM)) {
1781 dev_err(dev->class_dev, "error! bad PCI region!\n");
1784 brbase = ioremap_nocache(pci_resource_start(pcidev, 0), brlen);
1786 dev_err(dev->class_dev, "error! failed to map registers!\n");
1789 writel(0x80, brbase + 0x50);
1791 /* Enable "enhanced" features of board. */
1792 dio200_write8(dev, DIO200_ENHANCE, 1);
1796 static void dio200_report_attach(struct comedi_device *dev, unsigned int irq)
1798 const struct dio200_board *thisboard = comedi_board(dev);
1799 struct dio200_private *devpriv = dev->private;
1800 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1804 if (is_isa_board(thisboard))
1805 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1806 "(base %#lx) ", devpriv->io.u.iobase);
1807 else if (is_pci_board(thisboard))
1808 tmplen = scnprintf(tmpbuf, sizeof(tmpbuf),
1809 "(pci %s) ", pci_name(pcidev));
1813 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1815 (dev->irq ? "" : " UNAVAILABLE"));
1817 tmplen += scnprintf(&tmpbuf[tmplen], sizeof(tmpbuf) - tmplen,
1819 dev_info(dev->class_dev, "%s %sattached\n", dev->board_name, tmpbuf);
1822 static int dio200_common_attach(struct comedi_device *dev, unsigned int irq,
1823 unsigned long req_irq_flags)
1825 const struct dio200_board *thisboard = comedi_board(dev);
1826 struct dio200_private *devpriv = dev->private;
1827 const struct dio200_layout *layout = dio200_board_layout(thisboard);
1828 struct comedi_subdevice *s;
1833 devpriv->intr_sd = -1;
1834 dev->board_name = thisboard->name;
1836 ret = comedi_alloc_subdevices(dev, layout->n_subdevs);
1840 for (n = 0; n < dev->n_subdevices; n++) {
1841 s = &dev->subdevices[n];
1842 switch (layout->sdtype[n]) {
1844 /* counter subdevice (8254) */
1845 ret = dio200_subdev_8254_init(dev, s,
1851 /* digital i/o subdevice (8255) */
1852 ret = dio200_subdev_8255_init(dev, s,
1858 /* 'INTERRUPT' subdevice */
1860 ret = dio200_subdev_intr_init(dev, s,
1866 devpriv->intr_sd = n;
1868 s->type = COMEDI_SUBD_UNUSED;
1872 /* Only on PCIe boards. */
1874 ret = dio200_subdev_timer_init(dev, s);
1878 s->type = COMEDI_SUBD_UNUSED;
1882 s->type = COMEDI_SUBD_UNUSED;
1886 sdx = devpriv->intr_sd;
1887 if (sdx >= 0 && sdx < dev->n_subdevices)
1888 dev->read_subdev = &dev->subdevices[sdx];
1890 if (request_irq(irq, dio200_interrupt, req_irq_flags,
1891 DIO200_DRIVER_NAME, dev) >= 0) {
1894 dev_warn(dev->class_dev,
1895 "warning! irq %u unavailable!\n", irq);
1898 dio200_report_attach(dev, irq);
1903 * Attach is called by the Comedi core to configure the driver
1904 * for a particular board. If you specified a board_name array
1905 * in the driver structure, dev->board_ptr contains that
1908 static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1910 const struct dio200_board *thisboard = comedi_board(dev);
1911 struct dio200_private *devpriv;
1914 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach\n");
1916 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1919 dev->private = devpriv;
1921 /* Process options and reserve resources according to bus type. */
1922 if (is_isa_board(thisboard)) {
1923 unsigned long iobase;
1926 iobase = it->options[0];
1927 irq = it->options[1];
1928 ret = dio200_request_region(dev, iobase, thisboard->mainsize);
1931 devpriv->io.u.iobase = iobase;
1932 devpriv->io.regtype = io_regtype;
1933 return dio200_common_attach(dev, irq, 0);
1934 } else if (is_pci_board(thisboard)) {
1935 dev_err(dev->class_dev,
1936 "Manual configuration of PCI board '%s' is not supported\n",
1940 dev_err(dev->class_dev, DIO200_DRIVER_NAME
1941 ": BUG! cannot determine board type!\n");
1947 * The attach_pci hook (if non-NULL) is called at PCI probe time in preference
1948 * to the "manual" attach hook. dev->board_ptr is NULL on entry. There should
1949 * be a board entry matching the supplied PCI device.
1951 static int __devinit dio200_attach_pci(struct comedi_device *dev,
1952 struct pci_dev *pci_dev)
1954 const struct dio200_board *thisboard;
1955 struct dio200_private *devpriv;
1956 resource_size_t base, len;
1963 dev_info(dev->class_dev, DIO200_DRIVER_NAME ": attach pci %s\n",
1966 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1969 dev->private = devpriv;
1971 dev->board_ptr = dio200_find_pci_board(pci_dev);
1972 if (dev->board_ptr == NULL) {
1973 dev_err(dev->class_dev, "BUG! cannot determine board type!\n");
1976 thisboard = comedi_board(dev);
1977 ret = comedi_pci_enable(pci_dev, DIO200_DRIVER_NAME);
1979 dev_err(dev->class_dev,
1980 "error! cannot enable PCI device and request regions!\n");
1983 bar = thisboard->mainbar;
1984 base = pci_resource_start(pci_dev, bar);
1985 len = pci_resource_len(pci_dev, bar);
1986 if (len < thisboard->mainsize) {
1987 dev_err(dev->class_dev, "error! PCI region size too small!\n");
1990 if ((pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) != 0) {
1991 devpriv->io.u.membase = ioremap_nocache(base, len);
1992 if (!devpriv->io.u.membase) {
1993 dev_err(dev->class_dev,
1994 "error! cannot remap registers\n");
1997 devpriv->io.regtype = mmio_regtype;
1999 devpriv->io.u.iobase = (unsigned long)base;
2000 devpriv->io.regtype = io_regtype;
2002 switch (thisboard->model)
2007 ret = dio200_pcie_board_setup(dev);
2014 return dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
2017 static void dio200_detach(struct comedi_device *dev)
2019 const struct dio200_board *thisboard = comedi_board(dev);
2020 struct dio200_private *devpriv = dev->private;
2021 const struct dio200_layout *layout;
2024 if (!thisboard || !devpriv)
2027 free_irq(dev->irq, dev);
2028 if (dev->subdevices) {
2029 layout = dio200_board_layout(thisboard);
2030 for (n = 0; n < dev->n_subdevices; n++) {
2031 struct comedi_subdevice *s = &dev->subdevices[n];
2032 switch (layout->sdtype[n]) {
2034 dio200_subdev_8254_cleanup(dev, s);
2037 dio200_subdev_8255_cleanup(dev, s);
2040 dio200_subdev_intr_cleanup(dev, s);
2043 /* Only on PCIe boards. */
2045 dio200_subdev_timer_cleanup(dev, s);
2052 if (is_isa_board(thisboard)) {
2053 if (devpriv->io.regtype == io_regtype)
2054 release_region(devpriv->io.u.iobase,
2055 thisboard->mainsize);
2056 } else if (is_pci_board(thisboard)) {
2057 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2059 if (devpriv->io.regtype != no_regtype) {
2060 if (devpriv->io.regtype == mmio_regtype)
2061 iounmap(devpriv->io.u.membase);
2062 comedi_pci_disable(pcidev);
2069 * The struct comedi_driver structure tells the Comedi core module
2070 * which functions to call to configure/deconfigure (attach/detach)
2071 * the board, and also about the kernel module that contains
2074 static struct comedi_driver amplc_dio200_driver = {
2075 .driver_name = DIO200_DRIVER_NAME,
2076 .module = THIS_MODULE,
2077 .attach = dio200_attach,
2078 .attach_pci = dio200_attach_pci,
2079 .detach = dio200_detach,
2080 .board_name = &dio200_boards[0].name,
2081 .offset = sizeof(struct dio200_board),
2082 .num_names = ARRAY_SIZE(dio200_boards),
2086 static DEFINE_PCI_DEVICE_TABLE(dio200_pci_table) = {
2087 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI215) },
2088 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI272) },
2089 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE236) },
2090 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE215) },
2091 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCIE296) },
2095 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
2097 static int __devinit amplc_dio200_pci_probe(struct pci_dev *dev,
2098 const struct pci_device_id
2101 return comedi_pci_auto_config(dev, &lc_dio200_driver);
2104 static void __devexit amplc_dio200_pci_remove(struct pci_dev *dev)
2106 comedi_pci_auto_unconfig(dev);
2109 static struct pci_driver amplc_dio200_pci_driver = {
2110 .name = DIO200_DRIVER_NAME,
2111 .id_table = dio200_pci_table,
2112 .probe = &lc_dio200_pci_probe,
2113 .remove = __devexit_p(&lc_dio200_pci_remove)
2115 module_comedi_pci_driver(amplc_dio200_driver, amplc_dio200_pci_driver);
2117 module_comedi_driver(amplc_dio200_driver);
2120 MODULE_AUTHOR("Comedi http://www.comedi.org");
2121 MODULE_DESCRIPTION("Comedi low-level driver");
2122 MODULE_LICENSE("GPL");