Pileus Git - ~andy/linux/blob - drivers/staging/brcm80211/brcmsmac/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <wlc_cfg.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <bcmdefs.h>
  25 #include <osl.h>
  26 #include <proto/802.11.h>
  27 #include <bcmwifi.h>
  28 #include <bcmutils.h>
  29 #include <siutils.h>
  30 #include <bcmendian.h>
  31 #include <wlioctl.h>
  32 #include <sbconfig.h>
  33 #include <sbchipc.h>
  34 #include <pcicfg.h>
  35 #include <sbhndpio.h>
  36 #include <sbhnddma.h>
  37 #include <hnddma.h>
  38 #include <hndpmu.h>
  39 #include <d11.h>
  40 #include <wlc_rate.h>
  41 #include <wlc_pub.h>
  42 #include <wlc_channel.h>
  43 #include <bcmsrom.h>
  44 #include <wlc_key.h>
  45 #include <bcmdevs.h>
  46 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
  47  * dependencies. Need to include these to files to allow a clean include of wlc.h
  48  * with WLC_HIGH defined.
  49  * At some point we may be able to skip the include of wlc.h and instead just
  50  * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
  51  */
  52 #include <wlc_event.h>
  53 #include <wlc_mac80211.h>
  54 #include <wlc_bmac.h>
  55 #include <wlc_phy_shim.h>
  56 #include <wlc_phy_hal.h>
  57 #include <wl_export.h>
  58 #include "wl_ucode.h"
  59 #include "d11ucode_ext.h"
  60 #include <bcmotp.h>
  61
  62 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
  63  * functions defined in the headers below. We should be eliminating those calls and
  64  * will be able to delete these include lines.
  65  */
  66 #include <wlc_antsel.h>
  67
  68 #include <pcie_core.h>
  69
  70 #include <wlc_alloc.h>
  71 #include <wl_dbg.h>
  72
  73 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  74
  75 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  76 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  77 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  78 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  79
  80 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  81
  82 #ifndef BMAC_DUP_TO_REMOVE
  83 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  84
  85 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  86
  87 #endif                          /* BMAC_DUP_TO_REMOVE */
  88
  89 #define DMAREG(wlc_hw, direction, fifonum) \
  90         ((direction == DMA_TX) ? \
  91                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
  92                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv))
  93
  94 /*
  95  * The following table lists the buffer memory allocated to xmt fifos in HW.
  96  * the size is in units of 256bytes(one block), total size is HW dependent
  97  * ucode has default fifo partition, sw can overwrite if necessary
  98  *
  99  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 100  * the twiki is updated before making changes.
 101  */
 102
 103 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
 104
 105 static u16 xmtfifo_sz[][NFIFO] = {
 106         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 107         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 108         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 109         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 110         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 111 };
 112
 113 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
 114 static void wlc_coreinit(struct wlc_info *wlc);
 115
 116 /* used by wlc_wakeucode_init() */
 117 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits);
 118 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 119                             const uint nbytes);
 120 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 121 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 122
 123 /* used by wlc_dpc() */
 124 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 125                                 u32 s2);
 126 static bool wlc_bmac_txstatus_corerev4(struct wlc_hw_info *wlc);
 127 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 128 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 129
 130 /* used by wlc_down() */
 131 static void wlc_flushqueues(struct wlc_info *wlc);
 132
 133 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 134 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 135 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 136
 137 /* Low Level Prototypes */
 138 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 139                                    u32 sel);
 140 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 141                                   u16 v, u32 sel);
 142 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 143 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 144 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 145 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 146 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 147 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 148 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 149 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 150 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 151 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 152 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 153 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 154 static void wlc_gpio_init(struct wlc_info *wlc);
 155 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 156                                       int len);
 157 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 158                                       int len);
 159 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 160 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 161 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 162                              chanspec_t chanspec);
 163 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 164                                         bool shortslot);
 165 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 166 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 167                                              u8 rate);
 168
 169 /* === Low Level functions === */
 170
 171 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 172 {
 173         wlc_hw->shortslot = shortslot;
 174
 175         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 176                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 177                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 178                 wlc_enable_mac(wlc_hw->wlc);
 179         }
 180 }
 181
 182 /*
 183  * Update the slot timing for standard 11b/g (20us slots)
 184  * or shortslot 11g (9us slots)
 185  * The PSM needs to be suspended for this call.
 186  */
 187 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 188                                         bool shortslot)
 189 {
 190         struct osl_info *osh;
 191         d11regs_t *regs;
 192
 193         osh = wlc_hw->osh;
 194         regs = wlc_hw->regs;
 195
 196         if (shortslot) {
 197                 /* 11g short slot: 11a timing */
 198                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 199                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 200         } else {
 201                 /* 11g long slot: 11b timing */
 202                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 203                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 204         }
 205 }
 206
 207 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 208 {
 209         /* init microcode host flags */
 210         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 211
 212         /* do band-specific ucode IHR, SHM, and SCR inits */
 213         if (D11REV_IS(wlc_hw->corerev, 23)) {
 214                 if (WLCISNPHY(wlc_hw->band)) {
 215                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 216                 } else {
 217                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 218                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 219                 }
 220         } else {
 221                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 222                         if (WLCISLCNPHY(wlc_hw->band)) {
 223                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 224                         } else
 225                                 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 226                                          __func__, wlc_hw->unit,
 227                                          wlc_hw->corerev);
 228                 } else {
 229                         WL_ERROR("%s: wl%d: unsupported corerev %d\n",
 230                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 231                 }
 232         }
 233 }
 234
 235 /* switch to new band but leave it inactive */
 236 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 237 {
 238         struct wlc_hw_info *wlc_hw = wlc->hw;
 239         u32 macintmask;
 240         u32 tmp;
 241
 242         WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
 243
 244         ASSERT(bandunit != wlc_hw->band->bandunit);
 245         ASSERT(si_iscoreup(wlc_hw->sih));
 246         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 247                0);
 248
 249         /* disable interrupts */
 250         macintmask = wl_intrsoff(wlc->wl);
 251
 252         /* radio off */
 253         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 254
 255         ASSERT(wlc_hw->clk);
 256
 257         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 258
 259         wlc_setxband(wlc_hw, bandunit);
 260
 261         return macintmask;
 262 }
 263
 264 /* Process received frames */
 265 /*
 266  * Return true if more frames need to be processed. false otherwise.
 267  * Param 'bound' indicates max. # frames to process before break out.
 268  */
 269 static bool BCMFASTPATH
 270 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 271 {
 272         struct sk_buff *p;
 273         struct sk_buff *head = NULL;
 274         struct sk_buff *tail = NULL;
 275         uint n = 0;
 276         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 277         u32 tsf_h, tsf_l;
 278         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 279
 280         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
 281         /* gather received frames */
 282         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 283
 284                 if (!tail)
 285                         head = tail = p;
 286                 else {
 287                         tail->prev = p;
 288                         tail = p;
 289                 }
 290
 291                 /* !give others some time to run! */
 292                 if (++n >= bound_limit)
 293                         break;
 294         }
 295
 296         /* get the TSF REG reading */
 297         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 298
 299         /* post more rbufs */
 300         dma_rxfill(wlc_hw->di[fifo]);
 301
 302         /* process each frame */
 303         while ((p = head) != NULL) {
 304                 head = head->prev;
 305                 p->prev = NULL;
 306
 307                 /* record the tsf_l in wlc_rxd11hdr */
 308                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 309                 wlc_rxhdr->tsf_l = htol32(tsf_l);
 310
 311                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 312                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 313
 314                 wlc_recv(wlc_hw->wlc, p);
 315         }
 316
 317         return n >= bound_limit;
 318 }
 319
 320 /* second-level interrupt processing
 321  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 322  *   Param 'bounded' indicates if applicable loops should be bounded.
 323  */
 324 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
 325 {
 326         u32 macintstatus;
 327         struct wlc_hw_info *wlc_hw = wlc->hw;
 328         d11regs_t *regs = wlc_hw->regs;
 329         bool fatal = false;
 330
 331         if (DEVICEREMOVED(wlc)) {
 332                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
 333                 wl_down(wlc->wl);
 334                 return false;
 335         }
 336
 337         /* grab and clear the saved software intstatus bits */
 338         macintstatus = wlc->macintstatus;
 339         wlc->macintstatus = 0;
 340
 341         WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
 342                  wlc_hw->unit, macintstatus);
 343
 344         if (macintstatus & MI_PRQ) {
 345                 /* Process probe request FIFO */
 346                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 347         }
 348
 349         /* BCN template is available */
 350         /* ZZZ: Use AP_ACTIVE ? */
 351         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 352             && (macintstatus & MI_BCNTPL)) {
 353                 wlc_update_beacon(wlc);
 354         }
 355
 356         /* PMQ entry addition */
 357         if (macintstatus & MI_PMQ) {
 358         }
 359
 360         /* tx status */
 361         if (macintstatus & MI_TFS) {
 362                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 363                         wlc->macintstatus |= MI_TFS;
 364                 if (fatal) {
 365                         WL_ERROR("MI_TFS: fatal\n");
 366                         goto fatal;
 367                 }
 368         }
 369
 370         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 371                 wlc_tbtt(wlc, regs);
 372
 373         /* ATIM window end */
 374         if (macintstatus & MI_ATIMWINEND) {
 375                 WL_TRACE("wlc_isr: end of ATIM window\n");
 376
 377                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 378                 wlc->qvalid = 0;
 379         }
 380
 381         /* phy tx error */
 382         if (macintstatus & MI_PHYTXERR) {
 383                 wlc->pub->_cnt->txphyerr++;
 384         }
 385
 386         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 387         if (macintstatus & MI_DMAINT) {
 388                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 389                         wlc->macintstatus |= MI_DMAINT;
 390                 }
 391         }
 392
 393         /* TX FIFO suspend/flush completion */
 394         if (macintstatus & MI_TXSTOP) {
 395                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 396                         /*      WL_ERROR("dpc: fifo_suspend_comlete\n"); */
 397                 }
 398         }
 399
 400         /* noise sample collected */
 401         if (macintstatus & MI_BG_NOISE) {
 402                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 403         }
 404
 405         if (macintstatus & MI_GP0) {
 406                 WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
 407                          wlc_hw->unit, wlc_hw->now);
 408
 409                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 410                                         __func__, wlc_hw->sih->chip,
 411                                         wlc_hw->sih->chiprev);
 412
 413                 wlc->pub->_cnt->psmwds++;
 414
 415                 /* big hammer */
 416                 wl_init(wlc->wl);
 417         }
 418
 419         /* gptimer timeout */
 420         if (macintstatus & MI_TO) {
 421                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 422         }
 423
 424         if (macintstatus & MI_RFDISABLE) {
 425                 WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
 426
 427                 wlc->pub->_cnt->rfdisable++;
 428                 wl_rfkill_set_hw_state(wlc->wl);
 429         }
 430
 431         /* send any enq'd tx packets. Just makes sure to jump start tx */
 432         if (!pktq_empty(&wlc->active_queue->q))
 433                 wlc_send_q(wlc, wlc->active_queue);
 434
 435         ASSERT(wlc_ps_check(wlc));
 436
 437         /* make sure the bound indication and the implementation are in sync */
 438         ASSERT(bounded == true || wlc->macintstatus == 0);
 439
 440         /* it isn't done and needs to be resched if macintstatus is non-zero */
 441         return wlc->macintstatus != 0;
 442
 443  fatal:
 444         wl_init(wlc->wl);
 445         return wlc->macintstatus != 0;
 446 }
 447
 448 /* common low-level watchdog code */
 449 void wlc_bmac_watchdog(void *arg)
 450 {
 451         struct wlc_info *wlc = (struct wlc_info *) arg;
 452         struct wlc_hw_info *wlc_hw = wlc->hw;
 453
 454         WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
 455
 456         if (!wlc_hw->up)
 457                 return;
 458
 459         /* increment second count */
 460         wlc_hw->now++;
 461
 462         /* Check for FIFO error interrupts */
 463         wlc_bmac_fifoerrors(wlc_hw);
 464
 465         /* make sure RX dma has buffers */
 466         dma_rxfill(wlc->hw->di[RX_FIFO]);
 467
 468         wlc_phy_watchdog(wlc_hw->band->pi);
 469 }
 470
 471 void
 472 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 473                       bool mute, struct txpwr_limits *txpwr)
 474 {
 475         uint bandunit;
 476
 477         WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
 478                  wlc_hw->unit, chanspec);
 479
 480         wlc_hw->chanspec = chanspec;
 481
 482         /* Switch bands if necessary */
 483         if (NBANDS_HW(wlc_hw) > 1) {
 484                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 485                 if (wlc_hw->band->bandunit != bandunit) {
 486                         /* wlc_bmac_setband disables other bandunit,
 487                          *  use light band switch if not up yet
 488                          */
 489                         if (wlc_hw->up) {
 490                                 wlc_phy_chanspec_radio_set(wlc_hw->
 491                                                            bandstate[bandunit]->
 492                                                            pi, chanspec);
 493                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 494                         } else {
 495                                 wlc_setxband(wlc_hw, bandunit);
 496                         }
 497                 }
 498         }
 499
 500         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 501
 502         if (!wlc_hw->up) {
 503                 if (wlc_hw->clk)
 504                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 505                                                   chanspec);
 506                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 507         } else {
 508                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 509                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 510
 511                 /* Update muting of the channel */
 512                 wlc_bmac_mute(wlc_hw, mute, 0);
 513         }
 514 }
 515
 516 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 517 {
 518         state->machwcap = wlc_hw->machwcap;
 519
 520         return 0;
 521 }
 522
 523 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 524 {
 525         uint i;
 526         char name[8];
 527         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 528         u16 pio_mhf2 = 0;
 529         struct wlc_hw_info *wlc_hw = wlc->hw;
 530         uint unit = wlc_hw->unit;
 531         wlc_tunables_t *tune = wlc->pub->tunables;
 532
 533         /* name and offsets for dma_attach */
 534         snprintf(name, sizeof(name), "wl%d", unit);
 535
 536         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 537                 uint addrwidth;
 538                 int dma_attach_err = 0;
 539                 struct osl_info *osh = wlc_hw->osh;
 540
 541                 /* Find out the DMA addressing capability and let OS know
 542                  * All the channels within one DMA core have 'common-minimum' same
 543                  * capability
 544                  */
 545                 addrwidth =
 546                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 547
 548                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 549                         WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
 550                                  unit);
 551                         return false;
 552                 }
 553
 554                 /*
 555                  * FIFO 0
 556                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 557                  * RX: RX_FIFO (RX data packets)
 558                  */
 559                 ASSERT(TX_AC_BK_FIFO == 0);
 560                 ASSERT(RX_FIFO == 0);
 561                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 562                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 563                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 564                                            (wme ? tune->ntxd : 0), tune->nrxd,
 565                                            tune->rxbufsz, -1, tune->nrxbufpost,
 566                                            WL_HWRXOFF, &wl_msg_level);
 567                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 568
 569                 /*
 570                  * FIFO 1
 571                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 572                  *   (legacy) TX_DATA_FIFO (TX data packets)
 573                  * RX: UNUSED
 574                  */
 575                 ASSERT(TX_AC_BE_FIFO == 1);
 576                 ASSERT(TX_DATA_FIFO == 1);
 577                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 578                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 579                                            tune->ntxd, 0, 0, -1, 0, 0,
 580                                            &wl_msg_level);
 581                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 582
 583                 /*
 584                  * FIFO 2
 585                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 586                  * RX: UNUSED
 587                  */
 588                 ASSERT(TX_AC_VI_FIFO == 2);
 589                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 590                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 591                                            tune->ntxd, 0, 0, -1, 0, 0,
 592                                            &wl_msg_level);
 593                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 594                 /*
 595                  * FIFO 3
 596                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 597                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 598                  * RX: RX_TXSTATUS_FIFO (transmit-status packets)
 599                  *      for corerev < 5 only
 600                  */
 601                 ASSERT(TX_AC_VO_FIFO == 3);
 602                 ASSERT(TX_CTL_FIFO == 3);
 603                 wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 604                                            DMAREG(wlc_hw, DMA_TX, 3),
 605                                            NULL, tune->ntxd, 0, 0, -1,
 606                                            0, 0, &wl_msg_level);
 607                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 608 /* Cleaner to leave this as if with AP defined */
 609
 610                 if (dma_attach_err) {
 611                         WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
 612                         return false;
 613                 }
 614
 615                 /* get pointer to dma engine tx flow control variable */
 616                 for (i = 0; i < NFIFO; i++)
 617                         if (wlc_hw->di[i])
 618                                 wlc_hw->txavail[i] =
 619                                     (uint *) dma_getvar(wlc_hw->di[i],
 620                                                         "&txavail");
 621         }
 622
 623         /* initial ucode host flags */
 624         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 625
 626         return true;
 627 }
 628
 629 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 630 {
 631         uint j;
 632
 633         for (j = 0; j < NFIFO; j++) {
 634                 if (wlc_hw->di[j]) {
 635                         dma_detach(wlc_hw->di[j]);
 636                         wlc_hw->di[j] = NULL;
 637                 }
 638         }
 639 }
 640
 641 /* low level attach
 642  *    run backplane attach, init nvram
 643  *    run phy attach
 644  *    initialize software state for each core and band
 645  *    put the whole chip in reset(driver down state), no clock
 646  */
 647 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 648                     bool piomode, struct osl_info *osh, void *regsva,
 649                     uint bustype, void *btparam)
 650 {
 651         struct wlc_hw_info *wlc_hw;
 652         d11regs_t *regs;
 653         char *macaddr = NULL;
 654         char *vars;
 655         uint err = 0;
 656         uint j;
 657         bool wme = false;
 658         shared_phy_params_t sha_params;
 659
 660         WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
 661                  unit, vendor, device);
 662
 663         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 664
 665         wme = true;
 666
 667         wlc_hw = wlc->hw;
 668         wlc_hw->wlc = wlc;
 669         wlc_hw->unit = unit;
 670         wlc_hw->osh = osh;
 671         wlc_hw->band = wlc_hw->bandstate[0];
 672         wlc_hw->_piomode = piomode;
 673
 674         /* populate struct wlc_hw_info with default values  */
 675         wlc_bmac_info_init(wlc_hw);
 676
 677         /*
 678          * Do the hardware portion of the attach.
 679          * Also initialize software state that depends on the particular hardware
 680          * we are running.
 681          */
 682         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 683                                 &wlc_hw->vars, &wlc_hw->vars_size);
 684         if (wlc_hw->sih == NULL) {
 685                 WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
 686                 err = 11;
 687                 goto fail;
 688         }
 689         vars = wlc_hw->vars;
 690
 691         /*
 692          * Get vendid/devid nvram overwrites, which could be different
 693          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 694          * SDIO_BUS, and SROMless devices on PCI_BUS.
 695          */
 696 #ifdef BCMBUSTYPE
 697         bustype = BCMBUSTYPE;
 698 #endif
 699         if (bustype != SI_BUS) {
 700                 char *var;
 701
 702                 var = getvar(vars, "vendid");
 703                 if (var) {
 704                         vendor = (u16) simple_strtoul(var, NULL, 0);
 705                         WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
 706                 }
 707                 var = getvar(vars, "devid");
 708                 if (var) {
 709                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 710                         if (devid != 0xffff) {
 711                                 device = devid;
 712                                 WL_ERROR("Overriding device id = 0x%x\n",
 713                                          device);
 714                         }
 715                 }
 716
 717                 /* verify again the device is supported */
 718                 if (!wlc_chipmatch(vendor, device)) {
 719                         WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
 720                                  unit, vendor, device);
 721                         err = 12;
 722                         goto fail;
 723                 }
 724         }
 725
 726         wlc_hw->vendorid = vendor;
 727         wlc_hw->deviceid = device;
 728
 729         /* set bar0 window to point at D11 core */
 730         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 731         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 732
 733         regs = wlc_hw->regs;
 734
 735         wlc->regs = wlc_hw->regs;
 736
 737         /* validate chip, chiprev and corerev */
 738         if (!wlc_isgoodchip(wlc_hw)) {
 739                 err = 13;
 740                 goto fail;
 741         }
 742
 743         /* initialize power control registers */
 744         si_clkctl_init(wlc_hw->sih);
 745
 746         /* request fastclock and force fastclock for the rest of attach
 747          * bring the d11 core out of reset.
 748          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 749          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 750          */
 751         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 752         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 753
 754         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 755                 WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
 756                          unit);
 757                 err = 14;
 758                 goto fail;
 759         }
 760
 761         /* get the board rev, used just below */
 762         j = getintvar(vars, "boardrev");
 763         /* promote srom boardrev of 0xFF to 1 */
 764         if (j == BOARDREV_PROMOTABLE)
 765                 j = BOARDREV_PROMOTED;
 766         wlc_hw->boardrev = (u16) j;
 767         if (!wlc_validboardtype(wlc_hw)) {
 768                 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
 769                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 770                 err = 15;
 771                 goto fail;
 772         }
 773         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 774         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 775         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 776
 777         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 778                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 779
 780         if ((wlc_hw->sih->bustype == PCI_BUS)
 781             && (si_pci_war16165(wlc_hw->sih)))
 782                 wlc->war16165 = true;
 783
 784         /* check device id(srom, nvram etc.) to set bands */
 785         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 786                 /* Dualband boards */
 787                 wlc_hw->_nbands = 2;
 788         } else
 789                 wlc_hw->_nbands = 1;
 790
 791         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 792                 wlc_hw->_nbands = 1;
 793
 794         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 795          * init of these values
 796          */
 797         wlc->vendorid = wlc_hw->vendorid;
 798         wlc->deviceid = wlc_hw->deviceid;
 799         wlc->pub->sih = wlc_hw->sih;
 800         wlc->pub->corerev = wlc_hw->corerev;
 801         wlc->pub->sromrev = wlc_hw->sromrev;
 802         wlc->pub->boardrev = wlc_hw->boardrev;
 803         wlc->pub->boardflags = wlc_hw->boardflags;
 804         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 805         wlc->pub->_nbands = wlc_hw->_nbands;
 806
 807         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 808
 809         if (wlc_hw->physhim == NULL) {
 810                 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 811                          unit);
 812                 err = 25;
 813                 goto fail;
 814         }
 815
 816         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 817         sha_params.osh = osh;
 818         sha_params.sih = wlc_hw->sih;
 819         sha_params.physhim = wlc_hw->physhim;
 820         sha_params.unit = unit;
 821         sha_params.corerev = wlc_hw->corerev;
 822         sha_params.vars = vars;
 823         sha_params.vid = wlc_hw->vendorid;
 824         sha_params.did = wlc_hw->deviceid;
 825         sha_params.chip = wlc_hw->sih->chip;
 826         sha_params.chiprev = wlc_hw->sih->chiprev;
 827         sha_params.chippkg = wlc_hw->sih->chippkg;
 828         sha_params.sromrev = wlc_hw->sromrev;
 829         sha_params.boardtype = wlc_hw->sih->boardtype;
 830         sha_params.boardrev = wlc_hw->boardrev;
 831         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 832         sha_params.boardflags = wlc_hw->boardflags;
 833         sha_params.boardflags2 = wlc_hw->boardflags2;
 834         sha_params.bustype = wlc_hw->sih->bustype;
 835         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 836
 837         /* alloc and save pointer to shared phy state area */
 838         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 839         if (!wlc_hw->phy_sh) {
 840                 err = 16;
 841                 goto fail;
 842         }
 843
 844         /* initialize software state for each core and band */
 845         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 846                 /*
 847                  * band0 is always 2.4Ghz
 848                  * band1, if present, is 5Ghz
 849                  */
 850
 851                 /* So if this is a single band 11a card, use band 1 */
 852                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 853                         j = BAND_5G_INDEX;
 854
 855                 wlc_setxband(wlc_hw, j);
 856
 857                 wlc_hw->band->bandunit = j;
 858                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 859                 wlc->band->bandunit = j;
 860                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 861                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 862
 863                 wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 864                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 865
 866                 /* init tx fifo size */
 867                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 868                        ARRAY_SIZE(xmtfifo_sz));
 869                 wlc_hw->xmtfifo_sz =
 870                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 871
 872                 /* Get a phy for this band */
 873                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 874                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
 875                 if (wlc_hw->band->pi == NULL) {
 876                         WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
 877                                  unit);
 878                         err = 17;
 879                         goto fail;
 880                 }
 881
 882                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 883
 884                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 885                                        &wlc_hw->band->phyrev,
 886                                        &wlc_hw->band->radioid,
 887                                        &wlc_hw->band->radiorev);
 888                 wlc_hw->band->abgphy_encore =
 889                     wlc_phy_get_encore(wlc_hw->band->pi);
 890                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 891                 wlc_hw->band->core_flags =
 892                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 893
 894                 /* verify good phy_type & supported phy revision */
 895                 if (WLCISNPHY(wlc_hw->band)) {
 896                         if (NCONF_HAS(wlc_hw->band->phyrev))
 897                                 goto good_phy;
 898                         else
 899                                 goto bad_phy;
 900                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 901                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 902                                 goto good_phy;
 903                         else
 904                                 goto bad_phy;
 905                 } else {
 906  bad_phy:
 907                         WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
 908                                  unit,
 909                                  wlc_hw->band->phytype, wlc_hw->band->phyrev);
 910                         err = 18;
 911                         goto fail;
 912                 }
 913
 914  good_phy:
 915                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 916                  * high level attach. However we can not make that change until all low level access
 917                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 918                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 919                  * low only init when all fns updated.
 920                  */
 921                 wlc->band->pi = wlc_hw->band->pi;
 922                 wlc->band->phytype = wlc_hw->band->phytype;
 923                 wlc->band->phyrev = wlc_hw->band->phyrev;
 924                 wlc->band->radioid = wlc_hw->band->radioid;
 925                 wlc->band->radiorev = wlc_hw->band->radiorev;
 926
 927                 /* default contention windows size limits */
 928                 wlc_hw->band->CWmin = APHY_CWMIN;
 929                 wlc_hw->band->CWmax = PHY_CWMAX;
 930
 931                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 932                         err = 19;
 933                         goto fail;
 934                 }
 935         }
 936
 937         /* disable core to match driver "down" state */
 938         wlc_coredisable(wlc_hw);
 939
 940         /* Match driver "down" state */
 941         if (wlc_hw->sih->bustype == PCI_BUS)
 942                 si_pci_down(wlc_hw->sih);
 943
 944         /* register sb interrupt callback functions */
 945         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 946                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 947
 948         /* turn off pll and xtal to match driver "down" state */
 949         wlc_bmac_xtal(wlc_hw, OFF);
 950
 951         /* *********************************************************************
 952          * The hardware is in the DOWN state at this point. D11 core
 953          * or cores are in reset with clocks off, and the board PLLs
 954          * are off if possible.
 955          *
 956          * Beyond this point, wlc->sbclk == false and chip registers
 957          * should not be touched.
 958          *********************************************************************
 959          */
 960
 961         /* init etheraddr state variables */
 962         macaddr = wlc_get_macaddr(wlc_hw);
 963         if (macaddr == NULL) {
 964                 WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
 965                 err = 21;
 966                 goto fail;
 967         }
 968         bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
 969         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 970             is_zero_ether_addr(wlc_hw->etheraddr)) {
 971                 WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
 972                          unit, macaddr);
 973                 err = 22;
 974                 goto fail;
 975         }
 976
 977         WL_TRACE("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 978                  __func__, wlc_hw->deviceid, wlc_hw->_nbands,
 979                  wlc_hw->sih->boardtype, macaddr);
 980
 981         return err;
 982
 983  fail:
 984         WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
 985         return err;
 986 }
 987
 988 /*
 989  * Initialize wlc_info default values ...
 990  * may get overrides later in this function
 991  *  BMAC_NOTES, move low out and resolve the dangling ones
 992  */
 993 void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
 994 {
 995         struct wlc_info *wlc = wlc_hw->wlc;
 996
 997         /* set default sw macintmask value */
 998         wlc->defmacintmask = DEF_MACINTMASK;
 999
1000         /* various 802.11g modes */
1001         wlc_hw->shortslot = false;
1002
1003         wlc_hw->SFBL = RETRY_SHORT_FB;
1004         wlc_hw->LFBL = RETRY_LONG_FB;
1005
1006         /* default mac retry limits */
1007         wlc_hw->SRL = RETRY_SHORT_DEF;
1008         wlc_hw->LRL = RETRY_LONG_DEF;
1009         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1010 }
1011
1012 /*
1013  * low level detach
1014  */
1015 int wlc_bmac_detach(struct wlc_info *wlc)
1016 {
1017         uint i;
1018         wlc_hwband_t *band;
1019         struct wlc_hw_info *wlc_hw = wlc->hw;
1020         int callbacks;
1021
1022         callbacks = 0;
1023
1024         if (wlc_hw->sih) {
1025                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1026                  * interrupt object may has been freed. this must be done before sb core switch
1027                  */
1028                 si_deregister_intr_callback(wlc_hw->sih);
1029
1030                 if (wlc_hw->sih->bustype == PCI_BUS)
1031                         si_pci_sleep(wlc_hw->sih);
1032         }
1033
1034         wlc_bmac_detach_dmapio(wlc_hw);
1035
1036         band = wlc_hw->band;
1037         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1038                 if (band->pi) {
1039                         /* Detach this band's phy */
1040                         wlc_phy_detach(band->pi);
1041                         band->pi = NULL;
1042                 }
1043                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1044         }
1045
1046         /* Free shared phy state */
1047         wlc_phy_shared_detach(wlc_hw->phy_sh);
1048
1049         wlc_phy_shim_detach(wlc_hw->physhim);
1050
1051         /* free vars */
1052         if (wlc_hw->vars) {
1053                 kfree(wlc_hw->vars);
1054                 wlc_hw->vars = NULL;
1055         }
1056
1057         if (wlc_hw->sih) {
1058                 si_detach(wlc_hw->sih);
1059                 wlc_hw->sih = NULL;
1060         }
1061
1062         return callbacks;
1063
1064 }
1065
1066 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1067 {
1068         WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1069
1070         wlc_hw->wlc->pub->_cnt->reset++;
1071
1072         /* reset the core */
1073         if (!DEVICEREMOVED(wlc_hw->wlc))
1074                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1075
1076         /* purge the dma rings */
1077         wlc_flushqueues(wlc_hw->wlc);
1078
1079         wlc_reset_bmac_done(wlc_hw->wlc);
1080 }
1081
1082 void
1083 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1084                           bool mute) {
1085         u32 macintmask;
1086         bool fastclk;
1087         struct wlc_info *wlc = wlc_hw->wlc;
1088
1089         WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1090
1091         /* request FAST clock if not on */
1092         fastclk = wlc_hw->forcefastclk;
1093         if (!fastclk)
1094                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1095
1096         /* disable interrupts */
1097         macintmask = wl_intrsoff(wlc->wl);
1098
1099         /* set up the specified band and chanspec */
1100         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1101         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1102
1103         /* do one-time phy inits and calibration */
1104         wlc_phy_cal_init(wlc_hw->band->pi);
1105
1106         /* core-specific initialization */
1107         wlc_coreinit(wlc);
1108
1109         /* suspend the tx fifos and mute the phy for preism cac time */
1110         if (mute)
1111                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1112
1113         /* band-specific inits */
1114         wlc_bmac_bsinit(wlc, chanspec);
1115
1116         /* restore macintmask */
1117         wl_intrsrestore(wlc->wl, macintmask);
1118
1119         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1120          * and wlc_enable_mac() will clear this override bit.
1121          */
1122         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1123
1124         /*
1125          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1126          */
1127         wlc_hw->mac_suspend_depth = 1;
1128
1129         /* restore the clk */
1130         if (!fastclk)
1131                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1132 }
1133
1134 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1135 {
1136         uint coremask;
1137
1138         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1139
1140         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1141
1142         /*
1143          * Enable pll and xtal, initialize the power control registers,
1144          * and force fastclock for the remainder of wlc_up().
1145          */
1146         wlc_bmac_xtal(wlc_hw, ON);
1147         si_clkctl_init(wlc_hw->sih);
1148         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1149
1150         /*
1151          * Configure pci/pcmcia here instead of in wlc_attach()
1152          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1153          */
1154         coremask = (1 << wlc_hw->wlc->core->coreidx);
1155
1156         if (wlc_hw->sih->bustype == PCI_BUS)
1157                 si_pci_setup(wlc_hw->sih, coremask);
1158
1159         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1160
1161         /*
1162          * Need to read the hwradio status here to cover the case where the system
1163          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1164          */
1165         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1166                 /* put SB PCI in down state again */
1167                 if (wlc_hw->sih->bustype == PCI_BUS)
1168                         si_pci_down(wlc_hw->sih);
1169                 wlc_bmac_xtal(wlc_hw, OFF);
1170                 return BCME_RADIOOFF;
1171         }
1172
1173         if (wlc_hw->sih->bustype == PCI_BUS)
1174                 si_pci_up(wlc_hw->sih);
1175
1176         /* reset the d11 core */
1177         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1178
1179         return 0;
1180 }
1181
1182 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1183 {
1184         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1185
1186         wlc_hw->up = true;
1187         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1188
1189         /* FULLY enable dynamic power control and d11 core interrupt */
1190         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1191         ASSERT(wlc_hw->wlc->macintmask == 0);
1192         wl_intrson(wlc_hw->wlc->wl);
1193         return 0;
1194 }
1195
1196 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1197 {
1198         bool dev_gone;
1199         uint callbacks = 0;
1200
1201         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1202
1203         if (!wlc_hw->up)
1204                 return callbacks;
1205
1206         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1207
1208         /* disable interrupts */
1209         if (dev_gone)
1210                 wlc_hw->wlc->macintmask = 0;
1211         else {
1212                 /* now disable interrupts */
1213                 wl_intrsoff(wlc_hw->wlc->wl);
1214
1215                 /* ensure we're running on the pll clock again */
1216                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1217         }
1218         /* down phy at the last of this stage */
1219         callbacks += wlc_phy_down(wlc_hw->band->pi);
1220
1221         return callbacks;
1222 }
1223
1224 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1225 {
1226         uint callbacks = 0;
1227         bool dev_gone;
1228
1229         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1230
1231         if (!wlc_hw->up)
1232                 return callbacks;
1233
1234         wlc_hw->up = false;
1235         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1236
1237         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1238
1239         if (dev_gone) {
1240                 wlc_hw->sbclk = false;
1241                 wlc_hw->clk = false;
1242                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1243
1244                 /* reclaim any posted packets */
1245                 wlc_flushqueues(wlc_hw->wlc);
1246         } else {
1247
1248                 /* Reset and disable the core */
1249                 if (si_iscoreup(wlc_hw->sih)) {
1250                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1251                             MCTL_EN_MAC)
1252                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1253                         callbacks += wl_reset(wlc_hw->wlc->wl);
1254                         wlc_coredisable(wlc_hw);
1255                 }
1256
1257                 /* turn off primary xtal and pll */
1258                 if (!wlc_hw->noreset) {
1259                         if (wlc_hw->sih->bustype == PCI_BUS)
1260                                 si_pci_down(wlc_hw->sih);
1261                         wlc_bmac_xtal(wlc_hw, OFF);
1262                 }
1263         }
1264
1265         return callbacks;
1266 }
1267
1268 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1269 {
1270         /* delay before first read of ucode state */
1271         udelay(40);
1272
1273         /* wait until ucode is no longer asleep */
1274         SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1275                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1276
1277         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1278 }
1279
1280 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1281 {
1282         bcopy(wlc_hw->etheraddr, ea, ETH_ALEN);
1283 }
1284
1285 int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1286 {
1287         return wlc_hw->band->bandtype;
1288 }
1289
1290 /* control chip clock to save power, enable dynamic clock or force fast clock */
1291 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1292 {
1293         if (PMUCTL_ENAB(wlc_hw->sih)) {
1294                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1295                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1296                  *      which means the FCA bit may not be set.
1297                  *      should wakeup mac if driver wants it to run on HT.
1298                  */
1299
1300                 if (wlc_hw->clk) {
1301                         if (mode == CLK_FAST) {
1302                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1303                                        CCS_FORCEHT);
1304
1305                                 udelay(64);
1306
1307                                 SPINWAIT(((R_REG
1308                                            (wlc_hw->osh,
1309                                             &wlc_hw->regs->
1310                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1311                                          PMU_MAX_TRANSITION_DLY);
1312                                 ASSERT(R_REG
1313                                        (wlc_hw->osh,
1314                                         &wlc_hw->regs->
1315                                         clk_ctl_st) & CCS_HTAVAIL);
1316                         } else {
1317                                 if ((wlc_hw->sih->pmurev == 0) &&
1318                                     (R_REG
1319                                      (wlc_hw->osh,
1320                                       &wlc_hw->regs->
1321                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1322                                         SPINWAIT(((R_REG
1323                                                    (wlc_hw->osh,
1324                                                     &wlc_hw->regs->
1325                                                     clk_ctl_st) & CCS_HTAVAIL)
1326                                                   == 0),
1327                                                  PMU_MAX_TRANSITION_DLY);
1328                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1329                                         ~CCS_FORCEHT);
1330                         }
1331                 }
1332                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1333         } else {
1334                 bool wakeup_ucode;
1335
1336                 /* old chips w/o PMU, force HT through cc,
1337                  * then use FCA to verify mac is running fast clock
1338                  */
1339
1340                 wakeup_ucode = false;
1341
1342                 if (wlc_hw->up && wakeup_ucode)
1343                         wlc_ucode_wake_override_set(wlc_hw,
1344                                                     WLC_WAKE_OVERRIDE_CLKCTL);
1345
1346                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1347
1348                 /* check fast clock is available (if core is not in reset) */
1349                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1350                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1351
1352                 /* keep the ucode wake bit on if forcefastclk is on
1353                  * since we do not want ucode to put us back to slow clock
1354                  * when it dozes for PM mode.
1355                  * Code below matches the wake override bit with current forcefastclk state
1356                  * Only setting bit in wake_override instead of waking ucode immediately
1357                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1358                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1359                  * (protected by an up check) was executed just below.
1360                  */
1361                 if (wlc_hw->forcefastclk)
1362                         mboolset(wlc_hw->wake_override,
1363                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1364                 else
1365                         mboolclr(wlc_hw->wake_override,
1366                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1367
1368                 /* ok to clear the wakeup now */
1369                 if (wlc_hw->up && wakeup_ucode)
1370                         wlc_ucode_wake_override_clear(wlc_hw,
1371                                                       WLC_WAKE_OVERRIDE_CLKCTL);
1372         }
1373 }
1374
1375 /* set initial host flags value */
1376 static void
1377 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1378 {
1379         struct wlc_hw_info *wlc_hw = wlc->hw;
1380
1381         memset(mhfs, 0, MHFMAX * sizeof(u16));
1382
1383         mhfs[MHF2] |= mhf2_init;
1384
1385         /* prohibit use of slowclock on multifunction boards */
1386         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1387                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1388
1389         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1390                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1391                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1392         }
1393 }
1394
1395 /* set or clear ucode host flag bits
1396  * it has an optimization for no-change write
1397  * it only writes through shared memory when the core has clock;
1398  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1399  *
1400  *
1401  * bands values are: WLC_BAND_AUTO <--- Current band only
1402  *                   WLC_BAND_5G   <--- 5G band only
1403  *                   WLC_BAND_2G   <--- 2G band only
1404  *                   WLC_BAND_ALL  <--- All bands
1405  */
1406 void
1407 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1408              int bands)
1409 {
1410         u16 save;
1411         u16 addr[MHFMAX] = {
1412                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1413                 M_HOST_FLAGS5
1414         };
1415         wlc_hwband_t *band;
1416
1417         ASSERT((val & ~mask) == 0);
1418         ASSERT(idx < MHFMAX);
1419         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1420
1421         switch (bands) {
1422                 /* Current band only or all bands,
1423                  * then set the band to current band
1424                  */
1425         case WLC_BAND_AUTO:
1426         case WLC_BAND_ALL:
1427                 band = wlc_hw->band;
1428                 break;
1429         case WLC_BAND_5G:
1430                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1431                 break;
1432         case WLC_BAND_2G:
1433                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1434                 break;
1435         default:
1436                 ASSERT(0);
1437                 band = NULL;
1438         }
1439
1440         if (band) {
1441                 save = band->mhfs[idx];
1442                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1443
1444                 /* optimization: only write through if changed, and
1445                  * changed band is the current band
1446                  */
1447                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1448                     && (band == wlc_hw->band))
1449                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1450                                            (u16) band->mhfs[idx]);
1451         }
1452
1453         if (bands == WLC_BAND_ALL) {
1454                 wlc_hw->bandstate[0]->mhfs[idx] =
1455                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1456                 wlc_hw->bandstate[1]->mhfs[idx] =
1457                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1458         }
1459 }
1460
1461 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1462 {
1463         wlc_hwband_t *band;
1464         ASSERT(idx < MHFMAX);
1465
1466         switch (bands) {
1467         case WLC_BAND_AUTO:
1468                 band = wlc_hw->band;
1469                 break;
1470         case WLC_BAND_5G:
1471                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1472                 break;
1473         case WLC_BAND_2G:
1474                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1475                 break;
1476         default:
1477                 ASSERT(0);
1478                 band = NULL;
1479         }
1480
1481         if (!band)
1482                 return 0;
1483
1484         return band->mhfs[idx];
1485 }
1486
1487 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1488 {
1489         u8 idx;
1490         u16 addr[] = {
1491                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1492                 M_HOST_FLAGS5
1493         };
1494
1495         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1496
1497         for (idx = 0; idx < MHFMAX; idx++) {
1498                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1499         }
1500 }
1501
1502 /* set the maccontrol register to desired reset state and
1503  * initialize the sw cache of the register
1504  */
1505 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1506 {
1507         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1508         wlc_hw->maccontrol = 0;
1509         wlc_hw->suspended_fifos = 0;
1510         wlc_hw->wake_override = 0;
1511         wlc_hw->mute_override = 0;
1512         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1513 }
1514
1515 /* set or clear maccontrol bits */
1516 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1517 {
1518         u32 maccontrol;
1519         u32 new_maccontrol;
1520
1521         ASSERT((val & ~mask) == 0);
1522
1523         maccontrol = wlc_hw->maccontrol;
1524         new_maccontrol = (maccontrol & ~mask) | val;
1525
1526         /* if the new maccontrol value is the same as the old, nothing to do */
1527         if (new_maccontrol == maccontrol)
1528                 return;
1529
1530         /* something changed, cache the new value */
1531         wlc_hw->maccontrol = new_maccontrol;
1532
1533         /* write the new values with overrides applied */
1534         wlc_mctrl_write(wlc_hw);
1535 }
1536
1537 /* write the software state of maccontrol and overrides to the maccontrol register */
1538 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1539 {
1540         u32 maccontrol = wlc_hw->maccontrol;
1541
1542         /* OR in the wake bit if overridden */
1543         if (wlc_hw->wake_override)
1544                 maccontrol |= MCTL_WAKE;
1545
1546         /* set AP and INFRA bits for mute if needed */
1547         if (wlc_hw->mute_override) {
1548                 maccontrol &= ~(MCTL_AP);
1549                 maccontrol |= MCTL_INFRA;
1550         }
1551
1552         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1553 }
1554
1555 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1556 {
1557         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1558
1559         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1560                 mboolset(wlc_hw->wake_override, override_bit);
1561                 return;
1562         }
1563
1564         mboolset(wlc_hw->wake_override, override_bit);
1565
1566         wlc_mctrl_write(wlc_hw);
1567         wlc_bmac_wait_for_wake(wlc_hw);
1568
1569         return;
1570 }
1571
1572 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1573 {
1574         ASSERT(wlc_hw->wake_override & override_bit);
1575
1576         mboolclr(wlc_hw->wake_override, override_bit);
1577
1578         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1579                 return;
1580
1581         wlc_mctrl_write(wlc_hw);
1582
1583         return;
1584 }
1585
1586 /* When driver needs ucode to stop beaconing, it has to make sure that
1587  * MCTL_AP is clear and MCTL_INFRA is set
1588  * Mode           MCTL_AP        MCTL_INFRA
1589  * AP                1              1
1590  * STA               0              1 <--- This will ensure no beacons
1591  * IBSS              0              0
1592  */
1593 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1594 {
1595         wlc_hw->mute_override = 1;
1596
1597         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1598          * override, then there is no change to write
1599          */
1600         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1601                 return;
1602
1603         wlc_mctrl_write(wlc_hw);
1604
1605         return;
1606 }
1607
1608 /* Clear the override on AP and INFRA bits */
1609 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1610 {
1611         if (wlc_hw->mute_override == 0)
1612                 return;
1613
1614         wlc_hw->mute_override = 0;
1615
1616         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1617          * override, then there is no change to write
1618          */
1619         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1620                 return;
1621
1622         wlc_mctrl_write(wlc_hw);
1623 }
1624
1625 /*
1626  * Write a MAC address to the rcmta structure
1627  */
1628 void
1629 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1630                    const u8 *addr)
1631 {
1632         d11regs_t *regs = wlc_hw->regs;
1633         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1634         u32 mac_hm;
1635         u16 mac_l;
1636         struct osl_info *osh;
1637
1638         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1639
1640         ASSERT(wlc_hw->corerev > 4);
1641
1642         mac_hm =
1643             (addr[3] << 24) | (addr[2] << 16) |
1644             (addr[1] << 8) | addr[0];
1645         mac_l = (addr[5] << 8) | addr[4];
1646
1647         osh = wlc_hw->osh;
1648
1649         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1650         (void)R_REG(osh, &regs->objaddr);
1651         W_REG(osh, &regs->objdata, mac_hm);
1652         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1653         (void)R_REG(osh, &regs->objaddr);
1654         W_REG(osh, objdata16, mac_l);
1655 }
1656
1657 /*
1658  * Write a MAC address to the given match reg offset in the RXE match engine.
1659  */
1660 void
1661 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1662                        const u8 *addr)
1663 {
1664         d11regs_t *regs;
1665         u16 mac_l;
1666         u16 mac_m;
1667         u16 mac_h;
1668         struct osl_info *osh;
1669
1670         WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1671
1672         ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1673
1674         regs = wlc_hw->regs;
1675         mac_l = addr[0] | (addr[1] << 8);
1676         mac_m = addr[2] | (addr[3] << 8);
1677         mac_h = addr[4] | (addr[5] << 8);
1678
1679         osh = wlc_hw->osh;
1680
1681         /* enter the MAC addr into the RXE match registers */
1682         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1683         W_REG(osh, &regs->rcm_mat_data, mac_l);
1684         W_REG(osh, &regs->rcm_mat_data, mac_m);
1685         W_REG(osh, &regs->rcm_mat_data, mac_h);
1686
1687 }
1688
1689 void
1690 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1691                             void *buf)
1692 {
1693         d11regs_t *regs;
1694         u32 word;
1695         bool be_bit;
1696 #ifdef IL_BIGENDIAN
1697         volatile u16 *dptr = NULL;
1698 #endif                          /* IL_BIGENDIAN */
1699         struct osl_info *osh;
1700
1701         WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1702
1703         regs = wlc_hw->regs;
1704         osh = wlc_hw->osh;
1705
1706         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1707         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1708         ASSERT((offset & ~0xffff) == 0);
1709
1710         W_REG(osh, &regs->tplatewrptr, offset);
1711
1712         /* if MCTL_BIGEND bit set in mac control register,
1713          * the chip swaps data in fifo, as well as data in
1714          * template ram
1715          */
1716         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1717
1718         while (len > 0) {
1719                 bcopy((u8 *) buf, &word, sizeof(u32));
1720
1721                 if (be_bit)
1722                         word = hton32(word);
1723                 else
1724                         word = htol32(word);
1725
1726                 W_REG(osh, &regs->tplatewrdata, word);
1727
1728                 buf = (u8 *) buf + sizeof(u32);
1729                 len -= sizeof(u32);
1730         }
1731 }
1732
1733 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1734 {
1735         struct osl_info *osh;
1736
1737         osh = wlc_hw->osh;
1738         wlc_hw->band->CWmin = newmin;
1739
1740         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1741         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1742         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1743 }
1744
1745 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1746 {
1747         struct osl_info *osh;
1748
1749         osh = wlc_hw->osh;
1750         wlc_hw->band->CWmax = newmax;
1751
1752         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1753         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1754         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1755 }
1756
1757 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1758 {
1759         bool fastclk;
1760         u32 tmp;
1761
1762         /* request FAST clock if not on */
1763         fastclk = wlc_hw->forcefastclk;
1764         if (!fastclk)
1765                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1766
1767         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1768
1769         ASSERT(wlc_hw->clk);
1770
1771         wlc_bmac_phy_reset(wlc_hw);
1772         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1773
1774         /* restore the clk */
1775         if (!fastclk)
1776                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1777 }
1778
1779 static void
1780 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1781 {
1782         d11regs_t *regs = wlc_hw->regs;
1783
1784         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1785                                     bcn);
1786         /* write beacon length to SCR */
1787         ASSERT(len < 65536);
1788         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1789         /* mark beacon0 valid */
1790         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1791 }
1792
1793 static void
1794 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1795 {
1796         d11regs_t *regs = wlc_hw->regs;
1797
1798         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1799                                     bcn);
1800         /* write beacon length to SCR */
1801         ASSERT(len < 65536);
1802         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1803         /* mark beacon1 valid */
1804         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1805 }
1806
1807 /* mac is assumed to be suspended at this point */
1808 void
1809 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1810                                bool both)
1811 {
1812         d11regs_t *regs = wlc_hw->regs;
1813
1814         if (both) {
1815                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1816                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1817         } else {
1818                 /* bcn 0 */
1819                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1820                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1821                 /* bcn 1 */
1822                 else if (!
1823                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1824                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1825                 else            /* one template should always have been available */
1826                         ASSERT(0);
1827         }
1828 }
1829
1830 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1831 {
1832         u16 v;
1833         struct wlc_info *wlc = wlc_hw->wlc;
1834         /* update SYNTHPU_DLY */
1835
1836         if (WLCISLCNPHY(wlc->band)) {
1837                 v = SYNTHPU_DLY_LPPHY_US;
1838         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1839                 v = SYNTHPU_DLY_NPHY_US;
1840         } else {
1841                 v = SYNTHPU_DLY_BPHY_US;
1842         }
1843
1844         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1845 }
1846
1847 /* band-specific init */
1848 static void
1849 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1850 {
1851         struct wlc_hw_info *wlc_hw = wlc->hw;
1852
1853         WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1854                  wlc_hw->unit, wlc_hw->band->bandunit);
1855
1856         /* sanity check */
1857         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1858             PHY_TYPE_LCNXN)
1859                 ASSERT((uint)
1860                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1861                        == wlc_hw->band->phytype);
1862
1863         wlc_ucode_bsinit(wlc_hw);
1864
1865         wlc_phy_init(wlc_hw->band->pi, chanspec);
1866
1867         wlc_ucode_txant_set(wlc_hw);
1868
1869         /* cwmin is band-specific, update hardware with value for current band */
1870         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1871         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1872
1873         wlc_bmac_update_slot_timing(wlc_hw,
1874                                     BAND_5G(wlc_hw->band->
1875                                             bandtype) ? true : wlc_hw->
1876                                     shortslot);
1877
1878         /* write phytype and phyvers */
1879         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1880         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1881
1882         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1883         wlc_upd_ofdm_pctl1_table(wlc_hw);
1884
1885         wlc_bmac_upd_synthpu(wlc_hw);
1886 }
1887
1888 void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1889 {
1890         WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1891
1892         wlc_hw->phyclk = clk;
1893
1894         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1895
1896                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1897                                (SICF_PRST | SICF_FGC));
1898                 udelay(1);
1899                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1900                 udelay(1);
1901
1902         } else {                /* take phy out of reset */
1903
1904                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1905                 udelay(1);
1906                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1907                 udelay(1);
1908
1909         }
1910 }
1911
1912 /* Perform a soft reset of the PHY PLL */
1913 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1914 {
1915         WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1916
1917         si_corereg(wlc_hw->sih, SI_CC_IDX,
1918                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1919         udelay(1);
1920         si_corereg(wlc_hw->sih, SI_CC_IDX,
1921                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1922         udelay(1);
1923         si_corereg(wlc_hw->sih, SI_CC_IDX,
1924                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1925         udelay(1);
1926         si_corereg(wlc_hw->sih, SI_CC_IDX,
1927                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1928         udelay(1);
1929 }
1930
1931 /* light way to turn on phy clock without reset for NPHY only
1932  *  refer to wlc_bmac_core_phy_clk for full version
1933  */
1934 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1935 {
1936         /* support(necessary for NPHY and HYPHY) only */
1937         if (!WLCISNPHY(wlc_hw->band))
1938                 return;
1939
1940         if (ON == clk)
1941                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1942         else
1943                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1944
1945 }
1946
1947 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1948 {
1949         if (ON == clk)
1950                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1951         else
1952                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1953 }
1954
1955 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1956 {
1957         wlc_phy_t *pih = wlc_hw->band->pi;
1958         u32 phy_bw_clkbits;
1959         bool phy_in_reset = false;
1960
1961         WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
1962
1963         if (pih == NULL)
1964                 return;
1965
1966         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1967
1968         /* Specfic reset sequence required for NPHY rev 3 and 4 */
1969         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1970             NREV_LE(wlc_hw->band->phyrev, 4)) {
1971                 /* Set the PHY bandwidth */
1972                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1973
1974                 udelay(1);
1975
1976                 /* Perform a soft reset of the PHY PLL */
1977                 wlc_bmac_core_phypll_reset(wlc_hw);
1978
1979                 /* reset the PHY */
1980                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1981                                (SICF_PRST | SICF_PCLKE));
1982                 phy_in_reset = true;
1983         } else {
1984
1985                 si_core_cflags(wlc_hw->sih,
1986                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1987                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1988         }
1989
1990         udelay(2);
1991         wlc_bmac_core_phy_clk(wlc_hw, ON);
1992
1993         if (pih)
1994                 wlc_phy_anacore(pih, ON);
1995 }
1996
1997 /* switch to and initialize new band */
1998 static void
1999 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
2000                                 chanspec_t chanspec) {
2001         struct wlc_info *wlc = wlc_hw->wlc;
2002         u32 macintmask;
2003
2004         ASSERT(NBANDS_HW(wlc_hw) > 1);
2005         ASSERT(bandunit != wlc_hw->band->bandunit);
2006
2007         /* Enable the d11 core before accessing it */
2008         if (!si_iscoreup(wlc_hw->sih)) {
2009                 si_core_reset(wlc_hw->sih, 0, 0);
2010                 ASSERT(si_iscoreup(wlc_hw->sih));
2011                 wlc_mctrl_reset(wlc_hw);
2012         }
2013
2014         macintmask = wlc_setband_inact(wlc, bandunit);
2015
2016         if (!wlc_hw->up)
2017                 return;
2018
2019         wlc_bmac_core_phy_clk(wlc_hw, ON);
2020
2021         /* band-specific initializations */
2022         wlc_bmac_bsinit(wlc, chanspec);
2023
2024         /*
2025          * If there are any pending software interrupt bits,
2026          * then replace these with a harmless nonzero value
2027          * so wlc_dpc() will re-enable interrupts when done.
2028          */
2029         if (wlc->macintstatus)
2030                 wlc->macintstatus = MI_DMAINT;
2031
2032         /* restore macintmask */
2033         wl_intrsrestore(wlc->wl, macintmask);
2034
2035         /* ucode should still be suspended.. */
2036         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2037                0);
2038 }
2039
2040 /* low-level band switch utility routine */
2041 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
2042 {
2043         WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
2044
2045         wlc_hw->band = wlc_hw->bandstate[bandunit];
2046
2047         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2048         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2049
2050         /* set gmode core flag */
2051         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2052                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2053                                ((bandunit == 0) ? SICF_GMODE : 0));
2054         }
2055 }
2056
2057 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
2058 {
2059
2060         /* reject unsupported corerev */
2061         if (!VALID_COREREV(wlc_hw->corerev)) {
2062                 WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
2063                 return false;
2064         }
2065
2066         return true;
2067 }
2068
2069 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
2070 {
2071         bool goodboard = true;
2072         uint boardrev = wlc_hw->boardrev;
2073
2074         if (boardrev == 0)
2075                 goodboard = false;
2076         else if (boardrev > 0xff) {
2077                 uint brt = (boardrev & 0xf000) >> 12;
2078                 uint b0 = (boardrev & 0xf00) >> 8;
2079                 uint b1 = (boardrev & 0xf0) >> 4;
2080                 uint b2 = boardrev & 0xf;
2081
2082                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2083                     || (b2 > 9))
2084                         goodboard = false;
2085         }
2086
2087         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2088                 return goodboard;
2089
2090         return goodboard;
2091 }
2092
2093 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
2094 {
2095         const char *varname = "macaddr";
2096         char *macaddr;
2097
2098         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2099         macaddr = getvar(wlc_hw->vars, varname);
2100         if (macaddr != NULL)
2101                 return macaddr;
2102
2103         if (NBANDS_HW(wlc_hw) > 1)
2104                 varname = "et1macaddr";
2105         else
2106                 varname = "il0macaddr";
2107
2108         macaddr = getvar(wlc_hw->vars, varname);
2109         if (macaddr == NULL) {
2110                 WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
2111                          wlc_hw->unit, varname);
2112         }
2113
2114         return macaddr;
2115 }
2116
2117 /*
2118  * Return true if radio is disabled, otherwise false.
2119  * hw radio disable signal is an external pin, users activate it asynchronously
2120  * this function could be called when driver is down and w/o clock
2121  * it operates on different registers depending on corerev and boardflag.
2122  */
2123 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2124 {
2125         bool v, clk, xtal;
2126         u32 resetbits = 0, flags = 0;
2127
2128         xtal = wlc_hw->sbclk;
2129         if (!xtal)
2130                 wlc_bmac_xtal(wlc_hw, ON);
2131
2132         /* may need to take core out of reset first */
2133         clk = wlc_hw->clk;
2134         if (!clk) {
2135                 /*
2136                  * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2137                  * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2138                  */
2139                 flags |= SICF_PCLKE;
2140
2141                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2142                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2143                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2144                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2145                         wlc_hw->regs =
2146                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2147                                                      0);
2148                 si_core_reset(wlc_hw->sih, flags, resetbits);
2149                 wlc_mctrl_reset(wlc_hw);
2150         }
2151
2152         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2153
2154         /* put core back into reset */
2155         if (!clk)
2156                 si_core_disable(wlc_hw->sih, 0);
2157
2158         if (!xtal)
2159                 wlc_bmac_xtal(wlc_hw, OFF);
2160
2161         return v;
2162 }
2163
2164 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2165 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2166 {
2167         if (wlc_hw->wlc->pub->hw_up)
2168                 return;
2169
2170         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2171
2172         /*
2173          * Enable pll and xtal, initialize the power control registers,
2174          * and force fastclock for the remainder of wlc_up().
2175          */
2176         wlc_bmac_xtal(wlc_hw, ON);
2177         si_clkctl_init(wlc_hw->sih);
2178         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2179
2180         if (wlc_hw->sih->bustype == PCI_BUS) {
2181                 si_pci_fixcfg(wlc_hw->sih);
2182
2183                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2184                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2185                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2186                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2187                         wlc_hw->regs =
2188                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2189                                                      0);
2190         }
2191
2192         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2193         wlc_phy_por_inform(wlc_hw->band->pi);
2194
2195         wlc_hw->ucode_loaded = false;
2196         wlc_hw->wlc->pub->hw_up = true;
2197
2198         if ((wlc_hw->boardflags & BFL_FEM)
2199             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2200                 if (!
2201                     (wlc_hw->boardrev >= 0x1250
2202                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2203                         si_epa_4313war(wlc_hw->sih);
2204         }
2205 }
2206
2207 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2208 {
2209         struct hnddma_pub *di = wlc_hw->di[fifo];
2210         return dma_rxreset(di);
2211 }
2212
2213 /* d11 core reset
2214  *   ensure fask clock during reset
2215  *   reset dma
2216  *   reset d11(out of reset)
2217  *   reset phy(out of reset)
2218  *   clear software macintstatus for fresh new start
2219  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2220  */
2221 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2222 {
2223         d11regs_t *regs;
2224         uint i;
2225         bool fastclk;
2226         u32 resetbits = 0;
2227
2228         if (flags == WLC_USE_COREFLAGS)
2229                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2230
2231         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2232
2233         regs = wlc_hw->regs;
2234
2235         /* request FAST clock if not on  */
2236         fastclk = wlc_hw->forcefastclk;
2237         if (!fastclk)
2238                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2239
2240         /* reset the dma engines except first time thru */
2241         if (si_iscoreup(wlc_hw->sih)) {
2242                 for (i = 0; i < NFIFO; i++)
2243                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2244                                 WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
2245                                          wlc_hw->unit, __func__, i);
2246                         }
2247
2248                 if ((wlc_hw->di[RX_FIFO])
2249                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2250                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2251                                  wlc_hw->unit, __func__, RX_FIFO);
2252                 }
2253         }
2254         /* if noreset, just stop the psm and return */
2255         if (wlc_hw->noreset) {
2256                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2257                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2258                 return;
2259         }
2260
2261         /*
2262          * mac no longer enables phyclk automatically when driver accesses
2263          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2264          * band->pi is invalid. need to enable PHY CLK
2265          */
2266         flags |= SICF_PCLKE;
2267
2268         /* reset the core
2269          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2270          *  is cleared by the core_reset. have to re-request it.
2271          *  This adds some delay and we can optimize it by also requesting fastclk through
2272          *  chipcommon during this period if necessary. But that has to work coordinate
2273          *  with other driver like mips/arm since they may touch chipcommon as well.
2274          */
2275         wlc_hw->clk = false;
2276         si_core_reset(wlc_hw->sih, flags, resetbits);
2277         wlc_hw->clk = true;
2278         if (wlc_hw->band && wlc_hw->band->pi)
2279                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2280
2281         wlc_mctrl_reset(wlc_hw);
2282
2283         if (PMUCTL_ENAB(wlc_hw->sih))
2284                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2285
2286         wlc_bmac_phy_reset(wlc_hw);
2287
2288         /* turn on PHY_PLL */
2289         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2290
2291         /* clear sw intstatus */
2292         wlc_hw->wlc->macintstatus = 0;
2293
2294         /* restore the clk setting */
2295         if (!fastclk)
2296                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2297 }
2298
2299 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2300  * txfifo sizes needs to be modified(increased) since the newer cores
2301  * have more memory.
2302  */
2303 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2304 {
2305         d11regs_t *regs = wlc_hw->regs;
2306         u16 fifo_nu;
2307         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2308         u16 txfifo_def, txfifo_def1;
2309         u16 txfifo_cmd;
2310         struct osl_info *osh;
2311
2312         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2313         txfifo_startblk = TXFIFO_START_BLK;
2314
2315         osh = wlc_hw->osh;
2316
2317         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2318         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2319
2320                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2321                 txfifo_def = (txfifo_startblk & 0xff) |
2322                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2323                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2324                     ((((txfifo_endblk -
2325                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2326                 txfifo_cmd =
2327                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2328
2329                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2330                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2331                 W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2332
2333                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2334
2335                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2336         }
2337  exit:
2338         /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2339         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2340                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2341         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2342                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2343         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2344                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2345                             xmtfifo_sz[TX_AC_BK_FIFO]));
2346         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2347                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2348                             xmtfifo_sz[TX_BCMC_FIFO]));
2349 }
2350
2351 /* d11 core init
2352  *   reset PSM
2353  *   download ucode/PCM
2354  *   let ucode run to suspended
2355  *   download ucode inits
2356  *   config other core registers
2357  *   init dma
2358  */
2359 static void wlc_coreinit(struct wlc_info *wlc)
2360 {
2361         struct wlc_hw_info *wlc_hw = wlc->hw;
2362         d11regs_t *regs;
2363         u32 sflags;
2364         uint bcnint_us;
2365         uint i = 0;
2366         bool fifosz_fixup = false;
2367         struct osl_info *osh;
2368         int err = 0;
2369         u16 buf[NFIFO];
2370
2371         regs = wlc_hw->regs;
2372         osh = wlc_hw->osh;
2373
2374         WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2375
2376         /* reset PSM */
2377         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2378
2379         wlc_ucode_download(wlc_hw);
2380         /*
2381          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2382          */
2383         fifosz_fixup = true;
2384
2385         /* let the PSM run to the suspended state, set mode to BSS STA */
2386         W_REG(osh, &regs->macintstatus, -1);
2387         wlc_bmac_mctrl(wlc_hw, ~0,
2388                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2389
2390         /* wait for ucode to self-suspend after auto-init */
2391         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2392                  1000 * 1000);
2393         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2394                 WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2395                          wlc_hw->unit);
2396
2397         wlc_gpio_init(wlc);
2398
2399         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2400
2401         if (D11REV_IS(wlc_hw->corerev, 23)) {
2402                 if (WLCISNPHY(wlc_hw->band))
2403                         wlc_write_inits(wlc_hw, d11n0initvals16);
2404                 else
2405                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2406                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2407         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2408                 if (WLCISLCNPHY(wlc_hw->band)) {
2409                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2410                 } else {
2411                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2412                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2413                 }
2414         } else {
2415                 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
2416                          __func__, wlc_hw->unit, wlc_hw->corerev);
2417         }
2418
2419         /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2420         if (fifosz_fixup == true) {
2421                 wlc_corerev_fifofixup(wlc_hw);
2422         }
2423
2424         /* check txfifo allocations match between ucode and driver */
2425         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2426         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2427                 i = TX_AC_BE_FIFO;
2428                 err = -1;
2429         }
2430         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2431         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2432                 i = TX_AC_VI_FIFO;
2433                 err = -1;
2434         }
2435         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2436         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2437         buf[TX_AC_BK_FIFO] &= 0xff;
2438         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2439                 i = TX_AC_BK_FIFO;
2440                 err = -1;
2441         }
2442         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2443                 i = TX_AC_VO_FIFO;
2444                 err = -1;
2445         }
2446         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2447         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2448         buf[TX_BCMC_FIFO] &= 0xff;
2449         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2450                 i = TX_BCMC_FIFO;
2451                 err = -1;
2452         }
2453         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2454                 i = TX_ATIM_FIFO;
2455                 err = -1;
2456         }
2457         if (err != 0) {
2458                 WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
2459                          buf[i], wlc_hw->xmtfifo_sz[i], i);
2460                 ASSERT(0);
2461         }
2462
2463         /* make sure we can still talk to the mac */
2464         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2465
2466         /* band-specific inits done by wlc_bsinit() */
2467
2468         /* Set up frame burst size and antenna swap threshold init values */
2469         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2470         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2471
2472         /* enable one rx interrupt per received frame */
2473         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2474
2475         /* set the station mode (BSS STA) */
2476         wlc_bmac_mctrl(wlc_hw,
2477                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2478                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2479
2480         /* set up Beacon interval */
2481         bcnint_us = 0x8000 << 10;
2482         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2483         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2484         W_REG(osh, &regs->macintstatus, MI_GP1);
2485
2486         /* write interrupt mask */
2487         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2488
2489         /* allow the MAC to control the PHY clock (dynamic on/off) */
2490         wlc_bmac_macphyclk_set(wlc_hw, ON);
2491
2492         /* program dynamic clock control fast powerup delay register */
2493         wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2494         W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2495
2496         /* tell the ucode the corerev */
2497         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2498
2499         /* tell the ucode MAC capabilities */
2500         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2501                            (u16) (wlc_hw->machwcap & 0xffff));
2502         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2503                            (u16) ((wlc_hw->
2504                                       machwcap >> 16) & 0xffff));
2505
2506         /* write retry limits to SCR, this done after PSM init */
2507         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2508         (void)R_REG(osh, &regs->objaddr);
2509         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2510         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2511         (void)R_REG(osh, &regs->objaddr);
2512         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2513
2514         /* write rate fallback retry limits */
2515         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2516         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2517
2518         AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2519         W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2520
2521         /* dma initializations */
2522         wlc->txpend16165war = 0;
2523
2524         /* init the tx dma engines */
2525         for (i = 0; i < NFIFO; i++) {
2526                 if (wlc_hw->di[i])
2527                         dma_txinit(wlc_hw->di[i]);
2528         }
2529
2530         /* init the rx dma engine(s) and post receive buffers */
2531         dma_rxinit(wlc_hw->di[RX_FIFO]);
2532         dma_rxfill(wlc_hw->di[RX_FIFO]);
2533 }
2534
2535 /* This function is used for changing the tsf frac register
2536  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2537  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2538  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2539  * HTPHY Formula is 2^26/freq(MHz) e.g.
2540  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2541  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2542  * For spuron: 123MHz -> 2^26/123    = 545600.5
2543  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2544  * For spur off: 120MHz -> 2^26/120    = 559240.5
2545  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2546  */
2547
2548 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2549 {
2550         d11regs_t *regs;
2551         struct osl_info *osh;
2552         regs = wlc_hw->regs;
2553         osh = wlc_hw->osh;
2554
2555         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2556             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2557                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2558                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2559                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2560                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2561                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2562                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2563                 } else {        /* 120Mhz */
2564                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2565                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2566                 }
2567         } else if (WLCISLCNPHY(wlc_hw->band)) {
2568                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2569                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2570                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2571                 } else {        /* 80Mhz */
2572                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2573                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2574                 }
2575         }
2576 }
2577
2578 /* Initialize GPIOs that are controlled by D11 core */
2579 static void wlc_gpio_init(struct wlc_info *wlc)
2580 {
2581         struct wlc_hw_info *wlc_hw = wlc->hw;
2582         d11regs_t *regs;
2583         u32 gc, gm;
2584         struct osl_info *osh;
2585
2586         regs = wlc_hw->regs;
2587         osh = wlc_hw->osh;
2588
2589         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2590         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2591
2592         /*
2593          * Common GPIO setup:
2594          *      G0 = LED 0 = WLAN Activity
2595          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2596          *      G2 = LED 2 = WLAN 5 GHz Radio State
2597          *      G4 = radio disable input (HI enabled, LO disabled)
2598          */
2599
2600         gc = gm = 0;
2601
2602         /* Allocate GPIOs for mimo antenna diversity feature */
2603         if (WLANTSEL_ENAB(wlc)) {
2604                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2605                         /* Enable antenna diversity, use 2x3 mode */
2606                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2607                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2608                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2609                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2610
2611                         /* init superswitch control */
2612                         wlc_phy_antsel_init(wlc_hw->band->pi, false);
2613
2614                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2615                         ASSERT((gm & BOARD_GPIO_12) == 0);
2616                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2617                         /* The board itself is powered by these GPIOs (when not sending pattern)
2618                          * So set them high
2619                          */
2620                         OR_REG(osh, &regs->psm_gpio_oe,
2621                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2622                         OR_REG(osh, &regs->psm_gpio_out,
2623                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2624
2625                         /* Enable antenna diversity, use 2x4 mode */
2626                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2627                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2628                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2629                                      WLC_BAND_ALL);
2630
2631                         /* Configure the desired clock to be 4Mhz */
2632                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2633                                            ANTSEL_CLKDIV_4MHZ);
2634                 }
2635         }
2636         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2637         if (wlc_hw->boardflags & BFL_PACTRL)
2638                 gm |= gc |= BOARD_GPIO_PACTRL;
2639
2640         /* apply to gpiocontrol register */
2641         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2642 }
2643
2644 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2645 {
2646         struct wlc_info *wlc;
2647         wlc = wlc_hw->wlc;
2648
2649         if (wlc_hw->ucode_loaded)
2650                 return;
2651
2652         if (D11REV_IS(wlc_hw->corerev, 23)) {
2653                 if (WLCISNPHY(wlc_hw->band)) {
2654                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2655                                         bcm43xx_16_mimosz);
2656                         wlc_hw->ucode_loaded = true;
2657                 } else
2658                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2659                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2660         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2661                 if (WLCISLCNPHY(wlc_hw->band)) {
2662                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2663                                         bcm43xx_24_lcnsz);
2664                         wlc_hw->ucode_loaded = true;
2665                 } else {
2666                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2667                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2668                 }
2669         }
2670 }
2671
2672 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2673                               const uint nbytes) {
2674         struct osl_info *osh;
2675         d11regs_t *regs = wlc_hw->regs;
2676         uint i;
2677         uint count;
2678
2679         osh = wlc_hw->osh;
2680
2681         WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2682
2683         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2684
2685         count = (nbytes / sizeof(u32));
2686
2687         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2688         (void)R_REG(osh, &regs->objaddr);
2689         for (i = 0; i < count; i++)
2690                 W_REG(osh, &regs->objdata, ucode[i]);
2691 }
2692
2693 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits)
2694 {
2695         int i;
2696         struct osl_info *osh;
2697         volatile u8 *base;
2698
2699         WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2700
2701         osh = wlc_hw->osh;
2702         base = (volatile u8 *)wlc_hw->regs;
2703
2704         for (i = 0; inits[i].addr != 0xffff; i++) {
2705                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2706
2707                 if (inits[i].size == 2)
2708                         W_REG(osh, (u16 *)(base + inits[i].addr),
2709                               inits[i].value);
2710                 else if (inits[i].size == 4)
2711                         W_REG(osh, (u32 *)(base + inits[i].addr),
2712                               inits[i].value);
2713         }
2714 }
2715
2716 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2717 {
2718         u16 phyctl;
2719         u16 phytxant = wlc_hw->bmac_phytxant;
2720         u16 mask = PHY_TXC_ANT_MASK;
2721
2722         /* set the Probe Response frame phy control word */
2723         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2724         phyctl = (phyctl & ~mask) | phytxant;
2725         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2726
2727         /* set the Response (ACK/CTS) frame phy control word */
2728         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2729         phyctl = (phyctl & ~mask) | phytxant;
2730         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2731 }
2732
2733 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2734 {
2735         /* update sw state */
2736         wlc_hw->bmac_phytxant = phytxant;
2737
2738         /* push to ucode if up */
2739         if (!wlc_hw->up)
2740                 return;
2741         wlc_ucode_txant_set(wlc_hw);
2742
2743 }
2744
2745 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2746 {
2747         return (u16) wlc_hw->wlc->stf->txant;
2748 }
2749
2750 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2751 {
2752         wlc_hw->antsel_type = antsel_type;
2753
2754         /* Update the antsel type for phy module to use */
2755         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2756 }
2757
2758 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2759 {
2760         bool fatal = false;
2761         uint unit;
2762         uint intstatus, idx;
2763         d11regs_t *regs = wlc_hw->regs;
2764
2765         unit = wlc_hw->unit;
2766
2767         for (idx = 0; idx < NFIFO; idx++) {
2768                 /* read intstatus register and ignore any non-error bits */
2769                 intstatus =
2770                     R_REG(wlc_hw->osh,
2771                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2772                 if (!intstatus)
2773                         continue;
2774
2775                 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2776                          unit, idx, intstatus);
2777
2778                 if (intstatus & I_RO) {
2779                         WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
2780                                  unit, idx);
2781                         wlc_hw->wlc->pub->_cnt->rxoflo++;
2782                         fatal = true;
2783                 }
2784
2785                 if (intstatus & I_PC) {
2786                         WL_ERROR("wl%d: fifo %d: descriptor error\n",
2787                                  unit, idx);
2788                         wlc_hw->wlc->pub->_cnt->dmade++;
2789                         fatal = true;
2790                 }
2791
2792                 if (intstatus & I_PD) {
2793                         WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
2794                         wlc_hw->wlc->pub->_cnt->dmada++;
2795                         fatal = true;
2796                 }
2797
2798                 if (intstatus & I_DE) {
2799                         WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
2800                                  unit, idx);
2801                         wlc_hw->wlc->pub->_cnt->dmape++;
2802                         fatal = true;
2803                 }
2804
2805                 if (intstatus & I_RU) {
2806                         WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
2807                                  idx, unit);
2808                         wlc_hw->wlc->pub->_cnt->rxuflo[idx]++;
2809                 }
2810
2811                 if (intstatus & I_XU) {
2812                         WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
2813                                  idx, unit);
2814                         wlc_hw->wlc->pub->_cnt->txuflo++;
2815                         fatal = true;
2816                 }
2817
2818                 if (fatal) {
2819                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2820                         break;
2821                 } else
2822                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2823                               intstatus);
2824         }
2825 }
2826
2827 void wlc_intrson(struct wlc_info *wlc)
2828 {
2829         struct wlc_hw_info *wlc_hw = wlc->hw;
2830         ASSERT(wlc->defmacintmask);
2831         wlc->macintmask = wlc->defmacintmask;
2832         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2833 }
2834
2835 /* callback for siutils.c, which has only wlc handler, no wl
2836  * they both check up, not only because there is no need to off/restore d11 interrupt
2837  *  but also because per-port code may require sync with valid interrupt.
2838  */
2839
2840 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2841 {
2842         if (!wlc->hw->up)
2843                 return 0;
2844
2845         return wl_intrsoff(wlc->wl);
2846 }
2847
2848 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2849 {
2850         if (!wlc->hw->up)
2851                 return;
2852
2853         wl_intrsrestore(wlc->wl, macintmask);
2854 }
2855
2856 u32 wlc_intrsoff(struct wlc_info *wlc)
2857 {
2858         struct wlc_hw_info *wlc_hw = wlc->hw;
2859         u32 macintmask;
2860
2861         if (!wlc_hw->clk)
2862                 return 0;
2863
2864         macintmask = wlc->macintmask;   /* isr can still happen */
2865
2866         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
2867         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
2868         udelay(1);              /* ensure int line is no longer driven */
2869         wlc->macintmask = 0;
2870
2871         /* return previous macintmask; resolve race between us and our isr */
2872         return wlc->macintstatus ? 0 : macintmask;
2873 }
2874
2875 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2876 {
2877         struct wlc_hw_info *wlc_hw = wlc->hw;
2878         if (!wlc_hw->clk)
2879                 return;
2880
2881         wlc->macintmask = macintmask;
2882         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2883 }
2884
2885 void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2886 {
2887         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2888
2889         if (on) {
2890                 /* suspend tx fifos */
2891                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2892                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2893                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2894                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2895
2896                 /* zero the address match register so we do not send ACKs */
2897                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2898                                        null_ether_addr);
2899         } else {
2900                 /* resume tx fifos */
2901                 if (!wlc_hw->wlc->tx_suspended) {
2902                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2903                 }
2904                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2905                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2906                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2907
2908                 /* Restore address */
2909                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2910                                        wlc_hw->etheraddr);
2911         }
2912
2913         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2914
2915         if (on)
2916                 wlc_ucode_mute_override_set(wlc_hw);
2917         else
2918                 wlc_ucode_mute_override_clear(wlc_hw);
2919 }
2920
2921 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2922 {
2923         if (fifo >= NFIFO)
2924                 return BCME_RANGE;
2925
2926         *blocks = wlc_hw->xmtfifo_sz[fifo];
2927
2928         return 0;
2929 }
2930
2931 /* wlc_bmac_tx_fifo_suspended:
2932  * Check the MAC's tx suspend status for a tx fifo.
2933  *
2934  * When the MAC acknowledges a tx suspend, it indicates that no more
2935  * packets will be transmitted out the radio. This is independent of
2936  * DMA channel suspension---the DMA may have finished suspending, or may still
2937  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2938  * request.
2939  */
2940 bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2941 {
2942         /* check that a suspend has been requested and is no longer pending */
2943
2944         /*
2945          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2946          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2947          * chnstatus register.
2948          * The tx fifo suspend completion is independent of the DMA suspend completion and
2949          *   may be acked before or after the DMA is suspended.
2950          */
2951         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2952             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
2953              (1 << tx_fifo)) == 0)
2954                 return true;
2955
2956         return false;
2957 }
2958
2959 void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2960 {
2961         u8 fifo = 1 << tx_fifo;
2962
2963         /* Two clients of this code, 11h Quiet period and scanning. */
2964
2965         /* only suspend if not already suspended */
2966         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2967                 return;
2968
2969         /* force the core awake only if not already */
2970         if (wlc_hw->suspended_fifos == 0)
2971                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2972
2973         wlc_hw->suspended_fifos |= fifo;
2974
2975         if (wlc_hw->di[tx_fifo]) {
2976                 /* Suspending AMPDU transmissions in the middle can cause underflow
2977                  * which may result in mismatch between ucode and driver
2978                  * so suspend the mac before suspending the FIFO
2979                  */
2980                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2981                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
2982
2983                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2984
2985                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2986                         wlc_enable_mac(wlc_hw->wlc);
2987         }
2988 }
2989
2990 void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2991 {
2992         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2993          * here for PIO otherwise the watchdog will catch the inconsistency and fire
2994          */
2995         /* Two clients of this code, 11h Quiet period and scanning. */
2996         if (wlc_hw->di[tx_fifo])
2997                 dma_txresume(wlc_hw->di[tx_fifo]);
2998
2999         /* allow core to sleep again */
3000         if (wlc_hw->suspended_fifos == 0)
3001                 return;
3002         else {
3003                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3004                 if (wlc_hw->suspended_fifos == 0)
3005                         wlc_ucode_wake_override_clear(wlc_hw,
3006                                                       WLC_WAKE_OVERRIDE_TXFIFO);
3007         }
3008 }
3009
3010 /*
3011  * Read and clear macintmask and macintstatus and intstatus registers.
3012  * This routine should be called with interrupts off
3013  * Return:
3014  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
3015  *   0 if the interrupt is not for us, or we are in some special cases;
3016  *   device interrupt status bits otherwise.
3017  */
3018 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
3019 {
3020         struct wlc_hw_info *wlc_hw = wlc->hw;
3021         d11regs_t *regs = wlc_hw->regs;
3022         u32 macintstatus;
3023         u32 intstatus_rxfifo, intstatus_txsfifo;
3024         struct osl_info *osh;
3025
3026         osh = wlc_hw->osh;
3027
3028         /* macintstatus includes a DMA interrupt summary bit */
3029         macintstatus = R_REG(osh, &regs->macintstatus);
3030
3031         WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
3032
3033         /* detect cardbus removed, in power down(suspend) and in reset */
3034         if (DEVICEREMOVED(wlc))
3035                 return -1;
3036
3037         /* DEVICEREMOVED succeeds even when the core is still resetting,
3038          * handle that case here.
3039          */
3040         if (macintstatus == 0xffffffff)
3041                 return 0;
3042
3043         /* defer unsolicited interrupts */
3044         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3045
3046         /* if not for us */
3047         if (macintstatus == 0)
3048                 return 0;
3049
3050         /* interrupts are already turned off for CFE build
3051          * Caution: For CFE Turning off the interrupts again has some undesired
3052          * consequences
3053          */
3054         /* turn off the interrupts */
3055         W_REG(osh, &regs->macintmask, 0);
3056         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3057         wlc->macintmask = 0;
3058
3059         /* clear device interrupts */
3060         W_REG(osh, &regs->macintstatus, macintstatus);
3061
3062         /* MI_DMAINT is indication of non-zero intstatus */
3063         if (macintstatus & MI_DMAINT) {
3064                 /*
3065                  * only fifo interrupt enabled is I_RI in RX_FIFO. If
3066                  * MI_DMAINT is set, assume it is set and clear the interrupt.
3067                  */
3068                 W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3069                       DEF_RXINTMASK);
3070         }
3071
3072         return macintstatus;
3073 }
3074
3075 /* Update wlc->macintstatus and wlc->intstatus[]. */
3076 /* Return true if they are updated successfully. false otherwise */
3077 bool wlc_intrsupd(struct wlc_info *wlc)
3078 {
3079         u32 macintstatus;
3080
3081         ASSERT(wlc->macintstatus != 0);
3082
3083         /* read and clear macintstatus and intstatus registers */
3084         macintstatus = wlc_intstatus(wlc, false);
3085
3086         /* device is removed */
3087         if (macintstatus == 0xffffffff)
3088                 return false;
3089
3090         /* update interrupt status in software */
3091         wlc->macintstatus |= macintstatus;
3092
3093         return true;
3094 }
3095
3096 /*
3097  * First-level interrupt processing.
3098  * Return true if this was our interrupt, false otherwise.
3099  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3100  * false otherwise.
3101  */
3102 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3103 {
3104         struct wlc_hw_info *wlc_hw = wlc->hw;
3105         u32 macintstatus;
3106
3107         *wantdpc = false;
3108
3109         if (!wlc_hw->up || !wlc->macintmask)
3110                 return false;
3111
3112         /* read and clear macintstatus and intstatus registers */
3113         macintstatus = wlc_intstatus(wlc, true);
3114
3115         if (macintstatus == 0xffffffff)
3116                 WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
3117
3118         /* it is not for us */
3119         if (macintstatus == 0)
3120                 return false;
3121
3122         *wantdpc = true;
3123
3124         /* save interrupt status bits */
3125         ASSERT(wlc->macintstatus == 0);
3126         wlc->macintstatus = macintstatus;
3127
3128         return true;
3129
3130 }
3131
3132 /* process tx completion events for corerev < 5 */
3133 static bool wlc_bmac_txstatus_corerev4(struct wlc_hw_info *wlc_hw)
3134 {
3135         struct sk_buff *status_p;
3136         tx_status_t *txs;
3137         struct osl_info *osh;
3138         bool fatal = false;
3139
3140         WL_TRACE("wl%d: wlc_txstatusrecv\n", wlc_hw->unit);
3141
3142         osh = wlc_hw->osh;
3143
3144         while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3145
3146                 txs = (tx_status_t *) status_p->data;
3147                 /* MAC uses little endian only */
3148                 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3149
3150                 /* shift low bits for tx_status_t status compatibility */
3151                 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3152                     | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3153
3154                 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3155
3156                 pkt_buf_free_skb(osh, status_p, false);
3157         }
3158
3159         if (fatal)
3160                 return true;
3161
3162         /* post more rbufs */
3163         dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3164
3165         return false;
3166 }
3167
3168 static bool BCMFASTPATH
3169 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3170 {
3171         /* discard intermediate indications for ucode with one legitimate case:
3172          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3173          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3174          *   transmission count)
3175          */
3176         if (!(txs->status & TX_STATUS_AMPDU)
3177             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3178                 return false;
3179         }
3180
3181         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3182 }
3183
3184 /* process tx completion events in BMAC
3185  * Return true if more tx status need to be processed. false otherwise.
3186  */
3187 static bool BCMFASTPATH
3188 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3189 {
3190         bool morepending = false;
3191         struct wlc_info *wlc = wlc_hw->wlc;
3192
3193         WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3194
3195         {
3196                 d11regs_t *regs;
3197                 struct osl_info *osh;
3198                 tx_status_t txstatus, *txs;
3199                 u32 s1, s2;
3200                 uint n = 0;
3201                 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3202                 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3203
3204                 txs = &txstatus;
3205                 regs = wlc_hw->regs;
3206                 osh = wlc_hw->osh;
3207                 while (!(*fatal)
3208                        && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3209
3210                         if (s1 == 0xffffffff) {
3211                                 WL_ERROR("wl%d: %s: dead chip\n",
3212                                          wlc_hw->unit, __func__);
3213                                 ASSERT(s1 != 0xffffffff);
3214                                 return morepending;
3215                         }
3216
3217                         s2 = R_REG(osh, &regs->frmtxstatus2);
3218
3219                         txs->status = s1 & TXS_STATUS_MASK;
3220                         txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3221                         txs->sequence = s2 & TXS_SEQ_MASK;
3222                         txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3223                         txs->lasttxtime = 0;
3224
3225                         *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3226
3227                         /* !give others some time to run! */
3228                         if (++n >= max_tx_num)
3229                                 break;
3230                 }
3231
3232                 if (*fatal)
3233                         return 0;
3234
3235                 if (n >= max_tx_num)
3236                         morepending = true;
3237         }
3238
3239         if (!pktq_empty(&wlc->active_queue->q))
3240                 wlc_send_q(wlc, wlc->active_queue);
3241
3242         return morepending;
3243 }
3244
3245 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3246 {
3247         struct wlc_hw_info *wlc_hw = wlc->hw;
3248         d11regs_t *regs = wlc_hw->regs;
3249         u32 mc, mi;
3250         struct osl_info *osh;
3251
3252         WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3253                  wlc_hw->unit, wlc_hw->band->bandunit);
3254
3255         /*
3256          * Track overlapping suspend requests
3257          */
3258         wlc_hw->mac_suspend_depth++;
3259         if (wlc_hw->mac_suspend_depth > 1)
3260                 return;
3261
3262         osh = wlc_hw->osh;
3263
3264         /* force the core awake */
3265         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3266
3267         mc = R_REG(osh, &regs->maccontrol);
3268
3269         if (mc == 0xffffffff) {
3270                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3271                 wl_down(wlc->wl);
3272                 return;
3273         }
3274         ASSERT(!(mc & MCTL_PSM_JMP_0));
3275         ASSERT(mc & MCTL_PSM_RUN);
3276         ASSERT(mc & MCTL_EN_MAC);
3277
3278         mi = R_REG(osh, &regs->macintstatus);
3279         if (mi == 0xffffffff) {
3280                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3281                 wl_down(wlc->wl);
3282                 return;
3283         }
3284         ASSERT(!(mi & MI_MACSSPNDD));
3285
3286         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3287
3288         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3289                  WLC_MAX_MAC_SUSPEND);
3290
3291         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3292                 WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
3293                          wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3294                 WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
3295                          wlc_hw->unit,
3296                          R_REG(osh, &regs->psmdebug),
3297                          R_REG(osh, &regs->phydebug),
3298                          R_REG(osh, &regs->psm_brc));
3299         }
3300
3301         mc = R_REG(osh, &regs->maccontrol);
3302         if (mc == 0xffffffff) {
3303                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3304                 wl_down(wlc->wl);
3305                 return;
3306         }
3307         ASSERT(!(mc & MCTL_PSM_JMP_0));
3308         ASSERT(mc & MCTL_PSM_RUN);
3309         ASSERT(!(mc & MCTL_EN_MAC));
3310 }
3311
3312 void wlc_enable_mac(struct wlc_info *wlc)
3313 {
3314         struct wlc_hw_info *wlc_hw = wlc->hw;
3315         d11regs_t *regs = wlc_hw->regs;
3316         u32 mc, mi;
3317         struct osl_info *osh;
3318
3319         WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3320                  wlc_hw->unit, wlc->band->bandunit);
3321
3322         /*
3323          * Track overlapping suspend requests
3324          */
3325         ASSERT(wlc_hw->mac_suspend_depth > 0);
3326         wlc_hw->mac_suspend_depth--;
3327         if (wlc_hw->mac_suspend_depth > 0)
3328                 return;
3329
3330         osh = wlc_hw->osh;
3331
3332         mc = R_REG(osh, &regs->maccontrol);
3333         ASSERT(!(mc & MCTL_PSM_JMP_0));
3334         ASSERT(!(mc & MCTL_EN_MAC));
3335         ASSERT(mc & MCTL_PSM_RUN);
3336
3337         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3338         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3339
3340         mc = R_REG(osh, &regs->maccontrol);
3341         ASSERT(!(mc & MCTL_PSM_JMP_0));
3342         ASSERT(mc & MCTL_EN_MAC);
3343         ASSERT(mc & MCTL_PSM_RUN);
3344
3345         mi = R_REG(osh, &regs->macintstatus);
3346         ASSERT(!(mi & MI_MACSSPNDD));
3347
3348         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3349 }
3350
3351 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3352 {
3353         u8 rate;
3354         u8 rates[8] = {
3355                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3356                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3357         };
3358         u16 entry_ptr;
3359         u16 pctl1;
3360         uint i;
3361
3362         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3363                 return;
3364
3365         /* walk the phy rate table and update the entries */
3366         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3367                 rate = rates[i];
3368
3369                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3370
3371                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3372                 pctl1 =
3373                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3374
3375                 /* modify the value */
3376                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3377                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3378
3379                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3380                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3381                                    pctl1);
3382         }
3383 }
3384
3385 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3386 {
3387         uint i;
3388         u8 plcp_rate = 0;
3389         struct plcp_signal_rate_lookup {
3390                 u8 rate;
3391                 u8 signal_rate;
3392         };
3393         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3394         const struct plcp_signal_rate_lookup rate_lookup[] = {
3395                 {WLC_RATE_6M, 0xB},
3396                 {WLC_RATE_9M, 0xF},
3397                 {WLC_RATE_12M, 0xA},
3398                 {WLC_RATE_18M, 0xE},
3399                 {WLC_RATE_24M, 0x9},
3400                 {WLC_RATE_36M, 0xD},
3401                 {WLC_RATE_48M, 0x8},
3402                 {WLC_RATE_54M, 0xC}
3403         };
3404
3405         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3406                 if (rate == rate_lookup[i].rate) {
3407                         plcp_rate = rate_lookup[i].signal_rate;
3408                         break;
3409                 }
3410         }
3411
3412         /* Find the SHM pointer to the rate table entry by looking in the
3413          * Direct-map Table
3414          */
3415         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3416 }
3417
3418 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3419 {
3420         wlc_hw->hw_stf_ss_opmode = stf_mode;
3421
3422         if (wlc_hw->clk)
3423                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3424 }
3425
3426 void BCMFASTPATH
3427 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3428                   u32 *tsf_h_ptr)
3429 {
3430         d11regs_t *regs = wlc_hw->regs;
3431
3432         /* read the tsf timer low, then high to get an atomic read */
3433         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3434         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3435
3436         return;
3437 }
3438
3439 bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3440 {
3441         d11regs_t *regs;
3442         u32 w, val;
3443         volatile u16 *reg16;
3444         struct osl_info *osh;
3445
3446         WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3447
3448         regs = wlc_hw->regs;
3449         osh = wlc_hw->osh;
3450
3451         /* Validate dchip register access */
3452
3453         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3454         (void)R_REG(osh, &regs->objaddr);
3455         w = R_REG(osh, &regs->objdata);
3456
3457         /* Can we write and read back a 32bit register? */
3458         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3459         (void)R_REG(osh, &regs->objaddr);
3460         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3461
3462         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3463         (void)R_REG(osh, &regs->objaddr);
3464         val = R_REG(osh, &regs->objdata);
3465         if (val != (u32) 0xaa5555aa) {
3466                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
3467                          wlc_hw->unit, val);
3468                 return false;
3469         }
3470
3471         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3472         (void)R_REG(osh, &regs->objaddr);
3473         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3474
3475         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3476         (void)R_REG(osh, &regs->objaddr);
3477         val = R_REG(osh, &regs->objdata);
3478         if (val != (u32) 0x55aaaa55) {
3479                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
3480                          wlc_hw->unit, val);
3481                 return false;
3482         }
3483
3484         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3485         (void)R_REG(osh, &regs->objaddr);
3486         W_REG(osh, &regs->objdata, w);
3487
3488         /* clear CFPStart */
3489         W_REG(osh, &regs->tsf_cfpstart, 0);
3490
3491         w = R_REG(osh, &regs->maccontrol);
3492         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3493             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3494                 WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
3495                          wlc_hw->unit, w,
3496                          (MCTL_IHR_EN | MCTL_WAKE),
3497                          (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3498                 return false;
3499         }
3500
3501         return true;
3502 }
3503
3504 #define PHYPLL_WAIT_US  100000
3505
3506 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3507 {
3508         d11regs_t *regs;
3509         struct osl_info *osh;
3510         u32 tmp;
3511
3512         WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3513
3514         tmp = 0;
3515         regs = wlc_hw->regs;
3516         osh = wlc_hw->osh;
3517
3518         if (on) {
3519                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3520                         OR_REG(osh, &regs->clk_ctl_st,
3521                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3522                                 CCS_ERSRC_REQ_PHYPLL));
3523                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3524                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3525                                  PHYPLL_WAIT_US);
3526
3527                         tmp = R_REG(osh, &regs->clk_ctl_st);
3528                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3529                             (CCS_ERSRC_AVAIL_HT)) {
3530                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3531                                          __func__);
3532                                 ASSERT(0);
3533                         }
3534                 } else {
3535                         OR_REG(osh, &regs->clk_ctl_st,
3536                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3537                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3538                                   (CCS_ERSRC_AVAIL_D11PLL |
3539                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3540                                  (CCS_ERSRC_AVAIL_D11PLL |
3541                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3542
3543                         tmp = R_REG(osh, &regs->clk_ctl_st);
3544                         if ((tmp &
3545                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3546                             !=
3547                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3548                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3549                                          __func__);
3550                                 ASSERT(0);
3551                         }
3552                 }
3553         } else {
3554                 /* Since the PLL may be shared, other cores can still be requesting it;
3555                  * so we'll deassert the request but not wait for status to comply.
3556                  */
3557                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3558                 tmp = R_REG(osh, &regs->clk_ctl_st);
3559         }
3560 }
3561
3562 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3563 {
3564         bool dev_gone;
3565
3566         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3567
3568         ASSERT(!wlc_hw->up);
3569
3570         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3571
3572         if (dev_gone)
3573                 return;
3574
3575         if (wlc_hw->noreset)
3576                 return;
3577
3578         /* radio off */
3579         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3580
3581         /* turn off analog core */
3582         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3583
3584         /* turn off PHYPLL to save power */
3585         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3586
3587         /* No need to set wlc->pub->radio_active = OFF
3588          * because this function needs down capability and
3589          * radio_active is designed for BCMNODOWN.
3590          */
3591
3592         /* remove gpio controls */
3593         if (wlc_hw->ucode_dbgsel)
3594                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3595
3596         wlc_hw->clk = false;
3597         si_core_disable(wlc_hw->sih, 0);
3598         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3599 }
3600
3601 /* power both the pll and external oscillator on/off */
3602 void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3603 {
3604         WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3605
3606         /* dont power down if plldown is false or we must poll hw radio disable */
3607         if (!want && wlc_hw->pllreq)
3608                 return;
3609
3610         if (wlc_hw->sih)
3611                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3612
3613         wlc_hw->sbclk = want;
3614         if (!wlc_hw->sbclk) {
3615                 wlc_hw->clk = false;
3616                 if (wlc_hw->band && wlc_hw->band->pi)
3617                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3618         }
3619 }
3620
3621 static void wlc_flushqueues(struct wlc_info *wlc)
3622 {
3623         struct wlc_hw_info *wlc_hw = wlc->hw;
3624         uint i;
3625
3626         wlc->txpend16165war = 0;
3627
3628         /* free any posted tx packets */
3629         for (i = 0; i < NFIFO; i++)
3630                 if (wlc_hw->di[i]) {
3631                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3632                         TXPKTPENDCLR(wlc, i);
3633                         WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3634                                  i);
3635                 }
3636
3637         /* free any posted rx packets */
3638         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3639 }
3640
3641 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3642 {
3643         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3644 }
3645
3646 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3647 {
3648         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3649 }
3650
3651 /* Set a range of shared memory to a value.
3652  * SHM 'offset' needs to be an even address and
3653  * Buffer length 'len' must be an even number of bytes
3654  */
3655 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3656 {
3657         int i;
3658
3659         /* offset and len need to be even */
3660         ASSERT((offset & 1) == 0);
3661         ASSERT((len & 1) == 0);
3662
3663         if (len <= 0)
3664                 return;
3665
3666         for (i = 0; i < len; i += 2) {
3667                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3668         }
3669 }
3670
3671 static u16
3672 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3673 {
3674         d11regs_t *regs = wlc_hw->regs;
3675         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3676         volatile u16 *objdata_hi = objdata_lo + 1;
3677         u16 v;
3678
3679         ASSERT((offset & 1) == 0);
3680
3681         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3682         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3683         if (offset & 2) {
3684                 v = R_REG(wlc_hw->osh, objdata_hi);
3685         } else {
3686                 v = R_REG(wlc_hw->osh, objdata_lo);
3687         }
3688
3689         return v;
3690 }
3691
3692 static void
3693 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3694 {
3695         d11regs_t *regs = wlc_hw->regs;
3696         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3697         volatile u16 *objdata_hi = objdata_lo + 1;
3698
3699         ASSERT((offset & 1) == 0);
3700
3701         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3702         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3703         if (offset & 2) {
3704                 W_REG(wlc_hw->osh, objdata_hi, v);
3705         } else {
3706                 W_REG(wlc_hw->osh, objdata_lo, v);
3707         }
3708 }
3709
3710 /* Copy a buffer to shared memory of specified type .
3711  * SHM 'offset' needs to be an even address and
3712  * Buffer length 'len' must be an even number of bytes
3713  * 'sel' selects the type of memory
3714  */
3715 void
3716 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3717                        int len, u32 sel)
3718 {
3719         u16 v;
3720         const u8 *p = (const u8 *)buf;
3721         int i;
3722
3723         /* offset and len need to be even */
3724         ASSERT((offset & 1) == 0);
3725         ASSERT((len & 1) == 0);
3726
3727         if (len <= 0)
3728                 return;
3729
3730         for (i = 0; i < len; i += 2) {
3731                 v = p[i] | (p[i + 1] << 8);
3732                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3733         }
3734 }
3735
3736 /* Copy a piece of shared memory of specified type to a buffer .
3737  * SHM 'offset' needs to be an even address and
3738  * Buffer length 'len' must be an even number of bytes
3739  * 'sel' selects the type of memory
3740  */
3741 void
3742 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3743                          int len, u32 sel)
3744 {
3745         u16 v;
3746         u8 *p = (u8 *) buf;
3747         int i;
3748
3749         /* offset and len need to be even */
3750         ASSERT((offset & 1) == 0);
3751         ASSERT((len & 1) == 0);
3752
3753         if (len <= 0)
3754                 return;
3755
3756         for (i = 0; i < len; i += 2) {
3757                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3758                 p[i] = v & 0xFF;
3759                 p[i + 1] = (v >> 8) & 0xFF;
3760         }
3761 }
3762
3763 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3764 {
3765         WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3766                  wlc_hw->vars_size);
3767
3768         *buf = wlc_hw->vars;
3769         *len = wlc_hw->vars_size;
3770 }
3771
3772 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3773 {
3774         wlc_hw->SRL = SRL;
3775         wlc_hw->LRL = LRL;
3776
3777         /* write retry limit to SCR, shouldn't need to suspend */
3778         if (wlc_hw->up) {
3779                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3780                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3781                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3782                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
3783                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3784                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3785                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3786                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
3787         }
3788 }
3789
3790 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3791 {
3792         wlc_hw->noreset = noreset_flag;
3793 }
3794
3795 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3796 {
3797         ASSERT(req_bit);
3798
3799         if (set) {
3800                 if (mboolisset(wlc_hw->pllreq, req_bit))
3801                         return;
3802
3803                 mboolset(wlc_hw->pllreq, req_bit);
3804
3805                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3806                         if (!wlc_hw->sbclk) {
3807                                 wlc_bmac_xtal(wlc_hw, ON);
3808                         }
3809                 }
3810         } else {
3811                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3812                         return;
3813
3814                 mboolclr(wlc_hw->pllreq, req_bit);
3815
3816                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3817                         if (wlc_hw->sbclk) {
3818                                 wlc_bmac_xtal(wlc_hw, OFF);
3819                         }
3820                 }
3821         }
3822
3823         return;
3824 }
3825
3826 /* this will be true for all ai chips */
3827 bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
3828 {
3829         return true;
3830 }
3831
3832 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3833 {
3834         u16 table_ptr;
3835         u8 phy_rate, index;
3836
3837         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3838         /* XXX4321 fixup needed ? */
3839         if (IS_OFDM(rate))
3840                 table_ptr = M_RT_DIRMAP_A;
3841         else
3842                 table_ptr = M_RT_DIRMAP_B;
3843
3844         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3845          * the index into the rate table.
3846          */
3847         phy_rate = rate_info[rate] & RATE_MASK;
3848         index = phy_rate & 0xf;
3849
3850         /* Find the SHM pointer to the rate table entry by looking in the
3851          * Direct-map Table
3852          */
3853         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3854 }
3855
3856 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3857 {
3858         wlc_hw->antsel_avail = antsel_avail;
3859 }