Pileus Git - ~andy/linux/blob - drivers/staging/brcm80211/brcmsmac/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23
  24 #include <proto/802.11.h>
  25 #include <bcmdefs.h>
  26 #include <bcmdevs.h>
  27 #include <bcmwifi.h>
  28 #include <siutils.h>
  29 #include <bcmsrom.h>
  30 #include <bcmotp.h>
  31 #include <bcmutils.h>
  32 #include <wlioctl.h>
  33 #include <sbconfig.h>
  34 #include <sbchipc.h>
  35 #include <pcicfg.h>
  36 #include <sbhnddma.h>
  37 #include <hnddma.h>
  38 #include <hndpmu.h>
  39
  40 #include "wlc_types.h"
  41 #include "d11.h"
  42 #include "wlc_cfg.h"
  43 #include "wlc_rate.h"
  44 #include "wlc_scb.h"
  45 #include "wlc_pub.h"
  46 #include "wlc_key.h"
  47 #include "wlc_phy_shim.h"
  48 #include "phy/wlc_phy_hal.h"
  49 #include "wlc_channel.h"
  50 #include "wlc_main.h"
  51 #include "wl_export.h"
  52 #include "wl_ucode.h"
  53 #include "wlc_antsel.h"
  54 #include "pcie_core.h"
  55 #include "wlc_alloc.h"
  56 #include "wl_dbg.h"
  57 #include "wlc_bmac.h"
  58
  59 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  60
  61 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  62 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  63 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  64 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  65
  66 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  67
  68 #ifndef BMAC_DUP_TO_REMOVE
  69 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  70
  71 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  72
  73 #endif                          /* BMAC_DUP_TO_REMOVE */
  74
  75 #define DMAREG(wlc_hw, direction, fifonum) \
  76         ((direction == DMA_TX) ? \
  77                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
  78                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
  79
  80 /*
  81  * The following table lists the buffer memory allocated to xmt fifos in HW.
  82  * the size is in units of 256bytes(one block), total size is HW dependent
  83  * ucode has default fifo partition, sw can overwrite if necessary
  84  *
  85  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  86  * the twiki is updated before making changes.
  87  */
  88
  89 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
  90
  91 static u16 xmtfifo_sz[][NFIFO] = {
  92         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  93         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  94         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  95         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  96         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  97 };
  98
  99 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
 100 static void wlc_coreinit(struct wlc_info *wlc);
 101
 102 /* used by wlc_wakeucode_init() */
 103 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
 104                             const struct d11init *inits);
 105 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 106                             const uint nbytes);
 107 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 108 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 109
 110 /* used by wlc_dpc() */
 111 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 112                                 u32 s2);
 113 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 114 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 115
 116 /* used by wlc_down() */
 117 static void wlc_flushqueues(struct wlc_info *wlc);
 118
 119 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 120 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 121 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 122 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
 123                                        uint tx_fifo);
 124 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 125 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 126
 127 /* Low Level Prototypes */
 128 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
 129 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
 130 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
 131 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 132                                    u32 sel);
 133 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 134                                   u16 v, u32 sel);
 135 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
 136 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 137 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 138 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 139 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 140 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 141 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
 142 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 143 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 144 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 145 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
 146 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 147 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 148 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 149 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 150 static void wlc_gpio_init(struct wlc_info *wlc);
 151 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 152                                       int len);
 153 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 154                                       int len);
 155 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 156 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 157 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 158                              chanspec_t chanspec);
 159 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 160                                         bool shortslot);
 161 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 162 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 163                                              u8 rate);
 164
 165 /* === Low Level functions === */
 166
 167 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 168 {
 169         wlc_hw->shortslot = shortslot;
 170
 171         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 172                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 173                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 174                 wlc_enable_mac(wlc_hw->wlc);
 175         }
 176 }
 177
 178 /*
 179  * Update the slot timing for standard 11b/g (20us slots)
 180  * or shortslot 11g (9us slots)
 181  * The PSM needs to be suspended for this call.
 182  */
 183 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 184                                         bool shortslot)
 185 {
 186         d11regs_t *regs;
 187
 188         regs = wlc_hw->regs;
 189
 190         if (shortslot) {
 191                 /* 11g short slot: 11a timing */
 192                 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
 193                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 194         } else {
 195                 /* 11g long slot: 11b timing */
 196                 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
 197                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 198         }
 199 }
 200
 201 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 202 {
 203         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
 204
 205         /* init microcode host flags */
 206         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 207
 208         /* do band-specific ucode IHR, SHM, and SCR inits */
 209         if (D11REV_IS(wlc_hw->corerev, 23)) {
 210                 if (WLCISNPHY(wlc_hw->band)) {
 211                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 212                 } else {
 213                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
 214                                   " %d\n", __func__, wlc_hw->unit,
 215                                   wlc_hw->corerev);
 216                 }
 217         } else {
 218                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 219                         if (WLCISLCNPHY(wlc_hw->band)) {
 220                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 221                         } else
 222                                 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
 223                                           " core rev %d\n", __func__,
 224                                           wlc_hw->unit, wlc_hw->corerev);
 225                 } else {
 226                         wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
 227                                 __func__, wlc_hw->unit, wlc_hw->corerev);
 228                 }
 229         }
 230 }
 231
 232 /* switch to new band but leave it inactive */
 233 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 234 {
 235         struct wlc_hw_info *wlc_hw = wlc->hw;
 236         u32 macintmask;
 237
 238         WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
 239
 240         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
 241
 242         /* disable interrupts */
 243         macintmask = wl_intrsoff(wlc->wl);
 244
 245         /* radio off */
 246         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 247
 248         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 249
 250         wlc_setxband(wlc_hw, bandunit);
 251
 252         return macintmask;
 253 }
 254
 255 /* Process received frames */
 256 /*
 257  * Return true if more frames need to be processed. false otherwise.
 258  * Param 'bound' indicates max. # frames to process before break out.
 259  */
 260 static bool BCMFASTPATH
 261 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 262 {
 263         struct sk_buff *p;
 264         struct sk_buff *head = NULL;
 265         struct sk_buff *tail = NULL;
 266         uint n = 0;
 267         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 268         u32 tsf_h, tsf_l;
 269         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 270
 271         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
 272         /* gather received frames */
 273         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 274
 275                 if (!tail)
 276                         head = tail = p;
 277                 else {
 278                         tail->prev = p;
 279                         tail = p;
 280                 }
 281
 282                 /* !give others some time to run! */
 283                 if (++n >= bound_limit)
 284                         break;
 285         }
 286
 287         /* get the TSF REG reading */
 288         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 289
 290         /* post more rbufs */
 291         dma_rxfill(wlc_hw->di[fifo]);
 292
 293         /* process each frame */
 294         while ((p = head) != NULL) {
 295                 head = head->prev;
 296                 p->prev = NULL;
 297
 298                 /* record the tsf_l in wlc_rxd11hdr */
 299                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 300                 wlc_rxhdr->tsf_l = cpu_to_le32(tsf_l);
 301
 302                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 303                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 304
 305                 wlc_recv(wlc_hw->wlc, p);
 306         }
 307
 308         return n >= bound_limit;
 309 }
 310
 311 /* second-level interrupt processing
 312  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 313  *   Param 'bounded' indicates if applicable loops should be bounded.
 314  */
 315 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
 316 {
 317         u32 macintstatus;
 318         struct wlc_hw_info *wlc_hw = wlc->hw;
 319         d11regs_t *regs = wlc_hw->regs;
 320         bool fatal = false;
 321         struct wiphy *wiphy = wlc->wiphy;
 322
 323         if (DEVICEREMOVED(wlc)) {
 324                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
 325                           __func__);
 326                 wl_down(wlc->wl);
 327                 return false;
 328         }
 329
 330         /* grab and clear the saved software intstatus bits */
 331         macintstatus = wlc->macintstatus;
 332         wlc->macintstatus = 0;
 333
 334         WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
 335                  wlc_hw->unit, macintstatus);
 336
 337         WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
 338
 339         /* BCN template is available */
 340         /* ZZZ: Use AP_ACTIVE ? */
 341         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 342             && (macintstatus & MI_BCNTPL)) {
 343                 wlc_update_beacon(wlc);
 344         }
 345
 346         /* PMQ entry addition */
 347         if (macintstatus & MI_PMQ) {
 348         }
 349
 350         /* tx status */
 351         if (macintstatus & MI_TFS) {
 352                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 353                         wlc->macintstatus |= MI_TFS;
 354                 if (fatal) {
 355                         wiphy_err(wiphy, "MI_TFS: fatal\n");
 356                         goto fatal;
 357                 }
 358         }
 359
 360         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 361                 wlc_tbtt(wlc, regs);
 362
 363         /* ATIM window end */
 364         if (macintstatus & MI_ATIMWINEND) {
 365                 WL_TRACE("wlc_isr: end of ATIM window\n");
 366
 367                 OR_REG(&regs->maccommand, wlc->qvalid);
 368                 wlc->qvalid = 0;
 369         }
 370
 371         /* phy tx error */
 372         if (macintstatus & MI_PHYTXERR) {
 373                 wlc->pub->_cnt->txphyerr++;
 374         }
 375
 376         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 377         if (macintstatus & MI_DMAINT) {
 378                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 379                         wlc->macintstatus |= MI_DMAINT;
 380                 }
 381         }
 382
 383         /* TX FIFO suspend/flush completion */
 384         if (macintstatus & MI_TXSTOP) {
 385                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 386                         /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
 387                 }
 388         }
 389
 390         /* noise sample collected */
 391         if (macintstatus & MI_BG_NOISE) {
 392                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 393         }
 394
 395         if (macintstatus & MI_GP0) {
 396                 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
 397                         "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
 398
 399                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 400                                         __func__, wlc_hw->sih->chip,
 401                                         wlc_hw->sih->chiprev);
 402
 403                 wlc->pub->_cnt->psmwds++;
 404
 405                 /* big hammer */
 406                 wl_init(wlc->wl);
 407         }
 408
 409         /* gptimer timeout */
 410         if (macintstatus & MI_TO) {
 411                 W_REG(&regs->gptimer, 0);
 412         }
 413
 414         if (macintstatus & MI_RFDISABLE) {
 415                 WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
 416
 417                 wlc->pub->_cnt->rfdisable++;
 418                 wl_rfkill_set_hw_state(wlc->wl);
 419         }
 420
 421         /* send any enq'd tx packets. Just makes sure to jump start tx */
 422         if (!pktq_empty(&wlc->pkt_queue->q))
 423                 wlc_send_q(wlc);
 424
 425         /* it isn't done and needs to be resched if macintstatus is non-zero */
 426         return wlc->macintstatus != 0;
 427
 428  fatal:
 429         wl_init(wlc->wl);
 430         return wlc->macintstatus != 0;
 431 }
 432
 433 /* common low-level watchdog code */
 434 void wlc_bmac_watchdog(void *arg)
 435 {
 436         struct wlc_info *wlc = (struct wlc_info *) arg;
 437         struct wlc_hw_info *wlc_hw = wlc->hw;
 438
 439         WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
 440
 441         if (!wlc_hw->up)
 442                 return;
 443
 444         /* increment second count */
 445         wlc_hw->now++;
 446
 447         /* Check for FIFO error interrupts */
 448         wlc_bmac_fifoerrors(wlc_hw);
 449
 450         /* make sure RX dma has buffers */
 451         dma_rxfill(wlc->hw->di[RX_FIFO]);
 452
 453         wlc_phy_watchdog(wlc_hw->band->pi);
 454 }
 455
 456 void
 457 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 458                       bool mute, struct txpwr_limits *txpwr)
 459 {
 460         uint bandunit;
 461
 462         WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
 463                  wlc_hw->unit, chanspec);
 464
 465         wlc_hw->chanspec = chanspec;
 466
 467         /* Switch bands if necessary */
 468         if (NBANDS_HW(wlc_hw) > 1) {
 469                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 470                 if (wlc_hw->band->bandunit != bandunit) {
 471                         /* wlc_bmac_setband disables other bandunit,
 472                          *  use light band switch if not up yet
 473                          */
 474                         if (wlc_hw->up) {
 475                                 wlc_phy_chanspec_radio_set(wlc_hw->
 476                                                            bandstate[bandunit]->
 477                                                            pi, chanspec);
 478                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 479                         } else {
 480                                 wlc_setxband(wlc_hw, bandunit);
 481                         }
 482                 }
 483         }
 484
 485         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 486
 487         if (!wlc_hw->up) {
 488                 if (wlc_hw->clk)
 489                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 490                                                   chanspec);
 491                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 492         } else {
 493                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 494                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 495
 496                 /* Update muting of the channel */
 497                 wlc_bmac_mute(wlc_hw, mute, 0);
 498         }
 499 }
 500
 501 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 502 {
 503         state->machwcap = wlc_hw->machwcap;
 504
 505         return 0;
 506 }
 507
 508 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 509 {
 510         uint i;
 511         char name[8];
 512         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 513         u16 pio_mhf2 = 0;
 514         struct wlc_hw_info *wlc_hw = wlc->hw;
 515         uint unit = wlc_hw->unit;
 516         wlc_tunables_t *tune = wlc->pub->tunables;
 517         struct wiphy *wiphy = wlc->wiphy;
 518
 519         /* name and offsets for dma_attach */
 520         snprintf(name, sizeof(name), "wl%d", unit);
 521
 522         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 523                 uint addrwidth;
 524                 int dma_attach_err = 0;
 525                 /* Find out the DMA addressing capability and let OS know
 526                  * All the channels within one DMA core have 'common-minimum' same
 527                  * capability
 528                  */
 529                 addrwidth =
 530                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 531
 532                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 533                         wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
 534                                   "resources failed\n", unit);
 535                         return false;
 536                 }
 537
 538                 /*
 539                  * FIFO 0
 540                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 541                  * RX: RX_FIFO (RX data packets)
 542                  */
 543                 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
 544                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 545                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 546                                            (wme ? tune->ntxd : 0), tune->nrxd,
 547                                            tune->rxbufsz, -1, tune->nrxbufpost,
 548                                            WL_HWRXOFF, &wl_msg_level);
 549                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 550
 551                 /*
 552                  * FIFO 1
 553                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 554                  *   (legacy) TX_DATA_FIFO (TX data packets)
 555                  * RX: UNUSED
 556                  */
 557                 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
 558                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 559                                            tune->ntxd, 0, 0, -1, 0, 0,
 560                                            &wl_msg_level);
 561                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 562
 563                 /*
 564                  * FIFO 2
 565                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 566                  * RX: UNUSED
 567                  */
 568                 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
 569                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 570                                            tune->ntxd, 0, 0, -1, 0, 0,
 571                                            &wl_msg_level);
 572                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 573                 /*
 574                  * FIFO 3
 575                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 576                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 577                  */
 578                 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
 579                                            DMAREG(wlc_hw, DMA_TX, 3),
 580                                            NULL, tune->ntxd, 0, 0, -1,
 581                                            0, 0, &wl_msg_level);
 582                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 583 /* Cleaner to leave this as if with AP defined */
 584
 585                 if (dma_attach_err) {
 586                         wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
 587                                   "\n", unit);
 588                         return false;
 589                 }
 590
 591                 /* get pointer to dma engine tx flow control variable */
 592                 for (i = 0; i < NFIFO; i++)
 593                         if (wlc_hw->di[i])
 594                                 wlc_hw->txavail[i] =
 595                                     (uint *) dma_getvar(wlc_hw->di[i],
 596                                                         "&txavail");
 597         }
 598
 599         /* initial ucode host flags */
 600         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 601
 602         return true;
 603 }
 604
 605 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 606 {
 607         uint j;
 608
 609         for (j = 0; j < NFIFO; j++) {
 610                 if (wlc_hw->di[j]) {
 611                         dma_detach(wlc_hw->di[j]);
 612                         wlc_hw->di[j] = NULL;
 613                 }
 614         }
 615 }
 616
 617 /* low level attach
 618  *    run backplane attach, init nvram
 619  *    run phy attach
 620  *    initialize software state for each core and band
 621  *    put the whole chip in reset(driver down state), no clock
 622  */
 623 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 624                     bool piomode, void *regsva, uint bustype, void *btparam)
 625 {
 626         struct wlc_hw_info *wlc_hw;
 627         d11regs_t *regs;
 628         char *macaddr = NULL;
 629         char *vars;
 630         uint err = 0;
 631         uint j;
 632         bool wme = false;
 633         shared_phy_params_t sha_params;
 634         struct wiphy *wiphy = wlc->wiphy;
 635
 636         WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
 637                  unit, vendor, device);
 638
 639
 640         wme = true;
 641
 642         wlc_hw = wlc->hw;
 643         wlc_hw->wlc = wlc;
 644         wlc_hw->unit = unit;
 645         wlc_hw->band = wlc_hw->bandstate[0];
 646         wlc_hw->_piomode = piomode;
 647
 648         /* populate struct wlc_hw_info with default values  */
 649         wlc_bmac_info_init(wlc_hw);
 650
 651         /*
 652          * Do the hardware portion of the attach.
 653          * Also initialize software state that depends on the particular hardware
 654          * we are running.
 655          */
 656         wlc_hw->sih = si_attach((uint) device, regsva, bustype, btparam,
 657                                 &wlc_hw->vars, &wlc_hw->vars_size);
 658         if (wlc_hw->sih == NULL) {
 659                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
 660                           unit);
 661                 err = 11;
 662                 goto fail;
 663         }
 664         vars = wlc_hw->vars;
 665
 666         /*
 667          * Get vendid/devid nvram overwrites, which could be different
 668          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 669          * SDIO_BUS, and SROMless devices on PCI_BUS.
 670          */
 671 #ifdef BCMBUSTYPE
 672         bustype = BCMBUSTYPE;
 673 #endif
 674         if (bustype != SI_BUS) {
 675                 char *var;
 676
 677                 var = getvar(vars, "vendid");
 678                 if (var) {
 679                         vendor = (u16) simple_strtoul(var, NULL, 0);
 680                         wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
 681                                   vendor);
 682                 }
 683                 var = getvar(vars, "devid");
 684                 if (var) {
 685                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 686                         if (devid != 0xffff) {
 687                                 device = devid;
 688                                 wiphy_err(wiphy, "Overriding device id = 0x%x"
 689                                           "\n", device);
 690                         }
 691                 }
 692
 693                 /* verify again the device is supported */
 694                 if (!wlc_chipmatch(vendor, device)) {
 695                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
 696                                 "vendor/device (0x%x/0x%x)\n",
 697                                  unit, vendor, device);
 698                         err = 12;
 699                         goto fail;
 700                 }
 701         }
 702
 703         wlc_hw->vendorid = vendor;
 704         wlc_hw->deviceid = device;
 705
 706         /* set bar0 window to point at D11 core */
 707         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 708         wlc_hw->corerev = ai_corerev(wlc_hw->sih);
 709
 710         regs = wlc_hw->regs;
 711
 712         wlc->regs = wlc_hw->regs;
 713
 714         /* validate chip, chiprev and corerev */
 715         if (!wlc_isgoodchip(wlc_hw)) {
 716                 err = 13;
 717                 goto fail;
 718         }
 719
 720         /* initialize power control registers */
 721         si_clkctl_init(wlc_hw->sih);
 722
 723         /* request fastclock and force fastclock for the rest of attach
 724          * bring the d11 core out of reset.
 725          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 726          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 727          */
 728         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 729         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 730
 731         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 732                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
 733                         "failed\n", unit);
 734                 err = 14;
 735                 goto fail;
 736         }
 737
 738         /* get the board rev, used just below */
 739         j = getintvar(vars, "boardrev");
 740         /* promote srom boardrev of 0xFF to 1 */
 741         if (j == BOARDREV_PROMOTABLE)
 742                 j = BOARDREV_PROMOTED;
 743         wlc_hw->boardrev = (u16) j;
 744         if (!wlc_validboardtype(wlc_hw)) {
 745                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
 746                         "board type (0x%x)" " or revision level (0x%x)\n",
 747                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 748                 err = 15;
 749                 goto fail;
 750         }
 751         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 752         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 753         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 754
 755         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 756                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 757
 758         if ((wlc_hw->sih->bustype == PCI_BUS)
 759             && (si_pci_war16165(wlc_hw->sih)))
 760                 wlc->war16165 = true;
 761
 762         /* check device id(srom, nvram etc.) to set bands */
 763         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 764                 /* Dualband boards */
 765                 wlc_hw->_nbands = 2;
 766         } else
 767                 wlc_hw->_nbands = 1;
 768
 769         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 770                 wlc_hw->_nbands = 1;
 771
 772         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 773          * init of these values
 774          */
 775         wlc->vendorid = wlc_hw->vendorid;
 776         wlc->deviceid = wlc_hw->deviceid;
 777         wlc->pub->sih = wlc_hw->sih;
 778         wlc->pub->corerev = wlc_hw->corerev;
 779         wlc->pub->sromrev = wlc_hw->sromrev;
 780         wlc->pub->boardrev = wlc_hw->boardrev;
 781         wlc->pub->boardflags = wlc_hw->boardflags;
 782         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 783         wlc->pub->_nbands = wlc_hw->_nbands;
 784
 785         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 786
 787         if (wlc_hw->physhim == NULL) {
 788                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
 789                         "failed\n", unit);
 790                 err = 25;
 791                 goto fail;
 792         }
 793
 794         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 795         sha_params.sih = wlc_hw->sih;
 796         sha_params.physhim = wlc_hw->physhim;
 797         sha_params.unit = unit;
 798         sha_params.corerev = wlc_hw->corerev;
 799         sha_params.vars = vars;
 800         sha_params.vid = wlc_hw->vendorid;
 801         sha_params.did = wlc_hw->deviceid;
 802         sha_params.chip = wlc_hw->sih->chip;
 803         sha_params.chiprev = wlc_hw->sih->chiprev;
 804         sha_params.chippkg = wlc_hw->sih->chippkg;
 805         sha_params.sromrev = wlc_hw->sromrev;
 806         sha_params.boardtype = wlc_hw->sih->boardtype;
 807         sha_params.boardrev = wlc_hw->boardrev;
 808         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 809         sha_params.boardflags = wlc_hw->boardflags;
 810         sha_params.boardflags2 = wlc_hw->boardflags2;
 811         sha_params.bustype = wlc_hw->sih->bustype;
 812         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 813
 814         /* alloc and save pointer to shared phy state area */
 815         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 816         if (!wlc_hw->phy_sh) {
 817                 err = 16;
 818                 goto fail;
 819         }
 820
 821         /* initialize software state for each core and band */
 822         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 823                 /*
 824                  * band0 is always 2.4Ghz
 825                  * band1, if present, is 5Ghz
 826                  */
 827
 828                 /* So if this is a single band 11a card, use band 1 */
 829                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 830                         j = BAND_5G_INDEX;
 831
 832                 wlc_setxband(wlc_hw, j);
 833
 834                 wlc_hw->band->bandunit = j;
 835                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 836                 wlc->band->bandunit = j;
 837                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 838                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 839
 840                 wlc_hw->machwcap = R_REG(&regs->machwcap);
 841                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 842
 843                 /* init tx fifo size */
 844                 wlc_hw->xmtfifo_sz =
 845                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 846
 847                 /* Get a phy for this band */
 848                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 849                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
 850                         wlc->wiphy);
 851                 if (wlc_hw->band->pi == NULL) {
 852                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
 853                                   "attach failed\n", unit);
 854                         err = 17;
 855                         goto fail;
 856                 }
 857
 858                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 859
 860                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 861                                        &wlc_hw->band->phyrev,
 862                                        &wlc_hw->band->radioid,
 863                                        &wlc_hw->band->radiorev);
 864                 wlc_hw->band->abgphy_encore =
 865                     wlc_phy_get_encore(wlc_hw->band->pi);
 866                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 867                 wlc_hw->band->core_flags =
 868                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 869
 870                 /* verify good phy_type & supported phy revision */
 871                 if (WLCISNPHY(wlc_hw->band)) {
 872                         if (NCONF_HAS(wlc_hw->band->phyrev))
 873                                 goto good_phy;
 874                         else
 875                                 goto bad_phy;
 876                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 877                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 878                                 goto good_phy;
 879                         else
 880                                 goto bad_phy;
 881                 } else {
 882  bad_phy:
 883                         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
 884                                   "phy type/rev (%d/%d)\n", unit,
 885                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
 886                         err = 18;
 887                         goto fail;
 888                 }
 889
 890  good_phy:
 891                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 892                  * high level attach. However we can not make that change until all low level access
 893                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 894                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 895                  * low only init when all fns updated.
 896                  */
 897                 wlc->band->pi = wlc_hw->band->pi;
 898                 wlc->band->phytype = wlc_hw->band->phytype;
 899                 wlc->band->phyrev = wlc_hw->band->phyrev;
 900                 wlc->band->radioid = wlc_hw->band->radioid;
 901                 wlc->band->radiorev = wlc_hw->band->radiorev;
 902
 903                 /* default contention windows size limits */
 904                 wlc_hw->band->CWmin = APHY_CWMIN;
 905                 wlc_hw->band->CWmax = PHY_CWMAX;
 906
 907                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 908                         err = 19;
 909                         goto fail;
 910                 }
 911         }
 912
 913         /* disable core to match driver "down" state */
 914         wlc_coredisable(wlc_hw);
 915
 916         /* Match driver "down" state */
 917         if (wlc_hw->sih->bustype == PCI_BUS)
 918                 si_pci_down(wlc_hw->sih);
 919
 920         /* register sb interrupt callback functions */
 921         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 922                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 923
 924         /* turn off pll and xtal to match driver "down" state */
 925         wlc_bmac_xtal(wlc_hw, OFF);
 926
 927         /* *********************************************************************
 928          * The hardware is in the DOWN state at this point. D11 core
 929          * or cores are in reset with clocks off, and the board PLLs
 930          * are off if possible.
 931          *
 932          * Beyond this point, wlc->sbclk == false and chip registers
 933          * should not be touched.
 934          *********************************************************************
 935          */
 936
 937         /* init etheraddr state variables */
 938         macaddr = wlc_get_macaddr(wlc_hw);
 939         if (macaddr == NULL) {
 940                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
 941                           unit);
 942                 err = 21;
 943                 goto fail;
 944         }
 945         bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
 946         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 947             is_zero_ether_addr(wlc_hw->etheraddr)) {
 948                 wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
 949                           unit, macaddr);
 950                 err = 22;
 951                 goto fail;
 952         }
 953
 954         WL_TRACE("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 955                  __func__, wlc_hw->deviceid, wlc_hw->_nbands,
 956                  wlc_hw->sih->boardtype, macaddr);
 957
 958         return err;
 959
 960  fail:
 961         wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
 962                   err);
 963         return err;
 964 }
 965
 966 /*
 967  * Initialize wlc_info default values ...
 968  * may get overrides later in this function
 969  *  BMAC_NOTES, move low out and resolve the dangling ones
 970  */
 971 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
 972 {
 973         struct wlc_info *wlc = wlc_hw->wlc;
 974
 975         /* set default sw macintmask value */
 976         wlc->defmacintmask = DEF_MACINTMASK;
 977
 978         /* various 802.11g modes */
 979         wlc_hw->shortslot = false;
 980
 981         wlc_hw->SFBL = RETRY_SHORT_FB;
 982         wlc_hw->LFBL = RETRY_LONG_FB;
 983
 984         /* default mac retry limits */
 985         wlc_hw->SRL = RETRY_SHORT_DEF;
 986         wlc_hw->LRL = RETRY_LONG_DEF;
 987         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
 988 }
 989
 990 /*
 991  * low level detach
 992  */
 993 int wlc_bmac_detach(struct wlc_info *wlc)
 994 {
 995         uint i;
 996         struct wlc_hwband *band;
 997         struct wlc_hw_info *wlc_hw = wlc->hw;
 998         int callbacks;
 999
1000         callbacks = 0;
1001
1002         if (wlc_hw->sih) {
1003                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1004                  * interrupt object may has been freed. this must be done before sb core switch
1005                  */
1006                 si_deregister_intr_callback(wlc_hw->sih);
1007
1008                 if (wlc_hw->sih->bustype == PCI_BUS)
1009                         si_pci_sleep(wlc_hw->sih);
1010         }
1011
1012         wlc_bmac_detach_dmapio(wlc_hw);
1013
1014         band = wlc_hw->band;
1015         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1016                 if (band->pi) {
1017                         /* Detach this band's phy */
1018                         wlc_phy_detach(band->pi);
1019                         band->pi = NULL;
1020                 }
1021                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1022         }
1023
1024         /* Free shared phy state */
1025         wlc_phy_shared_detach(wlc_hw->phy_sh);
1026
1027         wlc_phy_shim_detach(wlc_hw->physhim);
1028
1029         /* free vars */
1030         kfree(wlc_hw->vars);
1031         wlc_hw->vars = NULL;
1032
1033         if (wlc_hw->sih) {
1034                 si_detach(wlc_hw->sih);
1035                 wlc_hw->sih = NULL;
1036         }
1037
1038         return callbacks;
1039
1040 }
1041
1042 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1043 {
1044         WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1045
1046         wlc_hw->wlc->pub->_cnt->reset++;
1047
1048         /* reset the core */
1049         if (!DEVICEREMOVED(wlc_hw->wlc))
1050                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1051
1052         /* purge the dma rings */
1053         wlc_flushqueues(wlc_hw->wlc);
1054
1055         wlc_reset_bmac_done(wlc_hw->wlc);
1056 }
1057
1058 void
1059 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1060                           bool mute) {
1061         u32 macintmask;
1062         bool fastclk;
1063         struct wlc_info *wlc = wlc_hw->wlc;
1064
1065         WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1066
1067         /* request FAST clock if not on */
1068         fastclk = wlc_hw->forcefastclk;
1069         if (!fastclk)
1070                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1071
1072         /* disable interrupts */
1073         macintmask = wl_intrsoff(wlc->wl);
1074
1075         /* set up the specified band and chanspec */
1076         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1077         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1078
1079         /* do one-time phy inits and calibration */
1080         wlc_phy_cal_init(wlc_hw->band->pi);
1081
1082         /* core-specific initialization */
1083         wlc_coreinit(wlc);
1084
1085         /* suspend the tx fifos and mute the phy for preism cac time */
1086         if (mute)
1087                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1088
1089         /* band-specific inits */
1090         wlc_bmac_bsinit(wlc, chanspec);
1091
1092         /* restore macintmask */
1093         wl_intrsrestore(wlc->wl, macintmask);
1094
1095         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1096          * and wlc_enable_mac() will clear this override bit.
1097          */
1098         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1099
1100         /*
1101          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1102          */
1103         wlc_hw->mac_suspend_depth = 1;
1104
1105         /* restore the clk */
1106         if (!fastclk)
1107                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1108 }
1109
1110 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1111 {
1112         uint coremask;
1113
1114         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1115
1116         /*
1117          * Enable pll and xtal, initialize the power control registers,
1118          * and force fastclock for the remainder of wlc_up().
1119          */
1120         wlc_bmac_xtal(wlc_hw, ON);
1121         si_clkctl_init(wlc_hw->sih);
1122         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1123
1124         /*
1125          * Configure pci/pcmcia here instead of in wlc_attach()
1126          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1127          */
1128         coremask = (1 << wlc_hw->wlc->core->coreidx);
1129
1130         if (wlc_hw->sih->bustype == PCI_BUS)
1131                 si_pci_setup(wlc_hw->sih, coremask);
1132
1133         /*
1134          * Need to read the hwradio status here to cover the case where the system
1135          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1136          */
1137         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1138                 /* put SB PCI in down state again */
1139                 if (wlc_hw->sih->bustype == PCI_BUS)
1140                         si_pci_down(wlc_hw->sih);
1141                 wlc_bmac_xtal(wlc_hw, OFF);
1142                 return -ENOMEDIUM;
1143         }
1144
1145         if (wlc_hw->sih->bustype == PCI_BUS)
1146                 si_pci_up(wlc_hw->sih);
1147
1148         /* reset the d11 core */
1149         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1150
1151         return 0;
1152 }
1153
1154 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1155 {
1156         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1157
1158         wlc_hw->up = true;
1159         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1160
1161         /* FULLY enable dynamic power control and d11 core interrupt */
1162         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1163         wl_intrson(wlc_hw->wlc->wl);
1164         return 0;
1165 }
1166
1167 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1168 {
1169         bool dev_gone;
1170         uint callbacks = 0;
1171
1172         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1173
1174         if (!wlc_hw->up)
1175                 return callbacks;
1176
1177         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1178
1179         /* disable interrupts */
1180         if (dev_gone)
1181                 wlc_hw->wlc->macintmask = 0;
1182         else {
1183                 /* now disable interrupts */
1184                 wl_intrsoff(wlc_hw->wlc->wl);
1185
1186                 /* ensure we're running on the pll clock again */
1187                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1188         }
1189         /* down phy at the last of this stage */
1190         callbacks += wlc_phy_down(wlc_hw->band->pi);
1191
1192         return callbacks;
1193 }
1194
1195 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1196 {
1197         uint callbacks = 0;
1198         bool dev_gone;
1199
1200         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1201
1202         if (!wlc_hw->up)
1203                 return callbacks;
1204
1205         wlc_hw->up = false;
1206         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1207
1208         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1209
1210         if (dev_gone) {
1211                 wlc_hw->sbclk = false;
1212                 wlc_hw->clk = false;
1213                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1214
1215                 /* reclaim any posted packets */
1216                 wlc_flushqueues(wlc_hw->wlc);
1217         } else {
1218
1219                 /* Reset and disable the core */
1220                 if (ai_iscoreup(wlc_hw->sih)) {
1221                         if (R_REG(&wlc_hw->regs->maccontrol) &
1222                             MCTL_EN_MAC)
1223                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1224                         callbacks += wl_reset(wlc_hw->wlc->wl);
1225                         wlc_coredisable(wlc_hw);
1226                 }
1227
1228                 /* turn off primary xtal and pll */
1229                 if (!wlc_hw->noreset) {
1230                         if (wlc_hw->sih->bustype == PCI_BUS)
1231                                 si_pci_down(wlc_hw->sih);
1232                         wlc_bmac_xtal(wlc_hw, OFF);
1233                 }
1234         }
1235
1236         return callbacks;
1237 }
1238
1239 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1240 {
1241         /* delay before first read of ucode state */
1242         udelay(40);
1243
1244         /* wait until ucode is no longer asleep */
1245         SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1246                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1247 }
1248
1249 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1250 {
1251         memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1252 }
1253
1254 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1255 {
1256         return wlc_hw->band->bandtype;
1257 }
1258
1259 /* control chip clock to save power, enable dynamic clock or force fast clock */
1260 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1261 {
1262         if (PMUCTL_ENAB(wlc_hw->sih)) {
1263                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1264                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1265                  *      which means the FCA bit may not be set.
1266                  *      should wakeup mac if driver wants it to run on HT.
1267                  */
1268
1269                 if (wlc_hw->clk) {
1270                         if (mode == CLK_FAST) {
1271                                 OR_REG(&wlc_hw->regs->clk_ctl_st,
1272                                        CCS_FORCEHT);
1273
1274                                 udelay(64);
1275
1276                                 SPINWAIT(((R_REG
1277                                            (&wlc_hw->regs->
1278                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1279                                          PMU_MAX_TRANSITION_DLY);
1280                                 WARN_ON(!(R_REG
1281                                           (&wlc_hw->regs->
1282                                            clk_ctl_st) & CCS_HTAVAIL));
1283                         } else {
1284                                 if ((wlc_hw->sih->pmurev == 0) &&
1285                                     (R_REG
1286                                      (&wlc_hw->regs->
1287                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1288                                         SPINWAIT(((R_REG
1289                                                    (&wlc_hw->regs->
1290                                                     clk_ctl_st) & CCS_HTAVAIL)
1291                                                   == 0),
1292                                                  PMU_MAX_TRANSITION_DLY);
1293                                 AND_REG(&wlc_hw->regs->clk_ctl_st,
1294                                         ~CCS_FORCEHT);
1295                         }
1296                 }
1297                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1298         } else {
1299
1300                 /* old chips w/o PMU, force HT through cc,
1301                  * then use FCA to verify mac is running fast clock
1302                  */
1303
1304                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1305
1306                 /* check fast clock is available (if core is not in reset) */
1307                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1308                         WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1309                                   SISF_FCLKA));
1310
1311                 /* keep the ucode wake bit on if forcefastclk is on
1312                  * since we do not want ucode to put us back to slow clock
1313                  * when it dozes for PM mode.
1314                  * Code below matches the wake override bit with current forcefastclk state
1315                  * Only setting bit in wake_override instead of waking ucode immediately
1316                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1317                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1318                  * (protected by an up check) was executed just below.
1319                  */
1320                 if (wlc_hw->forcefastclk)
1321                         mboolset(wlc_hw->wake_override,
1322                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1323                 else
1324                         mboolclr(wlc_hw->wake_override,
1325                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1326         }
1327 }
1328
1329 /* set initial host flags value */
1330 static void
1331 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1332 {
1333         struct wlc_hw_info *wlc_hw = wlc->hw;
1334
1335         memset(mhfs, 0, MHFMAX * sizeof(u16));
1336
1337         mhfs[MHF2] |= mhf2_init;
1338
1339         /* prohibit use of slowclock on multifunction boards */
1340         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1341                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1342
1343         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1344                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1345                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1346         }
1347 }
1348
1349 /* set or clear ucode host flag bits
1350  * it has an optimization for no-change write
1351  * it only writes through shared memory when the core has clock;
1352  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1353  *
1354  *
1355  * bands values are: WLC_BAND_AUTO <--- Current band only
1356  *                   WLC_BAND_5G   <--- 5G band only
1357  *                   WLC_BAND_2G   <--- 2G band only
1358  *                   WLC_BAND_ALL  <--- All bands
1359  */
1360 void
1361 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1362              int bands)
1363 {
1364         u16 save;
1365         u16 addr[MHFMAX] = {
1366                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1367                 M_HOST_FLAGS5
1368         };
1369         struct wlc_hwband *band;
1370
1371         if ((val & ~mask) || idx >= MHFMAX)
1372                 return; /* error condition */
1373
1374         switch (bands) {
1375                 /* Current band only or all bands,
1376                  * then set the band to current band
1377                  */
1378         case WLC_BAND_AUTO:
1379         case WLC_BAND_ALL:
1380                 band = wlc_hw->band;
1381                 break;
1382         case WLC_BAND_5G:
1383                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1384                 break;
1385         case WLC_BAND_2G:
1386                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1387                 break;
1388         default:
1389                 band = NULL;    /* error condition */
1390         }
1391
1392         if (band) {
1393                 save = band->mhfs[idx];
1394                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1395
1396                 /* optimization: only write through if changed, and
1397                  * changed band is the current band
1398                  */
1399                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1400                     && (band == wlc_hw->band))
1401                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1402                                            (u16) band->mhfs[idx]);
1403         }
1404
1405         if (bands == WLC_BAND_ALL) {
1406                 wlc_hw->bandstate[0]->mhfs[idx] =
1407                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1408                 wlc_hw->bandstate[1]->mhfs[idx] =
1409                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1410         }
1411 }
1412
1413 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1414 {
1415         struct wlc_hwband *band;
1416
1417         if (idx >= MHFMAX)
1418                 return 0; /* error condition */
1419         switch (bands) {
1420         case WLC_BAND_AUTO:
1421                 band = wlc_hw->band;
1422                 break;
1423         case WLC_BAND_5G:
1424                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1425                 break;
1426         case WLC_BAND_2G:
1427                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1428                 break;
1429         default:
1430                 band = NULL;            /* error condition */
1431         }
1432
1433         if (!band)
1434                 return 0;
1435
1436         return band->mhfs[idx];
1437 }
1438
1439 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1440 {
1441         u8 idx;
1442         u16 addr[] = {
1443                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1444                 M_HOST_FLAGS5
1445         };
1446
1447         for (idx = 0; idx < MHFMAX; idx++) {
1448                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1449         }
1450 }
1451
1452 /* set the maccontrol register to desired reset state and
1453  * initialize the sw cache of the register
1454  */
1455 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1456 {
1457         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1458         wlc_hw->maccontrol = 0;
1459         wlc_hw->suspended_fifos = 0;
1460         wlc_hw->wake_override = 0;
1461         wlc_hw->mute_override = 0;
1462         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1463 }
1464
1465 /* set or clear maccontrol bits */
1466 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1467 {
1468         u32 maccontrol;
1469         u32 new_maccontrol;
1470
1471         if (val & ~mask)
1472                 return; /* error condition */
1473         maccontrol = wlc_hw->maccontrol;
1474         new_maccontrol = (maccontrol & ~mask) | val;
1475
1476         /* if the new maccontrol value is the same as the old, nothing to do */
1477         if (new_maccontrol == maccontrol)
1478                 return;
1479
1480         /* something changed, cache the new value */
1481         wlc_hw->maccontrol = new_maccontrol;
1482
1483         /* write the new values with overrides applied */
1484         wlc_mctrl_write(wlc_hw);
1485 }
1486
1487 /* write the software state of maccontrol and overrides to the maccontrol register */
1488 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1489 {
1490         u32 maccontrol = wlc_hw->maccontrol;
1491
1492         /* OR in the wake bit if overridden */
1493         if (wlc_hw->wake_override)
1494                 maccontrol |= MCTL_WAKE;
1495
1496         /* set AP and INFRA bits for mute if needed */
1497         if (wlc_hw->mute_override) {
1498                 maccontrol &= ~(MCTL_AP);
1499                 maccontrol |= MCTL_INFRA;
1500         }
1501
1502         W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1503 }
1504
1505 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1506 {
1507         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1508                 mboolset(wlc_hw->wake_override, override_bit);
1509                 return;
1510         }
1511
1512         mboolset(wlc_hw->wake_override, override_bit);
1513
1514         wlc_mctrl_write(wlc_hw);
1515         wlc_bmac_wait_for_wake(wlc_hw);
1516
1517         return;
1518 }
1519
1520 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1521 {
1522         mboolclr(wlc_hw->wake_override, override_bit);
1523
1524         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1525                 return;
1526
1527         wlc_mctrl_write(wlc_hw);
1528
1529         return;
1530 }
1531
1532 /* When driver needs ucode to stop beaconing, it has to make sure that
1533  * MCTL_AP is clear and MCTL_INFRA is set
1534  * Mode           MCTL_AP        MCTL_INFRA
1535  * AP                1              1
1536  * STA               0              1 <--- This will ensure no beacons
1537  * IBSS              0              0
1538  */
1539 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1540 {
1541         wlc_hw->mute_override = 1;
1542
1543         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1544          * override, then there is no change to write
1545          */
1546         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1547                 return;
1548
1549         wlc_mctrl_write(wlc_hw);
1550
1551         return;
1552 }
1553
1554 /* Clear the override on AP and INFRA bits */
1555 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1556 {
1557         if (wlc_hw->mute_override == 0)
1558                 return;
1559
1560         wlc_hw->mute_override = 0;
1561
1562         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1563          * override, then there is no change to write
1564          */
1565         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1566                 return;
1567
1568         wlc_mctrl_write(wlc_hw);
1569 }
1570
1571 /*
1572  * Write a MAC address to the rcmta structure
1573  */
1574 void
1575 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1576                    const u8 *addr)
1577 {
1578         d11regs_t *regs = wlc_hw->regs;
1579         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1580         u32 mac_hm;
1581         u16 mac_l;
1582
1583         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1584
1585         mac_hm =
1586             (addr[3] << 24) | (addr[2] << 16) |
1587             (addr[1] << 8) | addr[0];
1588         mac_l = (addr[5] << 8) | addr[4];
1589
1590         W_REG(&regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1591         (void)R_REG(&regs->objaddr);
1592         W_REG(&regs->objdata, mac_hm);
1593         W_REG(&regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1594         (void)R_REG(&regs->objaddr);
1595         W_REG(objdata16, mac_l);
1596 }
1597
1598 /*
1599  * Write a MAC address to the given match reg offset in the RXE match engine.
1600  */
1601 void
1602 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1603                        const u8 *addr)
1604 {
1605         d11regs_t *regs;
1606         u16 mac_l;
1607         u16 mac_m;
1608         u16 mac_h;
1609
1610         WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1611
1612         regs = wlc_hw->regs;
1613         mac_l = addr[0] | (addr[1] << 8);
1614         mac_m = addr[2] | (addr[3] << 8);
1615         mac_h = addr[4] | (addr[5] << 8);
1616
1617         /* enter the MAC addr into the RXE match registers */
1618         W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1619         W_REG(&regs->rcm_mat_data, mac_l);
1620         W_REG(&regs->rcm_mat_data, mac_m);
1621         W_REG(&regs->rcm_mat_data, mac_h);
1622
1623 }
1624
1625 void
1626 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1627                             void *buf)
1628 {
1629         d11regs_t *regs;
1630         u32 word;
1631         bool be_bit;
1632 #ifdef IL_BIGENDIAN
1633         volatile u16 *dptr = NULL;
1634 #endif                          /* IL_BIGENDIAN */
1635         WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1636
1637         regs = wlc_hw->regs;
1638         W_REG(&regs->tplatewrptr, offset);
1639
1640         /* if MCTL_BIGEND bit set in mac control register,
1641          * the chip swaps data in fifo, as well as data in
1642          * template ram
1643          */
1644         be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1645
1646         while (len > 0) {
1647                 memcpy(&word, buf, sizeof(u32));
1648
1649                 if (be_bit)
1650                         word = cpu_to_be32(word);
1651                 else
1652                         word = cpu_to_le32(word);
1653
1654                 W_REG(&regs->tplatewrdata, word);
1655
1656                 buf = (u8 *) buf + sizeof(u32);
1657                 len -= sizeof(u32);
1658         }
1659 }
1660
1661 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1662 {
1663         wlc_hw->band->CWmin = newmin;
1664
1665         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1666         (void)R_REG(&wlc_hw->regs->objaddr);
1667         W_REG(&wlc_hw->regs->objdata, newmin);
1668 }
1669
1670 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1671 {
1672         wlc_hw->band->CWmax = newmax;
1673
1674         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1675         (void)R_REG(&wlc_hw->regs->objaddr);
1676         W_REG(&wlc_hw->regs->objdata, newmax);
1677 }
1678
1679 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1680 {
1681         bool fastclk;
1682
1683         /* request FAST clock if not on */
1684         fastclk = wlc_hw->forcefastclk;
1685         if (!fastclk)
1686                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1687
1688         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1689
1690         wlc_bmac_phy_reset(wlc_hw);
1691         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1692
1693         /* restore the clk */
1694         if (!fastclk)
1695                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1696 }
1697
1698 static void
1699 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1700 {
1701         d11regs_t *regs = wlc_hw->regs;
1702
1703         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1704                                     bcn);
1705         /* write beacon length to SCR */
1706         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1707         /* mark beacon0 valid */
1708         OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1709 }
1710
1711 static void
1712 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1713 {
1714         d11regs_t *regs = wlc_hw->regs;
1715
1716         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1717                                     bcn);
1718         /* write beacon length to SCR */
1719         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1720         /* mark beacon1 valid */
1721         OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1722 }
1723
1724 /* mac is assumed to be suspended at this point */
1725 void
1726 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1727                                bool both)
1728 {
1729         d11regs_t *regs = wlc_hw->regs;
1730
1731         if (both) {
1732                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1733                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1734         } else {
1735                 /* bcn 0 */
1736                 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1737                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1738                 /* bcn 1 */
1739                 else if (!
1740                          (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1741                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1742         }
1743 }
1744
1745 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1746 {
1747         u16 v;
1748         struct wlc_info *wlc = wlc_hw->wlc;
1749         /* update SYNTHPU_DLY */
1750
1751         if (WLCISLCNPHY(wlc->band)) {
1752                 v = SYNTHPU_DLY_LPPHY_US;
1753         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1754                 v = SYNTHPU_DLY_NPHY_US;
1755         } else {
1756                 v = SYNTHPU_DLY_BPHY_US;
1757         }
1758
1759         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1760 }
1761
1762 /* band-specific init */
1763 static void
1764 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1765 {
1766         struct wlc_hw_info *wlc_hw = wlc->hw;
1767
1768         WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1769                  wlc_hw->unit, wlc_hw->band->bandunit);
1770
1771         wlc_ucode_bsinit(wlc_hw);
1772
1773         wlc_phy_init(wlc_hw->band->pi, chanspec);
1774
1775         wlc_ucode_txant_set(wlc_hw);
1776
1777         /* cwmin is band-specific, update hardware with value for current band */
1778         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1779         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1780
1781         wlc_bmac_update_slot_timing(wlc_hw,
1782                                     BAND_5G(wlc_hw->band->
1783                                             bandtype) ? true : wlc_hw->
1784                                     shortslot);
1785
1786         /* write phytype and phyvers */
1787         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1788         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1789
1790         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1791         wlc_upd_ofdm_pctl1_table(wlc_hw);
1792
1793         wlc_bmac_upd_synthpu(wlc_hw);
1794 }
1795
1796 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1797 {
1798         WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1799
1800         wlc_hw->phyclk = clk;
1801
1802         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1803
1804                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1805                                (SICF_PRST | SICF_FGC));
1806                 udelay(1);
1807                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1808                 udelay(1);
1809
1810         } else {                /* take phy out of reset */
1811
1812                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1813                 udelay(1);
1814                 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1815                 udelay(1);
1816
1817         }
1818 }
1819
1820 /* Perform a soft reset of the PHY PLL */
1821 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1822 {
1823         WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1824
1825         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1826                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1827         udelay(1);
1828         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1829                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1830         udelay(1);
1831         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1832                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1833         udelay(1);
1834         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1835                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1836         udelay(1);
1837 }
1838
1839 /* light way to turn on phy clock without reset for NPHY only
1840  *  refer to wlc_bmac_core_phy_clk for full version
1841  */
1842 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1843 {
1844         /* support(necessary for NPHY and HYPHY) only */
1845         if (!WLCISNPHY(wlc_hw->band))
1846                 return;
1847
1848         if (ON == clk)
1849                 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1850         else
1851                 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1852
1853 }
1854
1855 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1856 {
1857         if (ON == clk)
1858                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1859         else
1860                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1861 }
1862
1863 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1864 {
1865         wlc_phy_t *pih = wlc_hw->band->pi;
1866         u32 phy_bw_clkbits;
1867         bool phy_in_reset = false;
1868
1869         WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
1870
1871         if (pih == NULL)
1872                 return;
1873
1874         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1875
1876         /* Specific reset sequence required for NPHY rev 3 and 4 */
1877         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1878             NREV_LE(wlc_hw->band->phyrev, 4)) {
1879                 /* Set the PHY bandwidth */
1880                 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1881
1882                 udelay(1);
1883
1884                 /* Perform a soft reset of the PHY PLL */
1885                 wlc_bmac_core_phypll_reset(wlc_hw);
1886
1887                 /* reset the PHY */
1888                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1889                                (SICF_PRST | SICF_PCLKE));
1890                 phy_in_reset = true;
1891         } else {
1892
1893                 ai_core_cflags(wlc_hw->sih,
1894                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1895                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1896         }
1897
1898         udelay(2);
1899         wlc_bmac_core_phy_clk(wlc_hw, ON);
1900
1901         if (pih)
1902                 wlc_phy_anacore(pih, ON);
1903 }
1904
1905 /* switch to and initialize new band */
1906 static void
1907 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1908                                 chanspec_t chanspec) {
1909         struct wlc_info *wlc = wlc_hw->wlc;
1910         u32 macintmask;
1911
1912         /* Enable the d11 core before accessing it */
1913         if (!ai_iscoreup(wlc_hw->sih)) {
1914                 ai_core_reset(wlc_hw->sih, 0, 0);
1915                 wlc_mctrl_reset(wlc_hw);
1916         }
1917
1918         macintmask = wlc_setband_inact(wlc, bandunit);
1919
1920         if (!wlc_hw->up)
1921                 return;
1922
1923         wlc_bmac_core_phy_clk(wlc_hw, ON);
1924
1925         /* band-specific initializations */
1926         wlc_bmac_bsinit(wlc, chanspec);
1927
1928         /*
1929          * If there are any pending software interrupt bits,
1930          * then replace these with a harmless nonzero value
1931          * so wlc_dpc() will re-enable interrupts when done.
1932          */
1933         if (wlc->macintstatus)
1934                 wlc->macintstatus = MI_DMAINT;
1935
1936         /* restore macintmask */
1937         wl_intrsrestore(wlc->wl, macintmask);
1938
1939         /* ucode should still be suspended.. */
1940         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1941 }
1942
1943 /* low-level band switch utility routine */
1944 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1945 {
1946         WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
1947
1948         wlc_hw->band = wlc_hw->bandstate[bandunit];
1949
1950         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1951         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1952
1953         /* set gmode core flag */
1954         if (wlc_hw->sbclk && !wlc_hw->noreset) {
1955                 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1956                                ((bandunit == 0) ? SICF_GMODE : 0));
1957         }
1958 }
1959
1960 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1961 {
1962
1963         /* reject unsupported corerev */
1964         if (!VALID_COREREV(wlc_hw->corerev)) {
1965                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1966                           wlc_hw->corerev);
1967                 return false;
1968         }
1969
1970         return true;
1971 }
1972
1973 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1974 {
1975         bool goodboard = true;
1976         uint boardrev = wlc_hw->boardrev;
1977
1978         if (boardrev == 0)
1979                 goodboard = false;
1980         else if (boardrev > 0xff) {
1981                 uint brt = (boardrev & 0xf000) >> 12;
1982                 uint b0 = (boardrev & 0xf00) >> 8;
1983                 uint b1 = (boardrev & 0xf0) >> 4;
1984                 uint b2 = boardrev & 0xf;
1985
1986                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1987                     || (b2 > 9))
1988                         goodboard = false;
1989         }
1990
1991         if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1992                 return goodboard;
1993
1994         return goodboard;
1995 }
1996
1997 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1998 {
1999         const char *varname = "macaddr";
2000         char *macaddr;
2001
2002         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2003         macaddr = getvar(wlc_hw->vars, varname);
2004         if (macaddr != NULL)
2005                 return macaddr;
2006
2007         if (NBANDS_HW(wlc_hw) > 1)
2008                 varname = "et1macaddr";
2009         else
2010                 varname = "il0macaddr";
2011
2012         macaddr = getvar(wlc_hw->vars, varname);
2013         if (macaddr == NULL) {
2014                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
2015                           "getvar(%s) not found\n", wlc_hw->unit, varname);
2016         }
2017
2018         return macaddr;
2019 }
2020
2021 /*
2022  * Return true if radio is disabled, otherwise false.
2023  * hw radio disable signal is an external pin, users activate it asynchronously
2024  * this function could be called when driver is down and w/o clock
2025  * it operates on different registers depending on corerev and boardflag.
2026  */
2027 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2028 {
2029         bool v, clk, xtal;
2030         u32 resetbits = 0, flags = 0;
2031
2032         xtal = wlc_hw->sbclk;
2033         if (!xtal)
2034                 wlc_bmac_xtal(wlc_hw, ON);
2035
2036         /* may need to take core out of reset first */
2037         clk = wlc_hw->clk;
2038         if (!clk) {
2039                 /*
2040                  * mac no longer enables phyclk automatically when driver
2041                  * accesses phyreg throughput mac. This can be skipped since
2042                  * only mac reg is accessed below
2043                  */
2044                 flags |= SICF_PCLKE;
2045
2046                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2047                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2048                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2049                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2050                         wlc_hw->regs =
2051                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2052                                                      0);
2053                 ai_core_reset(wlc_hw->sih, flags, resetbits);
2054                 wlc_mctrl_reset(wlc_hw);
2055         }
2056
2057         v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2058
2059         /* put core back into reset */
2060         if (!clk)
2061                 ai_core_disable(wlc_hw->sih, 0);
2062
2063         if (!xtal)
2064                 wlc_bmac_xtal(wlc_hw, OFF);
2065
2066         return v;
2067 }
2068
2069 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2070 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2071 {
2072         if (wlc_hw->wlc->pub->hw_up)
2073                 return;
2074
2075         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2076
2077         /*
2078          * Enable pll and xtal, initialize the power control registers,
2079          * and force fastclock for the remainder of wlc_up().
2080          */
2081         wlc_bmac_xtal(wlc_hw, ON);
2082         si_clkctl_init(wlc_hw->sih);
2083         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2084
2085         if (wlc_hw->sih->bustype == PCI_BUS) {
2086                 si_pci_fixcfg(wlc_hw->sih);
2087
2088                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2089                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2090                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2091                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2092                         wlc_hw->regs =
2093                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2094                                                      0);
2095         }
2096
2097         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2098         wlc_phy_por_inform(wlc_hw->band->pi);
2099
2100         wlc_hw->ucode_loaded = false;
2101         wlc_hw->wlc->pub->hw_up = true;
2102
2103         if ((wlc_hw->boardflags & BFL_FEM)
2104             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2105                 if (!
2106                     (wlc_hw->boardrev >= 0x1250
2107                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2108                         si_epa_4313war(wlc_hw->sih);
2109         }
2110 }
2111
2112 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2113 {
2114         struct hnddma_pub *di = wlc_hw->di[fifo];
2115         return dma_rxreset(di);
2116 }
2117
2118 /* d11 core reset
2119  *   ensure fask clock during reset
2120  *   reset dma
2121  *   reset d11(out of reset)
2122  *   reset phy(out of reset)
2123  *   clear software macintstatus for fresh new start
2124  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2125  */
2126 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2127 {
2128         d11regs_t *regs;
2129         uint i;
2130         bool fastclk;
2131         u32 resetbits = 0;
2132
2133         if (flags == WLC_USE_COREFLAGS)
2134                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2135
2136         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2137
2138         regs = wlc_hw->regs;
2139
2140         /* request FAST clock if not on  */
2141         fastclk = wlc_hw->forcefastclk;
2142         if (!fastclk)
2143                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2144
2145         /* reset the dma engines except first time thru */
2146         if (ai_iscoreup(wlc_hw->sih)) {
2147                 for (i = 0; i < NFIFO; i++)
2148                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2149                                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2150                                           "dma_txreset[%d]: cannot stop dma\n",
2151                                            wlc_hw->unit, __func__, i);
2152                         }
2153
2154                 if ((wlc_hw->di[RX_FIFO])
2155                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2156                         wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2157                                   "[%d]: cannot stop dma\n",
2158                                   wlc_hw->unit, __func__, RX_FIFO);
2159                 }
2160         }
2161         /* if noreset, just stop the psm and return */
2162         if (wlc_hw->noreset) {
2163                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2164                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2165                 return;
2166         }
2167
2168         /*
2169          * mac no longer enables phyclk automatically when driver accesses
2170          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2171          * band->pi is invalid. need to enable PHY CLK
2172          */
2173         flags |= SICF_PCLKE;
2174
2175         /* reset the core
2176          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2177          *  is cleared by the core_reset. have to re-request it.
2178          *  This adds some delay and we can optimize it by also requesting fastclk through
2179          *  chipcommon during this period if necessary. But that has to work coordinate
2180          *  with other driver like mips/arm since they may touch chipcommon as well.
2181          */
2182         wlc_hw->clk = false;
2183         ai_core_reset(wlc_hw->sih, flags, resetbits);
2184         wlc_hw->clk = true;
2185         if (wlc_hw->band && wlc_hw->band->pi)
2186                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2187
2188         wlc_mctrl_reset(wlc_hw);
2189
2190         if (PMUCTL_ENAB(wlc_hw->sih))
2191                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2192
2193         wlc_bmac_phy_reset(wlc_hw);
2194
2195         /* turn on PHY_PLL */
2196         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2197
2198         /* clear sw intstatus */
2199         wlc_hw->wlc->macintstatus = 0;
2200
2201         /* restore the clk setting */
2202         if (!fastclk)
2203                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2204 }
2205
2206 /* txfifo sizes needs to be modified(increased) since the newer cores
2207  * have more memory.
2208  */
2209 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2210 {
2211         d11regs_t *regs = wlc_hw->regs;
2212         u16 fifo_nu;
2213         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2214         u16 txfifo_def, txfifo_def1;
2215         u16 txfifo_cmd;
2216
2217         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2218         txfifo_startblk = TXFIFO_START_BLK;
2219
2220         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2221         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2222
2223                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2224                 txfifo_def = (txfifo_startblk & 0xff) |
2225                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2226                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2227                     ((((txfifo_endblk -
2228                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2229                 txfifo_cmd =
2230                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2231
2232                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2233                 W_REG(&regs->xmtfifodef, txfifo_def);
2234                 W_REG(&regs->xmtfifodef1, txfifo_def1);
2235
2236                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2237
2238                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2239         }
2240         /*
2241          * need to propagate to shm location to be in sync since ucode/hw won't
2242          * do this
2243          */
2244         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2245                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2246         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2247                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2248         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2249                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2250                             xmtfifo_sz[TX_AC_BK_FIFO]));
2251         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2252                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2253                             xmtfifo_sz[TX_BCMC_FIFO]));
2254 }
2255
2256 /* d11 core init
2257  *   reset PSM
2258  *   download ucode/PCM
2259  *   let ucode run to suspended
2260  *   download ucode inits
2261  *   config other core registers
2262  *   init dma
2263  */
2264 static void wlc_coreinit(struct wlc_info *wlc)
2265 {
2266         struct wlc_hw_info *wlc_hw = wlc->hw;
2267         d11regs_t *regs;
2268         u32 sflags;
2269         uint bcnint_us;
2270         uint i = 0;
2271         bool fifosz_fixup = false;
2272         int err = 0;
2273         u16 buf[NFIFO];
2274         struct wiphy *wiphy = wlc->wiphy;
2275
2276         regs = wlc_hw->regs;
2277
2278         WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2279
2280         /* reset PSM */
2281         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2282
2283         wlc_ucode_download(wlc_hw);
2284         /*
2285          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2286          */
2287         fifosz_fixup = true;
2288
2289         /* let the PSM run to the suspended state, set mode to BSS STA */
2290         W_REG(&regs->macintstatus, -1);
2291         wlc_bmac_mctrl(wlc_hw, ~0,
2292                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2293
2294         /* wait for ucode to self-suspend after auto-init */
2295         SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2296                  1000 * 1000);
2297         if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2298                 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2299                           "suspend!\n", wlc_hw->unit);
2300
2301         wlc_gpio_init(wlc);
2302
2303         sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2304
2305         if (D11REV_IS(wlc_hw->corerev, 23)) {
2306                 if (WLCISNPHY(wlc_hw->band))
2307                         wlc_write_inits(wlc_hw, d11n0initvals16);
2308                 else
2309                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2310                                   " %d\n", __func__, wlc_hw->unit,
2311                                   wlc_hw->corerev);
2312         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2313                 if (WLCISLCNPHY(wlc_hw->band)) {
2314                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2315                 } else {
2316                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2317                                   " %d\n", __func__, wlc_hw->unit,
2318                                   wlc_hw->corerev);
2319                 }
2320         } else {
2321                 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2322                           __func__, wlc_hw->unit, wlc_hw->corerev);
2323         }
2324
2325         /* For old ucode, txfifo sizes needs to be modified(increased) */
2326         if (fifosz_fixup == true) {
2327                 wlc_corerev_fifofixup(wlc_hw);
2328         }
2329
2330         /* check txfifo allocations match between ucode and driver */
2331         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2332         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2333                 i = TX_AC_BE_FIFO;
2334                 err = -1;
2335         }
2336         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2337         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2338                 i = TX_AC_VI_FIFO;
2339                 err = -1;
2340         }
2341         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2342         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2343         buf[TX_AC_BK_FIFO] &= 0xff;
2344         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2345                 i = TX_AC_BK_FIFO;
2346                 err = -1;
2347         }
2348         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2349                 i = TX_AC_VO_FIFO;
2350                 err = -1;
2351         }
2352         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2353         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2354         buf[TX_BCMC_FIFO] &= 0xff;
2355         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2356                 i = TX_BCMC_FIFO;
2357                 err = -1;
2358         }
2359         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2360                 i = TX_ATIM_FIFO;
2361                 err = -1;
2362         }
2363         if (err != 0) {
2364                 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2365                           " driver size %d index %d\n", buf[i],
2366                           wlc_hw->xmtfifo_sz[i], i);
2367         }
2368
2369         /* make sure we can still talk to the mac */
2370         WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
2371
2372         /* band-specific inits done by wlc_bsinit() */
2373
2374         /* Set up frame burst size and antenna swap threshold init values */
2375         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2376         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2377
2378         /* enable one rx interrupt per received frame */
2379         W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2380
2381         /* set the station mode (BSS STA) */
2382         wlc_bmac_mctrl(wlc_hw,
2383                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2384                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2385
2386         /* set up Beacon interval */
2387         bcnint_us = 0x8000 << 10;
2388         W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2389         W_REG(&regs->tsf_cfpstart, bcnint_us);
2390         W_REG(&regs->macintstatus, MI_GP1);
2391
2392         /* write interrupt mask */
2393         W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2394
2395         /* allow the MAC to control the PHY clock (dynamic on/off) */
2396         wlc_bmac_macphyclk_set(wlc_hw, ON);
2397
2398         /* program dynamic clock control fast powerup delay register */
2399         wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2400         W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2401
2402         /* tell the ucode the corerev */
2403         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2404
2405         /* tell the ucode MAC capabilities */
2406         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2407                            (u16) (wlc_hw->machwcap & 0xffff));
2408         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2409                            (u16) ((wlc_hw->
2410                                       machwcap >> 16) & 0xffff));
2411
2412         /* write retry limits to SCR, this done after PSM init */
2413         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2414         (void)R_REG(&regs->objaddr);
2415         W_REG(&regs->objdata, wlc_hw->SRL);
2416         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2417         (void)R_REG(&regs->objaddr);
2418         W_REG(&regs->objdata, wlc_hw->LRL);
2419
2420         /* write rate fallback retry limits */
2421         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2422         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2423
2424         AND_REG(&regs->ifs_ctl, 0x0FFF);
2425         W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2426
2427         /* dma initializations */
2428         wlc->txpend16165war = 0;
2429
2430         /* init the tx dma engines */
2431         for (i = 0; i < NFIFO; i++) {
2432                 if (wlc_hw->di[i])
2433                         dma_txinit(wlc_hw->di[i]);
2434         }
2435
2436         /* init the rx dma engine(s) and post receive buffers */
2437         dma_rxinit(wlc_hw->di[RX_FIFO]);
2438         dma_rxfill(wlc_hw->di[RX_FIFO]);
2439 }
2440
2441 /* This function is used for changing the tsf frac register
2442  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2443  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2444  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2445  * HTPHY Formula is 2^26/freq(MHz) e.g.
2446  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2447  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2448  * For spuron: 123MHz -> 2^26/123    = 545600.5
2449  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2450  * For spur off: 120MHz -> 2^26/120    = 559240.5
2451  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2452  */
2453
2454 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2455 {
2456         d11regs_t *regs;
2457         regs = wlc_hw->regs;
2458
2459         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2460             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2461                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2462                         W_REG(&regs->tsf_clk_frac_l, 0x2082);
2463                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2464                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2465                         W_REG(&regs->tsf_clk_frac_l, 0x5341);
2466                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2467                 } else {        /* 120Mhz */
2468                         W_REG(&regs->tsf_clk_frac_l, 0x8889);
2469                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2470                 }
2471         } else if (WLCISLCNPHY(wlc_hw->band)) {
2472                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2473                         W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2474                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2475                 } else {        /* 80Mhz */
2476                         W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2477                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2478                 }
2479         }
2480 }
2481
2482 /* Initialize GPIOs that are controlled by D11 core */
2483 static void wlc_gpio_init(struct wlc_info *wlc)
2484 {
2485         struct wlc_hw_info *wlc_hw = wlc->hw;
2486         d11regs_t *regs;
2487         u32 gc, gm;
2488
2489         regs = wlc_hw->regs;
2490
2491         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2492         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2493
2494         /*
2495          * Common GPIO setup:
2496          *      G0 = LED 0 = WLAN Activity
2497          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2498          *      G2 = LED 2 = WLAN 5 GHz Radio State
2499          *      G4 = radio disable input (HI enabled, LO disabled)
2500          */
2501
2502         gc = gm = 0;
2503
2504         /* Allocate GPIOs for mimo antenna diversity feature */
2505         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2506                 /* Enable antenna diversity, use 2x3 mode */
2507                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2508                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2509                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2510                              MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2511
2512                 /* init superswitch control */
2513                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2514
2515         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2516                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2517                 /*
2518                  * The board itself is powered by these GPIOs
2519                  * (when not sending pattern) so set them high
2520                  */
2521                 OR_REG(&regs->psm_gpio_oe,
2522                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2523                 OR_REG(&regs->psm_gpio_out,
2524                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2525
2526                 /* Enable antenna diversity, use 2x4 mode */
2527                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2528                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2529                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2530                              WLC_BAND_ALL);
2531
2532                 /* Configure the desired clock to be 4Mhz */
2533                 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2534                                    ANTSEL_CLKDIV_4MHZ);
2535         }
2536
2537         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2538         if (wlc_hw->boardflags & BFL_PACTRL)
2539                 gm |= gc |= BOARD_GPIO_PACTRL;
2540
2541         /* apply to gpiocontrol register */
2542         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2543 }
2544
2545 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2546 {
2547         struct wlc_info *wlc;
2548         wlc = wlc_hw->wlc;
2549
2550         if (wlc_hw->ucode_loaded)
2551                 return;
2552
2553         if (D11REV_IS(wlc_hw->corerev, 23)) {
2554                 if (WLCISNPHY(wlc_hw->band)) {
2555                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2556                                         bcm43xx_16_mimosz);
2557                         wlc_hw->ucode_loaded = true;
2558                 } else
2559                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2560                                   "corerev %d\n",
2561                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2562         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2563                 if (WLCISLCNPHY(wlc_hw->band)) {
2564                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2565                                         bcm43xx_24_lcnsz);
2566                         wlc_hw->ucode_loaded = true;
2567                 } else {
2568                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2569                                   "corerev %d\n",
2570                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2571                 }
2572         }
2573 }
2574
2575 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2576                               const uint nbytes) {
2577         d11regs_t *regs = wlc_hw->regs;
2578         uint i;
2579         uint count;
2580
2581         WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2582
2583         count = (nbytes / sizeof(u32));
2584
2585         W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2586         (void)R_REG(&regs->objaddr);
2587         for (i = 0; i < count; i++)
2588                 W_REG(&regs->objdata, ucode[i]);
2589 }
2590
2591 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2592                             const struct d11init *inits)
2593 {
2594         int i;
2595         volatile u8 *base;
2596
2597         WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2598
2599         base = (volatile u8 *)wlc_hw->regs;
2600
2601         for (i = 0; inits[i].addr != 0xffff; i++) {
2602                 if (inits[i].size == 2)
2603                         W_REG((u16 *)(base + inits[i].addr),
2604                               inits[i].value);
2605                 else if (inits[i].size == 4)
2606                         W_REG((u32 *)(base + inits[i].addr),
2607                               inits[i].value);
2608         }
2609 }
2610
2611 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2612 {
2613         u16 phyctl;
2614         u16 phytxant = wlc_hw->bmac_phytxant;
2615         u16 mask = PHY_TXC_ANT_MASK;
2616
2617         /* set the Probe Response frame phy control word */
2618         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2619         phyctl = (phyctl & ~mask) | phytxant;
2620         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2621
2622         /* set the Response (ACK/CTS) frame phy control word */
2623         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2624         phyctl = (phyctl & ~mask) | phytxant;
2625         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2626 }
2627
2628 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2629 {
2630         /* update sw state */
2631         wlc_hw->bmac_phytxant = phytxant;
2632
2633         /* push to ucode if up */
2634         if (!wlc_hw->up)
2635                 return;
2636         wlc_ucode_txant_set(wlc_hw);
2637
2638 }
2639
2640 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2641 {
2642         return (u16) wlc_hw->wlc->stf->txant;
2643 }
2644
2645 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2646 {
2647         wlc_hw->antsel_type = antsel_type;
2648
2649         /* Update the antsel type for phy module to use */
2650         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2651 }
2652
2653 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2654 {
2655         bool fatal = false;
2656         uint unit;
2657         uint intstatus, idx;
2658         d11regs_t *regs = wlc_hw->regs;
2659         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2660
2661         unit = wlc_hw->unit;
2662
2663         for (idx = 0; idx < NFIFO; idx++) {
2664                 /* read intstatus register and ignore any non-error bits */
2665                 intstatus =
2666                     R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2667                 if (!intstatus)
2668                         continue;
2669
2670                 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2671                          unit, idx, intstatus);
2672
2673                 if (intstatus & I_RO) {
2674                         wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2675                                   "overflow\n", unit, idx);
2676                         wlc_hw->wlc->pub->_cnt->rxoflo++;
2677                         fatal = true;
2678                 }
2679
2680                 if (intstatus & I_PC) {
2681                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2682                                  unit, idx);
2683                         wlc_hw->wlc->pub->_cnt->dmade++;
2684                         fatal = true;
2685                 }
2686
2687                 if (intstatus & I_PD) {
2688                         wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2689                                   idx);
2690                         wlc_hw->wlc->pub->_cnt->dmada++;
2691                         fatal = true;
2692                 }
2693
2694                 if (intstatus & I_DE) {
2695                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2696                                   "error\n", unit, idx);
2697                         wlc_hw->wlc->pub->_cnt->dmape++;
2698                         fatal = true;
2699                 }
2700
2701                 if (intstatus & I_RU) {
2702                         wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2703                                   "underflow\n", idx, unit);
2704                         wlc_hw->wlc->pub->_cnt->rxuflo[idx]++;
2705                 }
2706
2707                 if (intstatus & I_XU) {
2708                         wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2709                                   "underflow\n", idx, unit);
2710                         wlc_hw->wlc->pub->_cnt->txuflo++;
2711                         fatal = true;
2712                 }
2713
2714                 if (fatal) {
2715                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2716                         break;
2717                 } else
2718                         W_REG(&regs->intctrlregs[idx].intstatus,
2719                               intstatus);
2720         }
2721 }
2722
2723 void wlc_intrson(struct wlc_info *wlc)
2724 {
2725         struct wlc_hw_info *wlc_hw = wlc->hw;
2726         wlc->macintmask = wlc->defmacintmask;
2727         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2728 }
2729
2730 /* callback for siutils.c, which has only wlc handler, no wl
2731  * they both check up, not only because there is no need to off/restore d11 interrupt
2732  *  but also because per-port code may require sync with valid interrupt.
2733  */
2734
2735 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2736 {
2737         if (!wlc->hw->up)
2738                 return 0;
2739
2740         return wl_intrsoff(wlc->wl);
2741 }
2742
2743 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2744 {
2745         if (!wlc->hw->up)
2746                 return;
2747
2748         wl_intrsrestore(wlc->wl, macintmask);
2749 }
2750
2751 u32 wlc_intrsoff(struct wlc_info *wlc)
2752 {
2753         struct wlc_hw_info *wlc_hw = wlc->hw;
2754         u32 macintmask;
2755
2756         if (!wlc_hw->clk)
2757                 return 0;
2758
2759         macintmask = wlc->macintmask;   /* isr can still happen */
2760
2761         W_REG(&wlc_hw->regs->macintmask, 0);
2762         (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2763         udelay(1);              /* ensure int line is no longer driven */
2764         wlc->macintmask = 0;
2765
2766         /* return previous macintmask; resolve race between us and our isr */
2767         return wlc->macintstatus ? 0 : macintmask;
2768 }
2769
2770 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2771 {
2772         struct wlc_hw_info *wlc_hw = wlc->hw;
2773         if (!wlc_hw->clk)
2774                 return;
2775
2776         wlc->macintmask = macintmask;
2777         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2778 }
2779
2780 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2781 {
2782         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2783
2784         if (on) {
2785                 /* suspend tx fifos */
2786                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2787                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2788                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2789                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2790
2791                 /* zero the address match register so we do not send ACKs */
2792                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2793                                        null_ether_addr);
2794         } else {
2795                 /* resume tx fifos */
2796                 if (!wlc_hw->wlc->tx_suspended) {
2797                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2798                 }
2799                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2800                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2801                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2802
2803                 /* Restore address */
2804                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2805                                        wlc_hw->etheraddr);
2806         }
2807
2808         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2809
2810         if (on)
2811                 wlc_ucode_mute_override_set(wlc_hw);
2812         else
2813                 wlc_ucode_mute_override_clear(wlc_hw);
2814 }
2815
2816 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2817 {
2818         if (fifo >= NFIFO)
2819                 return -EINVAL;
2820
2821         *blocks = wlc_hw->xmtfifo_sz[fifo];
2822
2823         return 0;
2824 }
2825
2826 /* wlc_bmac_tx_fifo_suspended:
2827  * Check the MAC's tx suspend status for a tx fifo.
2828  *
2829  * When the MAC acknowledges a tx suspend, it indicates that no more
2830  * packets will be transmitted out the radio. This is independent of
2831  * DMA channel suspension---the DMA may have finished suspending, or may still
2832  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2833  * request.
2834  */
2835 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2836 {
2837         /* check that a suspend has been requested and is no longer pending */
2838
2839         /*
2840          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2841          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2842          * chnstatus register.
2843          * The tx fifo suspend completion is independent of the DMA suspend completion and
2844          *   may be acked before or after the DMA is suspended.
2845          */
2846         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2847             (R_REG(&wlc_hw->regs->chnstatus) &
2848              (1 << tx_fifo)) == 0)
2849                 return true;
2850
2851         return false;
2852 }
2853
2854 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2855 {
2856         u8 fifo = 1 << tx_fifo;
2857
2858         /* Two clients of this code, 11h Quiet period and scanning. */
2859
2860         /* only suspend if not already suspended */
2861         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2862                 return;
2863
2864         /* force the core awake only if not already */
2865         if (wlc_hw->suspended_fifos == 0)
2866                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2867
2868         wlc_hw->suspended_fifos |= fifo;
2869
2870         if (wlc_hw->di[tx_fifo]) {
2871                 /* Suspending AMPDU transmissions in the middle can cause underflow
2872                  * which may result in mismatch between ucode and driver
2873                  * so suspend the mac before suspending the FIFO
2874                  */
2875                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2876                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
2877
2878                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2879
2880                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2881                         wlc_enable_mac(wlc_hw->wlc);
2882         }
2883 }
2884
2885 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2886 {
2887         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2888          * here for PIO otherwise the watchdog will catch the inconsistency and fire
2889          */
2890         /* Two clients of this code, 11h Quiet period and scanning. */
2891         if (wlc_hw->di[tx_fifo])
2892                 dma_txresume(wlc_hw->di[tx_fifo]);
2893
2894         /* allow core to sleep again */
2895         if (wlc_hw->suspended_fifos == 0)
2896                 return;
2897         else {
2898                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2899                 if (wlc_hw->suspended_fifos == 0)
2900                         wlc_ucode_wake_override_clear(wlc_hw,
2901                                                       WLC_WAKE_OVERRIDE_TXFIFO);
2902         }
2903 }
2904
2905 /*
2906  * Read and clear macintmask and macintstatus and intstatus registers.
2907  * This routine should be called with interrupts off
2908  * Return:
2909  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
2910  *   0 if the interrupt is not for us, or we are in some special cases;
2911  *   device interrupt status bits otherwise.
2912  */
2913 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2914 {
2915         struct wlc_hw_info *wlc_hw = wlc->hw;
2916         d11regs_t *regs = wlc_hw->regs;
2917         u32 macintstatus;
2918
2919         /* macintstatus includes a DMA interrupt summary bit */
2920         macintstatus = R_REG(&regs->macintstatus);
2921
2922         WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
2923
2924         /* detect cardbus removed, in power down(suspend) and in reset */
2925         if (DEVICEREMOVED(wlc))
2926                 return -1;
2927
2928         /* DEVICEREMOVED succeeds even when the core is still resetting,
2929          * handle that case here.
2930          */
2931         if (macintstatus == 0xffffffff)
2932                 return 0;
2933
2934         /* defer unsolicited interrupts */
2935         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2936
2937         /* if not for us */
2938         if (macintstatus == 0)
2939                 return 0;
2940
2941         /* interrupts are already turned off for CFE build
2942          * Caution: For CFE Turning off the interrupts again has some undesired
2943          * consequences
2944          */
2945         /* turn off the interrupts */
2946         W_REG(&regs->macintmask, 0);
2947         (void)R_REG(&regs->macintmask); /* sync readback */
2948         wlc->macintmask = 0;
2949
2950         /* clear device interrupts */
2951         W_REG(&regs->macintstatus, macintstatus);
2952
2953         /* MI_DMAINT is indication of non-zero intstatus */
2954         if (macintstatus & MI_DMAINT) {
2955                 /*
2956                  * only fifo interrupt enabled is I_RI in
2957                  * RX_FIFO. If MI_DMAINT is set, assume it
2958                  * is set and clear the interrupt.
2959                  */
2960                 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
2961                       DEF_RXINTMASK);
2962         }
2963
2964         return macintstatus;
2965 }
2966
2967 /* Update wlc->macintstatus and wlc->intstatus[]. */
2968 /* Return true if they are updated successfully. false otherwise */
2969 bool wlc_intrsupd(struct wlc_info *wlc)
2970 {
2971         u32 macintstatus;
2972
2973         /* read and clear macintstatus and intstatus registers */
2974         macintstatus = wlc_intstatus(wlc, false);
2975
2976         /* device is removed */
2977         if (macintstatus == 0xffffffff)
2978                 return false;
2979
2980         /* update interrupt status in software */
2981         wlc->macintstatus |= macintstatus;
2982
2983         return true;
2984 }
2985
2986 /*
2987  * First-level interrupt processing.
2988  * Return true if this was our interrupt, false otherwise.
2989  * *wantdpc will be set to true if further wlc_dpc() processing is required,
2990  * false otherwise.
2991  */
2992 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2993 {
2994         struct wlc_hw_info *wlc_hw = wlc->hw;
2995         u32 macintstatus;
2996
2997         *wantdpc = false;
2998
2999         if (!wlc_hw->up || !wlc->macintmask)
3000                 return false;
3001
3002         /* read and clear macintstatus and intstatus registers */
3003         macintstatus = wlc_intstatus(wlc, true);
3004
3005         if (macintstatus == 0xffffffff)
3006                 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
3007                           " path\n");
3008
3009         /* it is not for us */
3010         if (macintstatus == 0)
3011                 return false;
3012
3013         *wantdpc = true;
3014
3015         /* save interrupt status bits */
3016         wlc->macintstatus = macintstatus;
3017
3018         return true;
3019
3020 }
3021
3022 static bool BCMFASTPATH
3023 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3024 {
3025         /* discard intermediate indications for ucode with one legitimate case:
3026          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3027          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3028          *   transmission count)
3029          */
3030         if (!(txs->status & TX_STATUS_AMPDU)
3031             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3032                 return false;
3033         }
3034
3035         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3036 }
3037
3038 /* process tx completion events in BMAC
3039  * Return true if more tx status need to be processed. false otherwise.
3040  */
3041 static bool BCMFASTPATH
3042 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3043 {
3044         bool morepending = false;
3045         struct wlc_info *wlc = wlc_hw->wlc;
3046         d11regs_t *regs;
3047         tx_status_t txstatus, *txs;
3048         u32 s1, s2;
3049         uint n = 0;
3050         /*
3051          * Param 'max_tx_num' indicates max. # tx status to process before
3052          * break out.
3053          */
3054         uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3055
3056         WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3057
3058         txs = &txstatus;
3059         regs = wlc_hw->regs;
3060         while (!(*fatal)
3061                && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
3062
3063                 if (s1 == 0xffffffff) {
3064                         wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
3065                                 wlc_hw->unit, __func__);
3066                         return morepending;
3067                 }
3068
3069                         s2 = R_REG(&regs->frmtxstatus2);
3070
3071                 txs->status = s1 & TXS_STATUS_MASK;
3072                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3073                 txs->sequence = s2 & TXS_SEQ_MASK;
3074                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3075                 txs->lasttxtime = 0;
3076
3077                 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3078
3079                 /* !give others some time to run! */
3080                 if (++n >= max_tx_num)
3081                         break;
3082         }
3083
3084         if (*fatal)
3085                 return 0;
3086
3087         if (n >= max_tx_num)
3088                 morepending = true;
3089
3090         if (!pktq_empty(&wlc->pkt_queue->q))
3091                 wlc_send_q(wlc);
3092
3093         return morepending;
3094 }
3095
3096 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3097 {
3098         struct wlc_hw_info *wlc_hw = wlc->hw;
3099         d11regs_t *regs = wlc_hw->regs;
3100         u32 mc, mi;
3101         struct wiphy *wiphy = wlc->wiphy;
3102
3103         WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3104                  wlc_hw->unit, wlc_hw->band->bandunit);
3105
3106         /*
3107          * Track overlapping suspend requests
3108          */
3109         wlc_hw->mac_suspend_depth++;
3110         if (wlc_hw->mac_suspend_depth > 1)
3111                 return;
3112
3113         /* force the core awake */
3114         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3115
3116         mc = R_REG(&regs->maccontrol);
3117
3118         if (mc == 0xffffffff) {
3119                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3120                           __func__);
3121                 wl_down(wlc->wl);
3122                 return;
3123         }
3124         WARN_ON(mc & MCTL_PSM_JMP_0);
3125         WARN_ON(!(mc & MCTL_PSM_RUN));
3126         WARN_ON(!(mc & MCTL_EN_MAC));
3127
3128         mi = R_REG(&regs->macintstatus);
3129         if (mi == 0xffffffff) {
3130                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3131                           __func__);
3132                 wl_down(wlc->wl);
3133                 return;
3134         }
3135         WARN_ON(mi & MI_MACSSPNDD);
3136
3137         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3138
3139         SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3140                  WLC_MAX_MAC_SUSPEND);
3141
3142         if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3143                 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3144                           " and MI_MACSSPNDD is still not on.\n",
3145                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3146                 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3147                           "psm_brc 0x%04x\n", wlc_hw->unit,
3148                           R_REG(&regs->psmdebug),
3149                           R_REG(&regs->phydebug),
3150                           R_REG(&regs->psm_brc));
3151         }
3152
3153         mc = R_REG(&regs->maccontrol);
3154         if (mc == 0xffffffff) {
3155                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3156                           __func__);
3157                 wl_down(wlc->wl);
3158                 return;
3159         }
3160         WARN_ON(mc & MCTL_PSM_JMP_0);
3161         WARN_ON(!(mc & MCTL_PSM_RUN));
3162         WARN_ON(mc & MCTL_EN_MAC);
3163 }
3164
3165 void wlc_enable_mac(struct wlc_info *wlc)
3166 {
3167         struct wlc_hw_info *wlc_hw = wlc->hw;
3168         d11regs_t *regs = wlc_hw->regs;
3169         u32 mc, mi;
3170
3171         WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3172                  wlc_hw->unit, wlc->band->bandunit);
3173
3174         /*
3175          * Track overlapping suspend requests
3176          */
3177         wlc_hw->mac_suspend_depth--;
3178         if (wlc_hw->mac_suspend_depth > 0)
3179                 return;
3180
3181         mc = R_REG(&regs->maccontrol);
3182         WARN_ON(mc & MCTL_PSM_JMP_0);
3183         WARN_ON(mc & MCTL_EN_MAC);
3184         WARN_ON(!(mc & MCTL_PSM_RUN));
3185
3186         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3187         W_REG(&regs->macintstatus, MI_MACSSPNDD);
3188
3189         mc = R_REG(&regs->maccontrol);
3190         WARN_ON(mc & MCTL_PSM_JMP_0);
3191         WARN_ON(!(mc & MCTL_EN_MAC));
3192         WARN_ON(!(mc & MCTL_PSM_RUN));
3193
3194         mi = R_REG(&regs->macintstatus);
3195         WARN_ON(mi & MI_MACSSPNDD);
3196
3197         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3198 }
3199
3200 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3201 {
3202         u8 rate;
3203         u8 rates[8] = {
3204                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3205                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3206         };
3207         u16 entry_ptr;
3208         u16 pctl1;
3209         uint i;
3210
3211         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3212                 return;
3213
3214         /* walk the phy rate table and update the entries */
3215         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3216                 rate = rates[i];
3217
3218                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3219
3220                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3221                 pctl1 =
3222                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3223
3224                 /* modify the value */
3225                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3226                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3227
3228                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3229                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3230                                    pctl1);
3231         }
3232 }
3233
3234 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3235 {
3236         uint i;
3237         u8 plcp_rate = 0;
3238         struct plcp_signal_rate_lookup {
3239                 u8 rate;
3240                 u8 signal_rate;
3241         };
3242         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3243         const struct plcp_signal_rate_lookup rate_lookup[] = {
3244                 {WLC_RATE_6M, 0xB},
3245                 {WLC_RATE_9M, 0xF},
3246                 {WLC_RATE_12M, 0xA},
3247                 {WLC_RATE_18M, 0xE},
3248                 {WLC_RATE_24M, 0x9},
3249                 {WLC_RATE_36M, 0xD},
3250                 {WLC_RATE_48M, 0x8},
3251                 {WLC_RATE_54M, 0xC}
3252         };
3253
3254         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3255                 if (rate == rate_lookup[i].rate) {
3256                         plcp_rate = rate_lookup[i].signal_rate;
3257                         break;
3258                 }
3259         }
3260
3261         /* Find the SHM pointer to the rate table entry by looking in the
3262          * Direct-map Table
3263          */
3264         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3265 }
3266
3267 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3268 {
3269         wlc_hw->hw_stf_ss_opmode = stf_mode;
3270
3271         if (wlc_hw->clk)
3272                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3273 }
3274
3275 void BCMFASTPATH
3276 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3277                   u32 *tsf_h_ptr)
3278 {
3279         d11regs_t *regs = wlc_hw->regs;
3280
3281         /* read the tsf timer low, then high to get an atomic read */
3282         *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3283         *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3284
3285         return;
3286 }
3287
3288 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3289 {
3290         d11regs_t *regs;
3291         u32 w, val;
3292         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3293
3294         WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3295
3296         regs = wlc_hw->regs;
3297
3298         /* Validate dchip register access */
3299
3300         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3301         (void)R_REG(&regs->objaddr);
3302         w = R_REG(&regs->objdata);
3303
3304         /* Can we write and read back a 32bit register? */
3305         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3306         (void)R_REG(&regs->objaddr);
3307         W_REG(&regs->objdata, (u32) 0xaa5555aa);
3308
3309         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3310         (void)R_REG(&regs->objaddr);
3311         val = R_REG(&regs->objdata);
3312         if (val != (u32) 0xaa5555aa) {
3313                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3314                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
3315                 return false;
3316         }
3317
3318         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3319         (void)R_REG(&regs->objaddr);
3320         W_REG(&regs->objdata, (u32) 0x55aaaa55);
3321
3322         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3323         (void)R_REG(&regs->objaddr);
3324         val = R_REG(&regs->objdata);
3325         if (val != (u32) 0x55aaaa55) {
3326                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3327                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
3328                 return false;
3329         }
3330
3331         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3332         (void)R_REG(&regs->objaddr);
3333         W_REG(&regs->objdata, w);
3334
3335         /* clear CFPStart */
3336         W_REG(&regs->tsf_cfpstart, 0);
3337
3338         w = R_REG(&regs->maccontrol);
3339         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3340             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3341                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3342                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3343                           (MCTL_IHR_EN | MCTL_WAKE),
3344                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3345                 return false;
3346         }
3347
3348         return true;
3349 }
3350
3351 #define PHYPLL_WAIT_US  100000
3352
3353 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3354 {
3355         d11regs_t *regs;
3356         u32 tmp;
3357
3358         WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3359
3360         tmp = 0;
3361         regs = wlc_hw->regs;
3362
3363         if (on) {
3364                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3365                         OR_REG(&regs->clk_ctl_st,
3366                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3367                                 CCS_ERSRC_REQ_PHYPLL));
3368                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3369                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3370                                  PHYPLL_WAIT_US);
3371
3372                         tmp = R_REG(&regs->clk_ctl_st);
3373                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3374                             (CCS_ERSRC_AVAIL_HT)) {
3375                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3376                                           " PLL failed\n", __func__);
3377                         }
3378                 } else {
3379                         OR_REG(&regs->clk_ctl_st,
3380                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3381                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3382                                   (CCS_ERSRC_AVAIL_D11PLL |
3383                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3384                                  (CCS_ERSRC_AVAIL_D11PLL |
3385                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3386
3387                         tmp = R_REG(&regs->clk_ctl_st);
3388                         if ((tmp &
3389                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3390                             !=
3391                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3392                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3393                                           "PHY PLL failed\n", __func__);
3394                         }
3395                 }
3396         } else {
3397                 /* Since the PLL may be shared, other cores can still be requesting it;
3398                  * so we'll deassert the request but not wait for status to comply.
3399                  */
3400                 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3401                 tmp = R_REG(&regs->clk_ctl_st);
3402         }
3403 }
3404
3405 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3406 {
3407         bool dev_gone;
3408
3409         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3410
3411         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3412
3413         if (dev_gone)
3414                 return;
3415
3416         if (wlc_hw->noreset)
3417                 return;
3418
3419         /* radio off */
3420         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3421
3422         /* turn off analog core */
3423         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3424
3425         /* turn off PHYPLL to save power */
3426         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3427
3428         /* No need to set wlc->pub->radio_active = OFF
3429          * because this function needs down capability and
3430          * radio_active is designed for BCMNODOWN.
3431          */
3432
3433         /* remove gpio controls */
3434         if (wlc_hw->ucode_dbgsel)
3435                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3436
3437         wlc_hw->clk = false;
3438         ai_core_disable(wlc_hw->sih, 0);
3439         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3440 }
3441
3442 /* power both the pll and external oscillator on/off */
3443 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3444 {
3445         WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3446
3447         /* dont power down if plldown is false or we must poll hw radio disable */
3448         if (!want && wlc_hw->pllreq)
3449                 return;
3450
3451         if (wlc_hw->sih)
3452                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3453
3454         wlc_hw->sbclk = want;
3455         if (!wlc_hw->sbclk) {
3456                 wlc_hw->clk = false;
3457                 if (wlc_hw->band && wlc_hw->band->pi)
3458                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3459         }
3460 }
3461
3462 static void wlc_flushqueues(struct wlc_info *wlc)
3463 {
3464         struct wlc_hw_info *wlc_hw = wlc->hw;
3465         uint i;
3466
3467         wlc->txpend16165war = 0;
3468
3469         /* free any posted tx packets */
3470         for (i = 0; i < NFIFO; i++)
3471                 if (wlc_hw->di[i]) {
3472                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3473                         TXPKTPENDCLR(wlc, i);
3474                         WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3475                                  i);
3476                 }
3477
3478         /* free any posted rx packets */
3479         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3480 }
3481
3482 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3483 {
3484         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3485 }
3486
3487 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3488 {
3489         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3490 }
3491
3492 /* Set a range of shared memory to a value.
3493  * SHM 'offset' needs to be an even address and
3494  * Buffer length 'len' must be an even number of bytes
3495  */
3496 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3497 {
3498         int i;
3499
3500         if (len <= 0 || (offset & 1) || (len & 1))
3501                 return;
3502
3503         for (i = 0; i < len; i += 2) {
3504                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3505         }
3506 }
3507
3508 static u16
3509 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3510 {
3511         d11regs_t *regs = wlc_hw->regs;
3512         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3513         volatile u16 *objdata_hi = objdata_lo + 1;
3514         u16 v;
3515
3516         W_REG(&regs->objaddr, sel | (offset >> 2));
3517         (void)R_REG(&regs->objaddr);
3518         if (offset & 2) {
3519                 v = R_REG(objdata_hi);
3520         } else {
3521                 v = R_REG(objdata_lo);
3522         }
3523
3524         return v;
3525 }
3526
3527 static void
3528 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3529 {
3530         d11regs_t *regs = wlc_hw->regs;
3531         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3532         volatile u16 *objdata_hi = objdata_lo + 1;
3533
3534         W_REG(&regs->objaddr, sel | (offset >> 2));
3535         (void)R_REG(&regs->objaddr);
3536         if (offset & 2) {
3537                 W_REG(objdata_hi, v);
3538         } else {
3539                 W_REG(objdata_lo, v);
3540         }
3541 }
3542
3543 /* Copy a buffer to shared memory of specified type .
3544  * SHM 'offset' needs to be an even address and
3545  * Buffer length 'len' must be an even number of bytes
3546  * 'sel' selects the type of memory
3547  */
3548 void
3549 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3550                        int len, u32 sel)
3551 {
3552         u16 v;
3553         const u8 *p = (const u8 *)buf;
3554         int i;
3555
3556         if (len <= 0 || (offset & 1) || (len & 1))
3557                 return;
3558
3559         for (i = 0; i < len; i += 2) {
3560                 v = p[i] | (p[i + 1] << 8);
3561                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3562         }
3563 }
3564
3565 /* Copy a piece of shared memory of specified type to a buffer .
3566  * SHM 'offset' needs to be an even address and
3567  * Buffer length 'len' must be an even number of bytes
3568  * 'sel' selects the type of memory
3569  */
3570 void
3571 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3572                          int len, u32 sel)
3573 {
3574         u16 v;
3575         u8 *p = (u8 *) buf;
3576         int i;
3577
3578         if (len <= 0 || (offset & 1) || (len & 1))
3579                 return;
3580
3581         for (i = 0; i < len; i += 2) {
3582                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3583                 p[i] = v & 0xFF;
3584                 p[i + 1] = (v >> 8) & 0xFF;
3585         }
3586 }
3587
3588 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3589 {
3590         WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3591                  wlc_hw->vars_size);
3592
3593         *buf = wlc_hw->vars;
3594         *len = wlc_hw->vars_size;
3595 }
3596
3597 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3598 {
3599         wlc_hw->SRL = SRL;
3600         wlc_hw->LRL = LRL;
3601
3602         /* write retry limit to SCR, shouldn't need to suspend */
3603         if (wlc_hw->up) {
3604                 W_REG(&wlc_hw->regs->objaddr,
3605                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3606                 (void)R_REG(&wlc_hw->regs->objaddr);
3607                 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3608                 W_REG(&wlc_hw->regs->objaddr,
3609                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3610                 (void)R_REG(&wlc_hw->regs->objaddr);
3611                 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3612         }
3613 }
3614
3615 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3616 {
3617         wlc_hw->noreset = noreset_flag;
3618 }
3619
3620 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3621 {
3622         if (set) {
3623                 if (mboolisset(wlc_hw->pllreq, req_bit))
3624                         return;
3625
3626                 mboolset(wlc_hw->pllreq, req_bit);
3627
3628                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3629                         if (!wlc_hw->sbclk) {
3630                                 wlc_bmac_xtal(wlc_hw, ON);
3631                         }
3632                 }
3633         } else {
3634                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3635                         return;
3636
3637                 mboolclr(wlc_hw->pllreq, req_bit);
3638
3639                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3640                         if (wlc_hw->sbclk) {
3641                                 wlc_bmac_xtal(wlc_hw, OFF);
3642                         }
3643                 }
3644         }
3645
3646         return;
3647 }
3648
3649 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3650 {
3651         u16 table_ptr;
3652         u8 phy_rate, index;
3653
3654         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3655         /* XXX4321 fixup needed ? */
3656         if (IS_OFDM(rate))
3657                 table_ptr = M_RT_DIRMAP_A;
3658         else
3659                 table_ptr = M_RT_DIRMAP_B;
3660
3661         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3662          * the index into the rate table.
3663          */
3664         phy_rate = rate_info[rate] & WLC_RATE_MASK;
3665         index = phy_rate & 0xf;
3666
3667         /* Find the SHM pointer to the rate table entry by looking in the
3668          * Direct-map Table
3669          */
3670         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3671 }
3672
3673 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3674 {
3675         wlc_hw->antsel_avail = antsel_avail;
3676 }