Pileus Git - ~andy/linux/blob - drivers/staging/brcm80211/brcmsmac/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23
  24 #include <proto/802.11.h>
  25 #include <osl.h>
  26 #include <bcmdefs.h>
  27 #include <bcmdevs.h>
  28 #include <bcmwifi.h>
  29 #include <siutils.h>
  30 #include <bcmsrom.h>
  31 #include <bcmotp.h>
  32 #include <bcmutils.h>
  33 #include <wlioctl.h>
  34 #include <sbconfig.h>
  35 #include <sbchipc.h>
  36 #include <pcicfg.h>
  37 #include <sbhnddma.h>
  38 #include <hnddma.h>
  39 #include <hndpmu.h>
  40
  41 #include "wlc_types.h"
  42 #include "d11.h"
  43 #include "wlc_cfg.h"
  44 #include "wlc_rate.h"
  45 #include "wlc_scb.h"
  46 #include "wlc_pub.h"
  47 #include "wlc_key.h"
  48 #include "wlc_phy_shim.h"
  49 #include "phy/wlc_phy_hal.h"
  50 #include "wlc_channel.h"
  51 #include "wlc_bsscfg.h"
  52 #include "wlc_main.h"
  53 #include "wl_export.h"
  54 #include "wl_ucode.h"
  55 #include "wlc_antsel.h"
  56 #include "pcie_core.h"
  57 #include "wlc_alloc.h"
  58 #include "wl_dbg.h"
  59 #include "wlc_bmac.h"
  60
  61 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  62
  63 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  64 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  65 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  66 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  67
  68 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  69
  70 #ifndef BMAC_DUP_TO_REMOVE
  71 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  72
  73 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  74
  75 #endif                          /* BMAC_DUP_TO_REMOVE */
  76
  77 #define DMAREG(wlc_hw, direction, fifonum) \
  78         ((direction == DMA_TX) ? \
  79                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
  80                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
  81
  82 /*
  83  * The following table lists the buffer memory allocated to xmt fifos in HW.
  84  * the size is in units of 256bytes(one block), total size is HW dependent
  85  * ucode has default fifo partition, sw can overwrite if necessary
  86  *
  87  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  88  * the twiki is updated before making changes.
  89  */
  90
  91 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
  92
  93 static u16 xmtfifo_sz[][NFIFO] = {
  94         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  95         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  96         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  97         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  98         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  99 };
 100
 101 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
 102 static void wlc_coreinit(struct wlc_info *wlc);
 103
 104 /* used by wlc_wakeucode_init() */
 105 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
 106                             const struct d11init *inits);
 107 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 108                             const uint nbytes);
 109 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 110 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 111
 112 /* used by wlc_dpc() */
 113 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 114                                 u32 s2);
 115 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 116 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 117
 118 /* used by wlc_down() */
 119 static void wlc_flushqueues(struct wlc_info *wlc);
 120
 121 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 122 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 123 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 124 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
 125                                        uint tx_fifo);
 126 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 127 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 128
 129 /* Low Level Prototypes */
 130 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
 131 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
 132 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
 133 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 134                                    u32 sel);
 135 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 136                                   u16 v, u32 sel);
 137 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
 138 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 139 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 140 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 141 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 142 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 143 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
 144 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 145 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 146 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 147 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
 148 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 149 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 150 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 151 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 152 static void wlc_gpio_init(struct wlc_info *wlc);
 153 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 154                                       int len);
 155 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 156                                       int len);
 157 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 158 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 159 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 160                              chanspec_t chanspec);
 161 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 162                                         bool shortslot);
 163 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 164 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 165                                              u8 rate);
 166
 167 /* === Low Level functions === */
 168
 169 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 170 {
 171         wlc_hw->shortslot = shortslot;
 172
 173         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 174                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 175                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 176                 wlc_enable_mac(wlc_hw->wlc);
 177         }
 178 }
 179
 180 /*
 181  * Update the slot timing for standard 11b/g (20us slots)
 182  * or shortslot 11g (9us slots)
 183  * The PSM needs to be suspended for this call.
 184  */
 185 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 186                                         bool shortslot)
 187 {
 188         d11regs_t *regs;
 189
 190         regs = wlc_hw->regs;
 191
 192         if (shortslot) {
 193                 /* 11g short slot: 11a timing */
 194                 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
 195                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 196         } else {
 197                 /* 11g long slot: 11b timing */
 198                 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
 199                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 200         }
 201 }
 202
 203 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 204 {
 205         /* init microcode host flags */
 206         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 207
 208         /* do band-specific ucode IHR, SHM, and SCR inits */
 209         if (D11REV_IS(wlc_hw->corerev, 23)) {
 210                 if (WLCISNPHY(wlc_hw->band)) {
 211                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 212                 } else {
 213                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 214                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 215                 }
 216         } else {
 217                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 218                         if (WLCISLCNPHY(wlc_hw->band)) {
 219                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 220                         } else
 221                                 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 222                                          __func__, wlc_hw->unit,
 223                                          wlc_hw->corerev);
 224                 } else {
 225                         WL_ERROR("%s: wl%d: unsupported corerev %d\n",
 226                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 227                 }
 228         }
 229 }
 230
 231 /* switch to new band but leave it inactive */
 232 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 233 {
 234         struct wlc_hw_info *wlc_hw = wlc->hw;
 235         u32 macintmask;
 236
 237         WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
 238
 239         ASSERT(bandunit != wlc_hw->band->bandunit);
 240         ASSERT(si_iscoreup(wlc_hw->sih));
 241         ASSERT((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 242                0);
 243
 244         /* disable interrupts */
 245         macintmask = wl_intrsoff(wlc->wl);
 246
 247         /* radio off */
 248         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 249
 250         ASSERT(wlc_hw->clk);
 251
 252         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 253
 254         wlc_setxband(wlc_hw, bandunit);
 255
 256         return macintmask;
 257 }
 258
 259 /* Process received frames */
 260 /*
 261  * Return true if more frames need to be processed. false otherwise.
 262  * Param 'bound' indicates max. # frames to process before break out.
 263  */
 264 static bool BCMFASTPATH
 265 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 266 {
 267         struct sk_buff *p;
 268         struct sk_buff *head = NULL;
 269         struct sk_buff *tail = NULL;
 270         uint n = 0;
 271         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 272         u32 tsf_h, tsf_l;
 273         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 274
 275         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
 276         /* gather received frames */
 277         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 278
 279                 if (!tail)
 280                         head = tail = p;
 281                 else {
 282                         tail->prev = p;
 283                         tail = p;
 284                 }
 285
 286                 /* !give others some time to run! */
 287                 if (++n >= bound_limit)
 288                         break;
 289         }
 290
 291         /* get the TSF REG reading */
 292         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 293
 294         /* post more rbufs */
 295         dma_rxfill(wlc_hw->di[fifo]);
 296
 297         /* process each frame */
 298         while ((p = head) != NULL) {
 299                 head = head->prev;
 300                 p->prev = NULL;
 301
 302                 /* record the tsf_l in wlc_rxd11hdr */
 303                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 304                 wlc_rxhdr->tsf_l = cpu_to_le32(tsf_l);
 305
 306                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 307                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 308
 309                 wlc_recv(wlc_hw->wlc, p);
 310         }
 311
 312         return n >= bound_limit;
 313 }
 314
 315 /* second-level interrupt processing
 316  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 317  *   Param 'bounded' indicates if applicable loops should be bounded.
 318  */
 319 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
 320 {
 321         u32 macintstatus;
 322         struct wlc_hw_info *wlc_hw = wlc->hw;
 323         d11regs_t *regs = wlc_hw->regs;
 324         bool fatal = false;
 325
 326         if (DEVICEREMOVED(wlc)) {
 327                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
 328                 wl_down(wlc->wl);
 329                 return false;
 330         }
 331
 332         /* grab and clear the saved software intstatus bits */
 333         macintstatus = wlc->macintstatus;
 334         wlc->macintstatus = 0;
 335
 336         WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
 337                  wlc_hw->unit, macintstatus);
 338
 339         if (macintstatus & MI_PRQ) {
 340                 /* Process probe request FIFO */
 341                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 342         }
 343
 344         /* BCN template is available */
 345         /* ZZZ: Use AP_ACTIVE ? */
 346         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 347             && (macintstatus & MI_BCNTPL)) {
 348                 wlc_update_beacon(wlc);
 349         }
 350
 351         /* PMQ entry addition */
 352         if (macintstatus & MI_PMQ) {
 353         }
 354
 355         /* tx status */
 356         if (macintstatus & MI_TFS) {
 357                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 358                         wlc->macintstatus |= MI_TFS;
 359                 if (fatal) {
 360                         WL_ERROR("MI_TFS: fatal\n");
 361                         goto fatal;
 362                 }
 363         }
 364
 365         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 366                 wlc_tbtt(wlc, regs);
 367
 368         /* ATIM window end */
 369         if (macintstatus & MI_ATIMWINEND) {
 370                 WL_TRACE("wlc_isr: end of ATIM window\n");
 371
 372                 OR_REG(&regs->maccommand, wlc->qvalid);
 373                 wlc->qvalid = 0;
 374         }
 375
 376         /* phy tx error */
 377         if (macintstatus & MI_PHYTXERR) {
 378                 wlc->pub->_cnt->txphyerr++;
 379         }
 380
 381         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 382         if (macintstatus & MI_DMAINT) {
 383                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 384                         wlc->macintstatus |= MI_DMAINT;
 385                 }
 386         }
 387
 388         /* TX FIFO suspend/flush completion */
 389         if (macintstatus & MI_TXSTOP) {
 390                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 391                         /*      WL_ERROR("dpc: fifo_suspend_comlete\n"); */
 392                 }
 393         }
 394
 395         /* noise sample collected */
 396         if (macintstatus & MI_BG_NOISE) {
 397                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 398         }
 399
 400         if (macintstatus & MI_GP0) {
 401                 WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
 402                          wlc_hw->unit, wlc_hw->now);
 403
 404                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 405                                         __func__, wlc_hw->sih->chip,
 406                                         wlc_hw->sih->chiprev);
 407
 408                 wlc->pub->_cnt->psmwds++;
 409
 410                 /* big hammer */
 411                 wl_init(wlc->wl);
 412         }
 413
 414         /* gptimer timeout */
 415         if (macintstatus & MI_TO) {
 416                 W_REG(&regs->gptimer, 0);
 417         }
 418
 419         if (macintstatus & MI_RFDISABLE) {
 420                 WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
 421
 422                 wlc->pub->_cnt->rfdisable++;
 423                 wl_rfkill_set_hw_state(wlc->wl);
 424         }
 425
 426         /* send any enq'd tx packets. Just makes sure to jump start tx */
 427         if (!pktq_empty(&wlc->active_queue->q))
 428                 wlc_send_q(wlc, wlc->active_queue);
 429
 430         ASSERT(wlc_ps_check(wlc));
 431
 432         /* make sure the bound indication and the implementation are in sync */
 433         ASSERT(bounded == true || wlc->macintstatus == 0);
 434
 435         /* it isn't done and needs to be resched if macintstatus is non-zero */
 436         return wlc->macintstatus != 0;
 437
 438  fatal:
 439         wl_init(wlc->wl);
 440         return wlc->macintstatus != 0;
 441 }
 442
 443 /* common low-level watchdog code */
 444 void wlc_bmac_watchdog(void *arg)
 445 {
 446         struct wlc_info *wlc = (struct wlc_info *) arg;
 447         struct wlc_hw_info *wlc_hw = wlc->hw;
 448
 449         WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
 450
 451         if (!wlc_hw->up)
 452                 return;
 453
 454         /* increment second count */
 455         wlc_hw->now++;
 456
 457         /* Check for FIFO error interrupts */
 458         wlc_bmac_fifoerrors(wlc_hw);
 459
 460         /* make sure RX dma has buffers */
 461         dma_rxfill(wlc->hw->di[RX_FIFO]);
 462
 463         wlc_phy_watchdog(wlc_hw->band->pi);
 464 }
 465
 466 void
 467 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 468                       bool mute, struct txpwr_limits *txpwr)
 469 {
 470         uint bandunit;
 471
 472         WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
 473                  wlc_hw->unit, chanspec);
 474
 475         wlc_hw->chanspec = chanspec;
 476
 477         /* Switch bands if necessary */
 478         if (NBANDS_HW(wlc_hw) > 1) {
 479                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 480                 if (wlc_hw->band->bandunit != bandunit) {
 481                         /* wlc_bmac_setband disables other bandunit,
 482                          *  use light band switch if not up yet
 483                          */
 484                         if (wlc_hw->up) {
 485                                 wlc_phy_chanspec_radio_set(wlc_hw->
 486                                                            bandstate[bandunit]->
 487                                                            pi, chanspec);
 488                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 489                         } else {
 490                                 wlc_setxband(wlc_hw, bandunit);
 491                         }
 492                 }
 493         }
 494
 495         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 496
 497         if (!wlc_hw->up) {
 498                 if (wlc_hw->clk)
 499                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 500                                                   chanspec);
 501                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 502         } else {
 503                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 504                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 505
 506                 /* Update muting of the channel */
 507                 wlc_bmac_mute(wlc_hw, mute, 0);
 508         }
 509 }
 510
 511 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 512 {
 513         state->machwcap = wlc_hw->machwcap;
 514
 515         return 0;
 516 }
 517
 518 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 519 {
 520         uint i;
 521         char name[8];
 522         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 523         u16 pio_mhf2 = 0;
 524         struct wlc_hw_info *wlc_hw = wlc->hw;
 525         uint unit = wlc_hw->unit;
 526         wlc_tunables_t *tune = wlc->pub->tunables;
 527
 528         /* name and offsets for dma_attach */
 529         snprintf(name, sizeof(name), "wl%d", unit);
 530
 531         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 532                 uint addrwidth;
 533                 int dma_attach_err = 0;
 534                 struct osl_info *osh = wlc->osh;
 535
 536                 /* Find out the DMA addressing capability and let OS know
 537                  * All the channels within one DMA core have 'common-minimum' same
 538                  * capability
 539                  */
 540                 addrwidth =
 541                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 542
 543                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 544                         WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
 545                                  unit);
 546                         return false;
 547                 }
 548
 549                 /*
 550                  * FIFO 0
 551                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 552                  * RX: RX_FIFO (RX data packets)
 553                  */
 554                 ASSERT(TX_AC_BK_FIFO == 0);
 555                 ASSERT(RX_FIFO == 0);
 556                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 557                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 558                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 559                                            (wme ? tune->ntxd : 0), tune->nrxd,
 560                                            tune->rxbufsz, -1, tune->nrxbufpost,
 561                                            WL_HWRXOFF, &wl_msg_level);
 562                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 563
 564                 /*
 565                  * FIFO 1
 566                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 567                  *   (legacy) TX_DATA_FIFO (TX data packets)
 568                  * RX: UNUSED
 569                  */
 570                 ASSERT(TX_AC_BE_FIFO == 1);
 571                 ASSERT(TX_DATA_FIFO == 1);
 572                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 573                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 574                                            tune->ntxd, 0, 0, -1, 0, 0,
 575                                            &wl_msg_level);
 576                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 577
 578                 /*
 579                  * FIFO 2
 580                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 581                  * RX: UNUSED
 582                  */
 583                 ASSERT(TX_AC_VI_FIFO == 2);
 584                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 585                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 586                                            tune->ntxd, 0, 0, -1, 0, 0,
 587                                            &wl_msg_level);
 588                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 589                 /*
 590                  * FIFO 3
 591                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 592                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 593                  */
 594                 ASSERT(TX_AC_VO_FIFO == 3);
 595                 ASSERT(TX_CTL_FIFO == 3);
 596                 wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 597                                            DMAREG(wlc_hw, DMA_TX, 3),
 598                                            NULL, tune->ntxd, 0, 0, -1,
 599                                            0, 0, &wl_msg_level);
 600                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 601 /* Cleaner to leave this as if with AP defined */
 602
 603                 if (dma_attach_err) {
 604                         WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
 605                         return false;
 606                 }
 607
 608                 /* get pointer to dma engine tx flow control variable */
 609                 for (i = 0; i < NFIFO; i++)
 610                         if (wlc_hw->di[i])
 611                                 wlc_hw->txavail[i] =
 612                                     (uint *) dma_getvar(wlc_hw->di[i],
 613                                                         "&txavail");
 614         }
 615
 616         /* initial ucode host flags */
 617         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 618
 619         return true;
 620 }
 621
 622 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 623 {
 624         uint j;
 625
 626         for (j = 0; j < NFIFO; j++) {
 627                 if (wlc_hw->di[j]) {
 628                         dma_detach(wlc_hw->di[j]);
 629                         wlc_hw->di[j] = NULL;
 630                 }
 631         }
 632 }
 633
 634 /* low level attach
 635  *    run backplane attach, init nvram
 636  *    run phy attach
 637  *    initialize software state for each core and band
 638  *    put the whole chip in reset(driver down state), no clock
 639  */
 640 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 641                     bool piomode, void *regsva, uint bustype, void *btparam)
 642 {
 643         struct wlc_hw_info *wlc_hw;
 644         d11regs_t *regs;
 645         char *macaddr = NULL;
 646         char *vars;
 647         uint err = 0;
 648         uint j;
 649         bool wme = false;
 650         shared_phy_params_t sha_params;
 651
 652         WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
 653                  unit, vendor, device);
 654
 655         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 656
 657         wme = true;
 658
 659         wlc_hw = wlc->hw;
 660         wlc_hw->wlc = wlc;
 661         wlc_hw->unit = unit;
 662         wlc_hw->band = wlc_hw->bandstate[0];
 663         wlc_hw->_piomode = piomode;
 664
 665         /* populate struct wlc_hw_info with default values  */
 666         wlc_bmac_info_init(wlc_hw);
 667
 668         /*
 669          * Do the hardware portion of the attach.
 670          * Also initialize software state that depends on the particular hardware
 671          * we are running.
 672          */
 673         wlc_hw->sih = si_attach((uint) device, regsva, bustype, btparam,
 674                                 &wlc_hw->vars, &wlc_hw->vars_size);
 675         if (wlc_hw->sih == NULL) {
 676                 WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
 677                 err = 11;
 678                 goto fail;
 679         }
 680         vars = wlc_hw->vars;
 681
 682         /*
 683          * Get vendid/devid nvram overwrites, which could be different
 684          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 685          * SDIO_BUS, and SROMless devices on PCI_BUS.
 686          */
 687 #ifdef BCMBUSTYPE
 688         bustype = BCMBUSTYPE;
 689 #endif
 690         if (bustype != SI_BUS) {
 691                 char *var;
 692
 693                 var = getvar(vars, "vendid");
 694                 if (var) {
 695                         vendor = (u16) simple_strtoul(var, NULL, 0);
 696                         WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
 697                 }
 698                 var = getvar(vars, "devid");
 699                 if (var) {
 700                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 701                         if (devid != 0xffff) {
 702                                 device = devid;
 703                                 WL_ERROR("Overriding device id = 0x%x\n",
 704                                          device);
 705                         }
 706                 }
 707
 708                 /* verify again the device is supported */
 709                 if (!wlc_chipmatch(vendor, device)) {
 710                         WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
 711                                  unit, vendor, device);
 712                         err = 12;
 713                         goto fail;
 714                 }
 715         }
 716
 717         wlc_hw->vendorid = vendor;
 718         wlc_hw->deviceid = device;
 719
 720         /* set bar0 window to point at D11 core */
 721         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 722         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 723
 724         regs = wlc_hw->regs;
 725
 726         wlc->regs = wlc_hw->regs;
 727
 728         /* validate chip, chiprev and corerev */
 729         if (!wlc_isgoodchip(wlc_hw)) {
 730                 err = 13;
 731                 goto fail;
 732         }
 733
 734         /* initialize power control registers */
 735         si_clkctl_init(wlc_hw->sih);
 736
 737         /* request fastclock and force fastclock for the rest of attach
 738          * bring the d11 core out of reset.
 739          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 740          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 741          */
 742         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 743         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 744
 745         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 746                 WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
 747                          unit);
 748                 err = 14;
 749                 goto fail;
 750         }
 751
 752         /* get the board rev, used just below */
 753         j = getintvar(vars, "boardrev");
 754         /* promote srom boardrev of 0xFF to 1 */
 755         if (j == BOARDREV_PROMOTABLE)
 756                 j = BOARDREV_PROMOTED;
 757         wlc_hw->boardrev = (u16) j;
 758         if (!wlc_validboardtype(wlc_hw)) {
 759                 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
 760                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 761                 err = 15;
 762                 goto fail;
 763         }
 764         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 765         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 766         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 767
 768         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 769                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 770
 771         if ((wlc_hw->sih->bustype == PCI_BUS)
 772             && (si_pci_war16165(wlc_hw->sih)))
 773                 wlc->war16165 = true;
 774
 775         /* check device id(srom, nvram etc.) to set bands */
 776         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 777                 /* Dualband boards */
 778                 wlc_hw->_nbands = 2;
 779         } else
 780                 wlc_hw->_nbands = 1;
 781
 782         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 783                 wlc_hw->_nbands = 1;
 784
 785         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 786          * init of these values
 787          */
 788         wlc->vendorid = wlc_hw->vendorid;
 789         wlc->deviceid = wlc_hw->deviceid;
 790         wlc->pub->sih = wlc_hw->sih;
 791         wlc->pub->corerev = wlc_hw->corerev;
 792         wlc->pub->sromrev = wlc_hw->sromrev;
 793         wlc->pub->boardrev = wlc_hw->boardrev;
 794         wlc->pub->boardflags = wlc_hw->boardflags;
 795         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 796         wlc->pub->_nbands = wlc_hw->_nbands;
 797
 798         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 799
 800         if (wlc_hw->physhim == NULL) {
 801                 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 802                          unit);
 803                 err = 25;
 804                 goto fail;
 805         }
 806
 807         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 808         sha_params.osh = wlc->osh;
 809         sha_params.sih = wlc_hw->sih;
 810         sha_params.physhim = wlc_hw->physhim;
 811         sha_params.unit = unit;
 812         sha_params.corerev = wlc_hw->corerev;
 813         sha_params.vars = vars;
 814         sha_params.vid = wlc_hw->vendorid;
 815         sha_params.did = wlc_hw->deviceid;
 816         sha_params.chip = wlc_hw->sih->chip;
 817         sha_params.chiprev = wlc_hw->sih->chiprev;
 818         sha_params.chippkg = wlc_hw->sih->chippkg;
 819         sha_params.sromrev = wlc_hw->sromrev;
 820         sha_params.boardtype = wlc_hw->sih->boardtype;
 821         sha_params.boardrev = wlc_hw->boardrev;
 822         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 823         sha_params.boardflags = wlc_hw->boardflags;
 824         sha_params.boardflags2 = wlc_hw->boardflags2;
 825         sha_params.bustype = wlc_hw->sih->bustype;
 826         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 827
 828         /* alloc and save pointer to shared phy state area */
 829         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 830         if (!wlc_hw->phy_sh) {
 831                 err = 16;
 832                 goto fail;
 833         }
 834
 835         /* initialize software state for each core and band */
 836         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 837                 /*
 838                  * band0 is always 2.4Ghz
 839                  * band1, if present, is 5Ghz
 840                  */
 841
 842                 /* So if this is a single band 11a card, use band 1 */
 843                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 844                         j = BAND_5G_INDEX;
 845
 846                 wlc_setxband(wlc_hw, j);
 847
 848                 wlc_hw->band->bandunit = j;
 849                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 850                 wlc->band->bandunit = j;
 851                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 852                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 853
 854                 wlc_hw->machwcap = R_REG(&regs->machwcap);
 855                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 856
 857                 /* init tx fifo size */
 858                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 859                        ARRAY_SIZE(xmtfifo_sz));
 860                 wlc_hw->xmtfifo_sz =
 861                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 862
 863                 /* Get a phy for this band */
 864                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 865                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
 866                 if (wlc_hw->band->pi == NULL) {
 867                         WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
 868                                  unit);
 869                         err = 17;
 870                         goto fail;
 871                 }
 872
 873                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 874
 875                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 876                                        &wlc_hw->band->phyrev,
 877                                        &wlc_hw->band->radioid,
 878                                        &wlc_hw->band->radiorev);
 879                 wlc_hw->band->abgphy_encore =
 880                     wlc_phy_get_encore(wlc_hw->band->pi);
 881                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 882                 wlc_hw->band->core_flags =
 883                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 884
 885                 /* verify good phy_type & supported phy revision */
 886                 if (WLCISNPHY(wlc_hw->band)) {
 887                         if (NCONF_HAS(wlc_hw->band->phyrev))
 888                                 goto good_phy;
 889                         else
 890                                 goto bad_phy;
 891                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 892                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 893                                 goto good_phy;
 894                         else
 895                                 goto bad_phy;
 896                 } else {
 897  bad_phy:
 898                         WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
 899                                  unit,
 900                                  wlc_hw->band->phytype, wlc_hw->band->phyrev);
 901                         err = 18;
 902                         goto fail;
 903                 }
 904
 905  good_phy:
 906                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 907                  * high level attach. However we can not make that change until all low level access
 908                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 909                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 910                  * low only init when all fns updated.
 911                  */
 912                 wlc->band->pi = wlc_hw->band->pi;
 913                 wlc->band->phytype = wlc_hw->band->phytype;
 914                 wlc->band->phyrev = wlc_hw->band->phyrev;
 915                 wlc->band->radioid = wlc_hw->band->radioid;
 916                 wlc->band->radiorev = wlc_hw->band->radiorev;
 917
 918                 /* default contention windows size limits */
 919                 wlc_hw->band->CWmin = APHY_CWMIN;
 920                 wlc_hw->band->CWmax = PHY_CWMAX;
 921
 922                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 923                         err = 19;
 924                         goto fail;
 925                 }
 926         }
 927
 928         /* disable core to match driver "down" state */
 929         wlc_coredisable(wlc_hw);
 930
 931         /* Match driver "down" state */
 932         if (wlc_hw->sih->bustype == PCI_BUS)
 933                 si_pci_down(wlc_hw->sih);
 934
 935         /* register sb interrupt callback functions */
 936         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 937                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 938
 939         /* turn off pll and xtal to match driver "down" state */
 940         wlc_bmac_xtal(wlc_hw, OFF);
 941
 942         /* *********************************************************************
 943          * The hardware is in the DOWN state at this point. D11 core
 944          * or cores are in reset with clocks off, and the board PLLs
 945          * are off if possible.
 946          *
 947          * Beyond this point, wlc->sbclk == false and chip registers
 948          * should not be touched.
 949          *********************************************************************
 950          */
 951
 952         /* init etheraddr state variables */
 953         macaddr = wlc_get_macaddr(wlc_hw);
 954         if (macaddr == NULL) {
 955                 WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
 956                 err = 21;
 957                 goto fail;
 958         }
 959         bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
 960         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 961             is_zero_ether_addr(wlc_hw->etheraddr)) {
 962                 WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
 963                          unit, macaddr);
 964                 err = 22;
 965                 goto fail;
 966         }
 967
 968         WL_TRACE("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 969                  __func__, wlc_hw->deviceid, wlc_hw->_nbands,
 970                  wlc_hw->sih->boardtype, macaddr);
 971
 972         return err;
 973
 974  fail:
 975         WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
 976         return err;
 977 }
 978
 979 /*
 980  * Initialize wlc_info default values ...
 981  * may get overrides later in this function
 982  *  BMAC_NOTES, move low out and resolve the dangling ones
 983  */
 984 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
 985 {
 986         struct wlc_info *wlc = wlc_hw->wlc;
 987
 988         /* set default sw macintmask value */
 989         wlc->defmacintmask = DEF_MACINTMASK;
 990
 991         /* various 802.11g modes */
 992         wlc_hw->shortslot = false;
 993
 994         wlc_hw->SFBL = RETRY_SHORT_FB;
 995         wlc_hw->LFBL = RETRY_LONG_FB;
 996
 997         /* default mac retry limits */
 998         wlc_hw->SRL = RETRY_SHORT_DEF;
 999         wlc_hw->LRL = RETRY_LONG_DEF;
1000         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1001 }
1002
1003 /*
1004  * low level detach
1005  */
1006 int wlc_bmac_detach(struct wlc_info *wlc)
1007 {
1008         uint i;
1009         struct wlc_hwband *band;
1010         struct wlc_hw_info *wlc_hw = wlc->hw;
1011         int callbacks;
1012
1013         callbacks = 0;
1014
1015         if (wlc_hw->sih) {
1016                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1017                  * interrupt object may has been freed. this must be done before sb core switch
1018                  */
1019                 si_deregister_intr_callback(wlc_hw->sih);
1020
1021                 if (wlc_hw->sih->bustype == PCI_BUS)
1022                         si_pci_sleep(wlc_hw->sih);
1023         }
1024
1025         wlc_bmac_detach_dmapio(wlc_hw);
1026
1027         band = wlc_hw->band;
1028         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1029                 if (band->pi) {
1030                         /* Detach this band's phy */
1031                         wlc_phy_detach(band->pi);
1032                         band->pi = NULL;
1033                 }
1034                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1035         }
1036
1037         /* Free shared phy state */
1038         wlc_phy_shared_detach(wlc_hw->phy_sh);
1039
1040         wlc_phy_shim_detach(wlc_hw->physhim);
1041
1042         /* free vars */
1043         kfree(wlc_hw->vars);
1044         wlc_hw->vars = NULL;
1045
1046         if (wlc_hw->sih) {
1047                 si_detach(wlc_hw->sih);
1048                 wlc_hw->sih = NULL;
1049         }
1050
1051         return callbacks;
1052
1053 }
1054
1055 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1056 {
1057         WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1058
1059         wlc_hw->wlc->pub->_cnt->reset++;
1060
1061         /* reset the core */
1062         if (!DEVICEREMOVED(wlc_hw->wlc))
1063                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1064
1065         /* purge the dma rings */
1066         wlc_flushqueues(wlc_hw->wlc);
1067
1068         wlc_reset_bmac_done(wlc_hw->wlc);
1069 }
1070
1071 void
1072 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1073                           bool mute) {
1074         u32 macintmask;
1075         bool fastclk;
1076         struct wlc_info *wlc = wlc_hw->wlc;
1077
1078         WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1079
1080         /* request FAST clock if not on */
1081         fastclk = wlc_hw->forcefastclk;
1082         if (!fastclk)
1083                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1084
1085         /* disable interrupts */
1086         macintmask = wl_intrsoff(wlc->wl);
1087
1088         /* set up the specified band and chanspec */
1089         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1090         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1091
1092         /* do one-time phy inits and calibration */
1093         wlc_phy_cal_init(wlc_hw->band->pi);
1094
1095         /* core-specific initialization */
1096         wlc_coreinit(wlc);
1097
1098         /* suspend the tx fifos and mute the phy for preism cac time */
1099         if (mute)
1100                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1101
1102         /* band-specific inits */
1103         wlc_bmac_bsinit(wlc, chanspec);
1104
1105         /* restore macintmask */
1106         wl_intrsrestore(wlc->wl, macintmask);
1107
1108         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1109          * and wlc_enable_mac() will clear this override bit.
1110          */
1111         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1112
1113         /*
1114          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1115          */
1116         wlc_hw->mac_suspend_depth = 1;
1117
1118         /* restore the clk */
1119         if (!fastclk)
1120                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1121 }
1122
1123 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1124 {
1125         uint coremask;
1126
1127         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1128
1129         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1130
1131         /*
1132          * Enable pll and xtal, initialize the power control registers,
1133          * and force fastclock for the remainder of wlc_up().
1134          */
1135         wlc_bmac_xtal(wlc_hw, ON);
1136         si_clkctl_init(wlc_hw->sih);
1137         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1138
1139         /*
1140          * Configure pci/pcmcia here instead of in wlc_attach()
1141          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1142          */
1143         coremask = (1 << wlc_hw->wlc->core->coreidx);
1144
1145         if (wlc_hw->sih->bustype == PCI_BUS)
1146                 si_pci_setup(wlc_hw->sih, coremask);
1147
1148         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1149
1150         /*
1151          * Need to read the hwradio status here to cover the case where the system
1152          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1153          */
1154         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1155                 /* put SB PCI in down state again */
1156                 if (wlc_hw->sih->bustype == PCI_BUS)
1157                         si_pci_down(wlc_hw->sih);
1158                 wlc_bmac_xtal(wlc_hw, OFF);
1159                 return BCME_RADIOOFF;
1160         }
1161
1162         if (wlc_hw->sih->bustype == PCI_BUS)
1163                 si_pci_up(wlc_hw->sih);
1164
1165         /* reset the d11 core */
1166         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1167
1168         return 0;
1169 }
1170
1171 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1172 {
1173         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1174
1175         wlc_hw->up = true;
1176         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1177
1178         /* FULLY enable dynamic power control and d11 core interrupt */
1179         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1180         ASSERT(wlc_hw->wlc->macintmask == 0);
1181         wl_intrson(wlc_hw->wlc->wl);
1182         return 0;
1183 }
1184
1185 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1186 {
1187         bool dev_gone;
1188         uint callbacks = 0;
1189
1190         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1191
1192         if (!wlc_hw->up)
1193                 return callbacks;
1194
1195         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1196
1197         /* disable interrupts */
1198         if (dev_gone)
1199                 wlc_hw->wlc->macintmask = 0;
1200         else {
1201                 /* now disable interrupts */
1202                 wl_intrsoff(wlc_hw->wlc->wl);
1203
1204                 /* ensure we're running on the pll clock again */
1205                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1206         }
1207         /* down phy at the last of this stage */
1208         callbacks += wlc_phy_down(wlc_hw->band->pi);
1209
1210         return callbacks;
1211 }
1212
1213 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1214 {
1215         uint callbacks = 0;
1216         bool dev_gone;
1217
1218         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1219
1220         if (!wlc_hw->up)
1221                 return callbacks;
1222
1223         wlc_hw->up = false;
1224         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1225
1226         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1227
1228         if (dev_gone) {
1229                 wlc_hw->sbclk = false;
1230                 wlc_hw->clk = false;
1231                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1232
1233                 /* reclaim any posted packets */
1234                 wlc_flushqueues(wlc_hw->wlc);
1235         } else {
1236
1237                 /* Reset and disable the core */
1238                 if (si_iscoreup(wlc_hw->sih)) {
1239                         if (R_REG(&wlc_hw->regs->maccontrol) &
1240                             MCTL_EN_MAC)
1241                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1242                         callbacks += wl_reset(wlc_hw->wlc->wl);
1243                         wlc_coredisable(wlc_hw);
1244                 }
1245
1246                 /* turn off primary xtal and pll */
1247                 if (!wlc_hw->noreset) {
1248                         if (wlc_hw->sih->bustype == PCI_BUS)
1249                                 si_pci_down(wlc_hw->sih);
1250                         wlc_bmac_xtal(wlc_hw, OFF);
1251                 }
1252         }
1253
1254         return callbacks;
1255 }
1256
1257 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1258 {
1259         /* delay before first read of ucode state */
1260         udelay(40);
1261
1262         /* wait until ucode is no longer asleep */
1263         SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1264                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1265
1266         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1267 }
1268
1269 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1270 {
1271         memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1272 }
1273
1274 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1275 {
1276         return wlc_hw->band->bandtype;
1277 }
1278
1279 /* control chip clock to save power, enable dynamic clock or force fast clock */
1280 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1281 {
1282         if (PMUCTL_ENAB(wlc_hw->sih)) {
1283                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1284                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1285                  *      which means the FCA bit may not be set.
1286                  *      should wakeup mac if driver wants it to run on HT.
1287                  */
1288
1289                 if (wlc_hw->clk) {
1290                         if (mode == CLK_FAST) {
1291                                 OR_REG(&wlc_hw->regs->clk_ctl_st,
1292                                        CCS_FORCEHT);
1293
1294                                 udelay(64);
1295
1296                                 SPINWAIT(((R_REG
1297                                            (&wlc_hw->regs->
1298                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1299                                          PMU_MAX_TRANSITION_DLY);
1300                                 ASSERT(R_REG
1301                                        (&wlc_hw->regs->
1302                                         clk_ctl_st) & CCS_HTAVAIL);
1303                         } else {
1304                                 if ((wlc_hw->sih->pmurev == 0) &&
1305                                     (R_REG
1306                                      (&wlc_hw->regs->
1307                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1308                                         SPINWAIT(((R_REG
1309                                                    (&wlc_hw->regs->
1310                                                     clk_ctl_st) & CCS_HTAVAIL)
1311                                                   == 0),
1312                                                  PMU_MAX_TRANSITION_DLY);
1313                                 AND_REG(&wlc_hw->regs->clk_ctl_st,
1314                                         ~CCS_FORCEHT);
1315                         }
1316                 }
1317                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1318         } else {
1319
1320                 /* old chips w/o PMU, force HT through cc,
1321                  * then use FCA to verify mac is running fast clock
1322                  */
1323
1324                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1325
1326                 /* check fast clock is available (if core is not in reset) */
1327                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1328                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1329
1330                 /* keep the ucode wake bit on if forcefastclk is on
1331                  * since we do not want ucode to put us back to slow clock
1332                  * when it dozes for PM mode.
1333                  * Code below matches the wake override bit with current forcefastclk state
1334                  * Only setting bit in wake_override instead of waking ucode immediately
1335                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1336                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1337                  * (protected by an up check) was executed just below.
1338                  */
1339                 if (wlc_hw->forcefastclk)
1340                         mboolset(wlc_hw->wake_override,
1341                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1342                 else
1343                         mboolclr(wlc_hw->wake_override,
1344                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1345         }
1346 }
1347
1348 /* set initial host flags value */
1349 static void
1350 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1351 {
1352         struct wlc_hw_info *wlc_hw = wlc->hw;
1353
1354         memset(mhfs, 0, MHFMAX * sizeof(u16));
1355
1356         mhfs[MHF2] |= mhf2_init;
1357
1358         /* prohibit use of slowclock on multifunction boards */
1359         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1360                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1361
1362         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1363                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1364                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1365         }
1366 }
1367
1368 /* set or clear ucode host flag bits
1369  * it has an optimization for no-change write
1370  * it only writes through shared memory when the core has clock;
1371  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1372  *
1373  *
1374  * bands values are: WLC_BAND_AUTO <--- Current band only
1375  *                   WLC_BAND_5G   <--- 5G band only
1376  *                   WLC_BAND_2G   <--- 2G band only
1377  *                   WLC_BAND_ALL  <--- All bands
1378  */
1379 void
1380 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1381              int bands)
1382 {
1383         u16 save;
1384         u16 addr[MHFMAX] = {
1385                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1386                 M_HOST_FLAGS5
1387         };
1388         struct wlc_hwband *band;
1389
1390         ASSERT((val & ~mask) == 0);
1391         ASSERT(idx < MHFMAX);
1392         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1393
1394         switch (bands) {
1395                 /* Current band only or all bands,
1396                  * then set the band to current band
1397                  */
1398         case WLC_BAND_AUTO:
1399         case WLC_BAND_ALL:
1400                 band = wlc_hw->band;
1401                 break;
1402         case WLC_BAND_5G:
1403                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1404                 break;
1405         case WLC_BAND_2G:
1406                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1407                 break;
1408         default:
1409                 ASSERT(0);
1410                 band = NULL;
1411         }
1412
1413         if (band) {
1414                 save = band->mhfs[idx];
1415                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1416
1417                 /* optimization: only write through if changed, and
1418                  * changed band is the current band
1419                  */
1420                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1421                     && (band == wlc_hw->band))
1422                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1423                                            (u16) band->mhfs[idx]);
1424         }
1425
1426         if (bands == WLC_BAND_ALL) {
1427                 wlc_hw->bandstate[0]->mhfs[idx] =
1428                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1429                 wlc_hw->bandstate[1]->mhfs[idx] =
1430                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1431         }
1432 }
1433
1434 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1435 {
1436         struct wlc_hwband *band;
1437         ASSERT(idx < MHFMAX);
1438
1439         switch (bands) {
1440         case WLC_BAND_AUTO:
1441                 band = wlc_hw->band;
1442                 break;
1443         case WLC_BAND_5G:
1444                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1445                 break;
1446         case WLC_BAND_2G:
1447                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1448                 break;
1449         default:
1450                 ASSERT(0);
1451                 band = NULL;
1452         }
1453
1454         if (!band)
1455                 return 0;
1456
1457         return band->mhfs[idx];
1458 }
1459
1460 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1461 {
1462         u8 idx;
1463         u16 addr[] = {
1464                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1465                 M_HOST_FLAGS5
1466         };
1467
1468         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1469
1470         for (idx = 0; idx < MHFMAX; idx++) {
1471                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1472         }
1473 }
1474
1475 /* set the maccontrol register to desired reset state and
1476  * initialize the sw cache of the register
1477  */
1478 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1479 {
1480         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1481         wlc_hw->maccontrol = 0;
1482         wlc_hw->suspended_fifos = 0;
1483         wlc_hw->wake_override = 0;
1484         wlc_hw->mute_override = 0;
1485         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1486 }
1487
1488 /* set or clear maccontrol bits */
1489 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1490 {
1491         u32 maccontrol;
1492         u32 new_maccontrol;
1493
1494         ASSERT((val & ~mask) == 0);
1495
1496         maccontrol = wlc_hw->maccontrol;
1497         new_maccontrol = (maccontrol & ~mask) | val;
1498
1499         /* if the new maccontrol value is the same as the old, nothing to do */
1500         if (new_maccontrol == maccontrol)
1501                 return;
1502
1503         /* something changed, cache the new value */
1504         wlc_hw->maccontrol = new_maccontrol;
1505
1506         /* write the new values with overrides applied */
1507         wlc_mctrl_write(wlc_hw);
1508 }
1509
1510 /* write the software state of maccontrol and overrides to the maccontrol register */
1511 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1512 {
1513         u32 maccontrol = wlc_hw->maccontrol;
1514
1515         /* OR in the wake bit if overridden */
1516         if (wlc_hw->wake_override)
1517                 maccontrol |= MCTL_WAKE;
1518
1519         /* set AP and INFRA bits for mute if needed */
1520         if (wlc_hw->mute_override) {
1521                 maccontrol &= ~(MCTL_AP);
1522                 maccontrol |= MCTL_INFRA;
1523         }
1524
1525         W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1526 }
1527
1528 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1529 {
1530         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1531
1532         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1533                 mboolset(wlc_hw->wake_override, override_bit);
1534                 return;
1535         }
1536
1537         mboolset(wlc_hw->wake_override, override_bit);
1538
1539         wlc_mctrl_write(wlc_hw);
1540         wlc_bmac_wait_for_wake(wlc_hw);
1541
1542         return;
1543 }
1544
1545 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1546 {
1547         ASSERT(wlc_hw->wake_override & override_bit);
1548
1549         mboolclr(wlc_hw->wake_override, override_bit);
1550
1551         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1552                 return;
1553
1554         wlc_mctrl_write(wlc_hw);
1555
1556         return;
1557 }
1558
1559 /* When driver needs ucode to stop beaconing, it has to make sure that
1560  * MCTL_AP is clear and MCTL_INFRA is set
1561  * Mode           MCTL_AP        MCTL_INFRA
1562  * AP                1              1
1563  * STA               0              1 <--- This will ensure no beacons
1564  * IBSS              0              0
1565  */
1566 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1567 {
1568         wlc_hw->mute_override = 1;
1569
1570         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1571          * override, then there is no change to write
1572          */
1573         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1574                 return;
1575
1576         wlc_mctrl_write(wlc_hw);
1577
1578         return;
1579 }
1580
1581 /* Clear the override on AP and INFRA bits */
1582 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1583 {
1584         if (wlc_hw->mute_override == 0)
1585                 return;
1586
1587         wlc_hw->mute_override = 0;
1588
1589         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1590          * override, then there is no change to write
1591          */
1592         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1593                 return;
1594
1595         wlc_mctrl_write(wlc_hw);
1596 }
1597
1598 /*
1599  * Write a MAC address to the rcmta structure
1600  */
1601 void
1602 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1603                    const u8 *addr)
1604 {
1605         d11regs_t *regs = wlc_hw->regs;
1606         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1607         u32 mac_hm;
1608         u16 mac_l;
1609
1610         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1611
1612         mac_hm =
1613             (addr[3] << 24) | (addr[2] << 16) |
1614             (addr[1] << 8) | addr[0];
1615         mac_l = (addr[5] << 8) | addr[4];
1616
1617         W_REG(&regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1618         (void)R_REG(&regs->objaddr);
1619         W_REG(&regs->objdata, mac_hm);
1620         W_REG(&regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1621         (void)R_REG(&regs->objaddr);
1622         W_REG(objdata16, mac_l);
1623 }
1624
1625 /*
1626  * Write a MAC address to the given match reg offset in the RXE match engine.
1627  */
1628 void
1629 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1630                        const u8 *addr)
1631 {
1632         d11regs_t *regs;
1633         u16 mac_l;
1634         u16 mac_m;
1635         u16 mac_h;
1636
1637         WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1638
1639         ASSERT(match_reg_offset < RCM_SIZE);
1640
1641         regs = wlc_hw->regs;
1642         mac_l = addr[0] | (addr[1] << 8);
1643         mac_m = addr[2] | (addr[3] << 8);
1644         mac_h = addr[4] | (addr[5] << 8);
1645
1646         /* enter the MAC addr into the RXE match registers */
1647         W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1648         W_REG(&regs->rcm_mat_data, mac_l);
1649         W_REG(&regs->rcm_mat_data, mac_m);
1650         W_REG(&regs->rcm_mat_data, mac_h);
1651
1652 }
1653
1654 void
1655 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1656                             void *buf)
1657 {
1658         d11regs_t *regs;
1659         u32 word;
1660         bool be_bit;
1661 #ifdef IL_BIGENDIAN
1662         volatile u16 *dptr = NULL;
1663 #endif                          /* IL_BIGENDIAN */
1664         WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1665
1666         regs = wlc_hw->regs;
1667
1668         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1669         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1670         ASSERT((offset & ~0xffff) == 0);
1671
1672         W_REG(&regs->tplatewrptr, offset);
1673
1674         /* if MCTL_BIGEND bit set in mac control register,
1675          * the chip swaps data in fifo, as well as data in
1676          * template ram
1677          */
1678         be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1679
1680         while (len > 0) {
1681                 memcpy(&word, buf, sizeof(u32));
1682
1683                 if (be_bit)
1684                         word = cpu_to_be32(word);
1685                 else
1686                         word = cpu_to_le32(word);
1687
1688                 W_REG(&regs->tplatewrdata, word);
1689
1690                 buf = (u8 *) buf + sizeof(u32);
1691                 len -= sizeof(u32);
1692         }
1693 }
1694
1695 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1696 {
1697         wlc_hw->band->CWmin = newmin;
1698
1699         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1700         (void)R_REG(&wlc_hw->regs->objaddr);
1701         W_REG(&wlc_hw->regs->objdata, newmin);
1702 }
1703
1704 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1705 {
1706         wlc_hw->band->CWmax = newmax;
1707
1708         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1709         (void)R_REG(&wlc_hw->regs->objaddr);
1710         W_REG(&wlc_hw->regs->objdata, newmax);
1711 }
1712
1713 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1714 {
1715         bool fastclk;
1716
1717         /* request FAST clock if not on */
1718         fastclk = wlc_hw->forcefastclk;
1719         if (!fastclk)
1720                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1721
1722         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1723
1724         ASSERT(wlc_hw->clk);
1725
1726         wlc_bmac_phy_reset(wlc_hw);
1727         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1728
1729         /* restore the clk */
1730         if (!fastclk)
1731                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1732 }
1733
1734 static void
1735 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1736 {
1737         d11regs_t *regs = wlc_hw->regs;
1738
1739         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1740                                     bcn);
1741         /* write beacon length to SCR */
1742         ASSERT(len < 65536);
1743         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1744         /* mark beacon0 valid */
1745         OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1746 }
1747
1748 static void
1749 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1750 {
1751         d11regs_t *regs = wlc_hw->regs;
1752
1753         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1754                                     bcn);
1755         /* write beacon length to SCR */
1756         ASSERT(len < 65536);
1757         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1758         /* mark beacon1 valid */
1759         OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1760 }
1761
1762 /* mac is assumed to be suspended at this point */
1763 void
1764 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1765                                bool both)
1766 {
1767         d11regs_t *regs = wlc_hw->regs;
1768
1769         if (both) {
1770                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1771                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1772         } else {
1773                 /* bcn 0 */
1774                 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1775                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1776                 /* bcn 1 */
1777                 else if (!
1778                          (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1779                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1780                 else            /* one template should always have been available */
1781                         ASSERT(0);
1782         }
1783 }
1784
1785 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1786 {
1787         u16 v;
1788         struct wlc_info *wlc = wlc_hw->wlc;
1789         /* update SYNTHPU_DLY */
1790
1791         if (WLCISLCNPHY(wlc->band)) {
1792                 v = SYNTHPU_DLY_LPPHY_US;
1793         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1794                 v = SYNTHPU_DLY_NPHY_US;
1795         } else {
1796                 v = SYNTHPU_DLY_BPHY_US;
1797         }
1798
1799         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1800 }
1801
1802 /* band-specific init */
1803 static void
1804 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1805 {
1806         struct wlc_hw_info *wlc_hw = wlc->hw;
1807
1808         WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1809                  wlc_hw->unit, wlc_hw->band->bandunit);
1810
1811         /* sanity check */
1812         if (PHY_TYPE(R_REG(&wlc_hw->regs->phyversion)) !=
1813             PHY_TYPE_LCNXN)
1814                 ASSERT((uint)
1815                        PHY_TYPE(R_REG(&wlc_hw->regs->phyversion))
1816                        == wlc_hw->band->phytype);
1817
1818         wlc_ucode_bsinit(wlc_hw);
1819
1820         wlc_phy_init(wlc_hw->band->pi, chanspec);
1821
1822         wlc_ucode_txant_set(wlc_hw);
1823
1824         /* cwmin is band-specific, update hardware with value for current band */
1825         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1826         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1827
1828         wlc_bmac_update_slot_timing(wlc_hw,
1829                                     BAND_5G(wlc_hw->band->
1830                                             bandtype) ? true : wlc_hw->
1831                                     shortslot);
1832
1833         /* write phytype and phyvers */
1834         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1835         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1836
1837         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1838         wlc_upd_ofdm_pctl1_table(wlc_hw);
1839
1840         wlc_bmac_upd_synthpu(wlc_hw);
1841 }
1842
1843 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1844 {
1845         WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1846
1847         wlc_hw->phyclk = clk;
1848
1849         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1850
1851                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1852                                (SICF_PRST | SICF_FGC));
1853                 udelay(1);
1854                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1855                 udelay(1);
1856
1857         } else {                /* take phy out of reset */
1858
1859                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1860                 udelay(1);
1861                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1862                 udelay(1);
1863
1864         }
1865 }
1866
1867 /* Perform a soft reset of the PHY PLL */
1868 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1869 {
1870         WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1871
1872         si_corereg(wlc_hw->sih, SI_CC_IDX,
1873                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1874         udelay(1);
1875         si_corereg(wlc_hw->sih, SI_CC_IDX,
1876                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1877         udelay(1);
1878         si_corereg(wlc_hw->sih, SI_CC_IDX,
1879                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1880         udelay(1);
1881         si_corereg(wlc_hw->sih, SI_CC_IDX,
1882                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1883         udelay(1);
1884 }
1885
1886 /* light way to turn on phy clock without reset for NPHY only
1887  *  refer to wlc_bmac_core_phy_clk for full version
1888  */
1889 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1890 {
1891         /* support(necessary for NPHY and HYPHY) only */
1892         if (!WLCISNPHY(wlc_hw->band))
1893                 return;
1894
1895         if (ON == clk)
1896                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1897         else
1898                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1899
1900 }
1901
1902 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1903 {
1904         if (ON == clk)
1905                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1906         else
1907                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1908 }
1909
1910 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1911 {
1912         wlc_phy_t *pih = wlc_hw->band->pi;
1913         u32 phy_bw_clkbits;
1914         bool phy_in_reset = false;
1915
1916         WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
1917
1918         if (pih == NULL)
1919                 return;
1920
1921         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1922
1923         /* Specfic reset sequence required for NPHY rev 3 and 4 */
1924         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1925             NREV_LE(wlc_hw->band->phyrev, 4)) {
1926                 /* Set the PHY bandwidth */
1927                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1928
1929                 udelay(1);
1930
1931                 /* Perform a soft reset of the PHY PLL */
1932                 wlc_bmac_core_phypll_reset(wlc_hw);
1933
1934                 /* reset the PHY */
1935                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1936                                (SICF_PRST | SICF_PCLKE));
1937                 phy_in_reset = true;
1938         } else {
1939
1940                 si_core_cflags(wlc_hw->sih,
1941                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1942                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1943         }
1944
1945         udelay(2);
1946         wlc_bmac_core_phy_clk(wlc_hw, ON);
1947
1948         if (pih)
1949                 wlc_phy_anacore(pih, ON);
1950 }
1951
1952 /* switch to and initialize new band */
1953 static void
1954 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1955                                 chanspec_t chanspec) {
1956         struct wlc_info *wlc = wlc_hw->wlc;
1957         u32 macintmask;
1958
1959         ASSERT(NBANDS_HW(wlc_hw) > 1);
1960         ASSERT(bandunit != wlc_hw->band->bandunit);
1961
1962         /* Enable the d11 core before accessing it */
1963         if (!si_iscoreup(wlc_hw->sih)) {
1964                 si_core_reset(wlc_hw->sih, 0, 0);
1965                 ASSERT(si_iscoreup(wlc_hw->sih));
1966                 wlc_mctrl_reset(wlc_hw);
1967         }
1968
1969         macintmask = wlc_setband_inact(wlc, bandunit);
1970
1971         if (!wlc_hw->up)
1972                 return;
1973
1974         wlc_bmac_core_phy_clk(wlc_hw, ON);
1975
1976         /* band-specific initializations */
1977         wlc_bmac_bsinit(wlc, chanspec);
1978
1979         /*
1980          * If there are any pending software interrupt bits,
1981          * then replace these with a harmless nonzero value
1982          * so wlc_dpc() will re-enable interrupts when done.
1983          */
1984         if (wlc->macintstatus)
1985                 wlc->macintstatus = MI_DMAINT;
1986
1987         /* restore macintmask */
1988         wl_intrsrestore(wlc->wl, macintmask);
1989
1990         /* ucode should still be suspended.. */
1991         ASSERT((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
1992                0);
1993 }
1994
1995 /* low-level band switch utility routine */
1996 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1997 {
1998         WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
1999
2000         wlc_hw->band = wlc_hw->bandstate[bandunit];
2001
2002         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2003         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2004
2005         /* set gmode core flag */
2006         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2007                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2008                                ((bandunit == 0) ? SICF_GMODE : 0));
2009         }
2010 }
2011
2012 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
2013 {
2014
2015         /* reject unsupported corerev */
2016         if (!VALID_COREREV(wlc_hw->corerev)) {
2017                 WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
2018                 return false;
2019         }
2020
2021         return true;
2022 }
2023
2024 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
2025 {
2026         bool goodboard = true;
2027         uint boardrev = wlc_hw->boardrev;
2028
2029         if (boardrev == 0)
2030                 goodboard = false;
2031         else if (boardrev > 0xff) {
2032                 uint brt = (boardrev & 0xf000) >> 12;
2033                 uint b0 = (boardrev & 0xf00) >> 8;
2034                 uint b1 = (boardrev & 0xf0) >> 4;
2035                 uint b2 = boardrev & 0xf;
2036
2037                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2038                     || (b2 > 9))
2039                         goodboard = false;
2040         }
2041
2042         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2043                 return goodboard;
2044
2045         return goodboard;
2046 }
2047
2048 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
2049 {
2050         const char *varname = "macaddr";
2051         char *macaddr;
2052
2053         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2054         macaddr = getvar(wlc_hw->vars, varname);
2055         if (macaddr != NULL)
2056                 return macaddr;
2057
2058         if (NBANDS_HW(wlc_hw) > 1)
2059                 varname = "et1macaddr";
2060         else
2061                 varname = "il0macaddr";
2062
2063         macaddr = getvar(wlc_hw->vars, varname);
2064         if (macaddr == NULL) {
2065                 WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
2066                          wlc_hw->unit, varname);
2067         }
2068
2069         return macaddr;
2070 }
2071
2072 /*
2073  * Return true if radio is disabled, otherwise false.
2074  * hw radio disable signal is an external pin, users activate it asynchronously
2075  * this function could be called when driver is down and w/o clock
2076  * it operates on different registers depending on corerev and boardflag.
2077  */
2078 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2079 {
2080         bool v, clk, xtal;
2081         u32 resetbits = 0, flags = 0;
2082
2083         xtal = wlc_hw->sbclk;
2084         if (!xtal)
2085                 wlc_bmac_xtal(wlc_hw, ON);
2086
2087         /* may need to take core out of reset first */
2088         clk = wlc_hw->clk;
2089         if (!clk) {
2090                 /*
2091                  * mac no longer enables phyclk automatically when driver
2092                  * accesses phyreg throughput mac. This can be skipped since
2093                  * only mac reg is accessed below
2094                  */
2095                 flags |= SICF_PCLKE;
2096
2097                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2098                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2099                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2100                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2101                         wlc_hw->regs =
2102                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2103                                                      0);
2104                 si_core_reset(wlc_hw->sih, flags, resetbits);
2105                 wlc_mctrl_reset(wlc_hw);
2106         }
2107
2108         v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2109
2110         /* put core back into reset */
2111         if (!clk)
2112                 si_core_disable(wlc_hw->sih, 0);
2113
2114         if (!xtal)
2115                 wlc_bmac_xtal(wlc_hw, OFF);
2116
2117         return v;
2118 }
2119
2120 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2121 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2122 {
2123         if (wlc_hw->wlc->pub->hw_up)
2124                 return;
2125
2126         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2127
2128         /*
2129          * Enable pll and xtal, initialize the power control registers,
2130          * and force fastclock for the remainder of wlc_up().
2131          */
2132         wlc_bmac_xtal(wlc_hw, ON);
2133         si_clkctl_init(wlc_hw->sih);
2134         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2135
2136         if (wlc_hw->sih->bustype == PCI_BUS) {
2137                 si_pci_fixcfg(wlc_hw->sih);
2138
2139                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2140                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2141                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2142                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2143                         wlc_hw->regs =
2144                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2145                                                      0);
2146         }
2147
2148         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2149         wlc_phy_por_inform(wlc_hw->band->pi);
2150
2151         wlc_hw->ucode_loaded = false;
2152         wlc_hw->wlc->pub->hw_up = true;
2153
2154         if ((wlc_hw->boardflags & BFL_FEM)
2155             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2156                 if (!
2157                     (wlc_hw->boardrev >= 0x1250
2158                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2159                         si_epa_4313war(wlc_hw->sih);
2160         }
2161 }
2162
2163 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2164 {
2165         struct hnddma_pub *di = wlc_hw->di[fifo];
2166         return dma_rxreset(di);
2167 }
2168
2169 /* d11 core reset
2170  *   ensure fask clock during reset
2171  *   reset dma
2172  *   reset d11(out of reset)
2173  *   reset phy(out of reset)
2174  *   clear software macintstatus for fresh new start
2175  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2176  */
2177 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2178 {
2179         d11regs_t *regs;
2180         uint i;
2181         bool fastclk;
2182         u32 resetbits = 0;
2183
2184         if (flags == WLC_USE_COREFLAGS)
2185                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2186
2187         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2188
2189         regs = wlc_hw->regs;
2190
2191         /* request FAST clock if not on  */
2192         fastclk = wlc_hw->forcefastclk;
2193         if (!fastclk)
2194                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2195
2196         /* reset the dma engines except first time thru */
2197         if (si_iscoreup(wlc_hw->sih)) {
2198                 for (i = 0; i < NFIFO; i++)
2199                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2200                                 WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
2201                                          wlc_hw->unit, __func__, i);
2202                         }
2203
2204                 if ((wlc_hw->di[RX_FIFO])
2205                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2206                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2207                                  wlc_hw->unit, __func__, RX_FIFO);
2208                 }
2209         }
2210         /* if noreset, just stop the psm and return */
2211         if (wlc_hw->noreset) {
2212                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2213                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2214                 return;
2215         }
2216
2217         /*
2218          * mac no longer enables phyclk automatically when driver accesses
2219          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2220          * band->pi is invalid. need to enable PHY CLK
2221          */
2222         flags |= SICF_PCLKE;
2223
2224         /* reset the core
2225          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2226          *  is cleared by the core_reset. have to re-request it.
2227          *  This adds some delay and we can optimize it by also requesting fastclk through
2228          *  chipcommon during this period if necessary. But that has to work coordinate
2229          *  with other driver like mips/arm since they may touch chipcommon as well.
2230          */
2231         wlc_hw->clk = false;
2232         si_core_reset(wlc_hw->sih, flags, resetbits);
2233         wlc_hw->clk = true;
2234         if (wlc_hw->band && wlc_hw->band->pi)
2235                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2236
2237         wlc_mctrl_reset(wlc_hw);
2238
2239         if (PMUCTL_ENAB(wlc_hw->sih))
2240                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2241
2242         wlc_bmac_phy_reset(wlc_hw);
2243
2244         /* turn on PHY_PLL */
2245         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2246
2247         /* clear sw intstatus */
2248         wlc_hw->wlc->macintstatus = 0;
2249
2250         /* restore the clk setting */
2251         if (!fastclk)
2252                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2253 }
2254
2255 /* txfifo sizes needs to be modified(increased) since the newer cores
2256  * have more memory.
2257  */
2258 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2259 {
2260         d11regs_t *regs = wlc_hw->regs;
2261         u16 fifo_nu;
2262         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2263         u16 txfifo_def, txfifo_def1;
2264         u16 txfifo_cmd;
2265
2266         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2267         txfifo_startblk = TXFIFO_START_BLK;
2268
2269         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2270         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2271
2272                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2273                 txfifo_def = (txfifo_startblk & 0xff) |
2274                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2275                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2276                     ((((txfifo_endblk -
2277                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2278                 txfifo_cmd =
2279                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2280
2281                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2282                 W_REG(&regs->xmtfifodef, txfifo_def);
2283                 W_REG(&regs->xmtfifodef1, txfifo_def1);
2284
2285                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2286
2287                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2288         }
2289         /*
2290          * need to propagate to shm location to be in sync since ucode/hw won't
2291          * do this
2292          */
2293         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2294                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2295         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2296                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2297         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2298                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2299                             xmtfifo_sz[TX_AC_BK_FIFO]));
2300         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2301                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2302                             xmtfifo_sz[TX_BCMC_FIFO]));
2303 }
2304
2305 /* d11 core init
2306  *   reset PSM
2307  *   download ucode/PCM
2308  *   let ucode run to suspended
2309  *   download ucode inits
2310  *   config other core registers
2311  *   init dma
2312  */
2313 static void wlc_coreinit(struct wlc_info *wlc)
2314 {
2315         struct wlc_hw_info *wlc_hw = wlc->hw;
2316         d11regs_t *regs;
2317         u32 sflags;
2318         uint bcnint_us;
2319         uint i = 0;
2320         bool fifosz_fixup = false;
2321         int err = 0;
2322         u16 buf[NFIFO];
2323
2324         regs = wlc_hw->regs;
2325
2326         WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2327
2328         /* reset PSM */
2329         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2330
2331         wlc_ucode_download(wlc_hw);
2332         /*
2333          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2334          */
2335         fifosz_fixup = true;
2336
2337         /* let the PSM run to the suspended state, set mode to BSS STA */
2338         W_REG(&regs->macintstatus, -1);
2339         wlc_bmac_mctrl(wlc_hw, ~0,
2340                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2341
2342         /* wait for ucode to self-suspend after auto-init */
2343         SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2344                  1000 * 1000);
2345         if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2346                 WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2347                          wlc_hw->unit);
2348
2349         wlc_gpio_init(wlc);
2350
2351         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2352
2353         if (D11REV_IS(wlc_hw->corerev, 23)) {
2354                 if (WLCISNPHY(wlc_hw->band))
2355                         wlc_write_inits(wlc_hw, d11n0initvals16);
2356                 else
2357                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2358                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2359         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2360                 if (WLCISLCNPHY(wlc_hw->band)) {
2361                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2362                 } else {
2363                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2364                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2365                 }
2366         } else {
2367                 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
2368                          __func__, wlc_hw->unit, wlc_hw->corerev);
2369         }
2370
2371         /* For old ucode, txfifo sizes needs to be modified(increased) */
2372         if (fifosz_fixup == true) {
2373                 wlc_corerev_fifofixup(wlc_hw);
2374         }
2375
2376         /* check txfifo allocations match between ucode and driver */
2377         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2378         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2379                 i = TX_AC_BE_FIFO;
2380                 err = -1;
2381         }
2382         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2383         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2384                 i = TX_AC_VI_FIFO;
2385                 err = -1;
2386         }
2387         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2388         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2389         buf[TX_AC_BK_FIFO] &= 0xff;
2390         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2391                 i = TX_AC_BK_FIFO;
2392                 err = -1;
2393         }
2394         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2395                 i = TX_AC_VO_FIFO;
2396                 err = -1;
2397         }
2398         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2399         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2400         buf[TX_BCMC_FIFO] &= 0xff;
2401         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2402                 i = TX_BCMC_FIFO;
2403                 err = -1;
2404         }
2405         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2406                 i = TX_ATIM_FIFO;
2407                 err = -1;
2408         }
2409         if (err != 0) {
2410                 WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
2411                          buf[i], wlc_hw->xmtfifo_sz[i], i);
2412                 ASSERT(0);
2413         }
2414
2415         /* make sure we can still talk to the mac */
2416         ASSERT(R_REG(&regs->maccontrol) != 0xffffffff);
2417
2418         /* band-specific inits done by wlc_bsinit() */
2419
2420         /* Set up frame burst size and antenna swap threshold init values */
2421         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2422         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2423
2424         /* enable one rx interrupt per received frame */
2425         W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2426
2427         /* set the station mode (BSS STA) */
2428         wlc_bmac_mctrl(wlc_hw,
2429                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2430                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2431
2432         /* set up Beacon interval */
2433         bcnint_us = 0x8000 << 10;
2434         W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2435         W_REG(&regs->tsf_cfpstart, bcnint_us);
2436         W_REG(&regs->macintstatus, MI_GP1);
2437
2438         /* write interrupt mask */
2439         W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2440
2441         /* allow the MAC to control the PHY clock (dynamic on/off) */
2442         wlc_bmac_macphyclk_set(wlc_hw, ON);
2443
2444         /* program dynamic clock control fast powerup delay register */
2445         wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2446         W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2447
2448         /* tell the ucode the corerev */
2449         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2450
2451         /* tell the ucode MAC capabilities */
2452         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2453                            (u16) (wlc_hw->machwcap & 0xffff));
2454         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2455                            (u16) ((wlc_hw->
2456                                       machwcap >> 16) & 0xffff));
2457
2458         /* write retry limits to SCR, this done after PSM init */
2459         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2460         (void)R_REG(&regs->objaddr);
2461         W_REG(&regs->objdata, wlc_hw->SRL);
2462         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2463         (void)R_REG(&regs->objaddr);
2464         W_REG(&regs->objdata, wlc_hw->LRL);
2465
2466         /* write rate fallback retry limits */
2467         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2468         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2469
2470         AND_REG(&regs->ifs_ctl, 0x0FFF);
2471         W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2472
2473         /* dma initializations */
2474         wlc->txpend16165war = 0;
2475
2476         /* init the tx dma engines */
2477         for (i = 0; i < NFIFO; i++) {
2478                 if (wlc_hw->di[i])
2479                         dma_txinit(wlc_hw->di[i]);
2480         }
2481
2482         /* init the rx dma engine(s) and post receive buffers */
2483         dma_rxinit(wlc_hw->di[RX_FIFO]);
2484         dma_rxfill(wlc_hw->di[RX_FIFO]);
2485 }
2486
2487 /* This function is used for changing the tsf frac register
2488  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2489  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2490  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2491  * HTPHY Formula is 2^26/freq(MHz) e.g.
2492  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2493  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2494  * For spuron: 123MHz -> 2^26/123    = 545600.5
2495  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2496  * For spur off: 120MHz -> 2^26/120    = 559240.5
2497  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2498  */
2499
2500 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2501 {
2502         d11regs_t *regs;
2503         regs = wlc_hw->regs;
2504
2505         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2506             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2507                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2508                         W_REG(&regs->tsf_clk_frac_l, 0x2082);
2509                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2510                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2511                         W_REG(&regs->tsf_clk_frac_l, 0x5341);
2512                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2513                 } else {        /* 120Mhz */
2514                         W_REG(&regs->tsf_clk_frac_l, 0x8889);
2515                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2516                 }
2517         } else if (WLCISLCNPHY(wlc_hw->band)) {
2518                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2519                         W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2520                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2521                 } else {        /* 80Mhz */
2522                         W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2523                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2524                 }
2525         }
2526 }
2527
2528 /* Initialize GPIOs that are controlled by D11 core */
2529 static void wlc_gpio_init(struct wlc_info *wlc)
2530 {
2531         struct wlc_hw_info *wlc_hw = wlc->hw;
2532         d11regs_t *regs;
2533         u32 gc, gm;
2534
2535         regs = wlc_hw->regs;
2536
2537         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2538         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2539
2540         /*
2541          * Common GPIO setup:
2542          *      G0 = LED 0 = WLAN Activity
2543          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2544          *      G2 = LED 2 = WLAN 5 GHz Radio State
2545          *      G4 = radio disable input (HI enabled, LO disabled)
2546          */
2547
2548         gc = gm = 0;
2549
2550         /* Allocate GPIOs for mimo antenna diversity feature */
2551         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2552                 /* Enable antenna diversity, use 2x3 mode */
2553                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2554                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2555                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2556                              MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2557
2558                 /* init superswitch control */
2559                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2560
2561         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2562                 ASSERT((gm & BOARD_GPIO_12) == 0);
2563                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2564                 /*
2565                  * The board itself is powered by these GPIOs
2566                  * (when not sending pattern) so set them high
2567                  */
2568                 OR_REG(&regs->psm_gpio_oe,
2569                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2570                 OR_REG(&regs->psm_gpio_out,
2571                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2572
2573                 /* Enable antenna diversity, use 2x4 mode */
2574                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2575                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2576                 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2577                              WLC_BAND_ALL);
2578
2579                 /* Configure the desired clock to be 4Mhz */
2580                 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2581                                    ANTSEL_CLKDIV_4MHZ);
2582         }
2583
2584         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2585         if (wlc_hw->boardflags & BFL_PACTRL)
2586                 gm |= gc |= BOARD_GPIO_PACTRL;
2587
2588         /* apply to gpiocontrol register */
2589         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2590 }
2591
2592 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2593 {
2594         struct wlc_info *wlc;
2595         wlc = wlc_hw->wlc;
2596
2597         if (wlc_hw->ucode_loaded)
2598                 return;
2599
2600         if (D11REV_IS(wlc_hw->corerev, 23)) {
2601                 if (WLCISNPHY(wlc_hw->band)) {
2602                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2603                                         bcm43xx_16_mimosz);
2604                         wlc_hw->ucode_loaded = true;
2605                 } else
2606                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2607                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2608         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2609                 if (WLCISLCNPHY(wlc_hw->band)) {
2610                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2611                                         bcm43xx_24_lcnsz);
2612                         wlc_hw->ucode_loaded = true;
2613                 } else {
2614                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2615                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2616                 }
2617         }
2618 }
2619
2620 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2621                               const uint nbytes) {
2622         d11regs_t *regs = wlc_hw->regs;
2623         uint i;
2624         uint count;
2625
2626         WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2627
2628         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2629
2630         count = (nbytes / sizeof(u32));
2631
2632         W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2633         (void)R_REG(&regs->objaddr);
2634         for (i = 0; i < count; i++)
2635                 W_REG(&regs->objdata, ucode[i]);
2636 }
2637
2638 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2639                             const struct d11init *inits)
2640 {
2641         int i;
2642         volatile u8 *base;
2643
2644         WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2645
2646         base = (volatile u8 *)wlc_hw->regs;
2647
2648         for (i = 0; inits[i].addr != 0xffff; i++) {
2649                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2650
2651                 if (inits[i].size == 2)
2652                         W_REG((u16 *)(base + inits[i].addr),
2653                               inits[i].value);
2654                 else if (inits[i].size == 4)
2655                         W_REG((u32 *)(base + inits[i].addr),
2656                               inits[i].value);
2657         }
2658 }
2659
2660 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2661 {
2662         u16 phyctl;
2663         u16 phytxant = wlc_hw->bmac_phytxant;
2664         u16 mask = PHY_TXC_ANT_MASK;
2665
2666         /* set the Probe Response frame phy control word */
2667         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2668         phyctl = (phyctl & ~mask) | phytxant;
2669         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2670
2671         /* set the Response (ACK/CTS) frame phy control word */
2672         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2673         phyctl = (phyctl & ~mask) | phytxant;
2674         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2675 }
2676
2677 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2678 {
2679         /* update sw state */
2680         wlc_hw->bmac_phytxant = phytxant;
2681
2682         /* push to ucode if up */
2683         if (!wlc_hw->up)
2684                 return;
2685         wlc_ucode_txant_set(wlc_hw);
2686
2687 }
2688
2689 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2690 {
2691         return (u16) wlc_hw->wlc->stf->txant;
2692 }
2693
2694 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2695 {
2696         wlc_hw->antsel_type = antsel_type;
2697
2698         /* Update the antsel type for phy module to use */
2699         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2700 }
2701
2702 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2703 {
2704         bool fatal = false;
2705         uint unit;
2706         uint intstatus, idx;
2707         d11regs_t *regs = wlc_hw->regs;
2708
2709         unit = wlc_hw->unit;
2710
2711         for (idx = 0; idx < NFIFO; idx++) {
2712                 /* read intstatus register and ignore any non-error bits */
2713                 intstatus =
2714                     R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2715                 if (!intstatus)
2716                         continue;
2717
2718                 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2719                          unit, idx, intstatus);
2720
2721                 if (intstatus & I_RO) {
2722                         WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
2723                                  unit, idx);
2724                         wlc_hw->wlc->pub->_cnt->rxoflo++;
2725                         fatal = true;
2726                 }
2727
2728                 if (intstatus & I_PC) {
2729                         WL_ERROR("wl%d: fifo %d: descriptor error\n",
2730                                  unit, idx);
2731                         wlc_hw->wlc->pub->_cnt->dmade++;
2732                         fatal = true;
2733                 }
2734
2735                 if (intstatus & I_PD) {
2736                         WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
2737                         wlc_hw->wlc->pub->_cnt->dmada++;
2738                         fatal = true;
2739                 }
2740
2741                 if (intstatus & I_DE) {
2742                         WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
2743                                  unit, idx);
2744                         wlc_hw->wlc->pub->_cnt->dmape++;
2745                         fatal = true;
2746                 }
2747
2748                 if (intstatus & I_RU) {
2749                         WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
2750                                  idx, unit);
2751                         wlc_hw->wlc->pub->_cnt->rxuflo[idx]++;
2752                 }
2753
2754                 if (intstatus & I_XU) {
2755                         WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
2756                                  idx, unit);
2757                         wlc_hw->wlc->pub->_cnt->txuflo++;
2758                         fatal = true;
2759                 }
2760
2761                 if (fatal) {
2762                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2763                         break;
2764                 } else
2765                         W_REG(&regs->intctrlregs[idx].intstatus,
2766                               intstatus);
2767         }
2768 }
2769
2770 void wlc_intrson(struct wlc_info *wlc)
2771 {
2772         struct wlc_hw_info *wlc_hw = wlc->hw;
2773         ASSERT(wlc->defmacintmask);
2774         wlc->macintmask = wlc->defmacintmask;
2775         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2776 }
2777
2778 /* callback for siutils.c, which has only wlc handler, no wl
2779  * they both check up, not only because there is no need to off/restore d11 interrupt
2780  *  but also because per-port code may require sync with valid interrupt.
2781  */
2782
2783 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2784 {
2785         if (!wlc->hw->up)
2786                 return 0;
2787
2788         return wl_intrsoff(wlc->wl);
2789 }
2790
2791 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2792 {
2793         if (!wlc->hw->up)
2794                 return;
2795
2796         wl_intrsrestore(wlc->wl, macintmask);
2797 }
2798
2799 u32 wlc_intrsoff(struct wlc_info *wlc)
2800 {
2801         struct wlc_hw_info *wlc_hw = wlc->hw;
2802         u32 macintmask;
2803
2804         if (!wlc_hw->clk)
2805                 return 0;
2806
2807         macintmask = wlc->macintmask;   /* isr can still happen */
2808
2809         W_REG(&wlc_hw->regs->macintmask, 0);
2810         (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2811         udelay(1);              /* ensure int line is no longer driven */
2812         wlc->macintmask = 0;
2813
2814         /* return previous macintmask; resolve race between us and our isr */
2815         return wlc->macintstatus ? 0 : macintmask;
2816 }
2817
2818 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2819 {
2820         struct wlc_hw_info *wlc_hw = wlc->hw;
2821         if (!wlc_hw->clk)
2822                 return;
2823
2824         wlc->macintmask = macintmask;
2825         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2826 }
2827
2828 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2829 {
2830         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2831
2832         if (on) {
2833                 /* suspend tx fifos */
2834                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2835                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2836                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2837                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2838
2839                 /* zero the address match register so we do not send ACKs */
2840                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2841                                        null_ether_addr);
2842         } else {
2843                 /* resume tx fifos */
2844                 if (!wlc_hw->wlc->tx_suspended) {
2845                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2846                 }
2847                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2848                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2849                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2850
2851                 /* Restore address */
2852                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2853                                        wlc_hw->etheraddr);
2854         }
2855
2856         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2857
2858         if (on)
2859                 wlc_ucode_mute_override_set(wlc_hw);
2860         else
2861                 wlc_ucode_mute_override_clear(wlc_hw);
2862 }
2863
2864 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2865 {
2866         if (fifo >= NFIFO)
2867                 return BCME_RANGE;
2868
2869         *blocks = wlc_hw->xmtfifo_sz[fifo];
2870
2871         return 0;
2872 }
2873
2874 /* wlc_bmac_tx_fifo_suspended:
2875  * Check the MAC's tx suspend status for a tx fifo.
2876  *
2877  * When the MAC acknowledges a tx suspend, it indicates that no more
2878  * packets will be transmitted out the radio. This is independent of
2879  * DMA channel suspension---the DMA may have finished suspending, or may still
2880  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2881  * request.
2882  */
2883 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2884 {
2885         /* check that a suspend has been requested and is no longer pending */
2886
2887         /*
2888          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2889          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2890          * chnstatus register.
2891          * The tx fifo suspend completion is independent of the DMA suspend completion and
2892          *   may be acked before or after the DMA is suspended.
2893          */
2894         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2895             (R_REG(&wlc_hw->regs->chnstatus) &
2896              (1 << tx_fifo)) == 0)
2897                 return true;
2898
2899         return false;
2900 }
2901
2902 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2903 {
2904         u8 fifo = 1 << tx_fifo;
2905
2906         /* Two clients of this code, 11h Quiet period and scanning. */
2907
2908         /* only suspend if not already suspended */
2909         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2910                 return;
2911
2912         /* force the core awake only if not already */
2913         if (wlc_hw->suspended_fifos == 0)
2914                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2915
2916         wlc_hw->suspended_fifos |= fifo;
2917
2918         if (wlc_hw->di[tx_fifo]) {
2919                 /* Suspending AMPDU transmissions in the middle can cause underflow
2920                  * which may result in mismatch between ucode and driver
2921                  * so suspend the mac before suspending the FIFO
2922                  */
2923                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2924                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
2925
2926                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2927
2928                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2929                         wlc_enable_mac(wlc_hw->wlc);
2930         }
2931 }
2932
2933 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2934 {
2935         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2936          * here for PIO otherwise the watchdog will catch the inconsistency and fire
2937          */
2938         /* Two clients of this code, 11h Quiet period and scanning. */
2939         if (wlc_hw->di[tx_fifo])
2940                 dma_txresume(wlc_hw->di[tx_fifo]);
2941
2942         /* allow core to sleep again */
2943         if (wlc_hw->suspended_fifos == 0)
2944                 return;
2945         else {
2946                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2947                 if (wlc_hw->suspended_fifos == 0)
2948                         wlc_ucode_wake_override_clear(wlc_hw,
2949                                                       WLC_WAKE_OVERRIDE_TXFIFO);
2950         }
2951 }
2952
2953 /*
2954  * Read and clear macintmask and macintstatus and intstatus registers.
2955  * This routine should be called with interrupts off
2956  * Return:
2957  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
2958  *   0 if the interrupt is not for us, or we are in some special cases;
2959  *   device interrupt status bits otherwise.
2960  */
2961 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2962 {
2963         struct wlc_hw_info *wlc_hw = wlc->hw;
2964         d11regs_t *regs = wlc_hw->regs;
2965         u32 macintstatus;
2966
2967         /* macintstatus includes a DMA interrupt summary bit */
2968         macintstatus = R_REG(&regs->macintstatus);
2969
2970         WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
2971
2972         /* detect cardbus removed, in power down(suspend) and in reset */
2973         if (DEVICEREMOVED(wlc))
2974                 return -1;
2975
2976         /* DEVICEREMOVED succeeds even when the core is still resetting,
2977          * handle that case here.
2978          */
2979         if (macintstatus == 0xffffffff)
2980                 return 0;
2981
2982         /* defer unsolicited interrupts */
2983         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2984
2985         /* if not for us */
2986         if (macintstatus == 0)
2987                 return 0;
2988
2989         /* interrupts are already turned off for CFE build
2990          * Caution: For CFE Turning off the interrupts again has some undesired
2991          * consequences
2992          */
2993         /* turn off the interrupts */
2994         W_REG(&regs->macintmask, 0);
2995         (void)R_REG(&regs->macintmask); /* sync readback */
2996         wlc->macintmask = 0;
2997
2998         /* clear device interrupts */
2999         W_REG(&regs->macintstatus, macintstatus);
3000
3001         /* MI_DMAINT is indication of non-zero intstatus */
3002         if (macintstatus & MI_DMAINT) {
3003                 /*
3004                  * only fifo interrupt enabled is I_RI in
3005                  * RX_FIFO. If MI_DMAINT is set, assume it
3006                  * is set and clear the interrupt.
3007                  */
3008                 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
3009                       DEF_RXINTMASK);
3010         }
3011
3012         return macintstatus;
3013 }
3014
3015 /* Update wlc->macintstatus and wlc->intstatus[]. */
3016 /* Return true if they are updated successfully. false otherwise */
3017 bool wlc_intrsupd(struct wlc_info *wlc)
3018 {
3019         u32 macintstatus;
3020
3021         ASSERT(wlc->macintstatus != 0);
3022
3023         /* read and clear macintstatus and intstatus registers */
3024         macintstatus = wlc_intstatus(wlc, false);
3025
3026         /* device is removed */
3027         if (macintstatus == 0xffffffff)
3028                 return false;
3029
3030         /* update interrupt status in software */
3031         wlc->macintstatus |= macintstatus;
3032
3033         return true;
3034 }
3035
3036 /*
3037  * First-level interrupt processing.
3038  * Return true if this was our interrupt, false otherwise.
3039  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3040  * false otherwise.
3041  */
3042 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3043 {
3044         struct wlc_hw_info *wlc_hw = wlc->hw;
3045         u32 macintstatus;
3046
3047         *wantdpc = false;
3048
3049         if (!wlc_hw->up || !wlc->macintmask)
3050                 return false;
3051
3052         /* read and clear macintstatus and intstatus registers */
3053         macintstatus = wlc_intstatus(wlc, true);
3054
3055         if (macintstatus == 0xffffffff)
3056                 WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
3057
3058         /* it is not for us */
3059         if (macintstatus == 0)
3060                 return false;
3061
3062         *wantdpc = true;
3063
3064         /* save interrupt status bits */
3065         ASSERT(wlc->macintstatus == 0);
3066         wlc->macintstatus = macintstatus;
3067
3068         return true;
3069
3070 }
3071
3072 static bool BCMFASTPATH
3073 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3074 {
3075         /* discard intermediate indications for ucode with one legitimate case:
3076          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3077          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3078          *   transmission count)
3079          */
3080         if (!(txs->status & TX_STATUS_AMPDU)
3081             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3082                 return false;
3083         }
3084
3085         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3086 }
3087
3088 /* process tx completion events in BMAC
3089  * Return true if more tx status need to be processed. false otherwise.
3090  */
3091 static bool BCMFASTPATH
3092 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3093 {
3094         bool morepending = false;
3095         struct wlc_info *wlc = wlc_hw->wlc;
3096         d11regs_t *regs;
3097         tx_status_t txstatus, *txs;
3098         u32 s1, s2;
3099         uint n = 0;
3100         /*
3101          * Param 'max_tx_num' indicates max. # tx status to process before
3102          * break out.
3103          */
3104         uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3105
3106         WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3107
3108         txs = &txstatus;
3109         regs = wlc_hw->regs;
3110         while (!(*fatal)
3111                && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
3112
3113                 if (s1 == 0xffffffff) {
3114                         WL_ERROR("wl%d: %s: dead chip\n",
3115                                 wlc_hw->unit, __func__);
3116                         ASSERT(s1 != 0xffffffff);
3117                         return morepending;
3118                 }
3119
3120                         s2 = R_REG(&regs->frmtxstatus2);
3121
3122                 txs->status = s1 & TXS_STATUS_MASK;
3123                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3124                 txs->sequence = s2 & TXS_SEQ_MASK;
3125                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3126                 txs->lasttxtime = 0;
3127
3128                 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3129
3130                 /* !give others some time to run! */
3131                 if (++n >= max_tx_num)
3132                         break;
3133         }
3134
3135         if (*fatal)
3136                 return 0;
3137
3138         if (n >= max_tx_num)
3139                 morepending = true;
3140
3141         if (!pktq_empty(&wlc->active_queue->q))
3142                 wlc_send_q(wlc, wlc->active_queue);
3143
3144         return morepending;
3145 }
3146
3147 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3148 {
3149         struct wlc_hw_info *wlc_hw = wlc->hw;
3150         d11regs_t *regs = wlc_hw->regs;
3151         u32 mc, mi;
3152
3153         WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3154                  wlc_hw->unit, wlc_hw->band->bandunit);
3155
3156         /*
3157          * Track overlapping suspend requests
3158          */
3159         wlc_hw->mac_suspend_depth++;
3160         if (wlc_hw->mac_suspend_depth > 1)
3161                 return;
3162
3163         /* force the core awake */
3164         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3165
3166         mc = R_REG(&regs->maccontrol);
3167
3168         if (mc == 0xffffffff) {
3169                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3170                 wl_down(wlc->wl);
3171                 return;
3172         }
3173         ASSERT(!(mc & MCTL_PSM_JMP_0));
3174         ASSERT(mc & MCTL_PSM_RUN);
3175         ASSERT(mc & MCTL_EN_MAC);
3176
3177         mi = R_REG(&regs->macintstatus);
3178         if (mi == 0xffffffff) {
3179                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3180                 wl_down(wlc->wl);
3181                 return;
3182         }
3183         ASSERT(!(mi & MI_MACSSPNDD));
3184
3185         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3186
3187         SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3188                  WLC_MAX_MAC_SUSPEND);
3189
3190         if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3191                 WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
3192                          wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3193                 WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
3194                          wlc_hw->unit,
3195                          R_REG(&regs->psmdebug),
3196                          R_REG(&regs->phydebug),
3197                          R_REG(&regs->psm_brc));
3198         }
3199
3200         mc = R_REG(&regs->maccontrol);
3201         if (mc == 0xffffffff) {
3202                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3203                 wl_down(wlc->wl);
3204                 return;
3205         }
3206         ASSERT(!(mc & MCTL_PSM_JMP_0));
3207         ASSERT(mc & MCTL_PSM_RUN);
3208         ASSERT(!(mc & MCTL_EN_MAC));
3209 }
3210
3211 void wlc_enable_mac(struct wlc_info *wlc)
3212 {
3213         struct wlc_hw_info *wlc_hw = wlc->hw;
3214         d11regs_t *regs = wlc_hw->regs;
3215         u32 mc, mi;
3216
3217         WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3218                  wlc_hw->unit, wlc->band->bandunit);
3219
3220         /*
3221          * Track overlapping suspend requests
3222          */
3223         ASSERT(wlc_hw->mac_suspend_depth > 0);
3224         wlc_hw->mac_suspend_depth--;
3225         if (wlc_hw->mac_suspend_depth > 0)
3226                 return;
3227
3228         mc = R_REG(&regs->maccontrol);
3229         ASSERT(!(mc & MCTL_PSM_JMP_0));
3230         ASSERT(!(mc & MCTL_EN_MAC));
3231         ASSERT(mc & MCTL_PSM_RUN);
3232
3233         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3234         W_REG(&regs->macintstatus, MI_MACSSPNDD);
3235
3236         mc = R_REG(&regs->maccontrol);
3237         ASSERT(!(mc & MCTL_PSM_JMP_0));
3238         ASSERT(mc & MCTL_EN_MAC);
3239         ASSERT(mc & MCTL_PSM_RUN);
3240
3241         mi = R_REG(&regs->macintstatus);
3242         ASSERT(!(mi & MI_MACSSPNDD));
3243
3244         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3245 }
3246
3247 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3248 {
3249         u8 rate;
3250         u8 rates[8] = {
3251                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3252                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3253         };
3254         u16 entry_ptr;
3255         u16 pctl1;
3256         uint i;
3257
3258         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3259                 return;
3260
3261         /* walk the phy rate table and update the entries */
3262         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3263                 rate = rates[i];
3264
3265                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3266
3267                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3268                 pctl1 =
3269                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3270
3271                 /* modify the value */
3272                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3273                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3274
3275                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3276                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3277                                    pctl1);
3278         }
3279 }
3280
3281 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3282 {
3283         uint i;
3284         u8 plcp_rate = 0;
3285         struct plcp_signal_rate_lookup {
3286                 u8 rate;
3287                 u8 signal_rate;
3288         };
3289         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3290         const struct plcp_signal_rate_lookup rate_lookup[] = {
3291                 {WLC_RATE_6M, 0xB},
3292                 {WLC_RATE_9M, 0xF},
3293                 {WLC_RATE_12M, 0xA},
3294                 {WLC_RATE_18M, 0xE},
3295                 {WLC_RATE_24M, 0x9},
3296                 {WLC_RATE_36M, 0xD},
3297                 {WLC_RATE_48M, 0x8},
3298                 {WLC_RATE_54M, 0xC}
3299         };
3300
3301         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3302                 if (rate == rate_lookup[i].rate) {
3303                         plcp_rate = rate_lookup[i].signal_rate;
3304                         break;
3305                 }
3306         }
3307
3308         /* Find the SHM pointer to the rate table entry by looking in the
3309          * Direct-map Table
3310          */
3311         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3312 }
3313
3314 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3315 {
3316         wlc_hw->hw_stf_ss_opmode = stf_mode;
3317
3318         if (wlc_hw->clk)
3319                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3320 }
3321
3322 void BCMFASTPATH
3323 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3324                   u32 *tsf_h_ptr)
3325 {
3326         d11regs_t *regs = wlc_hw->regs;
3327
3328         /* read the tsf timer low, then high to get an atomic read */
3329         *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3330         *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3331
3332         return;
3333 }
3334
3335 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3336 {
3337         d11regs_t *regs;
3338         u32 w, val;
3339
3340         WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3341
3342         regs = wlc_hw->regs;
3343
3344         /* Validate dchip register access */
3345
3346         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3347         (void)R_REG(&regs->objaddr);
3348         w = R_REG(&regs->objdata);
3349
3350         /* Can we write and read back a 32bit register? */
3351         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3352         (void)R_REG(&regs->objaddr);
3353         W_REG(&regs->objdata, (u32) 0xaa5555aa);
3354
3355         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3356         (void)R_REG(&regs->objaddr);
3357         val = R_REG(&regs->objdata);
3358         if (val != (u32) 0xaa5555aa) {
3359                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
3360                          wlc_hw->unit, val);
3361                 return false;
3362         }
3363
3364         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3365         (void)R_REG(&regs->objaddr);
3366         W_REG(&regs->objdata, (u32) 0x55aaaa55);
3367
3368         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3369         (void)R_REG(&regs->objaddr);
3370         val = R_REG(&regs->objdata);
3371         if (val != (u32) 0x55aaaa55) {
3372                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
3373                          wlc_hw->unit, val);
3374                 return false;
3375         }
3376
3377         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3378         (void)R_REG(&regs->objaddr);
3379         W_REG(&regs->objdata, w);
3380
3381         /* clear CFPStart */
3382         W_REG(&regs->tsf_cfpstart, 0);
3383
3384         w = R_REG(&regs->maccontrol);
3385         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3386             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3387                 WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
3388                          wlc_hw->unit, w,
3389                          (MCTL_IHR_EN | MCTL_WAKE),
3390                          (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3391                 return false;
3392         }
3393
3394         return true;
3395 }
3396
3397 #define PHYPLL_WAIT_US  100000
3398
3399 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3400 {
3401         d11regs_t *regs;
3402         u32 tmp;
3403
3404         WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3405
3406         tmp = 0;
3407         regs = wlc_hw->regs;
3408
3409         if (on) {
3410                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3411                         OR_REG(&regs->clk_ctl_st,
3412                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3413                                 CCS_ERSRC_REQ_PHYPLL));
3414                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3415                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3416                                  PHYPLL_WAIT_US);
3417
3418                         tmp = R_REG(&regs->clk_ctl_st);
3419                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3420                             (CCS_ERSRC_AVAIL_HT)) {
3421                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3422                                          __func__);
3423                                 ASSERT(0);
3424                         }
3425                 } else {
3426                         OR_REG(&regs->clk_ctl_st,
3427                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3428                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3429                                   (CCS_ERSRC_AVAIL_D11PLL |
3430                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3431                                  (CCS_ERSRC_AVAIL_D11PLL |
3432                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3433
3434                         tmp = R_REG(&regs->clk_ctl_st);
3435                         if ((tmp &
3436                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3437                             !=
3438                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3439                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3440                                          __func__);
3441                                 ASSERT(0);
3442                         }
3443                 }
3444         } else {
3445                 /* Since the PLL may be shared, other cores can still be requesting it;
3446                  * so we'll deassert the request but not wait for status to comply.
3447                  */
3448                 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3449                 tmp = R_REG(&regs->clk_ctl_st);
3450         }
3451 }
3452
3453 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3454 {
3455         bool dev_gone;
3456
3457         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3458
3459         ASSERT(!wlc_hw->up);
3460
3461         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3462
3463         if (dev_gone)
3464                 return;
3465
3466         if (wlc_hw->noreset)
3467                 return;
3468
3469         /* radio off */
3470         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3471
3472         /* turn off analog core */
3473         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3474
3475         /* turn off PHYPLL to save power */
3476         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3477
3478         /* No need to set wlc->pub->radio_active = OFF
3479          * because this function needs down capability and
3480          * radio_active is designed for BCMNODOWN.
3481          */
3482
3483         /* remove gpio controls */
3484         if (wlc_hw->ucode_dbgsel)
3485                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3486
3487         wlc_hw->clk = false;
3488         si_core_disable(wlc_hw->sih, 0);
3489         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3490 }
3491
3492 /* power both the pll and external oscillator on/off */
3493 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3494 {
3495         WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3496
3497         /* dont power down if plldown is false or we must poll hw radio disable */
3498         if (!want && wlc_hw->pllreq)
3499                 return;
3500
3501         if (wlc_hw->sih)
3502                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3503
3504         wlc_hw->sbclk = want;
3505         if (!wlc_hw->sbclk) {
3506                 wlc_hw->clk = false;
3507                 if (wlc_hw->band && wlc_hw->band->pi)
3508                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3509         }
3510 }
3511
3512 static void wlc_flushqueues(struct wlc_info *wlc)
3513 {
3514         struct wlc_hw_info *wlc_hw = wlc->hw;
3515         uint i;
3516
3517         wlc->txpend16165war = 0;
3518
3519         /* free any posted tx packets */
3520         for (i = 0; i < NFIFO; i++)
3521                 if (wlc_hw->di[i]) {
3522                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3523                         TXPKTPENDCLR(wlc, i);
3524                         WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3525                                  i);
3526                 }
3527
3528         /* free any posted rx packets */
3529         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3530 }
3531
3532 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3533 {
3534         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3535 }
3536
3537 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3538 {
3539         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3540 }
3541
3542 /* Set a range of shared memory to a value.
3543  * SHM 'offset' needs to be an even address and
3544  * Buffer length 'len' must be an even number of bytes
3545  */
3546 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3547 {
3548         int i;
3549
3550         /* offset and len need to be even */
3551         ASSERT((offset & 1) == 0);
3552         ASSERT((len & 1) == 0);
3553
3554         if (len <= 0)
3555                 return;
3556
3557         for (i = 0; i < len; i += 2) {
3558                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3559         }
3560 }
3561
3562 static u16
3563 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3564 {
3565         d11regs_t *regs = wlc_hw->regs;
3566         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3567         volatile u16 *objdata_hi = objdata_lo + 1;
3568         u16 v;
3569
3570         ASSERT((offset & 1) == 0);
3571
3572         W_REG(&regs->objaddr, sel | (offset >> 2));
3573         (void)R_REG(&regs->objaddr);
3574         if (offset & 2) {
3575                 v = R_REG(objdata_hi);
3576         } else {
3577                 v = R_REG(objdata_lo);
3578         }
3579
3580         return v;
3581 }
3582
3583 static void
3584 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3585 {
3586         d11regs_t *regs = wlc_hw->regs;
3587         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3588         volatile u16 *objdata_hi = objdata_lo + 1;
3589
3590         ASSERT((offset & 1) == 0);
3591
3592         W_REG(&regs->objaddr, sel | (offset >> 2));
3593         (void)R_REG(&regs->objaddr);
3594         if (offset & 2) {
3595                 W_REG(objdata_hi, v);
3596         } else {
3597                 W_REG(objdata_lo, v);
3598         }
3599 }
3600
3601 /* Copy a buffer to shared memory of specified type .
3602  * SHM 'offset' needs to be an even address and
3603  * Buffer length 'len' must be an even number of bytes
3604  * 'sel' selects the type of memory
3605  */
3606 void
3607 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3608                        int len, u32 sel)
3609 {
3610         u16 v;
3611         const u8 *p = (const u8 *)buf;
3612         int i;
3613
3614         /* offset and len need to be even */
3615         ASSERT((offset & 1) == 0);
3616         ASSERT((len & 1) == 0);
3617
3618         if (len <= 0)
3619                 return;
3620
3621         for (i = 0; i < len; i += 2) {
3622                 v = p[i] | (p[i + 1] << 8);
3623                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3624         }
3625 }
3626
3627 /* Copy a piece of shared memory of specified type to a buffer .
3628  * SHM 'offset' needs to be an even address and
3629  * Buffer length 'len' must be an even number of bytes
3630  * 'sel' selects the type of memory
3631  */
3632 void
3633 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3634                          int len, u32 sel)
3635 {
3636         u16 v;
3637         u8 *p = (u8 *) buf;
3638         int i;
3639
3640         /* offset and len need to be even */
3641         ASSERT((offset & 1) == 0);
3642         ASSERT((len & 1) == 0);
3643
3644         if (len <= 0)
3645                 return;
3646
3647         for (i = 0; i < len; i += 2) {
3648                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3649                 p[i] = v & 0xFF;
3650                 p[i + 1] = (v >> 8) & 0xFF;
3651         }
3652 }
3653
3654 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3655 {
3656         WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3657                  wlc_hw->vars_size);
3658
3659         *buf = wlc_hw->vars;
3660         *len = wlc_hw->vars_size;
3661 }
3662
3663 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3664 {
3665         wlc_hw->SRL = SRL;
3666         wlc_hw->LRL = LRL;
3667
3668         /* write retry limit to SCR, shouldn't need to suspend */
3669         if (wlc_hw->up) {
3670                 W_REG(&wlc_hw->regs->objaddr,
3671                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3672                 (void)R_REG(&wlc_hw->regs->objaddr);
3673                 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3674                 W_REG(&wlc_hw->regs->objaddr,
3675                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3676                 (void)R_REG(&wlc_hw->regs->objaddr);
3677                 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3678         }
3679 }
3680
3681 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3682 {
3683         wlc_hw->noreset = noreset_flag;
3684 }
3685
3686 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3687 {
3688         ASSERT(req_bit);
3689
3690         if (set) {
3691                 if (mboolisset(wlc_hw->pllreq, req_bit))
3692                         return;
3693
3694                 mboolset(wlc_hw->pllreq, req_bit);
3695
3696                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3697                         if (!wlc_hw->sbclk) {
3698                                 wlc_bmac_xtal(wlc_hw, ON);
3699                         }
3700                 }
3701         } else {
3702                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3703                         return;
3704
3705                 mboolclr(wlc_hw->pllreq, req_bit);
3706
3707                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3708                         if (wlc_hw->sbclk) {
3709                                 wlc_bmac_xtal(wlc_hw, OFF);
3710                         }
3711                 }
3712         }
3713
3714         return;
3715 }
3716
3717 /* this will be true for all ai chips */
3718 bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
3719 {
3720         return true;
3721 }
3722
3723 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3724 {
3725         u16 table_ptr;
3726         u8 phy_rate, index;
3727
3728         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3729         /* XXX4321 fixup needed ? */
3730         if (IS_OFDM(rate))
3731                 table_ptr = M_RT_DIRMAP_A;
3732         else
3733                 table_ptr = M_RT_DIRMAP_B;
3734
3735         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3736          * the index into the rate table.
3737          */
3738         phy_rate = rate_info[rate] & RATE_MASK;
3739         index = phy_rate & 0xf;
3740
3741         /* Find the SHM pointer to the rate table entry by looking in the
3742          * Direct-map Table
3743          */
3744         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3745 }
3746
3747 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3748 {
3749         wlc_hw->antsel_avail = antsel_avail;
3750 }