2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _BRCM_TYPES_H_
18 #define _BRCM_TYPES_H_
20 #include <linux/types.h>
23 #define WL_CHAN_FREQ_RANGE_2G 0
24 #define WL_CHAN_FREQ_RANGE_5GL 1
25 #define WL_CHAN_FREQ_RANGE_5GM 2
26 #define WL_CHAN_FREQ_RANGE_5GH 3
28 #define MAX_DMA_SEGS 4
32 /* Board has gpio 9 controlling the PA */
33 #define BFL_PACTRL 0x00000002
34 /* Not ok to power down the chip pll and oscillator */
35 #define BFL_NOPLLDOWN 0x00000020
36 /* Board supports the Front End Module */
37 #define BFL_FEM 0x00000800
38 /* Board has an external LNA in 2.4GHz band */
39 #define BFL_EXTLNA 0x00001000
41 #define BFL_NOPA 0x00010000
42 /* Power topology uses BUCKBOOST */
43 #define BFL_BUCKBOOST 0x00200000
44 /* Board has FEM and switch to share antenna w/ BT */
45 #define BFL_FEM_BT 0x00400000
46 /* Power topology doesn't use CBUCK */
47 #define BFL_NOCBUCK 0x00800000
48 /* Power topology uses PALDO */
49 #define BFL_PALDO 0x02000000
50 /* Board has an external LNA in 5GHz band */
51 #define BFL_EXTLNA_5GHz 0x10000000
55 /* Board has an external rxbb regulator */
56 #define BFL2_RXBB_INT_REG_DIS 0x00000001
57 /* Flag to implement alternative A-band PLL settings */
58 #define BFL2_APLL_WAR 0x00000002
59 /* Board permits enabling TX Power Control */
60 #define BFL2_TXPWRCTRL_EN 0x00000004
61 /* Board supports the 2X4 diversity switch */
62 #define BFL2_2X4_DIV 0x00000008
63 /* Board supports 5G band power gain */
64 #define BFL2_5G_PWRGAIN 0x00000010
65 /* Board overrides ASPM and Clkreq settings */
66 #define BFL2_PCIEWAR_OVR 0x00000020
67 #define BFL2_LEGACY 0x00000080
68 /* 4321mcm93 board uses Skyworks FEM */
69 #define BFL2_SKWRKFEM_BRD 0x00000100
70 /* Board has a WAR for clock-harmonic spurs */
71 #define BFL2_SPUR_WAR 0x00000200
72 /* Flag to narrow G-band PLL loop b/w */
73 #define BFL2_GPLL_WAR 0x00000400
74 /* Tx CCK pkts on Ant 0 only */
75 #define BFL2_SINGLEANT_CCK 0x00001000
76 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
77 #define BFL2_2G_SPUR_WAR 0x00002000
78 /* Flag to widen G-band PLL loop b/w */
79 #define BFL2_GPLL_WAR2 0x00010000
80 #define BFL2_IPALVLSHIFT_3P3 0x00020000
81 /* Use internal envelope detector for TX IQCAL */
82 #define BFL2_INTERNDET_TXIQCAL 0x00040000
83 /* Keep the buffered Xtal output from radio "ON". Most drivers will turn it
84 * off without this flag to save power. */
85 #define BFL2_XTALBUFOUTEN 0x00080000
88 * board specific GPIO assignment, gpio 0-3 are also customer-configurable
92 /* bit 9 controls the PA on new 4306 boards */
93 #define BOARD_GPIO_PACTRL 0x200
94 #define BOARD_GPIO_12 0x1000
95 #define BOARD_GPIO_13 0x2000
97 /* **** Core type/rev defaults **** */
98 #define D11CONF 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
99 * also need to update wlc.h MAXCOREREV
102 #define NCONF 0x000001ff /* Supported nphy revs:
114 #define LCNCONF 0x00000007 /* Supported lcnphy revs:
115 * 0 4313a0, 4336a0, 4330a0
120 #define SSLPNCONF 0x0000000f /* Supported sslpnphy revs:
127 /********************************************************************
128 * Phy/Core Configuration. Defines macros to to check core phy/rev *
129 * compile-time configuration. Defines default core support. *
130 * ******************************************************************
133 /* Basic macros to check a configuration bitmask */
135 #define CONF_HAS(config, val) ((config) & (1 << (val)))
136 #define CONF_MSK(config, mask) ((config) & (mask))
137 #define MSK_RANGE(low, hi) ((1 << ((hi)+1)) - (1 << (low)))
138 #define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
140 #define CONF_IS(config, val) ((config) == (1 << (val)))
141 #define CONF_GE(config, val) ((config) & (0-(1 << (val))))
142 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
143 #define CONF_LT(config, val) ((config) & ((1 << (val))-1))
144 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1))
146 /* Wrappers for some of the above, specific to config constants */
148 #define NCONF_HAS(val) CONF_HAS(NCONF, val)
149 #define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
150 #define NCONF_IS(val) CONF_IS(NCONF, val)
151 #define NCONF_GE(val) CONF_GE(NCONF, val)
152 #define NCONF_GT(val) CONF_GT(NCONF, val)
153 #define NCONF_LT(val) CONF_LT(NCONF, val)
154 #define NCONF_LE(val) CONF_LE(NCONF, val)
156 #define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val)
157 #define LCNCONF_MSK(mask) CONF_MSK(LCNCONF, mask)
158 #define LCNCONF_IS(val) CONF_IS(LCNCONF, val)
159 #define LCNCONF_GE(val) CONF_GE(LCNCONF, val)
160 #define LCNCONF_GT(val) CONF_GT(LCNCONF, val)
161 #define LCNCONF_LT(val) CONF_LT(LCNCONF, val)
162 #define LCNCONF_LE(val) CONF_LE(LCNCONF, val)
164 #define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
165 #define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
166 #define D11CONF_IS(val) CONF_IS(D11CONF, val)
167 #define D11CONF_GE(val) CONF_GE(D11CONF, val)
168 #define D11CONF_GT(val) CONF_GT(D11CONF, val)
169 #define D11CONF_LT(val) CONF_LT(D11CONF, val)
170 #define D11CONF_LE(val) CONF_LE(D11CONF, val)
172 #define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
173 #define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
175 #define NREV_IS(var, val) \
176 (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
178 #define NREV_GE(var, val) \
179 (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
181 #define NREV_GT(var, val) \
182 (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
184 #define NREV_LT(var, val) \
185 (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
187 #define NREV_LE(var, val) \
188 (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
190 #define LCNREV_IS(var, val) \
191 (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
193 #define LCNREV_GE(var, val) \
194 (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
196 #define LCNREV_GT(var, val) \
197 (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
199 #define LCNREV_LT(var, val) \
200 (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
202 #define LCNREV_LE(var, val) \
203 (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
205 #define D11REV_IS(var, val) \
206 (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
208 #define D11REV_GE(var, val) \
209 (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
211 #define D11REV_GT(var, val) \
212 (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
214 #define D11REV_LT(var, val) \
215 (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
217 #define D11REV_LE(var, val) \
218 (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
220 #define PHYTYPE_IS(var, val)\
221 (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
223 /* Finally, early-exit from switch case if anyone wants it... */
225 #define CASECHECK(config, val) if (!(CONF_HAS(config, val))) break
226 #define CASEMSK(config, mask) if (!(CONF_MSK(config, mask))) break
228 /* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
230 #define _PHYCONF_N (1 << PHY_TYPE_N)
231 #define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
232 #define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
234 #define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
236 /* Utility macro to identify 802.11n (HT) capable PHYs */
237 #define PHYTYPE_11N_CAP(phytype) \
238 (PHYTYPE_IS(phytype, PHY_TYPE_N) || \
239 PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
240 PHYTYPE_IS(phytype, PHY_TYPE_SSN))
242 /* Last but not least: shorter wlc-specific var checks */
243 #define BRCMS_ISNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
244 #define BRCMS_ISLCNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
245 #define BRCMS_ISSSLPNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
247 #define BRCMS_PHY_11N_CAP(band) PHYTYPE_11N_CAP((band)->phytype)
249 /**********************************************************************
250 * ------------- End of Core phy/rev configuration. ----------------- *
251 * ********************************************************************
254 /*************************************************
255 * Defaults for tunables (e.g. sizing constants)
257 * For each new tunable, add a member to the end
258 * of struct brcms_tunables in brcms_c_pub.h to enable
259 * runtime checks of tunable values. (Directly
260 * using the macros in code invalidates ROM code)
262 * ***********************************************
265 /* Max # of entries in Tx FIFO based on 4kb page size */
267 /* Max # of entries in Rx FIFO based on 4kb page size */
269 /* try to keep this # rbufs posted to the chip */
270 #define NRXBUFPOST 32
271 /* Maximum SCBs in cache for STA */
274 /* max allowed number of mpdus in an ampdu (2 streams) */
275 #define AMPDU_NUM_MPDU 16
277 /* Count of packet callback structures. either of following
278 * 1. Set to the number of SCBs since a STA
279 * can queue up a rate callback for each IBSS STA it knows about, and an AP can
280 * queue up an "are you there?" Null Data callback for each associated STA
281 * 2. controlled by tunable config file
283 #define MAXPKTCB MAXSCB /* Max number of packet callbacks */
285 /* NetBSD also needs to keep track of this */
287 /* Number of BSS handled in ucode bcn/prb */
288 #define BRCMS_MAX_UCODE_BSS (16)
289 /* Number of BSS handled in sw bcn/prb */
290 #define BRCMS_MAX_UCODE_BSS4 (4)
291 /* max # BSS configs */
292 #define BRCMS_MAXBSSCFG (1)
293 /* max # available networks */
295 /* data msg txq hiwat mark */
296 #define BRCMS_DATAHIWAT 50
297 #define BRCMS_AMPDUDATAHIWAT 255
299 /* bounded rx loops */
300 #define RXBND 8 /* max # frames to process in brcms_c_recv() */
301 #define TXSBND 8 /* max # tx status to process in wlc_txstatus() */
303 #define BAND_5G(bt) ((bt) == BRCM_BAND_5G)
304 #define BAND_2G(bt) ((bt) == BRCM_BAND_2G)
306 #define BCMMSG(dev, fmt, args...) \
308 if (brcm_msg_level & LOG_TRACE_VAL) \
309 wiphy_err(dev, "%s: " fmt, __func__, ##args); \
312 #define WL_ERROR_ON() (brcm_msg_level & LOG_ERROR_VAL)
315 * Register access macros.
317 * These macro's take a pointer to the address to read as one of their
318 * arguments. The macro itself deduces the size of the IO transaction (u8, u16
319 * or u32). Advantage of this approach in combination with using a struct to
320 * define the registers in a register block, is that access size and access
321 * location are defined in only one spot. This reduces the risk of the
322 * programmer trying to use an unsupported transaction size on a register.
328 __typeof(*(r)) __osl_v; \
329 switch (sizeof(*(r))) { \
331 __osl_v = readb((u8 *)(r)); \
334 __osl_v = readw((u16 *)(r)); \
337 __osl_v = readl((u32 *)(r)); \
343 #define W_REG(r, v) do { \
344 switch (sizeof(*(r))) { \
346 writeb((u8)(v), (u8 *)(r)); \
349 writew((u16)(v), (u16 *)(r)); \
352 writel((u32)(v), (u32 *)(r)); \
357 #ifdef CONFIG_BCM47XX
359 * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
360 * transactions. As a fix, a read after write is performed on certain places
361 * in the code. Older chips and the newer 5357 family don't require this fix.
363 #define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
365 #define W_REG_FLUSH(r, v) W_REG((r), (v))
366 #endif /* CONFIG_BCM47XX */
368 #define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
369 #define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
371 #define SET_REG(r, mask, val) \
372 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
374 /* multi-bool data type: set of bools, mbool is true if any is set */
377 #define mboolset(mb, bit) ((mb) |= (bit))
379 #define mboolclr(mb, bit) ((mb) &= ~(bit))
380 /* true if one bool is set */
381 #define mboolisset(mb, bit) (((mb) & (bit)) != 0)
382 #define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
384 /* forward declarations */
386 struct ieee80211_sta;
387 struct ieee80211_tx_queue_params;
390 struct brcms_hardware;
394 struct brcms_txq_info;
400 struct brcms_d11rxhdr;
403 /* brcm_msg_level is a bit vector with defs in defs.h */
404 extern u32 brcm_msg_level;
406 #endif /* _BRCM_TYPES_H_ */