2 * Copyright (c) 2011 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _BRCM_AIUTILS_H_
18 #define _BRCM_AIUTILS_H_
23 * SOC Interconnect Address Map.
24 * All regions may not exist on all chips.
27 #define SI_SDRAM_BASE 0x00000000
28 /* Host Mode sb2pcitranslation0 (64 MB) */
29 #define SI_PCI_MEM 0x08000000
30 #define SI_PCI_MEM_SZ (64 * 1024 * 1024)
31 /* Host Mode sb2pcitranslation1 (64 MB) */
32 #define SI_PCI_CFG 0x0c000000
33 /* Region 2 for sdram (512 MB) */
34 #define SI_SDRAM_R2 0x80000000
36 /* Wrapper space base */
37 #define SI_WRAP_BASE 0x18100000
38 /* each core gets 4Kbytes for registers */
39 #define SI_CORE_SIZE 0x1000
41 * Max cores (this is arbitrary, for software
42 * convenience and could be changed if we
43 * make any larger chips
45 #define SI_MAXCORES 16
47 /* On-chip RAM on chips that also have DDR */
48 #define SI_FASTRAM 0x19000000
49 #define SI_FASTRAM_SWAPPED 0x19800000
51 /* Flash Region 2 (region 1 shadowed here) */
52 #define SI_FLASH2 0x1c000000
53 /* Size of Flash Region 2 */
54 #define SI_FLASH2_SZ 0x02000000
55 /* ARM Cortex-M3 ROM */
56 #define SI_ARMCM3_ROM 0x1e000000
57 /* MIPS Flash Region 1 */
58 #define SI_FLASH1 0x1fc00000
59 /* MIPS Size of Flash Region 1 */
60 #define SI_FLASH1_SZ 0x00400000
62 #define SI_ARM7S_ROM 0x20000000
63 /* ARM Cortex-M3 SRAM Region 2 */
64 #define SI_ARMCM3_SRAM2 0x60000000
65 /* ARM7TDMI-S SRAM Region 2 */
66 #define SI_ARM7S_SRAM2 0x80000000
67 /* ARM Flash Region 1 */
68 #define SI_ARM_FLASH1 0xffff0000
69 /* ARM Size of Flash Region 1 */
70 #define SI_ARM_FLASH1_SZ 0x00010000
72 /* Client Mode sb2pcitranslation2 (1 GB) */
73 #define SI_PCI_DMA 0x40000000
74 /* Client Mode sb2pcitranslation2 (1 GB) */
75 #define SI_PCI_DMA2 0x80000000
76 /* Client Mode sb2pcitranslation2 size in bytes */
77 #define SI_PCI_DMA_SZ 0x40000000
78 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
79 #define SI_PCIE_DMA_L32 0x00000000
80 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
81 #define SI_PCIE_DMA_H32 0x80000000
84 #define NODEV_CORE_ID 0x700 /* Invalid coreid */
85 #define CC_CORE_ID 0x800 /* chipcommon core */
86 #define ILINE20_CORE_ID 0x801 /* iline20 core */
87 #define SRAM_CORE_ID 0x802 /* sram core */
88 #define SDRAM_CORE_ID 0x803 /* sdram core */
89 #define PCI_CORE_ID 0x804 /* pci core */
90 #define MIPS_CORE_ID 0x805 /* mips core */
91 #define ENET_CORE_ID 0x806 /* enet mac core */
92 #define CODEC_CORE_ID 0x807 /* v90 codec core */
93 #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
94 #define ADSL_CORE_ID 0x809 /* ADSL core */
95 #define ILINE100_CORE_ID 0x80a /* iline100 core */
96 #define IPSEC_CORE_ID 0x80b /* ipsec core */
97 #define UTOPIA_CORE_ID 0x80c /* utopia core */
98 #define PCMCIA_CORE_ID 0x80d /* pcmcia core */
99 #define SOCRAM_CORE_ID 0x80e /* internal memory core */
100 #define MEMC_CORE_ID 0x80f /* memc sdram core */
101 #define OFDM_CORE_ID 0x810 /* OFDM phy core */
102 #define EXTIF_CORE_ID 0x811 /* external interface core */
103 #define D11_CORE_ID 0x812 /* 802.11 MAC core */
104 #define APHY_CORE_ID 0x813 /* 802.11a phy core */
105 #define BPHY_CORE_ID 0x814 /* 802.11b phy core */
106 #define GPHY_CORE_ID 0x815 /* 802.11g phy core */
107 #define MIPS33_CORE_ID 0x816 /* mips3302 core */
108 #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
109 #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
110 #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
111 #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
112 #define SDIOH_CORE_ID 0x81b /* sdio host core */
113 #define ROBO_CORE_ID 0x81c /* roboswitch core */
114 #define ATA100_CORE_ID 0x81d /* parallel ATA core */
115 #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
116 #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
117 #define PCIE_CORE_ID 0x820 /* pci express core */
118 #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
119 #define SRAMC_CORE_ID 0x822 /* SRAM controller core */
120 #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
121 #define ARM11_CORE_ID 0x824 /* ARM 1176 core */
122 #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
123 #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
124 #define PMU_CORE_ID 0x827 /* PMU core */
125 #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
126 #define SDIOD_CORE_ID 0x829 /* SDIO device core */
127 #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
128 #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
129 #define MIPS74K_CORE_ID 0x82c /* mips 74k core */
130 #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
131 #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
132 #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
133 #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
134 #define SC_CORE_ID 0x831 /* shared common core */
135 #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
136 #define SPIH_CORE_ID 0x833 /* SPI host core */
137 #define I2S_CORE_ID 0x834 /* I2S core */
138 #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
139 #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
140 #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
141 #define DEF_AI_COMP 0xfff /* Default component, in ai chips it
142 * maps all unused address ranges
145 /* chipcommon being the first core: */
148 /* SOC Interconnect types (aka chip types) */
151 /* Common core control flags */
152 #define SICF_BIST_EN 0x8000
153 #define SICF_PME_EN 0x4000
154 #define SICF_CORE_BITS 0x3ffc
155 #define SICF_FGC 0x0002
156 #define SICF_CLOCK_EN 0x0001
158 /* Common core status flags */
159 #define SISF_BIST_DONE 0x8000
160 #define SISF_BIST_ERROR 0x4000
161 #define SISF_GATED_CLK 0x2000
162 #define SISF_DMA64 0x1000
163 #define SISF_CORE_BITS 0x0fff
165 /* A register that is common to all cores to
166 * communicate w/PMU regarding clock control.
168 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
170 /* clk_ctl_st register */
171 #define CCS_FORCEALP 0x00000001 /* force ALP request */
172 #define CCS_FORCEHT 0x00000002 /* force HT request */
173 #define CCS_FORCEILP 0x00000004 /* force ILP request */
174 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
175 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
176 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
177 #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
178 #define CCS_ERSRC_REQ_SHIFT 8
179 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */
180 #define CCS_HTAVAIL 0x00020000 /* HT is available */
181 #define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
182 #define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
183 #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
184 #define CCS_ERSRC_STS_SHIFT 24
186 /* HT avail in chipc and pcmcia on 4328a0 */
187 #define CCS0_HTAVAIL 0x00010000
188 /* ALP avail in chipc and pcmcia on 4328a0 */
189 #define CCS0_ALPAVAIL 0x00020000
191 /* Not really related to SOC Interconnect, but a couple of software
192 * conventions for the use the flash space:
195 /* Minumum amount of flash we support */
196 #define FLASH_MIN 0x00020000 /* Minimum flash size */
198 /* A boot/binary may have an embedded block that describes its size */
199 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
200 #define BISZ_MAGIC 0x4249535a /* Marked with value: 'BISZ' */
201 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */
202 #define BISZ_TXTST_IDX 1 /* 1: text start */
203 #define BISZ_TXTEND_IDX 2 /* 2: text end */
204 #define BISZ_DATAST_IDX 3 /* 3: data start */
205 #define BISZ_DATAEND_IDX 4 /* 4: data end */
206 #define BISZ_BSSST_IDX 5 /* 5: bss start */
207 #define BISZ_BSSEND_IDX 6 /* 6: bss end */
208 #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
210 #define CC_SROM_OTP 0x800 /* SROM/OTP address space */
213 #define GPIO_ONTIME_SHIFT 16
215 /* Fields in clkdiv */
216 #define CLKD_OTP 0x000f0000
217 #define CLKD_OTP_SHIFT 16
219 /* When Srom support present, fields in sromcontrol */
220 #define SRC_START 0x80000000
221 #define SRC_BUSY 0x80000000
222 #define SRC_OPCODE 0x60000000
223 #define SRC_OP_READ 0x00000000
224 #define SRC_OP_WRITE 0x20000000
225 #define SRC_OP_WRDIS 0x40000000
226 #define SRC_OP_WREN 0x60000000
227 #define SRC_OTPSEL 0x00000010
228 #define SRC_LOCK 0x00000008
229 #define SRC_SIZE_MASK 0x00000006
230 #define SRC_SIZE_1K 0x00000000
231 #define SRC_SIZE_4K 0x00000002
232 #define SRC_SIZE_16K 0x00000004
233 #define SRC_SIZE_SHIFT 1
234 #define SRC_PRESENT 0x00000001
236 /* 4330 chip-specific ChipStatus register bits */
238 #define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6)
240 #define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6)
242 #define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0)
244 #define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4)
245 /* USB packet-oriented */
246 #define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6)
247 /* USB Direct Access */
248 #define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7)
249 #define CST4330_OTP_PRESENT 0x00000010
250 #define CST4330_LPO_AUTODET_EN 0x00000020
251 #define CST4330_ARMREMAP_0 0x00000040
252 /* takes priority over OTP if both set */
253 #define CST4330_SPROM_PRESENT 0x00000080
254 #define CST4330_ILPDIV_EN 0x00000100
255 #define CST4330_LPO_SEL 0x00000200
256 #define CST4330_RES_INIT_MODE_SHIFT 10
257 #define CST4330_RES_INIT_MODE_MASK 0x00000c00
258 #define CST4330_CBUCK_MODE_SHIFT 12
259 #define CST4330_CBUCK_MODE_MASK 0x00003000
260 #define CST4330_CBUCK_POWER_OK 0x00004000
261 #define CST4330_BB_PLL_LOCKED 0x00008000
264 #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
265 #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
266 #define BCM4717_PKG_ID 9 /* 4717 package id */
267 #define BCM4718_PKG_ID 10 /* 4718 package id */
268 #define HDLSIM_PKG_ID 14 /* HDL simulator package id */
269 #define HWSIM_PKG_ID 15 /* Hardware simulator package id */
270 #define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
272 /* these are router chips */
273 #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
274 #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
275 #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
276 #define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
277 #define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
280 #define SI_INFO(sih) ((struct si_info *)sih)
282 #define GOODCOREADDR(x, b) \
283 (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
284 IS_ALIGNED((x), SI_CORE_SIZE))
285 #define GOODREGS(regs) \
286 ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
287 #define BADCOREADDR 0
288 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
289 #define NOREV -1 /* Invalid rev */
291 /* Newer chips can access PCI/PCIE and CC core without requiring to change
294 #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
295 (((si)->pub.buscoretype == PCI_CORE_ID) && \
296 (si)->pub.buscorerev >= 13))
298 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
299 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
302 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
303 * before after core switching to avoid invalid register accesss inside ISR.
305 #define INTR_OFF(si, intr_val) \
306 if ((si)->intrsoff_fn && \
307 (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
308 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg)
309 #define INTR_RESTORE(si, intr_val) \
310 if ((si)->intrsrestore_fn && \
311 (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
312 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val)
314 /* dynamic clock control defines */
315 #define LPOMINFREQ 25000 /* low power oscillator min */
316 #define LPOMAXFREQ 43000 /* low power oscillator max */
317 #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
318 #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
319 #define PCIMINFREQ 25000000 /* 25 MHz */
320 #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
322 #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
323 #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
325 #define PCI(si) ((si)->pub.buscoretype == PCI_CORE_ID)
326 #define PCIE(si) ((si)->pub.buscoretype == PCIE_CORE_ID)
327 #define PCI_FORCEHT(si) \
328 (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
330 /* GPIO Based LED powersave defines */
331 #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
332 #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
334 #define DEFAULT_GPIOTIMERVAL \
335 ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
338 * Data structure to export all chip specific common variables
339 * public (read-only) portion of aiutils handle returned by si_attach()
342 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
343 uint buscorerev; /* buscore rev */
344 uint buscoreidx; /* buscore index */
345 int ccrev; /* chip common core rev */
346 u32 cccaps; /* chip common capabilities */
347 u32 cccaps_ext; /* chip common capabilities extension */
348 int pmurev; /* pmu core rev */
349 u32 pmucaps; /* pmu capabilities */
350 uint boardtype; /* board type */
351 uint boardvendor; /* board vendor */
352 uint boardflags; /* board flags */
353 uint boardflags2; /* board flags2 */
354 uint chip; /* chip number */
355 uint chiprev; /* chip revision */
356 uint chippkg; /* chip package option */
357 u32 chipst; /* chip status */
358 bool issim; /* chip is in simulation or emulation */
359 uint socirev; /* SOC interconnect rev */
365 * Many of the routines below take an 'sih' handle as their first arg.
366 * Allocate this by calling si_attach(). Free it by calling si_detach().
367 * At any one time, the sih is logically focused on one particular si core
368 * (the "current core").
369 * Use si_setcore() or si_setcoreidx() to change the association to another core
372 #define BADIDX (SI_MAXCORES + 1)
374 /* clkctl xtal what flags */
375 #define XTAL 0x1 /* primary crystal oscillator (2050) */
376 #define PLL 0x2 /* main chip pll */
378 /* clkctl clk mode */
379 #define CLK_FAST 0 /* force fast (pll) clock */
380 #define CLK_DYNAMIC 2 /* enable dynamic clock control */
382 /* GPIO usage priorities */
383 #define GPIO_DRV_PRIORITY 0 /* Driver */
384 #define GPIO_APP_PRIORITY 1 /* Application */
385 #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
389 /* GPIO pull up/down */
390 #define GPIO_PULLUP 0
391 #define GPIO_PULLDN 1
393 /* GPIO event regtype */
394 #define GPIO_REGEVT 0 /* GPIO register event */
395 #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
396 #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
399 #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
401 /* SI routine enumeration: to be used by update function with multiple hooks */
402 #define SI_DOATTACH 1
406 /* PMU clock/power control */
407 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
409 /* chipcommon clock/power control (exclusive with PMU's) */
410 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
411 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
413 /* External PA enable mask */
414 #define GPIO_CTRL_EPA_EN_MASK 0x40
416 #define SI_ERROR(args)
419 #define SI_MSG(args) printk args
424 /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
425 #define SI_VMSG(args)
427 #define IS_SIM(chippkg) \
428 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
435 void (*handler) (u32 stat, void *arg);
437 struct gpioh_item *next;
440 /* misc si info needed by some of the routines */
442 struct si_pub pub; /* back plane public state (must be first) */
443 struct pci_dev *pbus; /* handle to pci bus */
444 uint dev_coreid; /* the core provides driver functions */
445 void *intr_arg; /* interrupt callback function arg */
446 u32 (*intrsoff_fn) (void *intr_arg); /* turns chip interrupts off */
447 /* restore chip interrupts */
448 void (*intrsrestore_fn) (void *intr_arg, u32 arg);
449 /* check if interrupts are enabled */
450 bool (*intrsenabled_fn) (void *intr_arg);
452 struct pcicore_info *pch; /* PCI/E core handle */
457 void *curmap; /* current regs va */
458 void *regs[SI_MAXCORES]; /* other regs va */
460 uint curidx; /* current core index */
461 uint numcores; /* # discovered cores */
462 uint coreid[SI_MAXCORES]; /* id of each core */
463 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
464 void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
465 u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
466 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
467 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
469 void *curwrap; /* current wrapper va */
470 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
471 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
473 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
474 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
475 u32 oob_router; /* oob router registers for axi */
478 /* AMBA Interconnect exported externs */
479 extern uint ai_flag(struct si_pub *sih);
480 extern void ai_setint(struct si_pub *sih, int siflag);
481 extern uint ai_coreidx(struct si_pub *sih);
482 extern uint ai_corevendor(struct si_pub *sih);
483 extern uint ai_corerev(struct si_pub *sih);
484 extern bool ai_iscoreup(struct si_pub *sih);
485 extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
486 extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
487 extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
488 extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
490 extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
491 extern void ai_core_disable(struct si_pub *sih, u32 bits);
492 extern int ai_numaddrspaces(struct si_pub *sih);
493 extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
494 extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
495 extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
497 /* === exported functions === */
498 extern struct si_pub *ai_attach(void *regs, struct pci_dev *sdh, char **vars,
500 extern void ai_detach(struct si_pub *sih);
501 extern bool ai_pci_war16165(struct si_pub *sih);
503 extern uint ai_coreid(struct si_pub *sih);
504 extern uint ai_corerev(struct si_pub *sih);
505 extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
507 extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
508 extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
509 extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
510 extern bool ai_iscoreup(struct si_pub *sih);
511 extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
512 extern void *ai_setcoreidx(struct si_pub *sih, uint coreidx);
513 extern void *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
514 extern void *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
516 extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
517 extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
518 extern void ai_core_disable(struct si_pub *sih, u32 bits);
519 extern u32 ai_alp_clock(struct si_pub *sih);
520 extern u32 ai_ilp_clock(struct si_pub *sih);
521 extern void ai_pci_setup(struct si_pub *sih, uint coremask);
522 extern void ai_setint(struct si_pub *sih, int siflag);
523 extern bool ai_backplane64(struct si_pub *sih);
524 extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
525 void *intrsrestore_fn,
526 void *intrsenabled_fn, void *intr_arg);
527 extern void ai_deregister_intr_callback(struct si_pub *sih);
528 extern void ai_clkctl_init(struct si_pub *sih);
529 extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
530 extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
531 extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
532 extern bool ai_deviceremoved(struct si_pub *sih);
533 extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
537 extern bool ai_is_otp_disabled(struct si_pub *sih);
539 /* SPROM availability */
540 extern bool ai_is_sprom_available(struct si_pub *sih);
543 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
544 * The returned path is NULL terminated and has trailing '/'.
545 * Return 0 on success, nonzero otherwise.
547 extern int ai_devpath(struct si_pub *sih, char *path, int size);
548 /* Read variable with prepending the devpath to the name */
549 extern char *ai_getdevpathvar(struct si_pub *sih, const char *name);
550 extern int ai_getdevpathintvar(struct si_pub *sih, const char *name);
552 extern void ai_pci_sleep(struct si_pub *sih);
553 extern void ai_pci_down(struct si_pub *sih);
554 extern void ai_pci_up(struct si_pub *sih);
555 extern int ai_pci_fixcfg(struct si_pub *sih);
557 extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
558 /* Enable Ex-PA for 4313 */
559 extern void ai_epa_4313war(struct si_pub *sih);
561 char *ai_getnvramflvar(struct si_pub *sih, const char *name);
563 #endif /* _BRCM_AIUTILS_H_ */