Pileus Git - ~andy/linux/blob - drivers/staging/brcm80211/brcmfmac/dhd_sdio.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kthread.h>
  20 #include <linux/printk.h>
  21 #include <linux/pci_ids.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/sched.h>
  25 #include <linux/mmc/sdio.h>
  26 #include <linux/mmc/sdio_func.h>
  27 #include <linux/mmc/card.h>
  28 #include <linux/semaphore.h>
  29 #include <linux/firmware.h>
  30 #include <asm/unaligned.h>
  31 #include <defs.h>
  32 #include <brcmu_wifi.h>
  33 #include <brcmu_utils.h>
  34 #include <brcm_hw_ids.h>
  35 #include <soc.h>
  36 #include "sdio_host.h"
  37
  38 #ifdef BCMDBG
  39
  40 /* ARM trap handling */
  41 struct brcmf_trap {
  42         u32 type;
  43         u32 epc;
  44         u32 cpsr;
  45         u32 spsr;
  46         u32 r0;
  47         u32 r1;
  48         u32 r2;
  49         u32 r3;
  50         u32 r4;
  51         u32 r5;
  52         u32 r6;
  53         u32 r7;
  54         u32 r8;
  55         u32 r9;
  56         u32 r10;
  57         u32 r11;
  58         u32 r12;
  59         u32 r13;
  60         u32 r14;
  61         u32 pc;
  62 };
  63
  64 #define CBUF_LEN        (128)
  65
  66 struct rte_log {
  67         u32 buf;                /* Can't be pointer on (64-bit) hosts */
  68         uint buf_size;
  69         uint idx;
  70         char *_buf_compat;      /* Redundant pointer for backward compat. */
  71 };
  72
  73 struct rte_console {
  74         /* Virtual UART
  75          * When there is no UART (e.g. Quickturn),
  76          * the host should write a complete
  77          * input line directly into cbuf and then write
  78          * the length into vcons_in.
  79          * This may also be used when there is a real UART
  80          * (at risk of conflicting with
  81          * the real UART).  vcons_out is currently unused.
  82          */
  83         uint vcons_in;
  84         uint vcons_out;
  85
  86         /* Output (logging) buffer
  87          * Console output is written to a ring buffer log_buf at index log_idx.
  88          * The host may read the output when it sees log_idx advance.
  89          * Output will be lost if the output wraps around faster than the host
  90          * polls.
  91          */
  92         struct rte_log log;
  93
  94         /* Console input line buffer
  95          * Characters are read one at a time into cbuf
  96          * until <CR> is received, then
  97          * the buffer is processed as a command line.
  98          * Also used for virtual UART.
  99          */
 100         uint cbuf_idx;
 101         char cbuf[CBUF_LEN];
 102 };
 103
 104 #endif                          /* BCMDBG */
 105 #include <chipcommon.h>
 106
 107 #include "dhd.h"
 108 #include "dhd_bus.h"
 109 #include "dhd_proto.h"
 110 #include "dhd_dbg.h"
 111 #include <bcmchip.h>
 112
 113 #define TXQLEN          2048    /* bulk tx queue length */
 114 #define TXHI            (TXQLEN - 256)  /* turn on flow control above TXHI */
 115 #define TXLOW           (TXHI - 256)    /* turn off flow control below TXLOW */
 116 #define PRIOMASK        7
 117
 118 #define TXRETRIES       2       /* # of retries for tx frames */
 119
 120 #define BRCMF_RXBOUND   50      /* Default for max rx frames in
 121                                  one scheduling */
 122
 123 #define BRCMF_TXBOUND   20      /* Default for max tx frames in
 124                                  one scheduling */
 125
 126 #define BRCMF_TXMINMAX  1       /* Max tx frames if rx still pending */
 127
 128 #define MEMBLOCK        2048    /* Block size used for downloading
 129                                  of dongle image */
 130 #define MAX_DATA_BUF    (32 * 1024)     /* Must be large enough to hold
 131                                  biggest possible glom */
 132
 133 #define BRCMF_FIRSTREAD (1 << 6)
 134
 135
 136 /* SBSDIO_DEVICE_CTL */
 137
 138 /* 1: device will assert busy signal when receiving CMD53 */
 139 #define SBSDIO_DEVCTL_SETBUSY           0x01
 140 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
 141 #define SBSDIO_DEVCTL_SPI_INTR_SYNC     0x02
 142 /* 1: mask all interrupts to host except the chipActive (rev 8) */
 143 #define SBSDIO_DEVCTL_CA_INT_ONLY       0x04
 144 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
 145  * sdio bus power cycle to clear (rev 9) */
 146 #define SBSDIO_DEVCTL_PADS_ISO          0x08
 147 /* Force SD->SB reset mapping (rev 11) */
 148 #define SBSDIO_DEVCTL_SB_RST_CTL        0x30
 149 /*   Determined by CoreControl bit */
 150 #define SBSDIO_DEVCTL_RST_CORECTL       0x00
 151 /*   Force backplane reset */
 152 #define SBSDIO_DEVCTL_RST_BPRESET       0x10
 153 /*   Force no backplane reset */
 154 #define SBSDIO_DEVCTL_RST_NOBPRESET     0x20
 155
 156 /* SBSDIO_FUNC1_CHIPCLKCSR */
 157
 158 /* Force ALP request to backplane */
 159 #define SBSDIO_FORCE_ALP                0x01
 160 /* Force HT request to backplane */
 161 #define SBSDIO_FORCE_HT                 0x02
 162 /* Force ILP request to backplane */
 163 #define SBSDIO_FORCE_ILP                0x04
 164 /* Make ALP ready (power up xtal) */
 165 #define SBSDIO_ALP_AVAIL_REQ            0x08
 166 /* Make HT ready (power up PLL) */
 167 #define SBSDIO_HT_AVAIL_REQ             0x10
 168 /* Squelch clock requests from HW */
 169 #define SBSDIO_FORCE_HW_CLKREQ_OFF      0x20
 170 /* Status: ALP is ready */
 171 #define SBSDIO_ALP_AVAIL                0x40
 172 /* Status: HT is ready */
 173 #define SBSDIO_HT_AVAIL                 0x80
 174
 175 #define SBSDIO_AVBITS           (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
 176 #define SBSDIO_ALPAV(regval)    ((regval) & SBSDIO_AVBITS)
 177 #define SBSDIO_HTAV(regval)     (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
 178 #define SBSDIO_ALPONLY(regval)  (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
 179
 180 #define SBSDIO_CLKAV(regval, alponly) \
 181         (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
 182
 183 /* direct(mapped) cis space */
 184
 185 /* MAPPED common CIS address */
 186 #define SBSDIO_CIS_BASE_COMMON          0x1000
 187 /* maximum bytes in one CIS */
 188 #define SBSDIO_CIS_SIZE_LIMIT           0x200
 189 /* cis offset addr is < 17 bits */
 190 #define SBSDIO_CIS_OFT_ADDR_MASK        0x1FFFF
 191
 192 /* manfid tuple length, include tuple, link bytes */
 193 #define SBSDIO_CIS_MANFID_TUPLE_LEN     6
 194
 195 /* intstatus */
 196 #define I_SMB_SW0       (1 << 0)        /* To SB Mail S/W interrupt 0 */
 197 #define I_SMB_SW1       (1 << 1)        /* To SB Mail S/W interrupt 1 */
 198 #define I_SMB_SW2       (1 << 2)        /* To SB Mail S/W interrupt 2 */
 199 #define I_SMB_SW3       (1 << 3)        /* To SB Mail S/W interrupt 3 */
 200 #define I_SMB_SW_MASK   0x0000000f      /* To SB Mail S/W interrupts mask */
 201 #define I_SMB_SW_SHIFT  0       /* To SB Mail S/W interrupts shift */
 202 #define I_HMB_SW0       (1 << 4)        /* To Host Mail S/W interrupt 0 */
 203 #define I_HMB_SW1       (1 << 5)        /* To Host Mail S/W interrupt 1 */
 204 #define I_HMB_SW2       (1 << 6)        /* To Host Mail S/W interrupt 2 */
 205 #define I_HMB_SW3       (1 << 7)        /* To Host Mail S/W interrupt 3 */
 206 #define I_HMB_SW_MASK   0x000000f0      /* To Host Mail S/W interrupts mask */
 207 #define I_HMB_SW_SHIFT  4       /* To Host Mail S/W interrupts shift */
 208 #define I_WR_OOSYNC     (1 << 8)        /* Write Frame Out Of Sync */
 209 #define I_RD_OOSYNC     (1 << 9)        /* Read Frame Out Of Sync */
 210 #define I_PC            (1 << 10)       /* descriptor error */
 211 #define I_PD            (1 << 11)       /* data error */
 212 #define I_DE            (1 << 12)       /* Descriptor protocol Error */
 213 #define I_RU            (1 << 13)       /* Receive descriptor Underflow */
 214 #define I_RO            (1 << 14)       /* Receive fifo Overflow */
 215 #define I_XU            (1 << 15)       /* Transmit fifo Underflow */
 216 #define I_RI            (1 << 16)       /* Receive Interrupt */
 217 #define I_BUSPWR        (1 << 17)       /* SDIO Bus Power Change (rev 9) */
 218 #define I_XMTDATA_AVAIL (1 << 23)       /* bits in fifo */
 219 #define I_XI            (1 << 24)       /* Transmit Interrupt */
 220 #define I_RF_TERM       (1 << 25)       /* Read Frame Terminate */
 221 #define I_WF_TERM       (1 << 26)       /* Write Frame Terminate */
 222 #define I_PCMCIA_XU     (1 << 27)       /* PCMCIA Transmit FIFO Underflow */
 223 #define I_SBINT         (1 << 28)       /* sbintstatus Interrupt */
 224 #define I_CHIPACTIVE    (1 << 29)       /* chip from doze to active state */
 225 #define I_SRESET        (1 << 30)       /* CCCR RES interrupt */
 226 #define I_IOE2          (1U << 31)      /* CCCR IOE2 Bit Changed */
 227 #define I_ERRORS        (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
 228 #define I_DMA           (I_RI | I_XI | I_ERRORS)
 229
 230 /* corecontrol */
 231 #define CC_CISRDY               (1 << 0)        /* CIS Ready */
 232 #define CC_BPRESEN              (1 << 1)        /* CCCR RES signal */
 233 #define CC_F2RDY                (1 << 2)        /* set CCCR IOR2 bit */
 234 #define CC_CLRPADSISO           (1 << 3)        /* clear SDIO pads isolation */
 235 #define CC_XMTDATAAVAIL_MODE    (1 << 4)
 236 #define CC_XMTDATAAVAIL_CTRL    (1 << 5)
 237
 238 /* SDA_FRAMECTRL */
 239 #define SFC_RF_TERM     (1 << 0)        /* Read Frame Terminate */
 240 #define SFC_WF_TERM     (1 << 1)        /* Write Frame Terminate */
 241 #define SFC_CRC4WOOS    (1 << 2)        /* CRC error for write out of sync */
 242 #define SFC_ABORTALL    (1 << 3)        /* Abort all in-progress frames */
 243
 244 /* HW frame tag */
 245 #define SDPCM_FRAMETAG_LEN      4       /* 2 bytes len, 2 bytes check val */
 246
 247 /* Total length of frame header for dongle protocol */
 248 #define SDPCM_HDRLEN    (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
 249 #define SDPCM_RESERVE   (SDPCM_HDRLEN + BRCMF_SDALIGN)
 250
 251 /*
 252  * Software allocation of To SB Mailbox resources
 253  */
 254
 255 /* tosbmailbox bits corresponding to intstatus bits */
 256 #define SMB_NAK         (1 << 0)        /* Frame NAK */
 257 #define SMB_INT_ACK     (1 << 1)        /* Host Interrupt ACK */
 258 #define SMB_USE_OOB     (1 << 2)        /* Use OOB Wakeup */
 259 #define SMB_DEV_INT     (1 << 3)        /* Miscellaneous Interrupt */
 260
 261 /* tosbmailboxdata */
 262 #define SMB_DATA_VERSION_SHIFT  16      /* host protocol version */
 263
 264 /*
 265  * Software allocation of To Host Mailbox resources
 266  */
 267
 268 /* intstatus bits */
 269 #define I_HMB_FC_STATE  I_HMB_SW0       /* Flow Control State */
 270 #define I_HMB_FC_CHANGE I_HMB_SW1       /* Flow Control State Changed */
 271 #define I_HMB_FRAME_IND I_HMB_SW2       /* Frame Indication */
 272 #define I_HMB_HOST_INT  I_HMB_SW3       /* Miscellaneous Interrupt */
 273
 274 /* tohostmailboxdata */
 275 #define HMB_DATA_NAKHANDLED     1       /* retransmit NAK'd frame */
 276 #define HMB_DATA_DEVREADY       2       /* talk to host after enable */
 277 #define HMB_DATA_FC             4       /* per prio flowcontrol update flag */
 278 #define HMB_DATA_FWREADY        8       /* fw ready for protocol activity */
 279
 280 #define HMB_DATA_FCDATA_MASK    0xff000000
 281 #define HMB_DATA_FCDATA_SHIFT   24
 282
 283 #define HMB_DATA_VERSION_MASK   0x00ff0000
 284 #define HMB_DATA_VERSION_SHIFT  16
 285
 286 /*
 287  * Software-defined protocol header
 288  */
 289
 290 /* Current protocol version */
 291 #define SDPCM_PROT_VERSION      4
 292
 293 /* SW frame header */
 294 #define SDPCM_PACKET_SEQUENCE(p)        (((u8 *)p)[0] & 0xff)
 295
 296 #define SDPCM_CHANNEL_MASK              0x00000f00
 297 #define SDPCM_CHANNEL_SHIFT             8
 298 #define SDPCM_PACKET_CHANNEL(p)         (((u8 *)p)[1] & 0x0f)
 299
 300 #define SDPCM_NEXTLEN_OFFSET            2
 301
 302 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
 303 #define SDPCM_DOFFSET_OFFSET            3       /* Data Offset */
 304 #define SDPCM_DOFFSET_VALUE(p)          (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
 305 #define SDPCM_DOFFSET_MASK              0xff000000
 306 #define SDPCM_DOFFSET_SHIFT             24
 307 #define SDPCM_FCMASK_OFFSET             4       /* Flow control */
 308 #define SDPCM_FCMASK_VALUE(p)           (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
 309 #define SDPCM_WINDOW_OFFSET             5       /* Credit based fc */
 310 #define SDPCM_WINDOW_VALUE(p)           (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
 311
 312 #define SDPCM_SWHEADER_LEN      8       /* SW header is 64 bits */
 313
 314 /* logical channel numbers */
 315 #define SDPCM_CONTROL_CHANNEL   0       /* Control channel Id */
 316 #define SDPCM_EVENT_CHANNEL     1       /* Asyc Event Indication Channel Id */
 317 #define SDPCM_DATA_CHANNEL      2       /* Data Xmit/Recv Channel Id */
 318 #define SDPCM_GLOM_CHANNEL      3       /* For coalesced packets */
 319 #define SDPCM_TEST_CHANNEL      15      /* Reserved for test/debug packets */
 320
 321 #define SDPCM_SEQUENCE_WRAP     256     /* wrap-around val for 8bit frame seq */
 322
 323 #define SDPCM_GLOMDESC(p)       (((u8 *)p)[1] & 0x80)
 324
 325 /* For TEST_CHANNEL packets, define another 4-byte header */
 326 #define SDPCM_TEST_HDRLEN       4       /*
 327                                          * Generally: Cmd(1), Ext(1), Len(2);
 328                                          * Semantics of Ext byte depend on
 329                                          * command. Len is current or requested
 330                                          * frame length, not including test
 331                                          * header; sent little-endian.
 332                                          */
 333 #define SDPCM_TEST_DISCARD      0x01    /* Receiver discards. Ext:pattern id. */
 334 #define SDPCM_TEST_ECHOREQ      0x02    /* Echo request. Ext:pattern id. */
 335 #define SDPCM_TEST_ECHORSP      0x03    /* Echo response. Ext:pattern id. */
 336 #define SDPCM_TEST_BURST        0x04    /*
 337                                          * Receiver to send a burst.
 338                                          * Ext is a frame count
 339                                          */
 340 #define SDPCM_TEST_SEND         0x05    /*
 341                                          * Receiver sets send mode.
 342                                          * Ext is boolean on/off
 343                                          */
 344
 345 /* Handy macro for filling in datagen packets with a pattern */
 346 #define SDPCM_TEST_FILL(byteno, id)     ((u8)(id + byteno))
 347
 348 /*
 349  * Shared structure between dongle and the host.
 350  * The structure contains pointers to trap or assert information.
 351  */
 352 #define SDPCM_SHARED_VERSION       0x0002
 353 #define SDPCM_SHARED_VERSION_MASK  0x00FF
 354 #define SDPCM_SHARED_ASSERT_BUILT  0x0100
 355 #define SDPCM_SHARED_ASSERT        0x0200
 356 #define SDPCM_SHARED_TRAP          0x0400
 357
 358
 359 /* Space for header read, limit for data packets */
 360 #define MAX_HDR_READ    (1 << 6)
 361 #define MAX_RX_DATASZ   2048
 362
 363 /* Maximum milliseconds to wait for F2 to come up */
 364 #define BRCMF_WAIT_F2RDY        3000
 365
 366 /* Bump up limit on waiting for HT to account for first startup;
 367  * if the image is doing a CRC calculation before programming the PMU
 368  * for HT availability, it could take a couple hundred ms more, so
 369  * max out at a 1 second (1000000us).
 370  */
 371 #undef PMU_MAX_TRANSITION_DLY
 372 #define PMU_MAX_TRANSITION_DLY 1000000
 373
 374 /* Value for ChipClockCSR during initial setup */
 375 #define BRCMF_INIT_CLKCTL1      (SBSDIO_FORCE_HW_CLKREQ_OFF |   \
 376                                         SBSDIO_ALP_AVAIL_REQ)
 377
 378 /* Flags for SDH calls */
 379 #define F2SYNC  (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
 380
 381 /* sbimstate */
 382 #define SBIM_IBE                0x20000 /* inbanderror */
 383 #define SBIM_TO                 0x40000 /* timeout */
 384 #define SBIM_BY                 0x01800000      /* busy (sonics >= 2.3) */
 385 #define SBIM_RJ                 0x02000000      /* reject (sonics >= 2.3) */
 386
 387 /* sbtmstatelow */
 388
 389 /* reset */
 390 #define SBTML_RESET             0x0001
 391 /* reject field */
 392 #define SBTML_REJ_MASK          0x0006
 393 /* reject */
 394 #define SBTML_REJ               0x0002
 395 /* temporary reject, for error recovery */
 396 #define SBTML_TMPREJ            0x0004
 397
 398 /* Shift to locate the SI control flags in sbtml */
 399 #define SBTML_SICF_SHIFT        16
 400
 401 /* sbtmstatehigh */
 402 #define SBTMH_SERR              0x0001  /* serror */
 403 #define SBTMH_INT               0x0002  /* interrupt */
 404 #define SBTMH_BUSY              0x0004  /* busy */
 405 #define SBTMH_TO                0x0020  /* timeout (sonics >= 2.3) */
 406
 407 /* Shift to locate the SI status flags in sbtmh */
 408 #define SBTMH_SISF_SHIFT        16
 409
 410 /* sbidlow */
 411 #define SBIDL_INIT              0x80    /* initiator */
 412
 413 /* sbidhigh */
 414 #define SBIDH_RC_MASK           0x000f  /* revision code */
 415 #define SBIDH_RCE_MASK          0x7000  /* revision code extension field */
 416 #define SBIDH_RCE_SHIFT         8
 417 #define SBCOREREV(sbidh) \
 418         ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
 419           ((sbidh) & SBIDH_RC_MASK))
 420 #define SBIDH_CC_MASK           0x8ff0  /* core code */
 421 #define SBIDH_CC_SHIFT          4
 422 #define SBIDH_VC_MASK           0xffff0000      /* vendor code */
 423 #define SBIDH_VC_SHIFT          16
 424
 425 /*
 426  * Conversion of 802.1D priority to precedence level
 427  */
 428 #define PRIO2PREC(prio) \
 429         (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
 430         ((prio^2)) : (prio))
 431
 432 /*
 433  * Core reg address translation.
 434  * Both macro's returns a 32 bits byte address on the backplane bus.
 435  */
 436 #define CORE_CC_REG(base, field) \
 437                 (base + offsetof(struct chipcregs, field))
 438 #define CORE_BUS_REG(base, field) \
 439                 (base + offsetof(struct sdpcmd_regs, field))
 440 #define CORE_SB(base, field) \
 441                 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
 442
 443 /* core registers */
 444 struct sdpcmd_regs {
 445         u32 corecontrol;                /* 0x00, rev8 */
 446         u32 corestatus;                 /* rev8 */
 447         u32 PAD[1];
 448         u32 biststatus;                 /* rev8 */
 449
 450         /* PCMCIA access */
 451         u16 pcmciamesportaladdr;        /* 0x010, rev8 */
 452         u16 PAD[1];
 453         u16 pcmciamesportalmask;        /* rev8 */
 454         u16 PAD[1];
 455         u16 pcmciawrframebc;            /* rev8 */
 456         u16 PAD[1];
 457         u16 pcmciaunderflowtimer;       /* rev8 */
 458         u16 PAD[1];
 459
 460         /* interrupt */
 461         u32 intstatus;                  /* 0x020, rev8 */
 462         u32 hostintmask;                /* rev8 */
 463         u32 intmask;                    /* rev8 */
 464         u32 sbintstatus;                /* rev8 */
 465         u32 sbintmask;                  /* rev8 */
 466         u32 funcintmask;                /* rev4 */
 467         u32 PAD[2];
 468         u32 tosbmailbox;                /* 0x040, rev8 */
 469         u32 tohostmailbox;              /* rev8 */
 470         u32 tosbmailboxdata;            /* rev8 */
 471         u32 tohostmailboxdata;          /* rev8 */
 472
 473         /* synchronized access to registers in SDIO clock domain */
 474         u32 sdioaccess;                 /* 0x050, rev8 */
 475         u32 PAD[3];
 476
 477         /* PCMCIA frame control */
 478         u8 pcmciaframectrl;             /* 0x060, rev8 */
 479         u8 PAD[3];
 480         u8 pcmciawatermark;             /* rev8 */
 481         u8 PAD[155];
 482
 483         /* interrupt batching control */
 484         u32 intrcvlazy;                 /* 0x100, rev8 */
 485         u32 PAD[3];
 486
 487         /* counters */
 488         u32 cmd52rd;                    /* 0x110, rev8 */
 489         u32 cmd52wr;                    /* rev8 */
 490         u32 cmd53rd;                    /* rev8 */
 491         u32 cmd53wr;                    /* rev8 */
 492         u32 abort;                      /* rev8 */
 493         u32 datacrcerror;               /* rev8 */
 494         u32 rdoutofsync;                /* rev8 */
 495         u32 wroutofsync;                /* rev8 */
 496         u32 writebusy;                  /* rev8 */
 497         u32 readwait;                   /* rev8 */
 498         u32 readterm;                   /* rev8 */
 499         u32 writeterm;                  /* rev8 */
 500         u32 PAD[40];
 501         u32 clockctlstatus;             /* rev8 */
 502         u32 PAD[7];
 503
 504         u32 PAD[128];                   /* DMA engines */
 505
 506         /* SDIO/PCMCIA CIS region */
 507         char cis[512];                  /* 0x400-0x5ff, rev6 */
 508
 509         /* PCMCIA function control registers */
 510         char pcmciafcr[256];            /* 0x600-6ff, rev6 */
 511         u16 PAD[55];
 512
 513         /* PCMCIA backplane access */
 514         u16 backplanecsr;               /* 0x76E, rev6 */
 515         u16 backplaneaddr0;             /* rev6 */
 516         u16 backplaneaddr1;             /* rev6 */
 517         u16 backplaneaddr2;             /* rev6 */
 518         u16 backplaneaddr3;             /* rev6 */
 519         u16 backplanedata0;             /* rev6 */
 520         u16 backplanedata1;             /* rev6 */
 521         u16 backplanedata2;             /* rev6 */
 522         u16 backplanedata3;             /* rev6 */
 523         u16 PAD[31];
 524
 525         /* sprom "size" & "blank" info */
 526         u16 spromstatus;                /* 0x7BE, rev2 */
 527         u32 PAD[464];
 528
 529         u16 PAD[0x80];
 530 };
 531
 532 #ifdef BCMDBG
 533 /* Device console log buffer state */
 534 struct brcmf_console {
 535         uint count;             /* Poll interval msec counter */
 536         uint log_addr;          /* Log struct address (fixed) */
 537         struct rte_log log;     /* Log struct (host copy) */
 538         uint bufsize;           /* Size of log buffer */
 539         u8 *buf;                /* Log buffer (host copy) */
 540         uint last;              /* Last buffer read index */
 541 };
 542 #endif                          /* BCMDBG */
 543
 544 struct sdpcm_shared {
 545         u32 flags;
 546         u32 trap_addr;
 547         u32 assert_exp_addr;
 548         u32 assert_file_addr;
 549         u32 assert_line;
 550         u32 console_addr;       /* Address of struct rte_console */
 551         u32 msgtrace_addr;
 552         u8 tag[32];
 553 };
 554
 555
 556 /* misc chip info needed by some of the routines */
 557 struct chip_info {
 558         u32 chip;
 559         u32 chiprev;
 560         u32 cccorebase;
 561         u32 ccrev;
 562         u32 cccaps;
 563         u32 buscorebase; /* 32 bits backplane bus address */
 564         u32 buscorerev;
 565         u32 buscoretype;
 566         u32 ramcorebase;
 567         u32 armcorebase;
 568         u32 pmurev;
 569         u32 ramsize;
 570 };
 571
 572 /* Private data for SDIO bus interaction */
 573 struct brcmf_bus {
 574         struct brcmf_pub *drvr;
 575
 576         struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
 577         struct chip_info *ci;   /* Chip info struct */
 578         char *vars;             /* Variables (from CIS and/or other) */
 579         uint varsz;             /* Size of variables buffer */
 580
 581         u32 ramsize;            /* Size of RAM in SOCRAM (bytes) */
 582         u32 orig_ramsize;       /* Size of RAM in SOCRAM (bytes) */
 583
 584         u32 hostintmask;        /* Copy of Host Interrupt Mask */
 585         u32 intstatus;  /* Intstatus bits (events) pending */
 586         bool dpc_sched;         /* Indicates DPC schedule (intrpt rcvd) */
 587         bool fcstate;           /* State of dongle flow-control */
 588
 589         uint blocksize;         /* Block size of SDIO transfers */
 590         uint roundup;           /* Max roundup limit */
 591
 592         struct pktq txq;        /* Queue length used for flow-control */
 593         u8 flowcontrol; /* per prio flow control bitmask */
 594         u8 tx_seq;              /* Transmit sequence number (next) */
 595         u8 tx_max;              /* Maximum transmit sequence allowed */
 596
 597         u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
 598         u8 *rxhdr;              /* Header of current rx frame (in hdrbuf) */
 599         u16 nextlen;            /* Next Read Len from last header */
 600         u8 rx_seq;              /* Receive sequence number (expected) */
 601         bool rxskip;            /* Skip receive (awaiting NAK ACK) */
 602
 603         struct sk_buff *glomd;  /* Packet containing glomming descriptor */
 604         struct sk_buff *glom;   /* Packet chain for glommed superframe */
 605         uint glomerr;           /* Glom packet read errors */
 606
 607         u8 *rxbuf;              /* Buffer for receiving control packets */
 608         uint rxblen;            /* Allocated length of rxbuf */
 609         u8 *rxctl;              /* Aligned pointer into rxbuf */
 610         u8 *databuf;            /* Buffer for receiving big glom packet */
 611         u8 *dataptr;            /* Aligned pointer into databuf */
 612         uint rxlen;             /* Length of valid data in buffer */
 613
 614         u8 sdpcm_ver;   /* Bus protocol reported by dongle */
 615
 616         bool intr;              /* Use interrupts */
 617         bool poll;              /* Use polling */
 618         bool ipend;             /* Device interrupt is pending */
 619         uint intrcount;         /* Count of device interrupt callbacks */
 620         uint lastintrs;         /* Count as of last watchdog timer */
 621         uint spurious;          /* Count of spurious interrupts */
 622         uint pollrate;          /* Ticks between device polls */
 623         uint polltick;          /* Tick counter */
 624         uint pollcnt;           /* Count of active polls */
 625
 626 #ifdef BCMDBG
 627         struct brcmf_console console;   /* Console output polling support */
 628         uint console_addr;      /* Console address from shared struct */
 629 #endif                          /* BCMDBG */
 630
 631         uint regfails;          /* Count of R_REG failures */
 632
 633         uint clkstate;          /* State of sd and backplane clock(s) */
 634         bool activity;          /* Activity flag for clock down */
 635         s32 idletime;           /* Control for activity timeout */
 636         s32 idlecount;  /* Activity timeout counter */
 637         s32 idleclock;  /* How to set bus driver when idle */
 638         s32 sd_rxchain;
 639         bool use_rxchain;       /* If brcmf should use PKT chains */
 640         bool sleeping;          /* Is SDIO bus sleeping? */
 641         bool rxflow_mode;       /* Rx flow control mode */
 642         bool rxflow;            /* Is rx flow control on */
 643         bool alp_only;          /* Don't use HT clock (ALP only) */
 644 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
 645         bool usebufpool;
 646
 647         /* Some additional counters */
 648         uint tx_sderrs;         /* Count of tx attempts with sd errors */
 649         uint fcqueued;          /* Tx packets that got queued */
 650         uint rxrtx;             /* Count of rtx requests (NAK to dongle) */
 651         uint rx_toolong;        /* Receive frames too long to receive */
 652         uint rxc_errors;        /* SDIO errors when reading control frames */
 653         uint rx_hdrfail;        /* SDIO errors on header reads */
 654         uint rx_badhdr;         /* Bad received headers (roosync?) */
 655         uint rx_badseq;         /* Mismatched rx sequence number */
 656         uint fc_rcvd;           /* Number of flow-control events received */
 657         uint fc_xoff;           /* Number which turned on flow-control */
 658         uint fc_xon;            /* Number which turned off flow-control */
 659         uint rxglomfail;        /* Failed deglom attempts */
 660         uint rxglomframes;      /* Number of glom frames (superframes) */
 661         uint rxglompkts;        /* Number of packets from glom frames */
 662         uint f2rxhdrs;          /* Number of header reads */
 663         uint f2rxdata;          /* Number of frame data reads */
 664         uint f2txdata;          /* Number of f2 frame writes */
 665         uint f1regdata;         /* Number of f1 register accesses */
 666
 667         u8 *ctrl_frame_buf;
 668         u32 ctrl_frame_len;
 669         bool ctrl_frame_stat;
 670
 671         spinlock_t txqlock;
 672         wait_queue_head_t ctrl_wait;
 673         wait_queue_head_t ioctl_resp_wait;
 674
 675         struct timer_list timer;
 676         struct completion watchdog_wait;
 677         struct task_struct *watchdog_tsk;
 678         bool wd_timer_valid;
 679
 680         struct tasklet_struct tasklet;
 681         struct task_struct *dpc_tsk;
 682         struct completion dpc_wait;
 683
 684         bool threads_only;
 685         struct semaphore sdsem;
 686         spinlock_t sdlock;
 687
 688         const char *fw_name;
 689         const struct firmware *firmware;
 690         const char *nv_name;
 691         u32 fw_ptr;
 692 };
 693
 694 struct sbconfig {
 695         u32 PAD[2];
 696         u32 sbipsflag;  /* initiator port ocp slave flag */
 697         u32 PAD[3];
 698         u32 sbtpsflag;  /* target port ocp slave flag */
 699         u32 PAD[11];
 700         u32 sbtmerrloga;        /* (sonics >= 2.3) */
 701         u32 PAD;
 702         u32 sbtmerrlog; /* (sonics >= 2.3) */
 703         u32 PAD[3];
 704         u32 sbadmatch3; /* address match3 */
 705         u32 PAD;
 706         u32 sbadmatch2; /* address match2 */
 707         u32 PAD;
 708         u32 sbadmatch1; /* address match1 */
 709         u32 PAD[7];
 710         u32 sbimstate;  /* initiator agent state */
 711         u32 sbintvec;   /* interrupt mask */
 712         u32 sbtmstatelow;       /* target state */
 713         u32 sbtmstatehigh;      /* target state */
 714         u32 sbbwa0;             /* bandwidth allocation table0 */
 715         u32 PAD;
 716         u32 sbimconfiglow;      /* initiator configuration */
 717         u32 sbimconfighigh;     /* initiator configuration */
 718         u32 sbadmatch0; /* address match0 */
 719         u32 PAD;
 720         u32 sbtmconfiglow;      /* target configuration */
 721         u32 sbtmconfighigh;     /* target configuration */
 722         u32 sbbconfig;  /* broadcast configuration */
 723         u32 PAD;
 724         u32 sbbstate;   /* broadcast state */
 725         u32 PAD[3];
 726         u32 sbactcnfg;  /* activate configuration */
 727         u32 PAD[3];
 728         u32 sbflagst;   /* current sbflags */
 729         u32 PAD[3];
 730         u32 sbidlow;            /* identification */
 731         u32 sbidhigh;   /* identification */
 732 };
 733
 734 /* clkstate */
 735 #define CLK_NONE        0
 736 #define CLK_SDONLY      1
 737 #define CLK_PENDING     2       /* Not used yet */
 738 #define CLK_AVAIL       3
 739
 740 #ifdef BCMDBG
 741 static int qcount[NUMPRIO];
 742 static int tx_packets[NUMPRIO];
 743 #endif                          /* BCMDBG */
 744
 745 /* Deferred transmit */
 746 uint brcmf_deferred_tx = 1;
 747 module_param(brcmf_deferred_tx, uint, 0);
 748
 749 /* Watchdog thread priority, -1 to use kernel timer */
 750 int brcmf_watchdog_prio = 97;
 751 module_param(brcmf_watchdog_prio, int, 0);
 752
 753 /* Watchdog interval */
 754 uint brcmf_watchdog_ms = 10;
 755 module_param(brcmf_watchdog_ms, uint, 0);
 756
 757 /* DPC thread priority, -1 to use tasklet */
 758 int brcmf_dpc_prio = 98;
 759 module_param(brcmf_dpc_prio, int, 0);
 760
 761 #ifdef BCMDBG
 762 /* Console poll interval */
 763 uint brcmf_console_ms;
 764 module_param(brcmf_console_ms, uint, 0);
 765 #endif          /* BCMDBG */
 766
 767 /* Tx/Rx bounds */
 768 uint brcmf_txbound;
 769 uint brcmf_rxbound;
 770 module_param(brcmf_txbound, uint, 0);
 771 module_param(brcmf_rxbound, uint, 0);
 772 uint brcmf_txminmax;
 773
 774 int brcmf_idletime = 1;
 775 module_param(brcmf_idletime, int, 0);
 776
 777 /* SDIO Drive Strength (in milliamps) */
 778 uint brcmf_sdiod_drive_strength = 6;
 779 module_param(brcmf_sdiod_drive_strength, uint, 0);
 780
 781 /* Use polling */
 782 uint brcmf_poll;
 783 module_param(brcmf_poll, uint, 0);
 784
 785 /* Use interrupts */
 786 uint brcmf_intr = true;
 787 module_param(brcmf_intr, uint, 0);
 788
 789 /* IOCTL response timeout */
 790 static int brcmf_ioctl_timeout_msec = IOCTL_RESP_TIMEOUT;
 791
 792 /* override the RAM size if possible */
 793 #define DONGLE_MIN_MEMSIZE (128 * 1024)
 794 int brcmf_dongle_memsize;
 795 module_param(brcmf_dongle_memsize, int, 0);
 796
 797 static bool brcmf_alignctl;
 798
 799 static bool retrydata;
 800 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
 801
 802 static const uint firstread = BRCMF_FIRSTREAD;
 803
 804 /* Retry count for register access failures */
 805 static const uint retry_limit = 2;
 806
 807 /* Force even SD lengths (some host controllers mess up on odd bytes) */
 808 static bool forcealign;
 809
 810 #define ALIGNMENT  4
 811
 812 #define PKTALIGN(_p, _len, _align)                              \
 813         do {                                                            \
 814                 uint datalign;                                          \
 815                 datalign = (unsigned long)((_p)->data);                 \
 816                 datalign = roundup(datalign, (_align)) - datalign;      \
 817                 if (datalign)                                           \
 818                         skb_pull((_p), datalign);                       \
 819                 __skb_trim((_p), (_len));                               \
 820         } while (0)
 821
 822 /* Limit on rounding up frames */
 823 static const uint max_roundup = 512;
 824
 825 /* Try doing readahead */
 826 static bool brcmf_readahead;
 827
 828 /* To check if there's window offered */
 829 #define DATAOK(bus) \
 830         (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
 831         (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
 832
 833 /*
 834  * Reads a register in the SDIO hardware block. This block occupies a series of
 835  * adresses on the 32 bit backplane bus.
 836  */
 837 static void
 838 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
 839 {
 840         *retryvar = 0;
 841         do {
 842                 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
 843                                 bus->ci->buscorebase + reg_offset, sizeof(u32));
 844         } while (brcmf_sdcard_regfail(bus->sdiodev) &&
 845                  (++(*retryvar) <= retry_limit));
 846         if (*retryvar) {
 847                 bus->regfails += (*retryvar-1);
 848                 if (*retryvar > retry_limit) {
 849                         brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
 850                         *regvar = 0;
 851                 }
 852         }
 853 }
 854
 855 static void
 856 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
 857 {
 858         *retryvar = 0;
 859         do {
 860                 brcmf_sdcard_reg_write(bus->sdiodev,
 861                                        bus->ci->buscorebase + reg_offset,
 862                                        sizeof(u32), regval);
 863         } while (brcmf_sdcard_regfail(bus->sdiodev) &&
 864                  (++(*retryvar) <= retry_limit));
 865         if (*retryvar) {
 866                 bus->regfails += (*retryvar-1);
 867                 if (*retryvar > retry_limit)
 868                         brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
 869                                   reg_offset);
 870         }
 871 }
 872
 873 #define PKT_AVAILABLE()         (intstatus & I_HMB_FRAME_IND)
 874
 875 #define HOSTINTMASK             (I_HMB_SW_MASK | I_CHIPACTIVE)
 876
 877 #ifdef BCMDBG
 878 static int brcmf_sdbrcm_bus_console_in(struct brcmf_pub *drvr,
 879                                        unsigned char *msg, uint msglen);
 880 static int brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, u8 *data, uint size);
 881 static int brcmf_sdbrcm_mem_dump(struct brcmf_bus *bus);
 882 #endif                          /* BCMDBG  */
 883 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter);
 884
 885 static void brcmf_sdbrcm_release(struct brcmf_bus *bus);
 886 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus);
 887 static bool brcmf_sdbrcm_chipmatch(u16 chipid);
 888 static bool brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva);
 889 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus);
 890 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus);
 891 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus);
 892
 893 static uint brcmf_process_nvram_vars(char *varbuf, uint len);
 894
 895 static void brcmf_sdbrcm_setmemsize(struct brcmf_bus *bus, int mem_size);
 896 static int brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn,
 897                                uint flags, u8 *buf, uint nbytes,
 898                                struct sk_buff *pkt);
 899
 900 static bool brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus);
 901 static int  _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus);
 902
 903 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus);
 904 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus);
 905
 906 static void
 907 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase);
 908
 909 static int brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs);
 910
 911 static void
 912 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase);
 913
 914 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
 915                                         u32 drivestrength);
 916 static void brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus);
 917 static void brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar);
 918 static void brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus);
 919 static void brcmf_sdbrcm_watchdog(unsigned long data);
 920 static int brcmf_sdbrcm_watchdog_thread(void *data);
 921 static int brcmf_sdbrcm_dpc_thread(void *data);
 922 static void brcmf_sdbrcm_dpc_tasklet(unsigned long data);
 923 static void brcmf_sdbrcm_sched_dpc(struct brcmf_bus *bus);
 924 static void brcmf_sdbrcm_sdlock(struct brcmf_bus *bus);
 925 static void brcmf_sdbrcm_sdunlock(struct brcmf_bus *bus);
 926 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus);
 927 static int brcmf_sdbrcm_ioctl_resp_wait(struct brcmf_bus *bus, uint *condition,
 928                                         bool *pending);
 929 static int brcmf_sdbrcm_ioctl_resp_wake(struct brcmf_bus *bus);
 930
 931 /* Packet free applicable unconditionally for sdio and sdspi.
 932  * Conditional if bufpool was present for gspi bus.
 933  */
 934 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
 935 {
 936         if (bus->usebufpool)
 937                 brcmu_pkt_buf_free_skb(pkt);
 938 }
 939
 940 static void brcmf_sdbrcm_setmemsize(struct brcmf_bus *bus, int mem_size)
 941 {
 942         s32 min_size = DONGLE_MIN_MEMSIZE;
 943         /* Restrict the memsize to user specified limit */
 944         brcmf_dbg(ERROR, "user: Restrict the dongle ram size to %d, min %d\n",
 945                   brcmf_dongle_memsize, min_size);
 946         if ((brcmf_dongle_memsize > min_size) &&
 947             (brcmf_dongle_memsize < (s32) bus->orig_ramsize))
 948                 bus->ramsize = brcmf_dongle_memsize;
 949 }
 950
 951 static int brcmf_sdbrcm_set_siaddr_window(struct brcmf_bus *bus, u32 address)
 952 {
 953         int err = 0;
 954         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
 955                                SBSDIO_FUNC1_SBADDRLOW,
 956                                (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
 957         if (!err)
 958                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
 959                                  SBSDIO_FUNC1_SBADDRMID,
 960                                  (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
 961         if (!err)
 962                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
 963                                        SBSDIO_FUNC1_SBADDRHIGH,
 964                                        (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
 965                                        &err);
 966         return err;
 967 }
 968
 969 /* Turn backplane clock on or off */
 970 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
 971 {
 972         int err;
 973         u8 clkctl, clkreq, devctl;
 974         unsigned long timeout;
 975
 976         brcmf_dbg(TRACE, "Enter\n");
 977
 978         clkctl = 0;
 979
 980         if (on) {
 981                 /* Request HT Avail */
 982                 clkreq =
 983                     bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
 984
 985                 if ((bus->ci->chip == BCM4329_CHIP_ID)
 986                     && (bus->ci->chiprev == 0))
 987                         clkreq |= SBSDIO_FORCE_ALP;
 988
 989                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
 990                                        SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
 991                 if (err) {
 992                         brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
 993                         return -EBADE;
 994                 }
 995
 996                 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
 997                                && (bus->ci->buscorerev == 9))) {
 998                         u32 dummy, retries;
 999                         r_sdreg32(bus, &dummy,
1000                                   offsetof(struct sdpcmd_regs, clockctlstatus),
1001                                   &retries);
1002                 }
1003
1004                 /* Check current status */
1005                 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1006                                                SBSDIO_FUNC1_CHIPCLKCSR, &err);
1007                 if (err) {
1008                         brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
1009                         return -EBADE;
1010                 }
1011
1012                 /* Go to pending and await interrupt if appropriate */
1013                 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
1014                         /* Allow only clock-available interrupt */
1015                         devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
1016                                         SDIO_FUNC_1,
1017                                         SBSDIO_DEVICE_CTL, &err);
1018                         if (err) {
1019                                 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
1020                                           err);
1021                                 return -EBADE;
1022                         }
1023
1024                         devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
1025                         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1026                                                SBSDIO_DEVICE_CTL, devctl, &err);
1027                         brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
1028                         bus->clkstate = CLK_PENDING;
1029
1030                         return 0;
1031                 } else if (bus->clkstate == CLK_PENDING) {
1032                         /* Cancel CA-only interrupt filter */
1033                         devctl =
1034                             brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1035                                                   SBSDIO_DEVICE_CTL, &err);
1036                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
1037                         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1038                                 SBSDIO_DEVICE_CTL, devctl, &err);
1039                 }
1040
1041                 /* Otherwise, wait here (polling) for HT Avail */
1042                 timeout = jiffies +
1043                           msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
1044                 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
1045                         clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
1046                                                        SDIO_FUNC_1,
1047                                                        SBSDIO_FUNC1_CHIPCLKCSR,
1048                                                        &err);
1049                         if (time_after(jiffies, timeout))
1050                                 break;
1051                         else
1052                                 usleep_range(5000, 10000);
1053                 }
1054                 if (err) {
1055                         brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
1056                         return -EBADE;
1057                 }
1058                 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
1059                         brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
1060                                   PMU_MAX_TRANSITION_DLY, clkctl);
1061                         return -EBADE;
1062                 }
1063
1064                 /* Mark clock available */
1065                 bus->clkstate = CLK_AVAIL;
1066                 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
1067
1068 #if defined(BCMDBG)
1069                 if (bus->alp_only != true) {
1070                         if (SBSDIO_ALPONLY(clkctl))
1071                                 brcmf_dbg(ERROR, "HT Clock should be on\n");
1072                 }
1073 #endif                          /* defined (BCMDBG) */
1074
1075                 bus->activity = true;
1076         } else {
1077                 clkreq = 0;
1078
1079                 if (bus->clkstate == CLK_PENDING) {
1080                         /* Cancel CA-only interrupt filter */
1081                         devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
1082                                         SDIO_FUNC_1,
1083                                         SBSDIO_DEVICE_CTL, &err);
1084                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
1085                         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1086                                 SBSDIO_DEVICE_CTL, devctl, &err);
1087                 }
1088
1089                 bus->clkstate = CLK_SDONLY;
1090                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1091                         SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
1092                 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
1093                 if (err) {
1094                         brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
1095                                   err);
1096                         return -EBADE;
1097                 }
1098         }
1099         return 0;
1100 }
1101
1102 /* Change idle/active SD state */
1103 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
1104 {
1105         brcmf_dbg(TRACE, "Enter\n");
1106
1107         if (on)
1108                 bus->clkstate = CLK_SDONLY;
1109         else
1110                 bus->clkstate = CLK_NONE;
1111
1112         return 0;
1113 }
1114
1115 /* Transition SD and backplane clock readiness */
1116 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
1117 {
1118 #ifdef BCMDBG
1119         uint oldstate = bus->clkstate;
1120 #endif                          /* BCMDBG */
1121
1122         brcmf_dbg(TRACE, "Enter\n");
1123
1124         /* Early exit if we're already there */
1125         if (bus->clkstate == target) {
1126                 if (target == CLK_AVAIL) {
1127                         brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1128                         bus->activity = true;
1129                 }
1130                 return 0;
1131         }
1132
1133         switch (target) {
1134         case CLK_AVAIL:
1135                 /* Make sure SD clock is available */
1136                 if (bus->clkstate == CLK_NONE)
1137                         brcmf_sdbrcm_sdclk(bus, true);
1138                 /* Now request HT Avail on the backplane */
1139                 brcmf_sdbrcm_htclk(bus, true, pendok);
1140                 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1141                 bus->activity = true;
1142                 break;
1143
1144         case CLK_SDONLY:
1145                 /* Remove HT request, or bring up SD clock */
1146                 if (bus->clkstate == CLK_NONE)
1147                         brcmf_sdbrcm_sdclk(bus, true);
1148                 else if (bus->clkstate == CLK_AVAIL)
1149                         brcmf_sdbrcm_htclk(bus, false, false);
1150                 else
1151                         brcmf_dbg(ERROR, "request for %d -> %d\n",
1152                                   bus->clkstate, target);
1153                 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1154                 break;
1155
1156         case CLK_NONE:
1157                 /* Make sure to remove HT request */
1158                 if (bus->clkstate == CLK_AVAIL)
1159                         brcmf_sdbrcm_htclk(bus, false, false);
1160                 /* Now remove the SD clock */
1161                 brcmf_sdbrcm_sdclk(bus, false);
1162                 brcmf_sdbrcm_wd_timer(bus, 0);
1163                 break;
1164         }
1165 #ifdef BCMDBG
1166         brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
1167 #endif                          /* BCMDBG */
1168
1169         return 0;
1170 }
1171
1172 int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1173 {
1174         uint retries = 0;
1175
1176         brcmf_dbg(INFO, "request %s (currently %s)\n",
1177                   sleep ? "SLEEP" : "WAKE",
1178                   bus->sleeping ? "SLEEP" : "WAKE");
1179
1180         /* Done if we're already in the requested state */
1181         if (sleep == bus->sleeping)
1182                 return 0;
1183
1184         /* Going to sleep: set the alarm and turn off the lights... */
1185         if (sleep) {
1186                 /* Don't sleep if something is pending */
1187                 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1188                         return -EBUSY;
1189
1190                 /* Make sure the controller has the bus up */
1191                 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1192
1193                 /* Tell device to start using OOB wakeup */
1194                 w_sdreg32(bus, SMB_USE_OOB,
1195                           offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1196                 if (retries > retry_limit)
1197                         brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1198
1199                 /* Turn off our contribution to the HT clock request */
1200                 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1201
1202                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1203                         SBSDIO_FUNC1_CHIPCLKCSR,
1204                         SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1205
1206                 /* Isolate the bus */
1207                 if (bus->ci->chip != BCM4329_CHIP_ID) {
1208                         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1209                                 SBSDIO_DEVICE_CTL,
1210                                 SBSDIO_DEVCTL_PADS_ISO, NULL);
1211                 }
1212
1213                 /* Change state */
1214                 bus->sleeping = true;
1215
1216         } else {
1217                 /* Waking up: bus power up is ok, set local state */
1218
1219                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1220                         SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1221
1222                 /* Force pad isolation off if possible
1223                          (in case power never toggled) */
1224                 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1225                     && (bus->ci->buscorerev >= 10))
1226                         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1227                                 SBSDIO_DEVICE_CTL, 0, NULL);
1228
1229                 /* Make sure the controller has the bus up */
1230                 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1231
1232                 /* Send misc interrupt to indicate OOB not needed */
1233                 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1234                           &retries);
1235                 if (retries <= retry_limit)
1236                         w_sdreg32(bus, SMB_DEV_INT,
1237                                   offsetof(struct sdpcmd_regs, tosbmailbox),
1238                                   &retries);
1239
1240                 if (retries > retry_limit)
1241                         brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1242
1243                 /* Make sure we have SD bus access */
1244                 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1245
1246                 /* Change state */
1247                 bus->sleeping = false;
1248         }
1249
1250         return 0;
1251 }
1252
1253 #define BUS_WAKE(bus) \
1254         do { \
1255                 if ((bus)->sleeping) \
1256                         brcmf_sdbrcm_bussleep((bus), false); \
1257         } while (0);
1258
1259 /* Writes a HW/SW header into the packet and sends it. */
1260 /* Assumes: (a) header space already there, (b) caller holds lock */
1261 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
1262                               uint chan, bool free_pkt)
1263 {
1264         int ret;
1265         u8 *frame;
1266         u16 len, pad = 0;
1267         u32 swheader;
1268         uint retries = 0;
1269         struct sk_buff *new;
1270         int i;
1271
1272         brcmf_dbg(TRACE, "Enter\n");
1273
1274         if (bus->drvr->dongle_reset) {
1275                 ret = -EPERM;
1276                 goto done;
1277         }
1278
1279         frame = (u8 *) (pkt->data);
1280
1281         /* Add alignment padding, allocate new packet if needed */
1282         pad = ((unsigned long)frame % BRCMF_SDALIGN);
1283         if (pad) {
1284                 if (skb_headroom(pkt) < pad) {
1285                         brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
1286                                   skb_headroom(pkt), pad);
1287                         bus->drvr->tx_realloc++;
1288                         new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
1289                         if (!new) {
1290                                 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
1291                                           pkt->len + BRCMF_SDALIGN);
1292                                 ret = -ENOMEM;
1293                                 goto done;
1294                         }
1295
1296                         PKTALIGN(new, pkt->len, BRCMF_SDALIGN);
1297                         memcpy(new->data, pkt->data, pkt->len);
1298                         if (free_pkt)
1299                                 brcmu_pkt_buf_free_skb(pkt);
1300                         /* free the pkt if canned one is not used */
1301                         free_pkt = true;
1302                         pkt = new;
1303                         frame = (u8 *) (pkt->data);
1304                         /* precondition: (frame % BRCMF_SDALIGN) == 0) */
1305                         pad = 0;
1306                 } else {
1307                         skb_push(pkt, pad);
1308                         frame = (u8 *) (pkt->data);
1309                         /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
1310                         memset(frame, 0, pad + SDPCM_HDRLEN);
1311                 }
1312         }
1313         /* precondition: pad < BRCMF_SDALIGN */
1314
1315         /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1316         len = (u16) (pkt->len);
1317         *(u16 *) frame = cpu_to_le16(len);
1318         *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1319
1320         /* Software tag: channel, sequence number, data offset */
1321         swheader =
1322             ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1323             (((pad +
1324                SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1325
1326         put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1327         put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1328
1329 #ifdef BCMDBG
1330         tx_packets[pkt->priority]++;
1331         if (BRCMF_BYTES_ON() &&
1332             (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1333               (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1334                 printk(KERN_DEBUG "Tx Frame:\n");
1335                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1336         } else if (BRCMF_HDRS_ON()) {
1337                 printk(KERN_DEBUG "TxHdr:\n");
1338                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1339                                      frame, min_t(u16, len, 16));
1340         }
1341 #endif
1342
1343         /* Raise len to next SDIO block to eliminate tail command */
1344         if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1345                 u16 pad = bus->blocksize - (len % bus->blocksize);
1346                 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1347                                 len += pad;
1348         } else if (len % BRCMF_SDALIGN) {
1349                 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
1350         }
1351
1352         /* Some controllers have trouble with odd bytes -- round to even */
1353         if (forcealign && (len & (ALIGNMENT - 1)))
1354                         len = roundup(len, ALIGNMENT);
1355
1356         do {
1357                 ret = brcmf_sdbrcm_send_buf(bus,
1358                         brcmf_sdcard_cur_sbwad(bus->sdiodev),
1359                         SDIO_FUNC_2, F2SYNC, frame, len, pkt);
1360                 bus->f2txdata++;
1361
1362                 if (ret < 0) {
1363                         /* On failure, abort the command
1364                          and terminate the frame */
1365                         brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
1366                                   ret);
1367                         bus->tx_sderrs++;
1368
1369                         brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1370                         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1371                                          SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1372                                          NULL);
1373                         bus->f1regdata++;
1374
1375                         for (i = 0; i < 3; i++) {
1376                                 u8 hi, lo;
1377                                 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
1378                                                      SDIO_FUNC_1,
1379                                                      SBSDIO_FUNC1_WFRAMEBCHI,
1380                                                      NULL);
1381                                 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
1382                                                      SDIO_FUNC_1,
1383                                                      SBSDIO_FUNC1_WFRAMEBCLO,
1384                                                      NULL);
1385                                 bus->f1regdata += 2;
1386                                 if ((hi == 0) && (lo == 0))
1387                                         break;
1388                         }
1389
1390                 }
1391                 if (ret == 0)
1392                         bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1393
1394         } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1395
1396 done:
1397         /* restore pkt buffer pointer before calling tx complete routine */
1398         skb_pull(pkt, SDPCM_HDRLEN + pad);
1399         brcmf_sdbrcm_sdunlock(bus);
1400         brcmf_txcomplete(bus->drvr, pkt, ret != 0);
1401         brcmf_sdbrcm_sdlock(bus);
1402
1403         if (free_pkt)
1404                 brcmu_pkt_buf_free_skb(pkt);
1405
1406         return ret;
1407 }
1408
1409 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
1410 {
1411         int ret = -EBADE;
1412         uint datalen, prec;
1413
1414         brcmf_dbg(TRACE, "Enter\n");
1415
1416         datalen = pkt->len;
1417
1418         /* Add space for the header */
1419         skb_push(pkt, SDPCM_HDRLEN);
1420         /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
1421
1422         prec = PRIO2PREC((pkt->priority & PRIOMASK));
1423
1424         /* Check for existing queue, current flow-control,
1425                          pending event, or pending clock */
1426         if (brcmf_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1427             || bus->dpc_sched || (!DATAOK(bus))
1428             || (bus->flowcontrol & NBITVAL(prec))
1429             || (bus->clkstate != CLK_AVAIL)) {
1430                 brcmf_dbg(TRACE, "deferring pktq len %d\n",
1431                           pktq_len(&bus->txq));
1432                 bus->fcqueued++;
1433
1434                 /* Priority based enq */
1435                 spin_lock_bh(&bus->txqlock);
1436                 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) ==
1437                     false) {
1438                         skb_pull(pkt, SDPCM_HDRLEN);
1439                         brcmf_txcomplete(bus->drvr, pkt, false);
1440                         brcmu_pkt_buf_free_skb(pkt);
1441                         brcmf_dbg(ERROR, "out of bus->txq !!!\n");
1442                         ret = -ENOSR;
1443                 } else {
1444                         ret = 0;
1445                 }
1446                 spin_unlock_bh(&bus->txqlock);
1447
1448                 if (pktq_len(&bus->txq) >= TXHI)
1449                         brcmf_txflowcontrol(bus->drvr, 0, ON);
1450
1451 #ifdef BCMDBG
1452                 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1453                         qcount[prec] = pktq_plen(&bus->txq, prec);
1454 #endif
1455                 /* Schedule DPC if needed to send queued packet(s) */
1456                 if (brcmf_deferred_tx && !bus->dpc_sched) {
1457                         bus->dpc_sched = true;
1458                         brcmf_sdbrcm_sched_dpc(bus);
1459                 }
1460         } else {
1461                 /* Lock: we're about to use shared data/code (and SDIO) */
1462                 brcmf_sdbrcm_sdlock(bus);
1463
1464                 /* Otherwise, send it now */
1465                 BUS_WAKE(bus);
1466                 /* Make sure back plane ht clk is on, no pending allowed */
1467                 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
1468
1469                 brcmf_dbg(TRACE, "calling txpkt\n");
1470                 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1471                 if (ret)
1472                         bus->drvr->tx_errors++;
1473                 else
1474                         bus->drvr->dstats.tx_bytes += datalen;
1475
1476                 if (bus->idletime == BRCMF_IDLE_IMMEDIATE &&
1477                     !bus->dpc_sched) {
1478                         bus->activity = false;
1479                         brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1480                 }
1481
1482                 brcmf_sdbrcm_sdunlock(bus);
1483         }
1484
1485         return ret;
1486 }
1487
1488 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
1489 {
1490         struct sk_buff *pkt;
1491         u32 intstatus = 0;
1492         uint retries = 0;
1493         int ret = 0, prec_out;
1494         uint cnt = 0;
1495         uint datalen;
1496         u8 tx_prec_map;
1497
1498         struct brcmf_pub *drvr = bus->drvr;
1499
1500         brcmf_dbg(TRACE, "Enter\n");
1501
1502         tx_prec_map = ~bus->flowcontrol;
1503
1504         /* Send frames until the limit or some other event */
1505         for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1506                 spin_lock_bh(&bus->txqlock);
1507                 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1508                 if (pkt == NULL) {
1509                         spin_unlock_bh(&bus->txqlock);
1510                         break;
1511                 }
1512                 spin_unlock_bh(&bus->txqlock);
1513                 datalen = pkt->len - SDPCM_HDRLEN;
1514
1515                 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1516                 if (ret)
1517                         bus->drvr->tx_errors++;
1518                 else
1519                         bus->drvr->dstats.tx_bytes += datalen;
1520
1521                 /* In poll mode, need to check for other events */
1522                 if (!bus->intr && cnt) {
1523                         /* Check device status, signal pending interrupt */
1524                         r_sdreg32(bus, &intstatus,
1525                                   offsetof(struct sdpcmd_regs, intstatus),
1526                                   &retries);
1527                         bus->f2txdata++;
1528                         if (brcmf_sdcard_regfail(bus->sdiodev))
1529                                 break;
1530                         if (intstatus & bus->hostintmask)
1531                                 bus->ipend = true;
1532                 }
1533         }
1534
1535         /* Deflow-control stack if needed */
1536         if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
1537             drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
1538                 brcmf_txflowcontrol(drvr, 0, OFF);
1539
1540         return cnt;
1541 }
1542
1543 int
1544 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
1545 {
1546         u8 *frame;
1547         u16 len;
1548         u32 swheader;
1549         uint retries = 0;
1550         u8 doff = 0;
1551         int ret = -1;
1552         int i;
1553
1554         brcmf_dbg(TRACE, "Enter\n");
1555
1556         if (bus->drvr->dongle_reset)
1557                 return -EIO;
1558
1559         /* Back the pointer to make a room for bus header */
1560         frame = msg - SDPCM_HDRLEN;
1561         len = (msglen += SDPCM_HDRLEN);
1562
1563         /* Add alignment padding (optional for ctl frames) */
1564         if (brcmf_alignctl) {
1565                 doff = ((unsigned long)frame % BRCMF_SDALIGN);
1566                 if (doff) {
1567                         frame -= doff;
1568                         len += doff;
1569                         msglen += doff;
1570                         memset(frame, 0, doff + SDPCM_HDRLEN);
1571                 }
1572                 /* precondition: doff < BRCMF_SDALIGN */
1573         }
1574         doff += SDPCM_HDRLEN;
1575
1576         /* Round send length to next SDIO block */
1577         if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1578                 u16 pad = bus->blocksize - (len % bus->blocksize);
1579                 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1580                         len += pad;
1581         } else if (len % BRCMF_SDALIGN) {
1582                 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
1583         }
1584
1585         /* Satisfy length-alignment requirements */
1586         if (forcealign && (len & (ALIGNMENT - 1)))
1587                 len = roundup(len, ALIGNMENT);
1588
1589         /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
1590
1591         /* Need to lock here to protect txseq and SDIO tx calls */
1592         brcmf_sdbrcm_sdlock(bus);
1593
1594         BUS_WAKE(bus);
1595
1596         /* Make sure backplane clock is on */
1597         brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1598
1599         /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1600         *(u16 *) frame = cpu_to_le16((u16) msglen);
1601         *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1602
1603         /* Software tag: channel, sequence number, data offset */
1604         swheader =
1605             ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1606              SDPCM_CHANNEL_MASK)
1607             | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1608                              SDPCM_DOFFSET_MASK);
1609         put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1610         put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1611
1612         if (!DATAOK(bus)) {
1613                 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1614                           bus->tx_max, bus->tx_seq);
1615                 bus->ctrl_frame_stat = true;
1616                 /* Send from dpc */
1617                 bus->ctrl_frame_buf = frame;
1618                 bus->ctrl_frame_len = len;
1619
1620                 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
1621
1622                 if (bus->ctrl_frame_stat == false) {
1623                         brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
1624                         ret = 0;
1625                 } else {
1626                         brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
1627                         ret = -1;
1628                 }
1629         }
1630
1631         if (ret == -1) {
1632 #ifdef BCMDBG
1633                 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1634                         printk(KERN_DEBUG "Tx Frame:\n");
1635                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1636                                              frame, len);
1637                 } else if (BRCMF_HDRS_ON()) {
1638                         printk(KERN_DEBUG "TxHdr:\n");
1639                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1640                                              frame, min_t(u16, len, 16));
1641                 }
1642 #endif
1643
1644                 do {
1645                         bus->ctrl_frame_stat = false;
1646                         ret = brcmf_sdbrcm_send_buf(bus,
1647                                 brcmf_sdcard_cur_sbwad(bus->sdiodev),
1648                                 SDIO_FUNC_2,
1649                                 F2SYNC, frame, len, NULL);
1650
1651                         if (ret < 0) {
1652                                 /* On failure, abort the command and
1653                                  terminate the frame */
1654                                 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
1655                                           ret);
1656                                 bus->tx_sderrs++;
1657
1658                                 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1659
1660                                 brcmf_sdcard_cfg_write(bus->sdiodev,
1661                                                  SDIO_FUNC_1,
1662                                                  SBSDIO_FUNC1_FRAMECTRL,
1663                                                  SFC_WF_TERM, NULL);
1664                                 bus->f1regdata++;
1665
1666                                 for (i = 0; i < 3; i++) {
1667                                         u8 hi, lo;
1668                                         hi = brcmf_sdcard_cfg_read(bus->sdiodev,
1669                                              SDIO_FUNC_1,
1670                                              SBSDIO_FUNC1_WFRAMEBCHI,
1671                                              NULL);
1672                                         lo = brcmf_sdcard_cfg_read(bus->sdiodev,
1673                                              SDIO_FUNC_1,
1674                                              SBSDIO_FUNC1_WFRAMEBCLO,
1675                                              NULL);
1676                                         bus->f1regdata += 2;
1677                                         if ((hi == 0) && (lo == 0))
1678                                                 break;
1679                                 }
1680
1681                         }
1682                         if (ret == 0)
1683                                 bus->tx_seq =
1684                                     (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1685
1686                 } while ((ret < 0) && retries++ < TXRETRIES);
1687         }
1688
1689         if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1690                 bus->activity = false;
1691                 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1692         }
1693
1694         brcmf_sdbrcm_sdunlock(bus);
1695
1696         if (ret)
1697                 bus->drvr->tx_ctlerrs++;
1698         else
1699                 bus->drvr->tx_ctlpkts++;
1700
1701         return ret ? -EIO : 0;
1702 }
1703
1704 int
1705 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
1706 {
1707         int timeleft;
1708         uint rxlen = 0;
1709         bool pending;
1710
1711         brcmf_dbg(TRACE, "Enter\n");
1712
1713         if (bus->drvr->dongle_reset)
1714                 return -EIO;
1715
1716         /* Wait until control frame is available */
1717         timeleft = brcmf_sdbrcm_ioctl_resp_wait(bus, &bus->rxlen, &pending);
1718
1719         brcmf_sdbrcm_sdlock(bus);
1720         rxlen = bus->rxlen;
1721         memcpy(msg, bus->rxctl, min(msglen, rxlen));
1722         bus->rxlen = 0;
1723         brcmf_sdbrcm_sdunlock(bus);
1724
1725         if (rxlen) {
1726                 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
1727                           rxlen, msglen);
1728         } else if (timeleft == 0) {
1729                 brcmf_dbg(ERROR, "resumed on timeout\n");
1730 #ifdef BCMDBG
1731                 brcmf_sdbrcm_sdlock(bus);
1732                 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1733                 brcmf_sdbrcm_sdunlock(bus);
1734 #endif                          /* BCMDBG */
1735         } else if (pending == true) {
1736                 brcmf_dbg(CTL, "cancelled\n");
1737                 return -ERESTARTSYS;
1738         } else {
1739                 brcmf_dbg(CTL, "resumed for unknown reason?\n");
1740 #ifdef BCMDBG
1741                 brcmf_sdbrcm_sdlock(bus);
1742                 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1743                 brcmf_sdbrcm_sdunlock(bus);
1744 #endif                          /* BCMDBG */
1745         }
1746
1747         if (rxlen)
1748                 bus->drvr->rx_ctlpkts++;
1749         else
1750                 bus->drvr->rx_ctlerrs++;
1751
1752         return rxlen ? (int)rxlen : -ETIMEDOUT;
1753 }
1754
1755 /* IOVar table */
1756 enum {
1757         IOV_INTR = 1,
1758         IOV_POLLRATE,
1759         IOV_SDREG,
1760         IOV_SBREG,
1761         IOV_SDCIS,
1762         IOV_MEMBYTES,
1763         IOV_MEMSIZE,
1764 #ifdef BCMDBG
1765         IOV_CHECKDIED,
1766         IOV_CONS,
1767         IOV_DCONSOLE_POLL,
1768 #endif
1769         IOV_DOWNLOAD,
1770         IOV_FORCEEVEN,
1771         IOV_SDIOD_DRIVE,
1772         IOV_READAHEAD,
1773         IOV_SDRXCHAIN,
1774         IOV_ALIGNCTL,
1775         IOV_SDALIGN,
1776         IOV_DEVRESET,
1777         IOV_TXBOUND,
1778         IOV_RXBOUND,
1779         IOV_TXMINMAX,
1780         IOV_IDLETIME,
1781         IOV_IDLECLOCK,
1782         IOV_SLEEP,
1783         IOV_WDTICK,
1784         IOV_IOCTLTIMEOUT,
1785         IOV_VARS
1786 };
1787
1788 const struct brcmu_iovar brcmf_sdio_iovars[] = {
1789         {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1790         {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1791         {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1792         {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1793         {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1794         {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1795         {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1796         {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1797         {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1798         {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1799         {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1800         {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1801         {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1802         {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1803         {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1804         {"wdtick", IOV_WDTICK, 0, IOVT_UINT32, 0},
1805         {"ioctl_timeout", IOV_IOCTLTIMEOUT, 0, IOVT_UINT32, 0},
1806 #ifdef BCMDBG
1807         {"cons", IOV_CONS, 0, IOVT_BUFFER, 0}
1808         ,
1809         {"dconpoll", IOV_DCONSOLE_POLL, 0, IOVT_UINT32, 0}
1810         ,
1811         {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(struct brcmf_sdreg)}
1812         ,
1813         {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(struct brcmf_sdreg)}
1814         ,
1815         {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, BRCMF_IOCTL_MAXLEN}
1816         ,
1817         {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1818         ,
1819         {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1820         ,
1821         {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1822         ,
1823         {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1824         ,
1825         {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1826         ,
1827 #endif                          /* BCMDBG */
1828
1829         {NULL, 0, 0, 0, 0}
1830 };
1831
1832 static void
1833 brcmf_dump_pct(struct brcmu_strbuf *strbuf, char *desc, uint num, uint div)
1834 {
1835         uint q1, q2;
1836
1837         if (!div) {
1838                 brcmu_bprintf(strbuf, "%s N/A", desc);
1839         } else {
1840                 q1 = num / div;
1841                 q2 = (100 * (num - (q1 * div))) / div;
1842                 brcmu_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1843         }
1844 }
1845
1846 void brcmf_sdbrcm_bus_dump(struct brcmf_pub *drvr, struct brcmu_strbuf *strbuf)
1847 {
1848         struct brcmf_bus *bus = drvr->bus;
1849
1850         brcmu_bprintf(strbuf, "Bus SDIO structure:\n");
1851         brcmu_bprintf(strbuf,
1852                     "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1853                     bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1854         brcmu_bprintf(strbuf,
1855                     "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1856                     bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1857                     bus->rxskip, bus->rxlen, bus->rx_seq);
1858         brcmu_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1859                     bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1860         brcmu_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1861                     bus->pollrate, bus->pollcnt, bus->regfails);
1862
1863         brcmu_bprintf(strbuf, "\nAdditional counters:\n");
1864         brcmu_bprintf(strbuf,
1865                     "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1866                     bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1867                     bus->rxc_errors);
1868         brcmu_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1869                     bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1870         brcmu_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1871                       bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1872         brcmu_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1873                     bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1874         brcmu_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs"
1875                       " %d\n",
1876                       (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1877                       bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1878         {
1879                 brcmf_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->drvr->rx_packets,
1880                              (bus->f2rxhdrs + bus->f2rxdata));
1881                 brcmf_dump_pct(strbuf, ", pkts/f1sd", bus->drvr->rx_packets,
1882                              bus->f1regdata);
1883                 brcmf_dump_pct(strbuf, ", pkts/sd", bus->drvr->rx_packets,
1884                              (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1885                 brcmf_dump_pct(strbuf, ", pkts/int", bus->drvr->rx_packets,
1886                              bus->intrcount);
1887                 brcmu_bprintf(strbuf, "\n");
1888
1889                 brcmf_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1890                              bus->drvr->rx_packets);
1891                 brcmf_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1892                              bus->rxglomframes);
1893                 brcmu_bprintf(strbuf, "\n");
1894
1895                 brcmf_dump_pct(strbuf, "Tx: pkts/f2wr", bus->drvr->tx_packets,
1896                              bus->f2txdata);
1897                 brcmf_dump_pct(strbuf, ", pkts/f1sd", bus->drvr->tx_packets,
1898                              bus->f1regdata);
1899                 brcmf_dump_pct(strbuf, ", pkts/sd", bus->drvr->tx_packets,
1900                              (bus->f2txdata + bus->f1regdata));
1901                 brcmf_dump_pct(strbuf, ", pkts/int", bus->drvr->tx_packets,
1902                              bus->intrcount);
1903                 brcmu_bprintf(strbuf, "\n");
1904
1905                 brcmf_dump_pct(strbuf, "Total: pkts/f2rw",
1906                              (bus->drvr->tx_packets + bus->drvr->rx_packets),
1907                              (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1908                 brcmf_dump_pct(strbuf, ", pkts/f1sd",
1909                              (bus->drvr->tx_packets + bus->drvr->rx_packets),
1910                              bus->f1regdata);
1911                 brcmf_dump_pct(strbuf, ", pkts/sd",
1912                              (bus->drvr->tx_packets + bus->drvr->rx_packets),
1913                              (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1914                               bus->f1regdata));
1915                 brcmf_dump_pct(strbuf, ", pkts/int",
1916                              (bus->drvr->tx_packets + bus->drvr->rx_packets),
1917                              bus->intrcount);
1918                 brcmu_bprintf(strbuf, "\n\n");
1919         }
1920
1921 #ifdef BCMDBG
1922         brcmu_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1923                       bus->dpc_sched, " not ");
1924         brcmu_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1925                     bus->roundup);
1926 #endif                          /* BCMDBG */
1927         brcmu_bprintf(strbuf,
1928                     "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1929                     bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1930                     bus->sleeping);
1931 }
1932
1933 void brcmf_bus_clearcounts(struct brcmf_pub *drvr)
1934 {
1935         struct brcmf_bus *bus = (struct brcmf_bus *) drvr->bus;
1936
1937         bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1938         bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1939         bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1940         bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1941         bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1942         bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1943 }
1944
1945 static int
1946 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
1947                  uint size)
1948 {
1949         int bcmerror = 0;
1950         u32 sdaddr;
1951         uint dsize;
1952
1953         /* Determine initial transfer parameters */
1954         sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1955         if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1956                 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1957         else
1958                 dsize = size;
1959
1960         /* Set the backplane window to include the start address */
1961         bcmerror = brcmf_sdbrcm_set_siaddr_window(bus, address);
1962         if (bcmerror) {
1963                 brcmf_dbg(ERROR, "window change failed\n");
1964                 goto xfer_done;
1965         }
1966
1967         /* Do the transfer(s) */
1968         while (size) {
1969                 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
1970                           write ? "write" : "read", dsize,
1971                           sdaddr, address & SBSDIO_SBWINDOW_MASK);
1972                 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
1973                                                sdaddr, data, dsize);
1974                 if (bcmerror) {
1975                         brcmf_dbg(ERROR, "membytes transfer failed\n");
1976                         break;
1977                 }
1978
1979                 /* Adjust for next transfer (if any) */
1980                 size -= dsize;
1981                 if (size) {
1982                         data += dsize;
1983                         address += dsize;
1984                         bcmerror = brcmf_sdbrcm_set_siaddr_window(bus, address);
1985                         if (bcmerror) {
1986                                 brcmf_dbg(ERROR, "window change failed\n");
1987                                 break;
1988                         }
1989                         sdaddr = 0;
1990                         dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1991                 }
1992         }
1993
1994 xfer_done:
1995         /* Return the window to backplane enumeration space for core access */
1996         if (brcmf_sdbrcm_set_siaddr_window(bus,
1997                                            brcmf_sdcard_cur_sbwad(
1998                                                         bus->sdiodev)))
1999                 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2000                           brcmf_sdcard_cur_sbwad(bus->sdiodev));
2001
2002         return bcmerror;
2003 }
2004
2005 #ifdef BCMDBG
2006 static int
2007 brcmf_sdbrcm_readshared(struct brcmf_bus *bus, struct sdpcm_shared *sh)
2008 {
2009         u32 addr;
2010         int rv;
2011
2012         /* Read last word in memory to determine address of
2013                          sdpcm_shared structure */
2014         rv = brcmf_sdbrcm_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr,
2015                                    4);
2016         if (rv < 0)
2017                 return rv;
2018
2019         addr = le32_to_cpu(addr);
2020
2021         brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
2022
2023         /*
2024          * Check if addr is valid.
2025          * NVRAM length at the end of memory should have been overwritten.
2026          */
2027         if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2028                 brcmf_dbg(ERROR, "address (0x%08x) of sdpcm_shared invalid\n",
2029                           addr);
2030                 return -EBADE;
2031         }
2032
2033         /* Read rte_shared structure */
2034         rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *) sh,
2035                               sizeof(struct sdpcm_shared));
2036         if (rv < 0)
2037                 return rv;
2038
2039         /* Endianness */
2040         sh->flags = le32_to_cpu(sh->flags);
2041         sh->trap_addr = le32_to_cpu(sh->trap_addr);
2042         sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2043         sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2044         sh->assert_line = le32_to_cpu(sh->assert_line);
2045         sh->console_addr = le32_to_cpu(sh->console_addr);
2046         sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2047
2048         if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2049                 brcmf_dbg(ERROR, "sdpcm_shared version %d in brcmf is different than sdpcm_shared version %d in dongle\n",
2050                           SDPCM_SHARED_VERSION,
2051                           sh->flags & SDPCM_SHARED_VERSION_MASK);
2052                 return -EBADE;
2053         }
2054
2055         return 0;
2056 }
2057
2058 static int brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, u8 *data, uint size)
2059 {
2060         int bcmerror = 0;
2061         uint msize = 512;
2062         char *mbuffer = NULL;
2063         uint maxstrlen = 256;
2064         char *str = NULL;
2065         struct brcmf_trap tr;
2066         struct sdpcm_shared sdpcm_shared;
2067         struct brcmu_strbuf strbuf;
2068
2069         brcmf_dbg(TRACE, "Enter\n");
2070
2071         if (data == NULL) {
2072                 /*
2073                  * Called after a rx ctrl timeout. "data" is NULL.
2074                  * allocate memory to trace the trap or assert.
2075                  */
2076                 size = msize;
2077                 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2078                 if (mbuffer == NULL) {
2079                         brcmf_dbg(ERROR, "kmalloc(%d) failed\n", msize);
2080                         bcmerror = -ENOMEM;
2081                         goto done;
2082                 }
2083         }
2084
2085         str = kmalloc(maxstrlen, GFP_ATOMIC);
2086         if (str == NULL) {
2087                 brcmf_dbg(ERROR, "kmalloc(%d) failed\n", maxstrlen);
2088                 bcmerror = -ENOMEM;
2089                 goto done;
2090         }
2091
2092         bcmerror = brcmf_sdbrcm_readshared(bus, &sdpcm_shared);
2093         if (bcmerror < 0)
2094                 goto done;
2095
2096         brcmu_binit(&strbuf, data, size);
2097
2098         brcmu_bprintf(&strbuf,
2099                     "msgtrace address : 0x%08X\nconsole address  : 0x%08X\n",
2100                     sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2101
2102         if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
2103                 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2104                  * (Avoids conflict with real asserts for programmatic
2105                  * parsing of output.)
2106                  */
2107                 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
2108
2109         if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2110             0) {
2111                 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2112                  * (Avoids conflict with real asserts for programmatic
2113                  * parsing of output.)
2114                  */
2115                 brcmu_bprintf(&strbuf, "No trap%s in dongle",
2116                             (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2117                             ? "/assrt" : "");
2118         } else {
2119                 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2120                         /* Download assert */
2121                         brcmu_bprintf(&strbuf, "Dongle assert");
2122                         if (sdpcm_shared.assert_exp_addr != 0) {
2123                                 str[0] = '\0';
2124                                 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2125                                                 sdpcm_shared.assert_exp_addr,
2126                                                 (u8 *) str, maxstrlen);
2127                                 if (bcmerror < 0)
2128                                         goto done;
2129
2130                                 str[maxstrlen - 1] = '\0';
2131                                 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
2132                         }
2133
2134                         if (sdpcm_shared.assert_file_addr != 0) {
2135                                 str[0] = '\0';
2136                                 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2137                                                 sdpcm_shared.assert_file_addr,
2138                                                 (u8 *) str, maxstrlen);
2139                                 if (bcmerror < 0)
2140                                         goto done;
2141
2142                                 str[maxstrlen - 1] = '\0';
2143                                 brcmu_bprintf(&strbuf, " file \"%s\"", str);
2144                         }
2145
2146                         brcmu_bprintf(&strbuf, " line %d ",
2147                                     sdpcm_shared.assert_line);
2148                 }
2149
2150                 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2151                         bcmerror = brcmf_sdbrcm_membytes(bus, false,
2152                                         sdpcm_shared.trap_addr, (u8 *)&tr,
2153                                         sizeof(struct brcmf_trap));
2154                         if (bcmerror < 0)
2155                                 goto done;
2156
2157                         brcmu_bprintf(&strbuf,
2158                                     "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2159                                     "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2160                                     "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2161                                     tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2162                                     tr.r14, tr.pc, sdpcm_shared.trap_addr,
2163                                     tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2164                                     tr.r6, tr.r7);
2165                 }
2166         }
2167
2168         if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2169                 brcmf_dbg(ERROR, "%s\n", strbuf.origbuf);
2170
2171 #ifdef BCMDBG
2172         if (sdpcm_shared.flags & SDPCM_SHARED_TRAP)
2173                 /* Mem dump to a file on device */
2174                 brcmf_sdbrcm_mem_dump(bus);
2175
2176 #endif                          /* BCMDBG */
2177
2178 done:
2179         kfree(mbuffer);
2180         kfree(str);
2181
2182         return bcmerror;
2183 }
2184
2185 static int brcmf_sdbrcm_mem_dump(struct brcmf_bus *bus)
2186 {
2187         int ret = 0;
2188         int size;               /* Full mem size */
2189         int start = 0;          /* Start address */
2190         int read_size = 0;      /* Read size of each iteration */
2191         u8 *buf = NULL, *databuf = NULL;
2192
2193         /* Get full mem size */
2194         size = bus->ramsize;
2195         buf = kmalloc(size, GFP_ATOMIC);
2196         if (!buf) {
2197                 brcmf_dbg(ERROR, "Out of memory (%d bytes)\n", size);
2198                 return -1;
2199         }
2200
2201         /* Read mem content */
2202         printk(KERN_DEBUG "Dump dongle memory");
2203         databuf = buf;
2204         while (size) {
2205                 read_size = min(MEMBLOCK, size);
2206                 ret = brcmf_sdbrcm_membytes(bus, false, start, databuf,
2207                                           read_size);
2208                 if (ret) {
2209                         brcmf_dbg(ERROR, "Error membytes %d\n", ret);
2210                         kfree(buf);
2211                         return -1;
2212                 }
2213                 printk(".");
2214
2215                 /* Decrement size and increment start address */
2216                 size -= read_size;
2217                 start += read_size;
2218                 databuf += read_size;
2219         }
2220         printk(KERN_DEBUG "Done\n");
2221
2222         /* free buf before return !!! */
2223         if (brcmf_write_to_file(bus->drvr, buf, bus->ramsize)) {
2224                 brcmf_dbg(ERROR, "Error writing to files\n");
2225                 return -1;
2226         }
2227
2228         /* buf free handled in brcmf_write_to_file, not here */
2229         return 0;
2230 }
2231
2232 #define CONSOLE_LINE_MAX        192
2233
2234 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2235 {
2236         struct brcmf_console *c = &bus->console;
2237         u8 line[CONSOLE_LINE_MAX], ch;
2238         u32 n, idx, addr;
2239         int rv;
2240
2241         /* Don't do anything until FWREADY updates console address */
2242         if (bus->console_addr == 0)
2243                 return 0;
2244
2245         /* Read console log struct */
2246         addr = bus->console_addr + offsetof(struct rte_console, log);
2247         rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log,
2248                                 sizeof(c->log));
2249         if (rv < 0)
2250                 return rv;
2251
2252         /* Allocate console buffer (one time only) */
2253         if (c->buf == NULL) {
2254                 c->bufsize = le32_to_cpu(c->log.buf_size);
2255                 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2256                 if (c->buf == NULL)
2257                         return -ENOMEM;
2258         }
2259
2260         idx = le32_to_cpu(c->log.idx);
2261
2262         /* Protect against corrupt value */
2263         if (idx > c->bufsize)
2264                 return -EBADE;
2265
2266         /* Skip reading the console buffer if the index pointer
2267          has not moved */
2268         if (idx == c->last)
2269                 return 0;
2270
2271         /* Read the console buffer */
2272         addr = le32_to_cpu(c->log.buf);
2273         rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2274         if (rv < 0)
2275                 return rv;
2276
2277         while (c->last != idx) {
2278                 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2279                         if (c->last == idx) {
2280                                 /* This would output a partial line.
2281                                  * Instead, back up
2282                                  * the buffer pointer and output this
2283                                  * line next time around.
2284                                  */
2285                                 if (c->last >= n)
2286                                         c->last -= n;
2287                                 else
2288                                         c->last = c->bufsize - n;
2289                                 goto break2;
2290                         }
2291                         ch = c->buf[c->last];
2292                         c->last = (c->last + 1) % c->bufsize;
2293                         if (ch == '\n')
2294                                 break;
2295                         line[n] = ch;
2296                 }
2297
2298                 if (n > 0) {
2299                         if (line[n - 1] == '\r')
2300                                 n--;
2301                         line[n] = 0;
2302                         printk(KERN_DEBUG "CONSOLE: %s\n", line);
2303                 }
2304         }
2305 break2:
2306
2307         return 0;
2308 }
2309 #endif                          /* BCMDBG */
2310
2311 int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
2312 {
2313         int bcmerror = 0;
2314
2315         brcmf_dbg(TRACE, "Enter\n");
2316
2317         /* Basic sanity checks */
2318         if (bus->drvr->up) {
2319                 bcmerror = -EISCONN;
2320                 goto err;
2321         }
2322         if (!len) {
2323                 bcmerror = -EOVERFLOW;
2324                 goto err;
2325         }
2326
2327         /* Free the old ones and replace with passed variables */
2328         kfree(bus->vars);
2329
2330         bus->vars = kmalloc(len, GFP_ATOMIC);
2331         bus->varsz = bus->vars ? len : 0;
2332         if (bus->vars == NULL) {
2333                 bcmerror = -ENOMEM;
2334                 goto err;
2335         }
2336
2337         /* Copy the passed variables, which should include the
2338                  terminating double-null */
2339         memcpy(bus->vars, arg, bus->varsz);
2340 err:
2341         return bcmerror;
2342 }
2343
2344 static int brcmf_sdbrcm_doiovar(struct brcmf_bus *bus,
2345                                 const struct brcmu_iovar *vi, u32 actionid,
2346                                 const char *name, void *params, int plen,
2347                                 void *arg, int len, int val_size)
2348 {
2349         int bcmerror = 0;
2350         s32 int_val = 0;
2351         bool bool_val = 0;
2352
2353         brcmf_dbg(TRACE, "Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
2354                   actionid, name, params, plen, arg, len, val_size);
2355
2356         bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2357         if (bcmerror != 0)
2358                 goto exit;
2359
2360         if (plen >= (int)sizeof(int_val))
2361                 memcpy(&int_val, params, sizeof(int_val));
2362
2363         bool_val = (int_val != 0) ? true : false;
2364
2365         /* Some ioctls use the bus */
2366         brcmf_sdbrcm_sdlock(bus);
2367
2368         /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2369         if (bus->drvr->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2370                                         actionid == IOV_GVAL(IOV_DEVRESET))) {
2371                 bcmerror = -EPERM;
2372                 goto exit;
2373         }
2374
2375         /* Handle sleep stuff before any clock mucking */
2376         if (vi->varid == IOV_SLEEP) {
2377                 if (IOV_ISSET(actionid)) {
2378                         bcmerror = brcmf_sdbrcm_bussleep(bus, bool_val);
2379                 } else {
2380                         int_val = (s32) bus->sleeping;
2381                         memcpy(arg, &int_val, val_size);
2382                 }
2383                 goto exit;
2384         }
2385
2386         /* Request clock to allow SDIO accesses */
2387         if (!bus->drvr->dongle_reset) {
2388                 BUS_WAKE(bus);
2389                 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2390         }
2391
2392         switch (actionid) {
2393         case IOV_GVAL(IOV_INTR):
2394                 int_val = (s32) bus->intr;
2395                 memcpy(arg, &int_val, val_size);
2396                 break;
2397
2398         case IOV_SVAL(IOV_INTR):
2399                 bus->intr = bool_val;
2400                 break;
2401
2402         case IOV_GVAL(IOV_POLLRATE):
2403                 int_val = (s32) bus->pollrate;
2404                 memcpy(arg, &int_val, val_size);
2405                 break;
2406
2407         case IOV_SVAL(IOV_POLLRATE):
2408                 bus->pollrate = (uint) int_val;
2409                 bus->poll = (bus->pollrate != 0);
2410                 break;
2411
2412         case IOV_GVAL(IOV_IDLETIME):
2413                 int_val = bus->idletime;
2414                 memcpy(arg, &int_val, val_size);
2415                 break;
2416
2417         case IOV_SVAL(IOV_IDLETIME):
2418                 if ((int_val < 0) && (int_val != BRCMF_IDLE_IMMEDIATE))
2419                         bcmerror = -EINVAL;
2420                 else
2421                         bus->idletime = int_val;
2422                 break;
2423
2424         case IOV_GVAL(IOV_IDLECLOCK):
2425                 int_val = (s32) bus->idleclock;
2426                 memcpy(arg, &int_val, val_size);
2427                 break;
2428
2429         case IOV_SVAL(IOV_IDLECLOCK):
2430                 bus->idleclock = int_val;
2431                 break;
2432
2433         case IOV_SVAL(IOV_MEMBYTES):
2434         case IOV_GVAL(IOV_MEMBYTES):
2435                 {
2436                         u32 address;
2437                         uint size, dsize;
2438                         u8 *data;
2439
2440                         bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2441
2442                         address = (u32) int_val;
2443                         memcpy(&int_val, (char *)params + sizeof(int_val),
2444                                sizeof(int_val));
2445                         size = (uint) int_val;
2446
2447                         /* Do some validation */
2448                         dsize = set ? plen - (2 * sizeof(int)) : len;
2449                         if (dsize < size) {
2450                                 brcmf_dbg(ERROR, "error on %s membytes, addr 0x%08x size %d dsize %d\n",
2451                                           set ? "set" : "get",
2452                                           address, size, dsize);
2453                                 bcmerror = -EINVAL;
2454                                 break;
2455                         }
2456
2457                         brcmf_dbg(INFO, "Request to %s %d bytes at address 0x%08x\n",
2458                                   set ? "write" : "read", size, address);
2459
2460                         /* If we know about SOCRAM, check for a fit */
2461                         if ((bus->orig_ramsize) &&
2462                             ((address > bus->orig_ramsize)
2463                              || (address + size > bus->orig_ramsize))) {
2464                                 brcmf_dbg(ERROR, "ramsize 0x%08x doesn't have %d bytes at 0x%08x\n",
2465                                           bus->orig_ramsize, size, address);
2466                                 bcmerror = -EINVAL;
2467                                 break;
2468                         }
2469
2470                         /* Generate the actual data pointer */
2471                         data =
2472                             set ? (u8 *) params +
2473                             2 * sizeof(int) : (u8 *) arg;
2474
2475                         /* Call to do the transfer */
2476                         bcmerror = brcmf_sdbrcm_membytes(bus, set, address,
2477                                                          data, size);
2478
2479                         break;
2480                 }
2481
2482         case IOV_GVAL(IOV_MEMSIZE):
2483                 int_val = (s32) bus->ramsize;
2484                 memcpy(arg, &int_val, val_size);
2485                 break;
2486
2487         case IOV_GVAL(IOV_SDIOD_DRIVE):
2488                 int_val = (s32) brcmf_sdiod_drive_strength;
2489                 memcpy(arg, &int_val, val_size);
2490                 break;
2491
2492         case IOV_SVAL(IOV_SDIOD_DRIVE):
2493                 brcmf_sdiod_drive_strength = int_val;
2494                 brcmf_sdbrcm_sdiod_drive_strength_init(bus,
2495                                              brcmf_sdiod_drive_strength);
2496                 break;
2497
2498         case IOV_SVAL(IOV_DOWNLOAD):
2499                 bcmerror = brcmf_sdbrcm_download_state(bus, bool_val);
2500                 break;
2501
2502         case IOV_SVAL(IOV_VARS):
2503                 bcmerror = brcmf_sdbrcm_downloadvars(bus, arg, len);
2504                 break;
2505
2506         case IOV_GVAL(IOV_READAHEAD):
2507                 int_val = (s32) brcmf_readahead;
2508                 memcpy(arg, &int_val, val_size);
2509                 break;
2510
2511         case IOV_SVAL(IOV_READAHEAD):
2512                 if (bool_val && !brcmf_readahead)
2513                         bus->nextlen = 0;
2514                 brcmf_readahead = bool_val;
2515                 break;
2516
2517         case IOV_GVAL(IOV_SDRXCHAIN):
2518                 int_val = (s32) bus->use_rxchain;
2519                 memcpy(arg, &int_val, val_size);
2520                 break;
2521
2522         case IOV_SVAL(IOV_SDRXCHAIN):
2523                 if (bool_val && !bus->sd_rxchain)
2524                         bcmerror = -ENOTSUPP;
2525                 else
2526                         bus->use_rxchain = bool_val;
2527                 break;
2528         case IOV_GVAL(IOV_ALIGNCTL):
2529                 int_val = (s32) brcmf_alignctl;
2530                 memcpy(arg, &int_val, val_size);
2531                 break;
2532
2533         case IOV_SVAL(IOV_ALIGNCTL):
2534                 brcmf_alignctl = bool_val;
2535                 break;
2536
2537         case IOV_GVAL(IOV_SDALIGN):
2538                 int_val = BRCMF_SDALIGN;
2539                 memcpy(arg, &int_val, val_size);
2540                 break;
2541
2542 #ifdef BCMDBG
2543         case IOV_GVAL(IOV_VARS):
2544                 if (bus->varsz < (uint) len)
2545                         memcpy(arg, bus->vars, bus->varsz);
2546                 else
2547                         bcmerror = -EOVERFLOW;
2548                 break;
2549 #endif                          /* BCMDBG */
2550
2551 #ifdef BCMDBG
2552         case IOV_GVAL(IOV_DCONSOLE_POLL):
2553                 int_val = (s32) brcmf_console_ms;
2554                 memcpy(arg, &int_val, val_size);
2555                 break;
2556
2557         case IOV_SVAL(IOV_DCONSOLE_POLL):
2558                 brcmf_console_ms = (uint) int_val;
2559                 break;
2560
2561         case IOV_SVAL(IOV_CONS):
2562                 if (len > 0)
2563                         bcmerror = brcmf_sdbrcm_bus_console_in(bus->drvr,
2564                                                                arg, len - 1);
2565                 break;
2566
2567         case IOV_GVAL(IOV_SDREG):
2568                 {
2569                         struct brcmf_sdreg *sd_ptr;
2570                         u32 addr, size;
2571
2572                         sd_ptr = (struct brcmf_sdreg *) params;
2573
2574                         addr = bus->ci->buscorebase + sd_ptr->offset;
2575                         size = sd_ptr->func;
2576                         int_val = (s32) brcmf_sdcard_reg_read(bus->sdiodev,
2577                                                               addr, size);
2578                         if (brcmf_sdcard_regfail(bus->sdiodev))
2579                                 bcmerror = -EIO;
2580                         memcpy(arg, &int_val, sizeof(s32));
2581                         break;
2582                 }
2583
2584         case IOV_SVAL(IOV_SDREG):
2585                 {
2586                         struct brcmf_sdreg *sd_ptr;
2587                         u32 addr, size;
2588
2589                         sd_ptr = (struct brcmf_sdreg *) params;
2590
2591                         addr = bus->ci->buscorebase + sd_ptr->offset;
2592                         size = sd_ptr->func;
2593                         brcmf_sdcard_reg_write(bus->sdiodev, addr, size,
2594                                                sd_ptr->value);
2595                         if (brcmf_sdcard_regfail(bus->sdiodev))
2596                                 bcmerror = -EIO;
2597                         break;
2598                 }
2599
2600                 /* Same as above, but offset is not backplane
2601                  (not SDIO core) */
2602         case IOV_GVAL(IOV_SBREG):
2603                 {
2604                         struct brcmf_sdreg sdreg;
2605                         u32 addr, size;
2606
2607                         memcpy(&sdreg, params, sizeof(sdreg));
2608
2609                         addr = SI_ENUM_BASE + sdreg.offset;
2610                         size = sdreg.func;
2611                         int_val = (s32) brcmf_sdcard_reg_read(bus->sdiodev,
2612                                                               addr, size);
2613                         if (brcmf_sdcard_regfail(bus->sdiodev))
2614                                 bcmerror = -EIO;
2615                         memcpy(arg, &int_val, sizeof(s32));
2616                         break;
2617                 }
2618
2619         case IOV_SVAL(IOV_SBREG):
2620                 {
2621                         struct brcmf_sdreg sdreg;
2622                         u32 addr, size;
2623
2624                         memcpy(&sdreg, params, sizeof(sdreg));
2625
2626                         addr = SI_ENUM_BASE + sdreg.offset;
2627                         size = sdreg.func;
2628                         brcmf_sdcard_reg_write(bus->sdiodev, addr, size,
2629                                                sdreg.value);
2630                         if (brcmf_sdcard_regfail(bus->sdiodev))
2631                                 bcmerror = -EIO;
2632                         break;
2633                 }
2634
2635         case IOV_GVAL(IOV_SDCIS):
2636                 {
2637                         *(char *)arg = 0;
2638
2639                         strcat(arg, "\nFunc 0\n");
2640                         brcmf_sdcard_cis_read(bus->sdiodev, 0x10,
2641                                         (u8 *) arg + strlen(arg),
2642                                         SBSDIO_CIS_SIZE_LIMIT);
2643                         strcat(arg, "\nFunc 1\n");
2644                         brcmf_sdcard_cis_read(bus->sdiodev, 0x11,
2645                                         (u8 *) arg + strlen(arg),
2646                                         SBSDIO_CIS_SIZE_LIMIT);
2647                         strcat(arg, "\nFunc 2\n");
2648                         brcmf_sdcard_cis_read(bus->sdiodev, 0x12,
2649                                         (u8 *) arg + strlen(arg),
2650                                         SBSDIO_CIS_SIZE_LIMIT);
2651                         break;
2652                 }
2653
2654         case IOV_GVAL(IOV_FORCEEVEN):
2655                 int_val = (s32) forcealign;
2656                 memcpy(arg, &int_val, val_size);
2657                 break;
2658
2659         case IOV_SVAL(IOV_FORCEEVEN):
2660                 forcealign = bool_val;
2661                 break;
2662
2663         case IOV_GVAL(IOV_TXBOUND):
2664                 int_val = (s32) brcmf_txbound;
2665                 memcpy(arg, &int_val, val_size);
2666                 break;
2667
2668         case IOV_SVAL(IOV_TXBOUND):
2669                 brcmf_txbound = (uint) int_val;
2670                 break;
2671
2672         case IOV_GVAL(IOV_RXBOUND):
2673                 int_val = (s32) brcmf_rxbound;
2674                 memcpy(arg, &int_val, val_size);
2675                 break;
2676
2677         case IOV_SVAL(IOV_RXBOUND):
2678                 brcmf_rxbound = (uint) int_val;
2679                 break;
2680
2681         case IOV_GVAL(IOV_TXMINMAX):
2682                 int_val = (s32) brcmf_txminmax;
2683                 memcpy(arg, &int_val, val_size);
2684                 break;
2685
2686         case IOV_SVAL(IOV_TXMINMAX):
2687                 brcmf_txminmax = (uint) int_val;
2688                 break;
2689 #endif                          /* BCMDBG */
2690
2691         case IOV_SVAL(IOV_DEVRESET):
2692                 brcmf_dbg(TRACE, "Called set IOV_DEVRESET=%d dongle_reset=%d busstate=%d\n",
2693                           bool_val, bus->drvr->dongle_reset,
2694                           bus->drvr->busstate);
2695
2696                 brcmf_bus_devreset(bus->drvr, (u8) bool_val);
2697
2698                 break;
2699
2700         case IOV_GVAL(IOV_DEVRESET):
2701                 brcmf_dbg(TRACE, "Called get IOV_DEVRESET\n");
2702
2703                 /* Get its status */
2704                 int_val = (bool) bus->drvr->dongle_reset;
2705                 memcpy(arg, &int_val, val_size);
2706
2707                 break;
2708
2709         case IOV_GVAL(IOV_WDTICK):
2710                 int_val = (s32) brcmf_watchdog_ms;
2711                 memcpy(arg, &int_val, val_size);
2712                 break;
2713
2714         case IOV_SVAL(IOV_WDTICK):
2715                 if (!bus->drvr->up) {
2716                         bcmerror = -ENOLINK;
2717                         break;
2718                 }
2719                 brcmf_sdbrcm_wd_timer(bus, (uint) int_val);
2720                 break;
2721
2722         case IOV_GVAL(IOV_IOCTLTIMEOUT):{
2723                         int_val = brcmf_ioctl_timeout_msec;
2724                         memcpy(arg, &int_val, sizeof(int_val));
2725                         break;
2726                 }
2727
2728         case IOV_SVAL(IOV_IOCTLTIMEOUT):{
2729                         if (int_val <= 0)
2730                                 bcmerror = -EINVAL;
2731                         else
2732                                 brcmf_ioctl_timeout_msec = int_val;
2733                         break;
2734                 }
2735
2736         default:
2737                 bcmerror = -ENOTSUPP;
2738                 break;
2739         }
2740
2741 exit:
2742         if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2743                 bus->activity = false;
2744                 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2745         }
2746
2747         brcmf_sdbrcm_sdunlock(bus);
2748
2749         if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2750                 brcmf_c_preinit_ioctls(bus->drvr);
2751
2752         return bcmerror;
2753 }
2754
2755 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
2756 {
2757         int bcmerror = 0;
2758         u32 varsize;
2759         u32 varaddr;
2760         u8 *vbuffer;
2761         u32 varsizew;
2762 #ifdef BCMDBG
2763         char *nvram_ularray;
2764 #endif                          /* BCMDBG */
2765
2766         /* Even if there are no vars are to be written, we still
2767                  need to set the ramsize. */
2768         varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2769         varaddr = (bus->ramsize - 4) - varsize;
2770
2771         if (bus->vars) {
2772                 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2773                 if (!vbuffer)
2774                         return -ENOMEM;
2775
2776                 memcpy(vbuffer, bus->vars, bus->varsz);
2777
2778                 /* Write the vars list */
2779                 bcmerror =
2780                     brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
2781 #ifdef BCMDBG
2782                 /* Verify NVRAM bytes */
2783                 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
2784                 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2785                 if (!nvram_ularray)
2786                         return -ENOMEM;
2787
2788                 /* Upload image to verify downloaded contents. */
2789                 memset(nvram_ularray, 0xaa, varsize);
2790
2791                 /* Read the vars list to temp buffer for comparison */
2792                 bcmerror =
2793                     brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
2794                                      varsize);
2795                 if (bcmerror) {
2796                         brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
2797                                   bcmerror, varsize, varaddr);
2798                 }
2799                 /* Compare the org NVRAM with the one read from RAM */
2800                 if (memcmp(vbuffer, nvram_ularray, varsize))
2801                         brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
2802                 else
2803                         brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
2804
2805                 kfree(nvram_ularray);
2806 #endif                          /* BCMDBG */
2807
2808                 kfree(vbuffer);
2809         }
2810
2811         /* adjust to the user specified RAM */
2812         brcmf_dbg(INFO, "Physical memory size: %d, usable memory size: %d\n",
2813                   bus->orig_ramsize, bus->ramsize);
2814         brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
2815                   varaddr, varsize);
2816         varsize = ((bus->orig_ramsize - 4) - varaddr);
2817
2818         /*
2819          * Determine the length token:
2820          * Varsize, converted to words, in lower 16-bits, checksum
2821          * in upper 16-bits.
2822          */
2823         if (bcmerror) {
2824                 varsizew = 0;
2825         } else {
2826                 varsizew = varsize / 4;
2827                 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2828                 varsizew = cpu_to_le32(varsizew);
2829         }
2830
2831         brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
2832                   varsize, varsizew);
2833
2834         /* Write the length token to the last word */
2835         bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->orig_ramsize - 4),
2836                                     (u8 *)&varsizew, 4);
2837
2838         return bcmerror;
2839 }
2840
2841 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
2842 {
2843         uint retries;
2844         u32 regdata;
2845         int bcmerror = 0;
2846
2847         /* To enter download state, disable ARM and reset SOCRAM.
2848          * To exit download state, simply reset ARM (default is RAM boot).
2849          */
2850         if (enter) {
2851                 bus->alp_only = true;
2852
2853                 brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
2854                                               bus->ci->armcorebase);
2855
2856                 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
2857
2858                 /* Clear the top bit of memory */
2859                 if (bus->ramsize) {
2860                         u32 zeros = 0;
2861                         brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
2862                                          (u8 *)&zeros, 4);
2863                 }
2864         } else {
2865                 regdata = brcmf_sdcard_reg_read(bus->sdiodev,
2866                         CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2867                 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2868                         (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2869                 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2870                         brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
2871                         bcmerror = -EBADE;
2872                         goto fail;
2873                 }
2874
2875                 bcmerror = brcmf_sdbrcm_write_vars(bus);
2876                 if (bcmerror) {
2877                         brcmf_dbg(ERROR, "no vars written to RAM\n");
2878                         bcmerror = 0;
2879                 }
2880
2881                 w_sdreg32(bus, 0xFFFFFFFF,
2882                           offsetof(struct sdpcmd_regs, intstatus), &retries);
2883
2884                 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
2885
2886                 /* Allow HT Clock now that the ARM is running. */
2887                 bus->alp_only = false;
2888
2889                 bus->drvr->busstate = BRCMF_BUS_LOAD;
2890         }
2891 fail:
2892         return bcmerror;
2893 }
2894
2895 int
2896 brcmf_sdbrcm_bus_iovar_op(struct brcmf_pub *drvr, const char *name,
2897                           void *params, int plen, void *arg, int len, bool set)
2898 {
2899         struct brcmf_bus *bus = drvr->bus;
2900         const struct brcmu_iovar *vi = NULL;
2901         int bcmerror = 0;
2902         int val_size;
2903         u32 actionid;
2904
2905         brcmf_dbg(TRACE, "Enter\n");
2906
2907         if (name == NULL || len < 0)
2908                 return -EINVAL;
2909
2910         /* Set does not take qualifiers */
2911         if (set && (params || plen))
2912                 return -EINVAL;
2913
2914         /* Get must have return space;*/
2915         if (!set && !(arg && len))
2916                 return -EINVAL;
2917
2918         /* Look up var locally; if not found pass to host driver */
2919         vi = brcmu_iovar_lookup(brcmf_sdio_iovars, name);
2920         if (vi == NULL) {
2921                 brcmf_sdbrcm_sdlock(bus);
2922
2923                 BUS_WAKE(bus);
2924
2925                 /* Turn on clock in case SD command needs backplane */
2926                 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2927
2928                 bcmerror = brcmf_sdcard_iovar_op(bus->sdiodev, name, params,
2929                                                  plen, arg, len, set);
2930
2931                 if (bus->idletime == BRCMF_IDLE_IMMEDIATE &&
2932                     !bus->dpc_sched) {
2933                         bus->activity = false;
2934                         brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2935                 }
2936
2937                 brcmf_sdbrcm_sdunlock(bus);
2938                 goto exit;
2939         }
2940
2941         brcmf_dbg(CTL, "%s %s, len %d plen %d\n",
2942                   name, set ? "set" : "get", len, plen);
2943
2944         /* set up 'params' pointer in case this is a set command so that
2945          * the convenience int and bool code can be common to set and get
2946          */
2947         if (params == NULL) {
2948                 params = arg;
2949                 plen = len;
2950         }
2951
2952         if (vi->type == IOVT_VOID)
2953                 val_size = 0;
2954         else if (vi->type == IOVT_BUFFER)
2955                 val_size = len;
2956         else
2957                 /* all other types are integer sized */
2958                 val_size = sizeof(int);
2959
2960         actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2961         bcmerror = brcmf_sdbrcm_doiovar(bus, vi, actionid, name, params, plen,
2962                                         arg, len, val_size);
2963
2964 exit:
2965         return bcmerror;
2966 }
2967
2968 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus, bool enforce_mutex)
2969 {
2970         u32 local_hostintmask;
2971         u8 saveclk;
2972         uint retries;
2973         int err;
2974
2975         brcmf_dbg(TRACE, "Enter\n");
2976
2977         if (enforce_mutex)
2978                 brcmf_sdbrcm_sdlock(bus);
2979
2980         BUS_WAKE(bus);
2981
2982         /* Enable clock for device interrupts */
2983         brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2984
2985         if (bus->watchdog_tsk) {
2986                 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2987                 kthread_stop(bus->watchdog_tsk);
2988                 bus->watchdog_tsk = NULL;
2989         }
2990
2991         if (bus->dpc_tsk) {
2992                 send_sig(SIGTERM, bus->dpc_tsk, 1);
2993                 kthread_stop(bus->dpc_tsk);
2994                 bus->dpc_tsk = NULL;
2995         } else
2996                 tasklet_kill(&bus->tasklet);
2997
2998         /* Disable and clear interrupts at the chip level also */
2999         w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3000         local_hostintmask = bus->hostintmask;
3001         bus->hostintmask = 0;
3002
3003         /* Change our idea of bus state */
3004         bus->drvr->busstate = BRCMF_BUS_DOWN;
3005
3006         /* Force clocks on backplane to be sure F2 interrupt propagates */
3007         saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3008                                         SBSDIO_FUNC1_CHIPCLKCSR, &err);
3009         if (!err) {
3010                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3011                                        SBSDIO_FUNC1_CHIPCLKCSR,
3012                                        (saveclk | SBSDIO_FORCE_HT), &err);
3013         }
3014         if (err)
3015                 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3016
3017         /* Turn off the bus (F2), free any pending packets */
3018         brcmf_dbg(INTR, "disable SDIO interrupts\n");
3019         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3020                          SDIO_FUNC_ENABLE_1, NULL);
3021
3022         /* Clear any pending interrupts now that F2 is disabled */
3023         w_sdreg32(bus, local_hostintmask,
3024                   offsetof(struct sdpcmd_regs, intstatus), &retries);
3025
3026         /* Turn off the backplane clock (only) */
3027         brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3028
3029         /* Clear the data packet queues */
3030         brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3031
3032         /* Clear any held glomming stuff */
3033         if (bus->glomd)
3034                 brcmu_pkt_buf_free_skb(bus->glomd);
3035
3036         if (bus->glom)
3037                 brcmu_pkt_buf_free_skb(bus->glom);
3038
3039         bus->glom = bus->glomd = NULL;
3040
3041         /* Clear rx control and wake any waiters */
3042         bus->rxlen = 0;
3043         brcmf_sdbrcm_ioctl_resp_wake(bus);
3044
3045         /* Reset some F2 state stuff */
3046         bus->rxskip = false;
3047         bus->tx_seq = bus->rx_seq = 0;
3048
3049         if (enforce_mutex)
3050                 brcmf_sdbrcm_sdunlock(bus);
3051 }
3052
3053 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr, bool enforce_mutex)
3054 {
3055         struct brcmf_bus *bus = drvr->bus;
3056         unsigned long timeout;
3057         uint retries = 0;
3058         u8 ready, enable;
3059         int err, ret = 0;
3060         u8 saveclk;
3061
3062         brcmf_dbg(TRACE, "Enter\n");
3063
3064         /* try to download image and nvram to the dongle */
3065         if (drvr->busstate == BRCMF_BUS_DOWN) {
3066                 if (!(brcmf_sdbrcm_download_firmware(bus)))
3067                         return -1;
3068         }
3069
3070         if (!bus->drvr)
3071                 return 0;
3072
3073         /* Start the watchdog timer */
3074         bus->drvr->tickcnt = 0;
3075         brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
3076
3077         if (enforce_mutex)
3078                 brcmf_sdbrcm_sdlock(bus);
3079
3080         /* Make sure backplane clock is on, needed to generate F2 interrupt */
3081         brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3082         if (bus->clkstate != CLK_AVAIL)
3083                 goto exit;
3084
3085         /* Force clocks on backplane to be sure F2 interrupt propagates */
3086         saveclk =
3087             brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3088                                   SBSDIO_FUNC1_CHIPCLKCSR, &err);
3089         if (!err) {
3090                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3091                                        SBSDIO_FUNC1_CHIPCLKCSR,
3092                                        (saveclk | SBSDIO_FORCE_HT), &err);
3093         }
3094         if (err) {
3095                 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3096                 goto exit;
3097         }
3098
3099         /* Enable function 2 (frame transfers) */
3100         w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3101                   offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3102         enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3103
3104         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3105                                enable, NULL);
3106
3107         timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3108         ready = 0;
3109         while (enable != ready) {
3110                 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3111                                               SDIO_CCCR_IORx, NULL);
3112                 if (time_after(jiffies, timeout))
3113                         break;
3114                 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3115                         /* prevent busy waiting if it takes too long */
3116                         msleep_interruptible(20);
3117         }
3118
3119         brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3120
3121         /* If F2 successfully enabled, set core and enable interrupts */
3122         if (ready == enable) {
3123                 /* Set up the interrupt mask and enable interrupts */
3124                 bus->hostintmask = HOSTINTMASK;
3125                 w_sdreg32(bus, bus->hostintmask,
3126                           offsetof(struct sdpcmd_regs, hostintmask), &retries);
3127
3128                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3129                                        SBSDIO_WATERMARK, 8, &err);
3130
3131                 /* Set bus state according to enable result */
3132                 drvr->busstate = BRCMF_BUS_DATA;
3133         }
3134
3135         else {
3136                 /* Disable F2 again */
3137                 enable = SDIO_FUNC_ENABLE_1;
3138                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3139                                        SDIO_CCCR_IOEx, enable, NULL);
3140         }
3141
3142         /* Restore previous clock setting */
3143         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3144                                SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3145
3146         /* If we didn't come up, turn off backplane clock */
3147         if (drvr->busstate != BRCMF_BUS_DATA)
3148                 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3149
3150 exit:
3151         if (enforce_mutex)
3152                 brcmf_sdbrcm_sdunlock(bus);
3153
3154         return ret;
3155 }
3156
3157 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
3158 {
3159         uint retries = 0;
3160         u16 lastrbc;
3161         u8 hi, lo;
3162         int err;
3163
3164         brcmf_dbg(ERROR, "%sterminate frame%s\n",
3165                   abort ? "abort command, " : "",
3166                   rtx ? ", send NAK" : "");
3167
3168         if (abort)
3169                 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
3170
3171         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3172                                SBSDIO_FUNC1_FRAMECTRL,
3173                                SFC_RF_TERM, &err);
3174         bus->f1regdata++;
3175
3176         /* Wait until the packet has been flushed (device/FIFO stable) */
3177         for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3178                 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3179                                            SBSDIO_FUNC1_RFRAMEBCHI, NULL);
3180                 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3181                                            SBSDIO_FUNC1_RFRAMEBCLO, NULL);
3182                 bus->f1regdata += 2;
3183
3184                 if ((hi == 0) && (lo == 0))
3185                         break;
3186
3187                 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3188                         brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
3189                                   lastrbc, (hi << 8) + lo);
3190                 }
3191                 lastrbc = (hi << 8) + lo;
3192         }
3193
3194         if (!retries)
3195                 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
3196         else
3197                 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
3198
3199         if (rtx) {
3200                 bus->rxrtx++;
3201                 w_sdreg32(bus, SMB_NAK,
3202                           offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
3203
3204                 bus->f1regdata++;
3205                 if (retries <= retry_limit)
3206                         bus->rxskip = true;
3207         }
3208
3209         /* Clear partial in any case */
3210         bus->nextlen = 0;
3211
3212         /* If we can't reach the device, signal failure */
3213         if (err || brcmf_sdcard_regfail(bus->sdiodev))
3214                 bus->drvr->busstate = BRCMF_BUS_DOWN;
3215 }
3216
3217 static void
3218 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
3219 {
3220         uint rdlen, pad;
3221
3222         int sdret;
3223
3224         brcmf_dbg(TRACE, "Enter\n");
3225
3226         /* Set rxctl for frame (w/optional alignment) */
3227         bus->rxctl = bus->rxbuf;
3228         if (brcmf_alignctl) {
3229                 bus->rxctl += firstread;
3230                 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
3231                 if (pad)
3232                         bus->rxctl += (BRCMF_SDALIGN - pad);
3233                 bus->rxctl -= firstread;
3234         }
3235
3236         /* Copy the already-read portion over */
3237         memcpy(bus->rxctl, hdr, firstread);
3238         if (len <= firstread)
3239                 goto gotpkt;
3240
3241         /* Raise rdlen to next SDIO block to avoid tail command */
3242         rdlen = len - firstread;
3243         if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3244                 pad = bus->blocksize - (rdlen % bus->blocksize);
3245                 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3246                     ((len + pad) < bus->drvr->maxctl))
3247                         rdlen += pad;
3248         } else if (rdlen % BRCMF_SDALIGN) {
3249                 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
3250         }
3251
3252         /* Satisfy length-alignment requirements */
3253         if (forcealign && (rdlen & (ALIGNMENT - 1)))
3254                 rdlen = roundup(rdlen, ALIGNMENT);
3255
3256         /* Drop if the read is too big or it exceeds our maximum */
3257         if ((rdlen + firstread) > bus->drvr->maxctl) {
3258                 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
3259                           rdlen, bus->drvr->maxctl);
3260                 bus->drvr->rx_errors++;
3261                 brcmf_sdbrcm_rxfail(bus, false, false);
3262                 goto done;
3263         }
3264
3265         if ((len - doff) > bus->drvr->maxctl) {
3266                 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
3267                           len, len - doff, bus->drvr->maxctl);
3268                 bus->drvr->rx_errors++;
3269                 bus->rx_toolong++;
3270                 brcmf_sdbrcm_rxfail(bus, false, false);
3271                 goto done;
3272         }
3273
3274         /* Read remainder of frame body into the rxctl buffer */
3275         sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
3276                                 brcmf_sdcard_cur_sbwad(bus->sdiodev),
3277                                 SDIO_FUNC_2,
3278                                 F2SYNC, (bus->rxctl + firstread), rdlen,
3279                                 NULL);
3280         bus->f2rxdata++;
3281
3282         /* Control frame failures need retransmission */
3283         if (sdret < 0) {
3284                 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
3285                           rdlen, sdret);
3286                 bus->rxc_errors++;
3287                 brcmf_sdbrcm_rxfail(bus, true, true);
3288                 goto done;
3289         }
3290
3291 gotpkt:
3292
3293 #ifdef BCMDBG
3294         if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
3295                 printk(KERN_DEBUG "RxCtrl:\n");
3296                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3297         }
3298 #endif
3299
3300         /* Point to valid data and indicate its length */
3301         bus->rxctl += doff;
3302         bus->rxlen = len - doff;
3303
3304 done:
3305         /* Awake any waiters */
3306         brcmf_sdbrcm_ioctl_resp_wake(bus);
3307 }
3308
3309 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
3310 {
3311         u16 dlen, totlen;
3312         u8 *dptr, num = 0;
3313
3314         u16 sublen, check;
3315         struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3316
3317         int errcode;
3318         u8 chan, seq, doff, sfdoff;
3319         u8 txmax;
3320
3321         int ifidx = 0;
3322         bool usechain = bus->use_rxchain;
3323
3324         /* If packets, issue read(s) and send up packet chain */
3325         /* Return sequence numbers consumed? */
3326
3327         brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom);
3328
3329         /* If there's a descriptor, generate the packet chain */
3330         if (bus->glomd) {
3331                 pfirst = plast = pnext = NULL;
3332                 dlen = (u16) (bus->glomd->len);
3333                 dptr = bus->glomd->data;
3334                 if (!dlen || (dlen & 1)) {
3335                         brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
3336                                   dlen);
3337                         dlen = 0;
3338                 }
3339
3340                 for (totlen = num = 0; dlen; num++) {
3341                         /* Get (and move past) next length */
3342                         sublen = get_unaligned_le16(dptr);
3343                         dlen -= sizeof(u16);
3344                         dptr += sizeof(u16);
3345                         if ((sublen < SDPCM_HDRLEN) ||
3346                             ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3347                                 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
3348                                           num, sublen);
3349                                 pnext = NULL;
3350                                 break;
3351                         }
3352                         if (sublen % BRCMF_SDALIGN) {
3353                                 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
3354                                           sublen, BRCMF_SDALIGN);
3355                                 usechain = false;
3356                         }
3357                         totlen += sublen;
3358
3359                         /* For last frame, adjust read len so total
3360                                  is a block multiple */
3361                         if (!dlen) {
3362                                 sublen +=
3363                                     (roundup(totlen, bus->blocksize) - totlen);
3364                                 totlen = roundup(totlen, bus->blocksize);
3365                         }
3366
3367                         /* Allocate/chain packet for next subframe */
3368                         pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
3369                         if (pnext == NULL) {
3370                                 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
3371                                           num, sublen);
3372                                 break;
3373                         }
3374                         if (!pfirst) {
3375                                 pfirst = plast = pnext;
3376                         } else {
3377                                 plast->next = pnext;
3378                                 plast = pnext;
3379                         }
3380
3381                         /* Adhere to start alignment requirements */
3382                         PKTALIGN(pnext, sublen, BRCMF_SDALIGN);
3383                 }
3384
3385                 /* If all allocations succeeded, save packet chain
3386                          in bus structure */
3387                 if (pnext) {
3388                         brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
3389                                   totlen, num);
3390                         if (BRCMF_GLOM_ON() && bus->nextlen) {
3391                                 if (totlen != bus->nextlen) {
3392                                         brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
3393                                                   bus->nextlen, totlen, rxseq);
3394                                 }
3395                         }
3396                         bus->glom = pfirst;
3397                         pfirst = pnext = NULL;
3398                 } else {
3399                         if (pfirst)
3400                                 brcmu_pkt_buf_free_skb(pfirst);
3401                         bus->glom = NULL;
3402                         num = 0;
3403                 }
3404
3405                 /* Done with descriptor packet */
3406                 brcmu_pkt_buf_free_skb(bus->glomd);
3407                 bus->glomd = NULL;
3408                 bus->nextlen = 0;
3409         }
3410
3411         /* Ok -- either we just generated a packet chain,
3412                  or had one from before */
3413         if (bus->glom) {
3414                 if (BRCMF_GLOM_ON()) {
3415                         brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
3416                         for (pnext = bus->glom; pnext; pnext = pnext->next) {
3417                                 brcmf_dbg(GLOM, "    %p: %p len 0x%04x (%d)\n",
3418                                           pnext, (u8 *) (pnext->data),
3419                                           pnext->len, pnext->len);
3420                         }
3421                 }
3422
3423                 pfirst = bus->glom;
3424                 dlen = (u16) brcmu_pkttotlen(pfirst);
3425
3426                 /* Do an SDIO read for the superframe.  Configurable iovar to
3427                  * read directly into the chained packet, or allocate a large
3428                  * packet and and copy into the chain.
3429                  */
3430                 if (usechain) {
3431                         errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
3432                                         brcmf_sdcard_cur_sbwad(bus->sdiodev),
3433                                         SDIO_FUNC_2,
3434                                         F2SYNC, (u8 *) pfirst->data, dlen,
3435                                         pfirst);
3436                 } else if (bus->dataptr) {
3437                         errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
3438                                         brcmf_sdcard_cur_sbwad(bus->sdiodev),
3439                                         SDIO_FUNC_2,
3440                                         F2SYNC, bus->dataptr, dlen,
3441                                         NULL);
3442                         sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
3443                                                 bus->dataptr);
3444                         if (sublen != dlen) {
3445                                 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
3446                                           dlen, sublen);
3447                                 errcode = -1;
3448                         }
3449                         pnext = NULL;
3450                 } else {
3451                         brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3452                                   dlen);
3453                         errcode = -1;
3454                 }
3455                 bus->f2rxdata++;
3456
3457                 /* On failure, kill the superframe, allow a couple retries */
3458                 if (errcode < 0) {
3459                         brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
3460                                   dlen, errcode);
3461                         bus->drvr->rx_errors++;
3462
3463                         if (bus->glomerr++ < 3) {
3464                                 brcmf_sdbrcm_rxfail(bus, true, true);
3465                         } else {
3466                                 bus->glomerr = 0;
3467                                 brcmf_sdbrcm_rxfail(bus, true, false);
3468                                 brcmu_pkt_buf_free_skb(bus->glom);
3469                                 bus->rxglomfail++;
3470                                 bus->glom = NULL;
3471                         }
3472                         return 0;
3473                 }
3474 #ifdef BCMDBG
3475                 if (BRCMF_GLOM_ON()) {
3476                         printk(KERN_DEBUG "SUPERFRAME:\n");
3477                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3478                                 pfirst->data, min_t(int, pfirst->len, 48));
3479                 }
3480 #endif
3481
3482                 /* Validate the superframe header */
3483                 dptr = (u8 *) (pfirst->data);
3484                 sublen = get_unaligned_le16(dptr);
3485                 check = get_unaligned_le16(dptr + sizeof(u16));
3486
3487                 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3488                 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3489                 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3490                 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3491                         brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
3492                                   bus->nextlen, seq);
3493                         bus->nextlen = 0;
3494                 }
3495                 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3496                 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3497
3498                 errcode = 0;
3499                 if ((u16)~(sublen ^ check)) {
3500                         brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
3501                                   sublen, check);
3502                         errcode = -1;
3503                 } else if (roundup(sublen, bus->blocksize) != dlen) {
3504                         brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
3505                                   sublen, roundup(sublen, bus->blocksize),
3506                                   dlen);
3507                         errcode = -1;
3508                 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3509                            SDPCM_GLOM_CHANNEL) {
3510                         brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
3511                                   SDPCM_PACKET_CHANNEL(
3512                                           &dptr[SDPCM_FRAMETAG_LEN]));
3513                         errcode = -1;
3514                 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3515                         brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
3516                         errcode = -1;
3517                 } else if ((doff < SDPCM_HDRLEN) ||
3518                            (doff > (pfirst->len - SDPCM_HDRLEN))) {
3519                         brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
3520                                   doff, sublen, pfirst->len, SDPCM_HDRLEN);
3521                         errcode = -1;
3522                 }
3523
3524                 /* Check sequence number of superframe SW header */
3525                 if (rxseq != seq) {
3526                         brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
3527                                   seq, rxseq);
3528                         bus->rx_badseq++;
3529                         rxseq = seq;
3530                 }
3531
3532                 /* Check window for sanity */
3533                 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3534                         brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
3535                                   txmax, bus->tx_seq);
3536                         txmax = bus->tx_seq + 2;
3537                 }
3538                 bus->tx_max = txmax;
3539
3540                 /* Remove superframe header, remember offset */
3541                 skb_pull(pfirst, doff);
3542                 sfdoff = doff;
3543
3544                 /* Validate all the subframe headers */
3545                 for (num = 0, pnext = pfirst; pnext && !errcode;
3546                      num++, pnext = pnext->next) {
3547                         dptr = (u8 *) (pnext->data);
3548                         dlen = (u16) (pnext->len);
3549                         sublen = get_unaligned_le16(dptr);
3550                         check = get_unaligned_le16(dptr + sizeof(u16));
3551                         chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3552                         doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3553 #ifdef BCMDBG
3554                         if (BRCMF_GLOM_ON()) {
3555                                 printk(KERN_DEBUG "subframe:\n");
3556                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3557                                                      dptr, 32);
3558                         }
3559 #endif
3560
3561                         if ((u16)~(sublen ^ check)) {
3562                                 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
3563                                           num, sublen, check);
3564                                 errcode = -1;
3565                         } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3566                                 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
3567                                           num, sublen, dlen);
3568                                 errcode = -1;
3569                         } else if ((chan != SDPCM_DATA_CHANNEL) &&
3570                                    (chan != SDPCM_EVENT_CHANNEL)) {
3571                                 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
3572                                           num, chan);
3573                                 errcode = -1;
3574                         } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3575                                 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
3576                                           num, doff, sublen, SDPCM_HDRLEN);
3577                                 errcode = -1;
3578                         }
3579                 }
3580
3581                 if (errcode) {
3582                         /* Terminate frame on error, request
3583                                  a couple retries */
3584                         if (bus->glomerr++ < 3) {
3585                                 /* Restore superframe header space */
3586                                 skb_push(pfirst, sfdoff);
3587                                 brcmf_sdbrcm_rxfail(bus, true, true);
3588                         } else {
3589                                 bus->glomerr = 0;
3590                                 brcmf_sdbrcm_rxfail(bus, true, false);
3591                                 brcmu_pkt_buf_free_skb(bus->glom);
3592                                 bus->rxglomfail++;
3593                                 bus->glom = NULL;
3594                         }
3595                         bus->nextlen = 0;
3596                         return 0;
3597                 }
3598
3599                 /* Basic SD framing looks ok - process each packet (header) */
3600                 save_pfirst = pfirst;
3601                 bus->glom = NULL;
3602                 plast = NULL;
3603
3604                 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3605                         pnext = pfirst->next;
3606                         pfirst->next = NULL;
3607
3608                         dptr = (u8 *) (pfirst->data);
3609                         sublen = get_unaligned_le16(dptr);
3610                         chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3611                         seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3612                         doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3613
3614                         brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
3615                                   num, pfirst, pfirst->data,
3616                                   pfirst->len, sublen, chan, seq);
3617
3618                         /* precondition: chan == SDPCM_DATA_CHANNEL ||
3619                                          chan == SDPCM_EVENT_CHANNEL */
3620
3621                         if (rxseq != seq) {
3622                                 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
3623                                           seq, rxseq);
3624                                 bus->rx_badseq++;
3625                                 rxseq = seq;
3626                         }
3627 #ifdef BCMDBG
3628                         if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
3629                                 printk(KERN_DEBUG "Rx Subframe Data:\n");
3630                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3631                                                      dptr, dlen);
3632                         }
3633 #endif
3634
3635                         __skb_trim(pfirst, sublen);
3636                         skb_pull(pfirst, doff);
3637
3638                         if (pfirst->len == 0) {
3639                                 brcmu_pkt_buf_free_skb(pfirst);
3640                                 if (plast)
3641                                         plast->next = pnext;
3642                                 else
3643                                         save_pfirst = pnext;
3644
3645                                 continue;
3646                         } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
3647                                                        pfirst) != 0) {
3648                                 brcmf_dbg(ERROR, "rx protocol error\n");
3649                                 bus->drvr->rx_errors++;
3650                                 brcmu_pkt_buf_free_skb(pfirst);
3651                                 if (plast)
3652                                         plast->next = pnext;
3653                                 else
3654                                         save_pfirst = pnext;
3655
3656                                 continue;
3657                         }
3658
3659                         /* this packet will go up, link back into
3660                                  chain and count it */
3661                         pfirst->next = pnext;
3662                         plast = pfirst;
3663                         num++;
3664
3665 #ifdef BCMDBG
3666                         if (BRCMF_GLOM_ON()) {
3667                                 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
3668                                           num, pfirst, pfirst->data,
3669                                           pfirst->len, pfirst->next,
3670                                           pfirst->prev);
3671                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3672                                                 pfirst->data,
3673                                                 min_t(int, pfirst->len, 32));
3674                         }
3675 #endif                          /* BCMDBG */
3676                 }
3677                 if (num) {
3678                         brcmf_sdbrcm_sdunlock(bus);
3679                         brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
3680                         brcmf_sdbrcm_sdlock(bus);
3681                 }
3682
3683                 bus->rxglomframes++;
3684                 bus->rxglompkts += num;
3685         }
3686         return num;
3687 }
3688
3689 /* Return true if there may be more frames to read */
3690 static uint
3691 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
3692 {
3693         u16 len, check; /* Extracted hardware header fields */
3694         u8 chan, seq, doff;     /* Extracted software header fields */
3695         u8 fcbits;              /* Extracted fcbits from software header */
3696
3697         struct sk_buff *pkt;            /* Packet for event or data frames */
3698         u16 pad;                /* Number of pad bytes to read */
3699         u16 rdlen;              /* Total number of bytes to read */
3700         u8 rxseq;               /* Next sequence number to expect */
3701         uint rxleft = 0;        /* Remaining number of frames allowed */
3702         int sdret;              /* Return code from calls */
3703         u8 txmax;               /* Maximum tx sequence offered */
3704         bool len_consistent;    /* Result of comparing readahead len and
3705                                          len from hw-hdr */
3706         u8 *rxbuf;
3707         int ifidx = 0;
3708         uint rxcount = 0;       /* Total frames read */
3709
3710         brcmf_dbg(TRACE, "Enter\n");
3711
3712         /* Not finished unless we encounter no more frames indication */
3713         *finished = false;
3714
3715         for (rxseq = bus->rx_seq, rxleft = maxframes;
3716              !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
3717              rxseq++, rxleft--) {
3718
3719                 /* Handle glomming separately */
3720                 if (bus->glom || bus->glomd) {
3721                         u8 cnt;
3722                         brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
3723                                   bus->glomd, bus->glom);
3724                         cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
3725                         brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
3726                         rxseq += cnt - 1;
3727                         rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3728                         continue;
3729                 }
3730
3731                 /* Try doing single read if we can */
3732                 if (brcmf_readahead && bus->nextlen) {
3733                         u16 nextlen = bus->nextlen;
3734                         bus->nextlen = 0;
3735
3736                         rdlen = len = nextlen << 4;
3737
3738                         /* Pad read to blocksize for efficiency */
3739                         if (bus->roundup && bus->blocksize
3740                             && (rdlen > bus->blocksize)) {
3741                                 pad =
3742                                     bus->blocksize -
3743                                     (rdlen % bus->blocksize);
3744                                 if ((pad <= bus->roundup)
3745                                     && (pad < bus->blocksize)
3746                                     && ((rdlen + pad + firstread) <
3747                                         MAX_RX_DATASZ))
3748                                         rdlen += pad;
3749                         } else if (rdlen % BRCMF_SDALIGN) {
3750                                 rdlen += BRCMF_SDALIGN -
3751                                          (rdlen % BRCMF_SDALIGN);
3752                         }
3753
3754                         /* We use bus->rxctl buffer in WinXP for initial
3755                          * control pkt receives.
3756                          * Later we use buffer-poll for data as well
3757                          * as control packets.
3758                          * This is required because dhd receives full
3759                          * frame in gSPI unlike SDIO.
3760                          * After the frame is received we have to
3761                          * distinguish whether it is data
3762                          * or non-data frame.
3763                          */
3764                         /* Allocate a packet buffer */
3765                         pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
3766                         if (!pkt) {
3767                                 /* Give up on data, request rtx of events */
3768                                 brcmf_dbg(ERROR, "(nextlen): brcmu_pkt_buf_get_skb failed: len %d rdlen %d expected rxseq %d\n",
3769                                           len, rdlen, rxseq);
3770                                 continue;
3771                         } else {
3772                                 PKTALIGN(pkt, rdlen, BRCMF_SDALIGN);
3773                                 rxbuf = (u8 *) (pkt->data);
3774                                 /* Read the entire frame */
3775                                 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
3776                                                 brcmf_sdcard_cur_sbwad(
3777                                                         bus->sdiodev),
3778                                                 SDIO_FUNC_2, F2SYNC,
3779                                                 rxbuf, rdlen,
3780                                                 pkt);
3781                                 bus->f2rxdata++;
3782
3783                                 if (sdret < 0) {
3784                                         brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
3785                                                   rdlen, sdret);
3786                                         brcmu_pkt_buf_free_skb(pkt);
3787                                         bus->drvr->rx_errors++;
3788                                         /* Force retry w/normal header read.
3789                                          * Don't attempt NAK for
3790                                          * gSPI
3791                                          */
3792                                         brcmf_sdbrcm_rxfail(bus, true, true);
3793                                         continue;
3794                                 }
3795                         }
3796
3797                         /* Now check the header */
3798                         memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3799
3800                         /* Extract hardware header fields */
3801                         len = get_unaligned_le16(bus->rxhdr);
3802                         check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3803
3804                         /* All zeros means readahead info was bad */
3805                         if (!(len | check)) {
3806                                 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
3807                                 brcmf_sdbrcm_pktfree2(bus, pkt);
3808                                 continue;
3809                         }
3810
3811                         /* Validate check bytes */
3812                         if ((u16)~(len ^ check)) {
3813                                 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
3814                                           nextlen, len, check);
3815                                 bus->rx_badhdr++;
3816                                 brcmf_sdbrcm_rxfail(bus, false, false);
3817                                 brcmf_sdbrcm_pktfree2(bus, pkt);
3818                                 continue;
3819                         }
3820
3821                         /* Validate frame length */
3822                         if (len < SDPCM_HDRLEN) {
3823                                 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
3824                                           len);
3825                                 brcmf_sdbrcm_pktfree2(bus, pkt);
3826                                 continue;
3827                         }
3828
3829                         /* Check for consistency withreadahead info */
3830                         len_consistent = (nextlen != (roundup(len, 16) >> 4));
3831                         if (len_consistent) {
3832                                 /* Mismatch, force retry w/normal
3833                                         header (may be >4K) */
3834                                 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
3835                                           nextlen, len, roundup(len, 16),
3836                                           rxseq);
3837                                 brcmf_sdbrcm_rxfail(bus, true, true);
3838                                 brcmf_sdbrcm_pktfree2(bus, pkt);
3839                                 continue;
3840                         }
3841
3842                         /* Extract software header fields */
3843                         chan = SDPCM_PACKET_CHANNEL(
3844                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3845                         seq = SDPCM_PACKET_SEQUENCE(
3846                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3847                         doff = SDPCM_DOFFSET_VALUE(
3848                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3849                         txmax = SDPCM_WINDOW_VALUE(
3850                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3851
3852                         bus->nextlen =
3853                             bus->rxhdr[SDPCM_FRAMETAG_LEN +
3854                                        SDPCM_NEXTLEN_OFFSET];
3855                         if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3856                                 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
3857                                           bus->nextlen, seq);
3858                                 bus->nextlen = 0;
3859                         }
3860
3861                         bus->drvr->rx_readahead_cnt++;
3862
3863                         /* Handle Flow Control */
3864                         fcbits = SDPCM_FCMASK_VALUE(
3865                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3866
3867                         if (bus->flowcontrol != fcbits) {
3868                                 if (~bus->flowcontrol & fcbits)
3869                                         bus->fc_xoff++;
3870
3871                                 if (bus->flowcontrol & ~fcbits)
3872                                         bus->fc_xon++;
3873
3874                                 bus->fc_rcvd++;
3875                                 bus->flowcontrol = fcbits;
3876                         }
3877
3878                         /* Check and update sequence number */
3879                         if (rxseq != seq) {
3880                                 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
3881                                           seq, rxseq);
3882                                 bus->rx_badseq++;
3883                                 rxseq = seq;
3884                         }
3885
3886                         /* Check window for sanity */
3887                         if ((u8) (txmax - bus->tx_seq) > 0x40) {
3888                                 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
3889                                           txmax, bus->tx_seq);
3890                                 txmax = bus->tx_seq + 2;
3891                         }
3892                         bus->tx_max = txmax;
3893
3894 #ifdef BCMDBG
3895                         if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
3896                                 printk(KERN_DEBUG "Rx Data:\n");
3897                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3898                                                      rxbuf, len);
3899                         } else if (BRCMF_HDRS_ON()) {
3900                                 printk(KERN_DEBUG "RxHdr:\n");
3901                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3902                                                      bus->rxhdr, SDPCM_HDRLEN);
3903                         }
3904 #endif
3905
3906                         if (chan == SDPCM_CONTROL_CHANNEL) {
3907                                 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
3908                                           seq);
3909                                 /* Force retry w/normal header read */
3910                                 bus->nextlen = 0;
3911                                 brcmf_sdbrcm_rxfail(bus, false, true);
3912                                 brcmf_sdbrcm_pktfree2(bus, pkt);
3913                                 continue;
3914                         }
3915
3916                         /* Validate data offset */
3917                         if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3918                                 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
3919                                           doff, len, SDPCM_HDRLEN);
3920                                 brcmf_sdbrcm_rxfail(bus, false, false);
3921                                 brcmf_sdbrcm_pktfree2(bus, pkt);
3922                                 continue;
3923                         }
3924
3925                         /* All done with this one -- now deliver the packet */
3926                         goto deliver;
3927                 }
3928
3929                 /* Read frame header (hardware and software) */
3930                 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
3931                                 brcmf_sdcard_cur_sbwad(bus->sdiodev),
3932                                 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
3933                                 NULL);
3934                 bus->f2rxhdrs++;
3935
3936                 if (sdret < 0) {
3937                         brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
3938                         bus->rx_hdrfail++;
3939                         brcmf_sdbrcm_rxfail(bus, true, true);
3940                         continue;
3941                 }
3942 #ifdef BCMDBG
3943                 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
3944                         printk(KERN_DEBUG "RxHdr:\n");
3945                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3946                                              bus->rxhdr, SDPCM_HDRLEN);
3947                 }
3948 #endif
3949
3950                 /* Extract hardware header fields */
3951                 len = get_unaligned_le16(bus->rxhdr);
3952                 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3953
3954                 /* All zeros means no more frames */
3955                 if (!(len | check)) {
3956                         *finished = true;
3957                         break;
3958                 }
3959
3960                 /* Validate check bytes */
3961                 if ((u16) ~(len ^ check)) {
3962                         brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
3963                                   len, check);
3964                         bus->rx_badhdr++;
3965                         brcmf_sdbrcm_rxfail(bus, false, false);
3966                         continue;
3967                 }
3968
3969                 /* Validate frame length */
3970                 if (len < SDPCM_HDRLEN) {
3971                         brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
3972                         continue;
3973                 }
3974
3975                 /* Extract software header fields */
3976                 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3977                 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3978                 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3979                 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3980
3981                 /* Validate data offset */
3982                 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3983                         brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
3984                                   doff, len, SDPCM_HDRLEN, seq);
3985                         bus->rx_badhdr++;
3986                         brcmf_sdbrcm_rxfail(bus, false, false);
3987                         continue;
3988                 }
3989
3990                 /* Save the readahead length if there is one */
3991                 bus->nextlen =
3992                     bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3993                 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3994                         brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
3995                                   bus->nextlen, seq);
3996                         bus->nextlen = 0;
3997                 }
3998
3999                 /* Handle Flow Control */
4000                 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4001
4002                 if (bus->flowcontrol != fcbits) {
4003                         if (~bus->flowcontrol & fcbits)
4004                                 bus->fc_xoff++;
4005
4006                         if (bus->flowcontrol & ~fcbits)
4007                                 bus->fc_xon++;
4008
4009                         bus->fc_rcvd++;
4010                         bus->flowcontrol = fcbits;
4011                 }
4012
4013                 /* Check and update sequence number */
4014                 if (rxseq != seq) {
4015                         brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
4016                         bus->rx_badseq++;
4017                         rxseq = seq;
4018                 }
4019
4020                 /* Check window for sanity */
4021                 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4022                         brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
4023                                   txmax, bus->tx_seq);
4024                         txmax = bus->tx_seq + 2;
4025                 }
4026                 bus->tx_max = txmax;
4027
4028                 /* Call a separate function for control frames */
4029                 if (chan == SDPCM_CONTROL_CHANNEL) {
4030                         brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
4031                         continue;
4032                 }
4033
4034                 /* precondition: chan is either SDPCM_DATA_CHANNEL,
4035                    SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
4036                    SDPCM_GLOM_CHANNEL */
4037
4038                 /* Length to read */
4039                 rdlen = (len > firstread) ? (len - firstread) : 0;
4040
4041                 /* May pad read to blocksize for efficiency */
4042                 if (bus->roundup && bus->blocksize &&
4043                         (rdlen > bus->blocksize)) {
4044                         pad = bus->blocksize - (rdlen % bus->blocksize);
4045                         if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4046                             ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4047                                 rdlen += pad;
4048                 } else if (rdlen % BRCMF_SDALIGN) {
4049                         rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
4050                 }
4051
4052                 /* Satisfy length-alignment requirements */
4053                 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4054                         rdlen = roundup(rdlen, ALIGNMENT);
4055
4056                 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4057                         /* Too long -- skip this frame */
4058                         brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
4059                                   len, rdlen);
4060                         bus->drvr->rx_errors++;
4061                         bus->rx_toolong++;
4062                         brcmf_sdbrcm_rxfail(bus, false, false);
4063                         continue;
4064                 }
4065
4066                 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + BRCMF_SDALIGN);
4067                 if (!pkt) {
4068                         /* Give up on data, request rtx of events */
4069                         brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
4070                                   rdlen, chan);
4071                         bus->drvr->rx_dropped++;
4072                         brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
4073                         continue;
4074                 }
4075
4076                 /* Leave room for what we already read, and align remainder */
4077                 skb_pull(pkt, firstread);
4078                 PKTALIGN(pkt, rdlen, BRCMF_SDALIGN);
4079
4080                 /* Read the remaining frame data */
4081                 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
4082                                 brcmf_sdcard_cur_sbwad(bus->sdiodev),
4083                                 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
4084                                 rdlen, pkt);
4085                 bus->f2rxdata++;
4086
4087                 if (sdret < 0) {
4088                         brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
4089                                   ((chan == SDPCM_EVENT_CHANNEL) ? "event"
4090                                    : ((chan == SDPCM_DATA_CHANNEL) ? "data"
4091                                       : "test")), sdret);
4092                         brcmu_pkt_buf_free_skb(pkt);
4093                         bus->drvr->rx_errors++;
4094                         brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
4095                         continue;
4096                 }
4097
4098                 /* Copy the already-read portion */
4099                 skb_push(pkt, firstread);
4100                 memcpy(pkt->data, bus->rxhdr, firstread);
4101
4102 #ifdef BCMDBG
4103                 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
4104                         printk(KERN_DEBUG "Rx Data:\n");
4105                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4106                                              pkt->data, len);
4107                 }
4108 #endif
4109
4110 deliver:
4111                 /* Save superframe descriptor and allocate packet frame */
4112                 if (chan == SDPCM_GLOM_CHANNEL) {
4113                         if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4114                                 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
4115                                           len);
4116 #ifdef BCMDBG
4117                                 if (BRCMF_GLOM_ON()) {
4118                                         printk(KERN_DEBUG "Glom Data:\n");
4119                                         print_hex_dump_bytes("",
4120                                                              DUMP_PREFIX_OFFSET,
4121                                                              pkt->data, len);
4122                                 }
4123 #endif
4124                                 __skb_trim(pkt, len);
4125                                 skb_pull(pkt, SDPCM_HDRLEN);
4126                                 bus->glomd = pkt;
4127                         } else {
4128                                 brcmf_dbg(ERROR, "%s: glom superframe w/o "
4129                                           "descriptor!\n", __func__);
4130                                 brcmf_sdbrcm_rxfail(bus, false, false);
4131                         }
4132                         continue;
4133                 }
4134
4135                 /* Fill in packet len and prio, deliver upward */
4136                 __skb_trim(pkt, len);
4137                 skb_pull(pkt, doff);
4138
4139                 if (pkt->len == 0) {
4140                         brcmu_pkt_buf_free_skb(pkt);
4141                         continue;
4142                 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
4143                         brcmf_dbg(ERROR, "rx protocol error\n");
4144                         brcmu_pkt_buf_free_skb(pkt);
4145                         bus->drvr->rx_errors++;
4146                         continue;
4147                 }
4148
4149                 /* Unlock during rx call */
4150                 brcmf_sdbrcm_sdunlock(bus);
4151                 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
4152                 brcmf_sdbrcm_sdlock(bus);
4153         }
4154         rxcount = maxframes - rxleft;
4155 #ifdef BCMDBG
4156         /* Message if we hit the limit */
4157         if (!rxleft)
4158                 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
4159                           maxframes);
4160         else
4161 #endif                          /* BCMDBG */
4162                 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
4163         /* Back off rxseq if awaiting rtx, update rx_seq */
4164         if (bus->rxskip)
4165                 rxseq--;
4166         bus->rx_seq = rxseq;
4167
4168         return rxcount;
4169 }
4170
4171 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
4172 {
4173         u32 intstatus = 0;
4174         u32 hmb_data;
4175         u8 fcbits;
4176         uint retries = 0;
4177
4178         brcmf_dbg(TRACE, "Enter\n");
4179
4180         /* Read mailbox data and ack that we did so */
4181         r_sdreg32(bus, &hmb_data,
4182                   offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
4183
4184         if (retries <= retry_limit)
4185                 w_sdreg32(bus, SMB_INT_ACK,
4186                           offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
4187         bus->f1regdata += 2;
4188
4189         /* Dongle recomposed rx frames, accept them again */
4190         if (hmb_data & HMB_DATA_NAKHANDLED) {
4191                 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
4192                           bus->rx_seq);
4193                 if (!bus->rxskip)
4194                         brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
4195
4196                 bus->rxskip = false;
4197                 intstatus |= I_HMB_FRAME_IND;
4198         }
4199
4200         /*
4201          * DEVREADY does not occur with gSPI.
4202          */
4203         if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4204                 bus->sdpcm_ver =
4205                     (hmb_data & HMB_DATA_VERSION_MASK) >>
4206                     HMB_DATA_VERSION_SHIFT;
4207                 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4208                         brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
4209                                   "expecting %d\n",
4210                                   bus->sdpcm_ver, SDPCM_PROT_VERSION);
4211                 else
4212                         brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
4213                                   bus->sdpcm_ver);
4214         }
4215
4216         /*
4217          * Flow Control has been moved into the RX headers and this out of band
4218          * method isn't used any more.
4219          * remaining backward compatible with older dongles.
4220          */
4221         if (hmb_data & HMB_DATA_FC) {
4222                 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4223                                                         HMB_DATA_FCDATA_SHIFT;
4224
4225                 if (fcbits & ~bus->flowcontrol)
4226                         bus->fc_xoff++;
4227
4228                 if (bus->flowcontrol & ~fcbits)
4229                         bus->fc_xon++;
4230
4231                 bus->fc_rcvd++;
4232                 bus->flowcontrol = fcbits;
4233         }
4234
4235         /* Shouldn't be any others */
4236         if (hmb_data & ~(HMB_DATA_DEVREADY |
4237                          HMB_DATA_NAKHANDLED |
4238                          HMB_DATA_FC |
4239                          HMB_DATA_FWREADY |
4240                          HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
4241                 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
4242                           hmb_data);
4243
4244         return intstatus;
4245 }
4246
4247 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
4248 {
4249         u32 intstatus, newstatus = 0;
4250         uint retries = 0;
4251         uint rxlimit = brcmf_rxbound;   /* Rx frames to read before resched */
4252         uint txlimit = brcmf_txbound;   /* Tx frames to send before resched */
4253         uint framecnt = 0;      /* Temporary counter of tx/rx frames */
4254         bool rxdone = true;     /* Flag for no more read data */
4255         bool resched = false;   /* Flag indicating resched wanted */
4256
4257         brcmf_dbg(TRACE, "Enter\n");
4258
4259         /* Start with leftover status bits */
4260         intstatus = bus->intstatus;
4261
4262         brcmf_sdbrcm_sdlock(bus);
4263
4264         /* If waiting for HTAVAIL, check status */
4265         if (bus->clkstate == CLK_PENDING) {
4266                 int err;
4267                 u8 clkctl, devctl = 0;
4268
4269 #ifdef BCMDBG
4270                 /* Check for inconsistent device control */
4271                 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4272                                                SBSDIO_DEVICE_CTL, &err);
4273                 if (err) {
4274                         brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
4275                         bus->drvr->busstate = BRCMF_BUS_DOWN;
4276                 }
4277 #endif                          /* BCMDBG */
4278
4279                 /* Read CSR, if clock on switch to AVAIL, else ignore */
4280                 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4281                                                SBSDIO_FUNC1_CHIPCLKCSR, &err);
4282                 if (err) {
4283                         brcmf_dbg(ERROR, "error reading CSR: %d\n",
4284                                   err);
4285                         bus->drvr->busstate = BRCMF_BUS_DOWN;
4286                 }
4287
4288                 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
4289                           devctl, clkctl);
4290
4291                 if (SBSDIO_HTAV(clkctl)) {
4292                         devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
4293                                                        SDIO_FUNC_1,
4294                                                        SBSDIO_DEVICE_CTL, &err);
4295                         if (err) {
4296                                 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
4297                                           err);
4298                                 bus->drvr->busstate = BRCMF_BUS_DOWN;
4299                         }
4300                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4301                         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4302                                 SBSDIO_DEVICE_CTL, devctl, &err);
4303                         if (err) {
4304                                 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
4305                                           err);
4306                                 bus->drvr->busstate = BRCMF_BUS_DOWN;
4307                         }
4308                         bus->clkstate = CLK_AVAIL;
4309                 } else {
4310                         goto clkwait;
4311                 }
4312         }
4313
4314         BUS_WAKE(bus);
4315
4316         /* Make sure backplane clock is on */
4317         brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
4318         if (bus->clkstate == CLK_PENDING)
4319                 goto clkwait;
4320
4321         /* Pending interrupt indicates new device status */
4322         if (bus->ipend) {
4323                 bus->ipend = false;
4324                 r_sdreg32(bus, &newstatus,
4325                           offsetof(struct sdpcmd_regs, intstatus), &retries);
4326                 bus->f1regdata++;
4327                 if (brcmf_sdcard_regfail(bus->sdiodev))
4328                         newstatus = 0;
4329                 newstatus &= bus->hostintmask;
4330                 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4331                 if (newstatus) {
4332                         w_sdreg32(bus, newstatus,
4333                                   offsetof(struct sdpcmd_regs, intstatus),
4334                                   &retries);
4335                         bus->f1regdata++;
4336                 }
4337         }
4338
4339         /* Merge new bits with previous */
4340         intstatus |= newstatus;
4341         bus->intstatus = 0;
4342
4343         /* Handle flow-control change: read new state in case our ack
4344          * crossed another change interrupt.  If change still set, assume
4345          * FC ON for safety, let next loop through do the debounce.
4346          */
4347         if (intstatus & I_HMB_FC_CHANGE) {
4348                 intstatus &= ~I_HMB_FC_CHANGE;
4349                 w_sdreg32(bus, I_HMB_FC_CHANGE,
4350                           offsetof(struct sdpcmd_regs, intstatus), &retries);
4351
4352                 r_sdreg32(bus, &newstatus,
4353                           offsetof(struct sdpcmd_regs, intstatus), &retries);
4354                 bus->f1regdata += 2;
4355                 bus->fcstate =
4356                     !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4357                 intstatus |= (newstatus & bus->hostintmask);
4358         }
4359
4360         /* Handle host mailbox indication */
4361         if (intstatus & I_HMB_HOST_INT) {
4362                 intstatus &= ~I_HMB_HOST_INT;
4363                 intstatus |= brcmf_sdbrcm_hostmail(bus);
4364         }
4365
4366         /* Generally don't ask for these, can get CRC errors... */
4367         if (intstatus & I_WR_OOSYNC) {
4368                 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
4369                 intstatus &= ~I_WR_OOSYNC;
4370         }
4371
4372         if (intstatus & I_RD_OOSYNC) {
4373                 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
4374                 intstatus &= ~I_RD_OOSYNC;
4375         }
4376
4377         if (intstatus & I_SBINT) {
4378                 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
4379                 intstatus &= ~I_SBINT;
4380         }
4381
4382         /* Would be active due to wake-wlan in gSPI */
4383         if (intstatus & I_CHIPACTIVE) {
4384                 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
4385                 intstatus &= ~I_CHIPACTIVE;
4386         }
4387
4388         /* Ignore frame indications if rxskip is set */
4389         if (bus->rxskip)
4390                 intstatus &= ~I_HMB_FRAME_IND;
4391
4392         /* On frame indication, read available frames */
4393         if (PKT_AVAILABLE()) {
4394                 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
4395                 if (rxdone || bus->rxskip)
4396                         intstatus &= ~I_HMB_FRAME_IND;
4397                 rxlimit -= min(framecnt, rxlimit);
4398         }
4399
4400         /* Keep still-pending events for next scheduling */
4401         bus->intstatus = intstatus;
4402
4403 clkwait:
4404         if (DATAOK(bus) && bus->ctrl_frame_stat &&
4405                 (bus->clkstate == CLK_AVAIL)) {
4406                 int ret, i;
4407
4408                 ret = brcmf_sdbrcm_send_buf(bus,
4409                         brcmf_sdcard_cur_sbwad(bus->sdiodev),
4410                         SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
4411                         (u32) bus->ctrl_frame_len, NULL);
4412
4413                 if (ret < 0) {
4414                         /* On failure, abort the command and
4415                                 terminate the frame */
4416                         brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
4417                                   ret);
4418                         bus->tx_sderrs++;
4419
4420                         brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
4421
4422                         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4423                                          SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4424                                          NULL);
4425                         bus->f1regdata++;
4426
4427                         for (i = 0; i < 3; i++) {
4428                                 u8 hi, lo;
4429                                 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
4430                                                      SDIO_FUNC_1,
4431                                                      SBSDIO_FUNC1_WFRAMEBCHI,
4432                                                      NULL);
4433                                 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
4434                                                      SDIO_FUNC_1,
4435                                                      SBSDIO_FUNC1_WFRAMEBCLO,
4436                                                      NULL);
4437                                 bus->f1regdata += 2;
4438                                 if ((hi == 0) && (lo == 0))
4439                                         break;
4440                         }
4441
4442                 }
4443                 if (ret == 0)
4444                         bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4445
4446                 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
4447                 bus->ctrl_frame_stat = false;
4448                 brcmf_sdbrcm_wait_event_wakeup(bus);
4449         }
4450         /* Send queued frames (limit 1 if rx may still be pending) */
4451         else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4452                  brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4453                  && DATAOK(bus)) {
4454                 framecnt = rxdone ? txlimit : min(txlimit, brcmf_txminmax);
4455                 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
4456                 txlimit -= framecnt;
4457         }
4458
4459         /* Resched if events or tx frames are pending,
4460                  else await next interrupt */
4461         /* On failed register access, all bets are off:
4462                  no resched or interrupts */
4463         if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
4464             brcmf_sdcard_regfail(bus->sdiodev)) {
4465                 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
4466                           brcmf_sdcard_regfail(bus->sdiodev));
4467                 bus->drvr->busstate = BRCMF_BUS_DOWN;
4468                 bus->intstatus = 0;
4469         } else if (bus->clkstate == CLK_PENDING) {
4470                 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
4471                 resched = true;
4472         } else if (bus->intstatus || bus->ipend ||
4473                 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
4474                  && DATAOK(bus)) || PKT_AVAILABLE()) {
4475                 resched = true;
4476         }
4477
4478         bus->dpc_sched = resched;
4479
4480         /* If we're done for now, turn off clock request. */
4481         if ((bus->clkstate != CLK_PENDING)
4482             && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
4483                 bus->activity = false;
4484                 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4485         }
4486
4487         brcmf_sdbrcm_sdunlock(bus);
4488
4489         return resched;
4490 }
4491
4492 void brcmf_sdbrcm_isr(void *arg)
4493 {
4494         struct brcmf_bus *bus = (struct brcmf_bus *) arg;
4495
4496         brcmf_dbg(TRACE, "Enter\n");
4497
4498         if (!bus) {
4499                 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
4500                 return;
4501         }
4502
4503         if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
4504                 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
4505                 return;
4506         }
4507         /* Count the interrupt call */
4508         bus->intrcount++;
4509         bus->ipend = true;
4510
4511         /* Shouldn't get this interrupt if we're sleeping? */
4512         if (bus->sleeping) {
4513                 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
4514                 return;
4515         }
4516
4517         /* Disable additional interrupts (is this needed now)? */
4518         if (!bus->intr)
4519                 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
4520
4521         bus->dpc_sched = true;
4522         brcmf_sdbrcm_sched_dpc(bus);
4523 }
4524
4525 extern bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
4526 {
4527         struct brcmf_bus *bus;
4528
4529         brcmf_dbg(TIMER, "Enter\n");
4530
4531         bus = drvr->bus;
4532
4533         if (bus->drvr->dongle_reset)
4534                 return false;
4535
4536         /* Ignore the timer if simulating bus down */
4537         if (bus->sleeping)
4538                 return false;
4539
4540         brcmf_sdbrcm_sdlock(bus);
4541
4542         /* Poll period: check device if appropriate. */
4543         if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4544                 u32 intstatus = 0;
4545
4546                 /* Reset poll tick */
4547                 bus->polltick = 0;
4548
4549                 /* Check device if no interrupts */
4550                 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4551
4552                         if (!bus->dpc_sched) {
4553                                 u8 devpend;
4554                                 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
4555                                                 SDIO_FUNC_0, SDIO_CCCR_INTx,
4556                                                 NULL);
4557                                 intstatus =
4558                                     devpend & (INTR_STATUS_FUNC1 |
4559                                                INTR_STATUS_FUNC2);
4560                         }
4561
4562                         /* If there is something, make like the ISR and
4563                                  schedule the DPC */
4564                         if (intstatus) {
4565                                 bus->pollcnt++;
4566                                 bus->ipend = true;
4567
4568                                 bus->dpc_sched = true;
4569                                 brcmf_sdbrcm_sched_dpc(bus);
4570
4571                         }
4572                 }
4573
4574                 /* Update interrupt tracking */
4575                 bus->lastintrs = bus->intrcount;
4576         }
4577 #ifdef BCMDBG
4578         /* Poll for console output periodically */
4579         if (drvr->busstate == BRCMF_BUS_DATA && brcmf_console_ms != 0) {
4580                 bus->console.count += brcmf_watchdog_ms;
4581                 if (bus->console.count >= brcmf_console_ms) {
4582                         bus->console.count -= brcmf_console_ms;
4583                         /* Make sure backplane clock is on */
4584                         brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4585                         if (brcmf_sdbrcm_readconsole(bus) < 0)
4586                                 brcmf_console_ms = 0;   /* On error,
4587                                                          stop trying */
4588                 }
4589         }
4590 #endif                          /* BCMDBG */
4591
4592         /* On idle timeout clear activity flag and/or turn off clock */
4593         if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4594                 if (++bus->idlecount >= bus->idletime) {
4595                         bus->idlecount = 0;
4596                         if (bus->activity) {
4597                                 bus->activity = false;
4598                                 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
4599                         } else {
4600                                 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4601                         }
4602                 }
4603         }
4604
4605         brcmf_sdbrcm_sdunlock(bus);
4606
4607         return bus->ipend;
4608 }
4609
4610 #ifdef BCMDBG
4611 static int brcmf_sdbrcm_bus_console_in(struct brcmf_pub *drvr,
4612                                        unsigned char *msg, uint msglen)
4613 {
4614         struct brcmf_bus *bus = drvr->bus;
4615         u32 addr, val;
4616         int rv;
4617         struct sk_buff *pkt;
4618
4619         /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4620         if (bus->console_addr == 0)
4621                 return -ENOTSUPP;
4622
4623         /* Exclusive bus access */
4624         brcmf_sdbrcm_sdlock(bus);
4625
4626         /* Don't allow input if dongle is in reset */
4627         if (bus->drvr->dongle_reset) {
4628                 brcmf_sdbrcm_sdunlock(bus);
4629                 return -EPERM;
4630         }
4631
4632         /* Request clock to allow SDIO accesses */
4633         BUS_WAKE(bus);
4634         /* No pend allowed since txpkt is called later, ht clk has to be on */
4635         brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4636
4637         /* Zero cbuf_index */
4638         addr = bus->console_addr + offsetof(struct rte_console, cbuf_idx);
4639         val = cpu_to_le32(0);
4640         rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4641         if (rv < 0)
4642                 goto done;
4643
4644         /* Write message into cbuf */
4645         addr = bus->console_addr + offsetof(struct rte_console, cbuf);
4646         rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)msg, msglen);
4647         if (rv < 0)
4648                 goto done;
4649
4650         /* Write length into vcons_in */
4651         addr = bus->console_addr + offsetof(struct rte_console, vcons_in);
4652         val = cpu_to_le32(msglen);
4653         rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4654         if (rv < 0)
4655                 goto done;
4656
4657         /* Bump dongle by sending an empty event pkt.
4658          * sdpcm_sendup (RX) checks for virtual console input.
4659          */
4660         pkt = brcmu_pkt_buf_get_skb(4 + SDPCM_RESERVE);
4661         if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
4662                 brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
4663
4664 done:
4665         if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
4666                 bus->activity = false;
4667                 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
4668         }
4669
4670         brcmf_sdbrcm_sdunlock(bus);
4671
4672         return rv;
4673 }
4674 #endif                          /* BCMDBG */
4675
4676 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
4677 {
4678         if (chipid == BCM4329_CHIP_ID)
4679                 return true;
4680         return false;
4681 }
4682
4683 void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4684                          u32 regsva, struct brcmf_sdio_dev *sdiodev)
4685 {
4686         int ret;
4687         struct brcmf_bus *bus;
4688
4689         /* Init global variables at run-time, not as part of the declaration.
4690          * This is required to support init/de-init of the driver.
4691          * Initialization
4692          * of globals as part of the declaration results in non-deterministic
4693          * behavior since the value of the globals may be different on the
4694          * first time that the driver is initialized vs subsequent
4695          * initializations.
4696          */
4697         brcmf_txbound = BRCMF_TXBOUND;
4698         brcmf_rxbound = BRCMF_RXBOUND;
4699         brcmf_alignctl = true;
4700         brcmf_readahead = true;
4701         retrydata = false;
4702         brcmf_dongle_memsize = 0;
4703         brcmf_txminmax = BRCMF_TXMINMAX;
4704
4705         forcealign = true;
4706
4707         brcmf_c_init();
4708
4709         brcmf_dbg(TRACE, "Enter\n");
4710
4711         /* We make an assumption about address window mappings:
4712          * regsva == SI_ENUM_BASE*/
4713
4714         /* Allocate private bus interface state */
4715         bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
4716         if (!bus) {
4717                 brcmf_dbg(ERROR, "kmalloc of struct dhd_bus failed\n");
4718                 goto fail;
4719         }
4720         bus->sdiodev = sdiodev;
4721         sdiodev->bus = bus;
4722         bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
4723         bus->usebufpool = false;        /* Use bufpool if allocated,
4724                                          else use locally malloced rxbuf */
4725
4726         /* attempt to attach to the dongle */
4727         if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4728                 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
4729                 goto fail;
4730         }
4731
4732         spin_lock_init(&bus->txqlock);
4733         init_waitqueue_head(&bus->ctrl_wait);
4734         init_waitqueue_head(&bus->ioctl_resp_wait);
4735
4736         /* Set up the watchdog timer */
4737         init_timer(&bus->timer);
4738         bus->timer.data = (unsigned long)bus;
4739         bus->timer.function = brcmf_sdbrcm_watchdog;
4740
4741         /* Initialize thread based operation and lock */
4742         if ((brcmf_watchdog_prio >= 0) && (brcmf_dpc_prio >= 0)) {
4743                 bus->threads_only = true;
4744                 sema_init(&bus->sdsem, 1);
4745         } else {
4746                 bus->threads_only = false;
4747                 spin_lock_init(&bus->sdlock);
4748         }
4749
4750         if (brcmf_dpc_prio >= 0) {
4751                 /* Initialize watchdog thread */
4752                 init_completion(&bus->watchdog_wait);
4753                 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4754                                                 bus, "brcmf_watchdog");
4755                 if (IS_ERR(bus->watchdog_tsk)) {
4756                         printk(KERN_WARNING
4757                                "brcmf_watchdog thread failed to start\n");
4758                         bus->watchdog_tsk = NULL;
4759                 }
4760         } else
4761                 bus->watchdog_tsk = NULL;
4762
4763         /* Set up the bottom half handler */
4764         if (brcmf_dpc_prio >= 0) {
4765                 /* Initialize DPC thread */
4766                 init_completion(&bus->dpc_wait);
4767                 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
4768                                            bus, "brcmf_dpc");
4769                 if (IS_ERR(bus->dpc_tsk)) {
4770                         printk(KERN_WARNING
4771                                "brcmf_dpc thread failed to start\n");
4772                         bus->dpc_tsk = NULL;
4773                 }
4774         } else {
4775                 tasklet_init(&bus->tasklet, brcmf_sdbrcm_dpc_tasklet,
4776                              (unsigned long)bus);
4777                 bus->dpc_tsk = NULL;
4778         }
4779
4780         /* Attach to the brcmf/OS/network interface */
4781         bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
4782         if (!bus->drvr) {
4783                 brcmf_dbg(ERROR, "brcmf_attach failed\n");
4784                 goto fail;
4785         }
4786
4787         /* Allocate buffers */
4788         if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4789                 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4790                 goto fail;
4791         }
4792
4793         if (!(brcmf_sdbrcm_probe_init(bus))) {
4794                 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4795                 goto fail;
4796         }
4797
4798         /* Register interrupt callback, but mask it (not operational yet). */
4799         brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4800         ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4801         if (ret != 0) {
4802                 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4803                 goto fail;
4804         }
4805         brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4806
4807         brcmf_dbg(INFO, "completed!!\n");
4808
4809         /* if firmware path present try to download and bring up bus */
4810         ret = brcmf_bus_start(bus->drvr);
4811         if (ret != 0) {
4812                 if (ret == -ENOLINK) {
4813                         brcmf_dbg(ERROR, "dongle is not responding\n");
4814                         goto fail;
4815                 }
4816         }
4817         /* Ok, have the per-port tell the stack we're open for business */
4818         if (brcmf_net_attach(bus->drvr, 0) != 0) {
4819                 brcmf_dbg(ERROR, "Net attach failed!!\n");
4820                 goto fail;
4821         }
4822
4823         return bus;
4824
4825 fail:
4826         brcmf_sdbrcm_release(bus);
4827         return NULL;
4828 }
4829
4830 static bool
4831 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4832 {
4833         u8 clkctl = 0;
4834         int err = 0;
4835         int reg_addr;
4836         u32 reg_val;
4837
4838         bus->alp_only = true;
4839
4840         /* Return the window to backplane enumeration space for core access */
4841         if (brcmf_sdbrcm_set_siaddr_window(bus, SI_ENUM_BASE))
4842                 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4843
4844 #ifdef BCMDBG
4845         printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4846                brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4847
4848 #endif                          /* BCMDBG */
4849
4850         /*
4851          * Force PLL off until brcmf_sdbrcm_chip_attach()
4852          * programs PLL control regs
4853          */
4854
4855         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4856                                SBSDIO_FUNC1_CHIPCLKCSR,
4857                                BRCMF_INIT_CLKCTL1, &err);
4858         if (!err)
4859                 clkctl =
4860                     brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4861                                           SBSDIO_FUNC1_CHIPCLKCSR, &err);
4862
4863         if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4864                 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4865                           err, BRCMF_INIT_CLKCTL1, clkctl);
4866                 goto fail;
4867         }
4868
4869         if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4870                 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4871                 goto fail;
4872         }
4873
4874         if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4875                 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4876                 goto fail;
4877         }
4878
4879         brcmf_sdbrcm_sdiod_drive_strength_init(bus, brcmf_sdiod_drive_strength);
4880
4881         /* Get info on the ARM and SOCRAM cores... */
4882         brcmf_sdcard_reg_read(bus->sdiodev,
4883                   CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4884         bus->orig_ramsize = bus->ci->ramsize;
4885         if (!(bus->orig_ramsize)) {
4886                 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4887                 goto fail;
4888         }
4889         bus->ramsize = bus->orig_ramsize;
4890         if (brcmf_dongle_memsize)
4891                 brcmf_sdbrcm_setmemsize(bus, brcmf_dongle_memsize);
4892
4893         brcmf_dbg(ERROR, "DHD: dongle ram size is set to %d(orig %d)\n",
4894                   bus->ramsize, bus->orig_ramsize);
4895
4896         /* Set core control so an SDIO reset does a backplane reset */
4897         reg_addr = bus->ci->buscorebase +
4898                    offsetof(struct sdpcmd_regs, corecontrol);
4899         reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4900         brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4901                                reg_val | CC_BPRESEN);
4902
4903         brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4904
4905         /* Locate an appropriately-aligned portion of hdrbuf */
4906         bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4907                                     BRCMF_SDALIGN);
4908
4909         /* Set the poll and/or interrupt flags */
4910         bus->intr = (bool) brcmf_intr;
4911         bus->poll = (bool) brcmf_poll;
4912         if (bus->poll)
4913                 bus->pollrate = 1;
4914
4915         return true;
4916
4917 fail:
4918         return false;
4919 }
4920
4921 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
4922 {
4923         brcmf_dbg(TRACE, "Enter\n");
4924
4925         if (bus->drvr->maxctl) {
4926                 bus->rxblen =
4927                     roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
4928                             ALIGNMENT) + BRCMF_SDALIGN;
4929                 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4930                 if (!(bus->rxbuf)) {
4931                         brcmf_dbg(ERROR, "kmalloc of %d-byte rxbuf failed\n",
4932                                   bus->rxblen);
4933                         goto fail;
4934                 }
4935         }
4936
4937         /* Allocate buffer to receive glomed packet */
4938         bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
4939         if (!(bus->databuf)) {
4940                 brcmf_dbg(ERROR, "kmalloc of %d-byte databuf failed\n",
4941                           MAX_DATA_BUF);
4942                 /* release rxbuf which was already located as above */
4943                 if (!bus->rxblen)
4944                         kfree(bus->rxbuf);
4945                 goto fail;
4946         }
4947
4948         /* Align the buffer */
4949         if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
4950                 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
4951                                ((unsigned long)bus->databuf % BRCMF_SDALIGN));
4952         else
4953                 bus->dataptr = bus->databuf;
4954
4955         return true;
4956
4957 fail:
4958         return false;
4959 }
4960
4961 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4962 {
4963         brcmf_dbg(TRACE, "Enter\n");
4964
4965         /* Disable F2 to clear any intermediate frame state on the dongle */
4966         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4967                                SDIO_FUNC_ENABLE_1, NULL);
4968
4969         bus->drvr->busstate = BRCMF_BUS_DOWN;
4970         bus->sleeping = false;
4971         bus->rxflow = false;
4972
4973         /* Done with backplane-dependent accesses, can drop clock... */
4974         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4975                                SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4976
4977         /* ...and initialize clock/power states */
4978         bus->clkstate = CLK_SDONLY;
4979         bus->idletime = (s32) brcmf_idletime;
4980         bus->idleclock = BRCMF_IDLE_ACTIVE;
4981
4982         /* Query the F2 block size, set roundup accordingly */
4983         bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4984         bus->roundup = min(max_roundup, bus->blocksize);
4985
4986         /* Query if bus module supports packet chaining,
4987                  default to use if supported */
4988         if (brcmf_sdcard_iovar_op(bus->sdiodev, "sd_rxchain", NULL, 0,
4989                             &bus->sd_rxchain, sizeof(s32),
4990                             false) != 0)
4991                 bus->sd_rxchain = false;
4992         else
4993                 brcmf_dbg(INFO, "bus module (through sdiocard API) %s chaining\n",
4994                           bus->sd_rxchain ? "supports" : "does not support");
4995
4996         bus->use_rxchain = (bool) bus->sd_rxchain;
4997
4998         return true;
4999 }
5000
5001 static bool
5002 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
5003 {
5004         bool ret;
5005
5006         /* Download the firmware */
5007         brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5008
5009         ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
5010
5011         brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
5012
5013         return ret;
5014 }
5015
5016 /* Detach and free everything */
5017 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
5018 {
5019         brcmf_dbg(TRACE, "Enter\n");
5020
5021         if (bus) {
5022                 /* De-register interrupt handler */
5023                 brcmf_sdcard_intr_dereg(bus->sdiodev);
5024
5025                 if (bus->drvr) {
5026                         brcmf_detach(bus->drvr);
5027                         brcmf_sdbrcm_release_dongle(bus);
5028                         bus->drvr = NULL;
5029                 }
5030
5031                 brcmf_sdbrcm_release_malloc(bus);
5032
5033                 kfree(bus);
5034         }
5035
5036         brcmf_dbg(TRACE, "Disconnected\n");
5037 }
5038
5039 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
5040 {
5041         brcmf_dbg(TRACE, "Enter\n");
5042
5043         if (bus->drvr && bus->drvr->dongle_reset)
5044                 return;
5045
5046         kfree(bus->rxbuf);
5047         bus->rxctl = bus->rxbuf = NULL;
5048         bus->rxlen = 0;
5049
5050         kfree(bus->databuf);
5051         bus->databuf = NULL;
5052 }
5053
5054 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
5055 {
5056         brcmf_dbg(TRACE, "Enter\n");
5057
5058         if (bus->drvr && bus->drvr->dongle_reset)
5059                 return;
5060
5061         if (bus->ci) {
5062                 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5063                 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
5064                 brcmf_sdbrcm_chip_detach(bus);
5065                 if (bus->vars && bus->varsz)
5066                         kfree(bus->vars);
5067                 bus->vars = NULL;
5068         }
5069
5070         brcmf_dbg(TRACE, "Disconnected\n");
5071 }
5072
5073 void brcmf_sdbrcm_disconnect(void *ptr)
5074 {
5075         struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
5076
5077         brcmf_dbg(TRACE, "Enter\n");
5078
5079         if (bus)
5080                 brcmf_sdbrcm_release(bus);
5081
5082         brcmf_dbg(TRACE, "Disconnected\n");
5083 }
5084
5085 int brcmf_bus_register(void)
5086 {
5087         brcmf_dbg(TRACE, "Enter\n");
5088
5089         /* Sanity check on the module parameters */
5090         do {
5091                 /* Both watchdog and DPC as tasklets are ok */
5092                 if ((brcmf_watchdog_prio < 0) && (brcmf_dpc_prio < 0))
5093                         break;
5094
5095                 /* If both watchdog and DPC are threads, TX must be deferred */
5096                 if ((brcmf_watchdog_prio >= 0) && (brcmf_dpc_prio >= 0)
5097                     && brcmf_deferred_tx)
5098                         break;
5099
5100                 brcmf_dbg(ERROR, "Invalid module parameters.\n");
5101                 return -EINVAL;
5102         } while (0);
5103
5104         return brcmf_sdio_register();
5105 }
5106
5107 void brcmf_bus_unregister(void)
5108 {
5109         brcmf_dbg(TRACE, "Enter\n");
5110
5111         brcmf_sdio_unregister();
5112 }
5113
5114 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
5115 {
5116         int offset = 0;
5117         uint len;
5118         u8 *memblock = NULL, *memptr;
5119         int ret;
5120
5121         brcmf_dbg(INFO, "Enter\n");
5122
5123         bus->fw_name = BCM4329_FW_NAME;
5124         ret = request_firmware(&bus->firmware, bus->fw_name,
5125                                &bus->sdiodev->func[2]->dev);
5126         if (ret) {
5127                 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
5128                 return ret;
5129         }
5130         bus->fw_ptr = 0;
5131
5132         memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
5133         if (memblock == NULL) {
5134                 brcmf_dbg(ERROR, "Failed to allocate memory %d bytes\n",
5135                           MEMBLOCK);
5136                 ret = -ENOMEM;
5137                 goto err;
5138         }
5139         if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
5140                 memptr += (BRCMF_SDALIGN -
5141                            ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
5142
5143         /* Download image */
5144         while ((len =
5145                 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
5146                 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
5147                 if (ret) {
5148                         brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
5149                                   ret, MEMBLOCK, offset);
5150                         goto err;
5151                 }
5152
5153                 offset += MEMBLOCK;
5154         }
5155
5156 err:
5157         kfree(memblock);
5158
5159         release_firmware(bus->firmware);
5160         bus->fw_ptr = 0;
5161
5162         return ret;
5163 }
5164
5165 /*
5166  * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5167  * and ending in a NUL.
5168  * Removes carriage returns, empty lines, comment lines, and converts
5169  * newlines to NULs.
5170  * Shortens buffer as needed and pads with NULs.  End of buffer is marked
5171  * by two NULs.
5172 */
5173
5174 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
5175 {
5176         char *dp;
5177         bool findNewline;
5178         int column;
5179         uint buf_len, n;
5180
5181         dp = varbuf;
5182
5183         findNewline = false;
5184         column = 0;
5185
5186         for (n = 0; n < len; n++) {
5187                 if (varbuf[n] == 0)
5188                         break;
5189                 if (varbuf[n] == '\r')
5190                         continue;
5191                 if (findNewline && varbuf[n] != '\n')
5192                         continue;
5193                 findNewline = false;
5194                 if (varbuf[n] == '#') {
5195                         findNewline = true;
5196                         continue;
5197                 }
5198                 if (varbuf[n] == '\n') {
5199                         if (column == 0)
5200                                 continue;
5201                         *dp++ = 0;
5202                         column = 0;
5203                         continue;
5204                 }
5205                 *dp++ = varbuf[n];
5206                 column++;
5207         }
5208         buf_len = dp - varbuf;
5209
5210         while (dp < varbuf + n)
5211                 *dp++ = 0;
5212
5213         return buf_len;
5214 }
5215
5216 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
5217 {
5218         uint len;
5219         char *memblock = NULL;
5220         char *bufp;
5221         int ret;
5222
5223         bus->nv_name = BCM4329_NV_NAME;
5224         ret = request_firmware(&bus->firmware, bus->nv_name,
5225                                &bus->sdiodev->func[2]->dev);
5226         if (ret) {
5227                 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
5228                 return ret;
5229         }
5230         bus->fw_ptr = 0;
5231
5232         memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5233         if (memblock == NULL) {
5234                 brcmf_dbg(ERROR, "Failed to allocate memory %d bytes\n",
5235                           MEMBLOCK);
5236                 ret = -ENOMEM;
5237                 goto err;
5238         }
5239
5240         len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
5241
5242         if (len > 0 && len < MEMBLOCK) {
5243                 bufp = (char *)memblock;
5244                 bufp[len] = 0;
5245                 len = brcmf_process_nvram_vars(bufp, len);
5246                 bufp += len;
5247                 *bufp++ = 0;
5248                 if (len)
5249                         ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
5250                 if (ret)
5251                         brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
5252         } else {
5253                 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
5254                 ret = -EIO;
5255         }
5256
5257 err:
5258         kfree(memblock);
5259
5260         release_firmware(bus->firmware);
5261         bus->fw_ptr = 0;
5262
5263         return ret;
5264 }
5265
5266 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
5267 {
5268         int bcmerror = -1;
5269
5270         /* Keep arm in reset */
5271         if (brcmf_sdbrcm_download_state(bus, true)) {
5272                 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
5273                 goto err;
5274         }
5275
5276         /* External image takes precedence if specified */
5277         if (brcmf_sdbrcm_download_code_file(bus)) {
5278                 brcmf_dbg(ERROR, "dongle image file download failed\n");
5279                 goto err;
5280         }
5281
5282         /* External nvram takes precedence if specified */
5283         if (brcmf_sdbrcm_download_nvram(bus))
5284                 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
5285
5286         /* Take arm out of reset */
5287         if (brcmf_sdbrcm_download_state(bus, false)) {
5288                 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
5289                 goto err;
5290         }
5291
5292         bcmerror = 0;
5293
5294 err:
5295         return bcmerror;
5296 }
5297
5298
5299 static int
5300 brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
5301                     u8 *buf, uint nbytes, struct sk_buff *pkt)
5302 {
5303         return brcmf_sdcard_send_buf
5304                 (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
5305 }
5306
5307 int brcmf_bus_devreset(struct brcmf_pub *drvr, u8 flag)
5308 {
5309         int bcmerror = 0;
5310         struct brcmf_bus *bus;
5311
5312         bus = drvr->bus;
5313
5314         if (flag == true) {
5315                 brcmf_sdbrcm_wd_timer(bus, 0);
5316                 if (!bus->drvr->dongle_reset) {
5317                         /* Expect app to have torn down any
5318                          connection before calling */
5319                         /* Stop the bus, disable F2 */
5320                         brcmf_sdbrcm_bus_stop(bus, false);
5321
5322                         /* Clean tx/rx buffer pointers,
5323                          detach from the dongle */
5324                         brcmf_sdbrcm_release_dongle(bus);
5325
5326                         bus->drvr->dongle_reset = true;
5327                         bus->drvr->up = false;
5328
5329                         brcmf_dbg(TRACE, "WLAN OFF DONE\n");
5330                         /* App can now remove power from device */
5331                 } else
5332                         bcmerror = -EIO;
5333         } else {
5334                 /* App must have restored power to device before calling */
5335
5336                 brcmf_dbg(TRACE, " == WLAN ON ==\n");
5337
5338                 if (bus->drvr->dongle_reset) {
5339                         /* Turn on WLAN */
5340
5341                         /* Attempt to re-attach & download */
5342                         if (brcmf_sdbrcm_probe_attach(bus, SI_ENUM_BASE)) {
5343                                 /* Attempt to download binary to the dongle */
5344                                 if (brcmf_sdbrcm_probe_init(bus)) {
5345                                         /* Re-init bus, enable F2 transfer */
5346                                         brcmf_sdbrcm_bus_init(bus->drvr, false);
5347
5348                                         bus->drvr->dongle_reset = false;
5349                                         bus->drvr->up = true;
5350
5351                                         brcmf_dbg(TRACE, "WLAN ON DONE\n");
5352                                 } else
5353                                         bcmerror = -EIO;
5354                         } else
5355                                 bcmerror = -EIO;
5356                 } else {
5357                         bcmerror = -EISCONN;
5358                         brcmf_dbg(ERROR, "Set DEVRESET=false invoked when device is on\n");
5359                         bcmerror = -EIO;
5360                 }
5361                 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
5362         }
5363         return bcmerror;
5364 }
5365
5366 static int
5367 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
5368                               struct chip_info *ci, u32 regs)
5369 {
5370         u32 regdata;
5371
5372         /*
5373          * Get CC core rev
5374          * Chipid is assume to be at offset 0 from regs arg
5375          * For different chiptypes or old sdio hosts w/o chipcommon,
5376          * other ways of recognition should be added here.
5377          */
5378         ci->cccorebase = regs;
5379         regdata = brcmf_sdcard_reg_read(sdiodev,
5380                                 CORE_CC_REG(ci->cccorebase, chipid), 4);
5381         ci->chip = regdata & CID_ID_MASK;
5382         ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
5383
5384         brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
5385
5386         /* Address of cores for new chips should be added here */
5387         switch (ci->chip) {
5388         case BCM4329_CHIP_ID:
5389                 ci->buscorebase = BCM4329_CORE_BUS_BASE;
5390                 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
5391                 ci->armcorebase = BCM4329_CORE_ARM_BASE;
5392                 ci->ramsize = BCM4329_RAMSIZE;
5393                 break;
5394         default:
5395                 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
5396                 return -ENODEV;
5397         }
5398
5399         regdata = brcmf_sdcard_reg_read(sdiodev,
5400                 CORE_SB(ci->cccorebase, sbidhigh), 4);
5401         ci->ccrev = SBCOREREV(regdata);
5402
5403         regdata = brcmf_sdcard_reg_read(sdiodev,
5404                 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
5405         ci->pmurev = regdata & PCAP_REV_MASK;
5406
5407         regdata = brcmf_sdcard_reg_read(sdiodev,
5408                                         CORE_SB(ci->buscorebase, sbidhigh), 4);
5409         ci->buscorerev = SBCOREREV(regdata);
5410         ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
5411
5412         brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
5413                   ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
5414
5415         /* get chipcommon capabilites */
5416         ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
5417                 CORE_CC_REG(ci->cccorebase, capabilities), 4);
5418
5419         return 0;
5420 }
5421
5422 static void
5423 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
5424 {
5425         u32 regdata;
5426
5427         regdata = brcmf_sdcard_reg_read(sdiodev,
5428                 CORE_SB(corebase, sbtmstatelow), 4);
5429         if (regdata & SBTML_RESET)
5430                 return;
5431
5432         regdata = brcmf_sdcard_reg_read(sdiodev,
5433                 CORE_SB(corebase, sbtmstatelow), 4);
5434         if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
5435                 /*
5436                  * set target reject and spin until busy is clear
5437                  * (preserve core-specific bits)
5438                  */
5439                 regdata = brcmf_sdcard_reg_read(sdiodev,
5440                         CORE_SB(corebase, sbtmstatelow), 4);
5441                 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
5442                                        4, regdata | SBTML_REJ);
5443
5444                 regdata = brcmf_sdcard_reg_read(sdiodev,
5445                         CORE_SB(corebase, sbtmstatelow), 4);
5446                 udelay(1);
5447                 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
5448                         CORE_SB(corebase, sbtmstatehigh), 4) &
5449                         SBTMH_BUSY), 100000);
5450
5451                 regdata = brcmf_sdcard_reg_read(sdiodev,
5452                         CORE_SB(corebase, sbtmstatehigh), 4);
5453                 if (regdata & SBTMH_BUSY)
5454                         brcmf_dbg(ERROR, "ARM core still busy\n");
5455
5456                 regdata = brcmf_sdcard_reg_read(sdiodev,
5457                         CORE_SB(corebase, sbidlow), 4);
5458                 if (regdata & SBIDL_INIT) {
5459                         regdata = brcmf_sdcard_reg_read(sdiodev,
5460                                 CORE_SB(corebase, sbimstate), 4) |
5461                                 SBIM_RJ;
5462                         brcmf_sdcard_reg_write(sdiodev,
5463                                 CORE_SB(corebase, sbimstate), 4,
5464                                 regdata);
5465                         regdata = brcmf_sdcard_reg_read(sdiodev,
5466                                 CORE_SB(corebase, sbimstate), 4);
5467                         udelay(1);
5468                         SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
5469                                 CORE_SB(corebase, sbimstate), 4) &
5470                                 SBIM_BY), 100000);
5471                 }
5472
5473                 /* set reset and reject while enabling the clocks */
5474                 brcmf_sdcard_reg_write(sdiodev,
5475                         CORE_SB(corebase, sbtmstatelow), 4,
5476                         (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
5477                         SBTML_REJ | SBTML_RESET));
5478                 regdata = brcmf_sdcard_reg_read(sdiodev,
5479                         CORE_SB(corebase, sbtmstatelow), 4);
5480                 udelay(10);
5481
5482                 /* clear the initiator reject bit */
5483                 regdata = brcmf_sdcard_reg_read(sdiodev,
5484                         CORE_SB(corebase, sbidlow), 4);
5485                 if (regdata & SBIDL_INIT) {
5486                         regdata = brcmf_sdcard_reg_read(sdiodev,
5487                                 CORE_SB(corebase, sbimstate), 4) &
5488                                 ~SBIM_RJ;
5489                         brcmf_sdcard_reg_write(sdiodev,
5490                                 CORE_SB(corebase, sbimstate), 4,
5491                                 regdata);
5492                 }
5493         }
5494
5495         /* leave reset and reject asserted */
5496         brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
5497                 (SBTML_REJ | SBTML_RESET));
5498         udelay(1);
5499 }
5500
5501 static int
5502 brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
5503 {
5504         struct chip_info *ci;
5505         int err;
5506         u8 clkval, clkset;
5507
5508         brcmf_dbg(TRACE, "Enter\n");
5509
5510         /* alloc chip_info_t */
5511         ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
5512         if (NULL == ci) {
5513                 brcmf_dbg(ERROR, "malloc failed!\n");
5514                 return -ENOMEM;
5515         }
5516
5517         /* bus/core/clk setup for register access */
5518         /* Try forcing SDIO core to do ALPAvail request only */
5519         clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
5520         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
5521                                SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
5522         if (err) {
5523                 brcmf_dbg(ERROR, "error writing for HT off\n");
5524                 goto fail;
5525         }
5526
5527         /* If register supported, wait for ALPAvail and then force ALP */
5528         /* This may take up to 15 milliseconds */
5529         clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
5530                         SBSDIO_FUNC1_CHIPCLKCSR, NULL);
5531         if ((clkval & ~SBSDIO_AVBITS) == clkset) {
5532                 SPINWAIT(((clkval =
5533                                 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
5534                                                 SBSDIO_FUNC1_CHIPCLKCSR,
5535                                                 NULL)),
5536                                 !SBSDIO_ALPAV(clkval)),
5537                                 PMU_MAX_TRANSITION_DLY);
5538                 if (!SBSDIO_ALPAV(clkval)) {
5539                         brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
5540                                   clkval);
5541                         err = -EBUSY;
5542                         goto fail;
5543                 }
5544                 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
5545                                 SBSDIO_FORCE_ALP;
5546                 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
5547                                 SBSDIO_FUNC1_CHIPCLKCSR,
5548                                 clkset, &err);
5549                 udelay(65);
5550         } else {
5551                 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
5552                           clkset, clkval);
5553                 err = -EACCES;
5554                 goto fail;
5555         }
5556
5557         /* Also, disable the extra SDIO pull-ups */
5558         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
5559                                SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
5560
5561         err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
5562         if (err)
5563                 goto fail;
5564
5565         /*
5566          * Make sure any on-chip ARM is off (in case strapping is wrong),
5567          * or downloaded code was already running.
5568          */
5569         brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
5570
5571         brcmf_sdcard_reg_write(bus->sdiodev,
5572                 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
5573         brcmf_sdcard_reg_write(bus->sdiodev,
5574                 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
5575
5576         /* Disable F2 to clear any intermediate frame state on the dongle */
5577         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
5578                 SDIO_FUNC_ENABLE_1, NULL);
5579
5580         /* WAR: cmd52 backplane read so core HW will drop ALPReq */
5581         clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
5582                         0, NULL);
5583
5584         /* Done with backplane-dependent accesses, can drop clock... */
5585         brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
5586                                SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5587
5588         bus->ci = ci;
5589         return 0;
5590 fail:
5591         bus->ci = NULL;
5592         kfree(ci);
5593         return err;
5594 }
5595
5596 static void
5597 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
5598 {
5599         u32 regdata;
5600
5601         /*
5602          * Must do the disable sequence first to work for
5603          * arbitrary current core state.
5604          */
5605         brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
5606
5607         /*
5608          * Now do the initialization sequence.
5609          * set reset while enabling the clock and
5610          * forcing them on throughout the core
5611          */
5612         brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
5613                 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
5614                 SBTML_RESET);
5615         udelay(1);
5616
5617         regdata = brcmf_sdcard_reg_read(sdiodev,
5618                                         CORE_SB(corebase, sbtmstatehigh), 4);
5619         if (regdata & SBTMH_SERR)
5620                 brcmf_sdcard_reg_write(sdiodev,
5621                                        CORE_SB(corebase, sbtmstatehigh), 4, 0);
5622
5623         regdata = brcmf_sdcard_reg_read(sdiodev,
5624                                         CORE_SB(corebase, sbimstate), 4);
5625         if (regdata & (SBIM_IBE | SBIM_TO))
5626                 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
5627                         regdata & ~(SBIM_IBE | SBIM_TO));
5628
5629         /* clear reset and allow it to propagate throughout the core */
5630         brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
5631                 (SICF_FGC << SBTML_SICF_SHIFT) |
5632                 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
5633         udelay(1);
5634
5635         /* leave clock enabled */
5636         brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
5637                 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
5638         udelay(1);
5639 }
5640
5641 /* SDIO Pad drive strength to select value mappings */
5642 struct sdiod_drive_str {
5643         u8 strength;    /* Pad Drive Strength in mA */
5644         u8 sel;         /* Chip-specific select value */
5645 };
5646
5647 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
5648 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
5649         {
5650         4, 0x2}, {
5651         2, 0x3}, {
5652         1, 0x0}, {
5653         0, 0x0}
5654         };
5655
5656 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
5657 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
5658         {
5659         12, 0x7}, {
5660         10, 0x6}, {
5661         8, 0x5}, {
5662         6, 0x4}, {
5663         4, 0x2}, {
5664         2, 0x1}, {
5665         0, 0x0}
5666         };
5667
5668 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
5669 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
5670         {
5671         32, 0x7}, {
5672         26, 0x6}, {
5673         22, 0x5}, {
5674         16, 0x4}, {
5675         12, 0x3}, {
5676         8, 0x2}, {
5677         4, 0x1}, {
5678         0, 0x0}
5679         };
5680
5681 #define SDIOD_DRVSTR_KEY(chip, pmu)     (((chip) << 16) | (pmu))
5682
5683 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
5684                                                    u32 drivestrength) {
5685         struct sdiod_drive_str *str_tab = NULL;
5686         u32 str_mask = 0;
5687         u32 str_shift = 0;
5688         char chn[8];
5689
5690         if (!(bus->ci->cccaps & CC_CAP_PMU))
5691                 return;
5692
5693         switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
5694         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
5695                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
5696                 str_mask = 0x30000000;
5697                 str_shift = 28;
5698                 break;
5699         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
5700         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
5701                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
5702                 str_mask = 0x00003800;
5703                 str_shift = 11;
5704                 break;
5705         case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
5706                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
5707                 str_mask = 0x00003800;
5708                 str_shift = 11;
5709                 break;
5710         default:
5711                 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
5712                           brcmu_chipname(bus->ci->chip, chn, 8),
5713                           bus->ci->chiprev, bus->ci->pmurev);
5714                 break;
5715         }
5716
5717         if (str_tab != NULL) {
5718                 u32 drivestrength_sel = 0;
5719                 u32 cc_data_temp;
5720                 int i;
5721
5722                 for (i = 0; str_tab[i].strength != 0; i++) {
5723                         if (drivestrength >= str_tab[i].strength) {
5724                                 drivestrength_sel = str_tab[i].sel;
5725                                 break;
5726                         }
5727                 }
5728
5729                 brcmf_sdcard_reg_write(bus->sdiodev,
5730                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
5731                         4, 1);
5732                 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
5733                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
5734                 cc_data_temp &= ~str_mask;
5735                 drivestrength_sel <<= str_shift;
5736                 cc_data_temp |= drivestrength_sel;
5737                 brcmf_sdcard_reg_write(bus->sdiodev,
5738                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
5739                         4, cc_data_temp);
5740
5741                 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
5742                           drivestrength, cc_data_temp);
5743         }
5744 }
5745
5746 static void
5747 brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
5748 {
5749         brcmf_dbg(TRACE, "Enter\n");
5750
5751         kfree(bus->ci);
5752         bus->ci = NULL;
5753 }
5754
5755 static void
5756 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
5757 {
5758         brcmf_sdbrcm_sdunlock(bus);
5759         wait_event_interruptible_timeout(bus->ctrl_wait,
5760                                          (*lockvar == false), HZ * 2);
5761         brcmf_sdbrcm_sdlock(bus);
5762         return;
5763 }
5764
5765 static void
5766 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
5767 {
5768         if (waitqueue_active(&bus->ctrl_wait))
5769                 wake_up_interruptible(&bus->ctrl_wait);
5770         return;
5771 }
5772
5773 static int
5774 brcmf_sdbrcm_watchdog_thread(void *data)
5775 {
5776         struct brcmf_bus *bus = (struct brcmf_bus *)data;
5777
5778         /* This thread doesn't need any user-level access,
5779         * so get rid of all our resources
5780         */
5781         if (brcmf_watchdog_prio > 0) {
5782                 struct sched_param param;
5783                 param.sched_priority = (brcmf_watchdog_prio < MAX_RT_PRIO) ?
5784                                        brcmf_watchdog_prio : (MAX_RT_PRIO - 1);
5785                 sched_setscheduler(current, SCHED_FIFO, &param);
5786         }
5787
5788         allow_signal(SIGTERM);
5789         /* Run until signal received */
5790         while (1) {
5791                 if (kthread_should_stop())
5792                         break;
5793                 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
5794                         if (bus->drvr->dongle_reset == false)
5795                                 brcmf_sdbrcm_bus_watchdog(bus->drvr);
5796                         /* Count the tick for reference */
5797                         bus->drvr->tickcnt++;
5798                 } else
5799                         break;
5800         }
5801         return 0;
5802 }
5803
5804 static void
5805 brcmf_sdbrcm_watchdog(unsigned long data)
5806 {
5807         struct brcmf_bus *bus = (struct brcmf_bus *)data;
5808
5809         if (brcmf_watchdog_prio >= 0) {
5810                 if (bus->watchdog_tsk)
5811                         complete(&bus->watchdog_wait);
5812                 else
5813                         return;
5814         } else {
5815                 brcmf_sdbrcm_bus_watchdog(bus->drvr);
5816
5817                 /* Count the tick for reference */
5818                 bus->drvr->tickcnt++;
5819         }
5820
5821         /* Reschedule the watchdog */
5822         if (bus->wd_timer_valid)
5823                 mod_timer(&bus->timer, jiffies + brcmf_watchdog_ms * HZ / 1000);
5824 }
5825
5826 void
5827 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
5828 {
5829         static uint save_ms;
5830
5831         /* don't start the wd until fw is loaded */
5832         if (bus->drvr->busstate == BRCMF_BUS_DOWN)
5833                 return;
5834
5835         /* Totally stop the timer */
5836         if (!wdtick && bus->wd_timer_valid == true) {
5837                 del_timer_sync(&bus->timer);
5838                 bus->wd_timer_valid = false;
5839                 save_ms = wdtick;
5840                 return;
5841         }
5842
5843         if (wdtick) {
5844                 brcmf_watchdog_ms = (uint) wdtick;
5845
5846                 if (save_ms != brcmf_watchdog_ms) {
5847                         if (bus->wd_timer_valid == true)
5848                                 /* Stop timer and restart at new value */
5849                                 del_timer_sync(&bus->timer);
5850
5851                         /* Create timer again when watchdog period is
5852                            dynamically changed or in the first instance
5853                          */
5854                         bus->timer.expires =
5855                                 jiffies + brcmf_watchdog_ms * HZ / 1000;
5856                         add_timer(&bus->timer);
5857
5858                 } else {
5859                         /* Re arm the timer, at last watchdog period */
5860                         mod_timer(&bus->timer,
5861                                 jiffies + brcmf_watchdog_ms * HZ / 1000);
5862                 }
5863
5864                 bus->wd_timer_valid = true;
5865                 save_ms = wdtick;
5866         }
5867 }
5868
5869 static int brcmf_sdbrcm_dpc_thread(void *data)
5870 {
5871         struct brcmf_bus *bus = (struct brcmf_bus *) data;
5872
5873         /* This thread doesn't need any user-level access,
5874          * so get rid of all our resources
5875          */
5876         if (brcmf_dpc_prio > 0) {
5877                 struct sched_param param;
5878                 param.sched_priority = (brcmf_dpc_prio < MAX_RT_PRIO) ?
5879                                        brcmf_dpc_prio : (MAX_RT_PRIO - 1);
5880                 sched_setscheduler(current, SCHED_FIFO, &param);
5881         }
5882
5883         allow_signal(SIGTERM);
5884         /* Run until signal received */
5885         while (1) {
5886                 if (kthread_should_stop())
5887                         break;
5888                 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
5889                         /* Call bus dpc unless it indicated down
5890                         (then clean stop) */
5891                         if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
5892                                 if (brcmf_sdbrcm_dpc(bus))
5893                                         complete(&bus->dpc_wait);
5894                         } else {
5895                                 brcmf_sdbrcm_bus_stop(bus, true);
5896                         }
5897                 } else
5898                         break;
5899         }
5900         return 0;
5901 }
5902
5903 static void brcmf_sdbrcm_dpc_tasklet(unsigned long data)
5904 {
5905         struct brcmf_bus *bus = (struct brcmf_bus *) data;
5906
5907         /* Call bus dpc unless it indicated down (then clean stop) */
5908         if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
5909                 if (brcmf_sdbrcm_dpc(bus))
5910                         tasklet_schedule(&bus->tasklet);
5911         } else
5912                 brcmf_sdbrcm_bus_stop(bus, true);
5913 }
5914
5915 static void brcmf_sdbrcm_sched_dpc(struct brcmf_bus *bus)
5916 {
5917         if (bus->dpc_tsk) {
5918                 complete(&bus->dpc_wait);
5919                 return;
5920         }
5921
5922         tasklet_schedule(&bus->tasklet);
5923 }
5924
5925 static void brcmf_sdbrcm_sdlock(struct brcmf_bus *bus)
5926 {
5927         if (bus->threads_only)
5928                 down(&bus->sdsem);
5929         else
5930                 spin_lock_bh(&bus->sdlock);
5931 }
5932
5933 static void brcmf_sdbrcm_sdunlock(struct brcmf_bus *bus)
5934 {
5935         if (bus->threads_only)
5936                 up(&bus->sdsem);
5937         else
5938                 spin_unlock_bh(&bus->sdlock);
5939 }
5940
5941 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
5942 {
5943         if (bus->firmware->size < bus->fw_ptr + len)
5944                 len = bus->firmware->size - bus->fw_ptr;
5945
5946         memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
5947         bus->fw_ptr += len;
5948         return len;
5949 }
5950
5951 MODULE_FIRMWARE(BCM4329_FW_NAME);
5952 MODULE_FIRMWARE(BCM4329_NV_NAME);
5953
5954 static int brcmf_sdbrcm_ioctl_resp_wait(struct brcmf_bus *bus, uint *condition,
5955                                         bool *pending)
5956 {
5957         DECLARE_WAITQUEUE(wait, current);
5958         int timeout = msecs_to_jiffies(brcmf_ioctl_timeout_msec);
5959
5960         /* Wait until control frame is available */
5961         add_wait_queue(&bus->ioctl_resp_wait, &wait);
5962         set_current_state(TASK_INTERRUPTIBLE);
5963
5964         while (!(*condition) && (!signal_pending(current) && timeout))
5965                 timeout = schedule_timeout(timeout);
5966
5967         if (signal_pending(current))
5968                 *pending = true;
5969
5970         set_current_state(TASK_RUNNING);
5971         remove_wait_queue(&bus->ioctl_resp_wait, &wait);
5972
5973         return timeout;
5974 }
5975
5976 static int brcmf_sdbrcm_ioctl_resp_wake(struct brcmf_bus *bus)
5977 {
5978         if (waitqueue_active(&bus->ioctl_resp_wait))
5979                 wake_up_interruptible(&bus->ioctl_resp_wait);
5980
5981         return 0;
5982 }