1 /***************************************************************************************
3 * Copyright (c) Beceem Communications Inc.
9 * This file has the prototypes,preprocessors and definitions various NVM libraries.
14 * -------- -------- ----------------------------------------------
15 * Name Date Created/reviewed/modified
19 ****************************************************************************************/
24 typedef struct _FLASH_SECTOR_INFO
28 } FLASH_SECTOR_INFO, *PFLASH_SECTOR_INFO;
30 typedef struct _FLASH_CS_INFO
33 /* let the magic number be 0xBECE-F1A5 - F1A5 for "flas-h" */
34 B_UINT32 FlashLayoutVersion;
35 B_UINT32 ISOImageVersion;
36 B_UINT32 SCSIFirmwareVersion;
37 B_UINT32 OffsetFromZeroForPart1ISOImage;
38 B_UINT32 OffsetFromZeroForScsiFirmware;
39 B_UINT32 SizeOfScsiFirmware;
40 B_UINT32 OffsetFromZeroForPart2ISOImage;
41 B_UINT32 OffsetFromZeroForCalibrationStart;
42 B_UINT32 OffsetFromZeroForCalibrationEnd;
43 B_UINT32 OffsetFromZeroForVSAStart;
44 B_UINT32 OffsetFromZeroForVSAEnd;
45 B_UINT32 OffsetFromZeroForControlSectionStart;
46 B_UINT32 OffsetFromZeroForControlSectionData;
47 B_UINT32 CDLessInactivityTimeout;
48 B_UINT32 NewImageSignature;
49 B_UINT32 FlashSectorSizeSig;
50 B_UINT32 FlashSectorSize;
51 B_UINT32 FlashWriteSupportSize;
52 B_UINT32 TotalFlashSize;
53 B_UINT32 FlashBaseAddr;
54 B_UINT32 FlashPartMaxSize;
55 B_UINT32 IsCDLessDeviceBootSig;
56 /* MSC Timeout after reset to switch from MSC to NW Mode */
57 B_UINT32 MassStorageTimeout;
58 } FLASH_CS_INFO, *PFLASH_CS_INFO;
60 #define FLASH2X_TOTAL_SIZE (64 * 1024 * 1024)
61 #define DEFAULT_SECTOR_SIZE (64 * 1024)
63 typedef struct _FLASH_2X_CS_INFO
65 /* magic number as 0xBECE-F1A5 - F1A5 for "flas-h" */
67 B_UINT32 FlashLayoutVersion;
68 B_UINT32 ISOImageVersion;
69 B_UINT32 SCSIFirmwareVersion;
70 B_UINT32 OffsetFromZeroForPart1ISOImage;
71 B_UINT32 OffsetFromZeroForScsiFirmware;
72 B_UINT32 SizeOfScsiFirmware;
73 B_UINT32 OffsetFromZeroForPart2ISOImage;
74 B_UINT32 OffsetFromZeroForDSDStart;
75 B_UINT32 OffsetFromZeroForDSDEnd;
76 B_UINT32 OffsetFromZeroForVSAStart;
77 B_UINT32 OffsetFromZeroForVSAEnd;
78 B_UINT32 OffsetFromZeroForControlSectionStart;
79 B_UINT32 OffsetFromZeroForControlSectionData;
80 /* NO Data Activity timeout to switch from MSC to NW Mode */
81 B_UINT32 CDLessInactivityTimeout;
82 B_UINT32 NewImageSignature;
83 B_UINT32 FlashSectorSizeSig;
84 B_UINT32 FlashSectorSize;
85 B_UINT32 FlashWriteSupportSize;
86 B_UINT32 TotalFlashSize;
87 B_UINT32 FlashBaseAddr;
88 B_UINT32 FlashPartMaxSize;
89 B_UINT32 IsCDLessDeviceBootSig;
90 /* MSC Timeout after reset to switch from MSC to NW Mode */
91 B_UINT32 MassStorageTimeout;
92 /* Flash Map 2.0 Field */
93 B_UINT32 OffsetISOImage1Part1Start;
94 B_UINT32 OffsetISOImage1Part1End;
95 B_UINT32 OffsetISOImage1Part2Start;
96 B_UINT32 OffsetISOImage1Part2End;
97 B_UINT32 OffsetISOImage1Part3Start;
98 B_UINT32 OffsetISOImage1Part3End;
99 B_UINT32 OffsetISOImage2Part1Start;
100 B_UINT32 OffsetISOImage2Part1End;
101 B_UINT32 OffsetISOImage2Part2Start;
102 B_UINT32 OffsetISOImage2Part2End;
103 B_UINT32 OffsetISOImage2Part3Start;
104 B_UINT32 OffsetISOImage2Part3End;
105 /* DSD Header offset from start of DSD */
106 B_UINT32 OffsetFromDSDStartForDSDHeader;
107 B_UINT32 OffsetFromZeroForDSD1Start;
108 B_UINT32 OffsetFromZeroForDSD1End;
109 B_UINT32 OffsetFromZeroForDSD2Start;
110 B_UINT32 OffsetFromZeroForDSD2End;
111 B_UINT32 OffsetFromZeroForVSA1Start;
112 B_UINT32 OffsetFromZeroForVSA1End;
113 B_UINT32 OffsetFromZeroForVSA2Start;
114 B_UINT32 OffsetFromZeroForVSA2End;
116 * ACCESS_BITS_PER_SECTOR 2
122 B_UINT32 SectorAccessBitMap[FLASH2X_TOTAL_SIZE / (DEFAULT_SECTOR_SIZE * 16)];
123 /* All expansions to the control data structure should add here */
124 } FLASH2X_CS_INFO, *PFLASH2X_CS_INFO;
126 typedef struct _VENDOR_SECTION_INFO
128 B_UINT32 OffsetFromZeroForSectionStart;
129 B_UINT32 OffsetFromZeroForSectionEnd;
130 B_UINT32 AccessFlags;
131 B_UINT32 Reserved[16];
132 } VENDOR_SECTION_INFO, *PVENDOR_SECTION_INFO;
134 typedef struct _FLASH2X_VENDORSPECIFIC_INFO
136 VENDOR_SECTION_INFO VendorSection[TOTAL_SECTIONS];
137 B_UINT32 Reserved[16];
138 } FLASH2X_VENDORSPECIFIC_INFO, *PFLASH2X_VENDORSPECIFIC_INFO;
140 typedef struct _DSD_HEADER
142 B_UINT32 DSDImageSize;
143 B_UINT32 DSDImageCRC;
144 B_UINT32 DSDImagePriority;
145 /* We should not consider right now. Reading reserve is worthless. */
146 B_UINT32 Reserved[252]; /* Resvd for DSD Header */
147 B_UINT32 DSDImageMagicNumber;
148 } DSD_HEADER, *PDSD_HEADER;
150 typedef struct _ISO_HEADER
152 B_UINT32 ISOImageMagicNumber;
153 B_UINT32 ISOImageSize;
154 B_UINT32 ISOImageCRC;
155 B_UINT32 ISOImagePriority;
156 /* We should not consider right now. Reading reserve is worthless. */
157 B_UINT32 Reserved[60]; /* Resvd for ISO Header extension */
158 } ISO_HEADER, *PISO_HEADER;
160 #define EEPROM_BEGIN_CIS (0)
161 #define EEPROM_BEGIN_NON_CIS (0x200)
162 #define EEPROM_END (0x2000)
163 #define INIT_PARAMS_SIGNATURE (0x95a7a597)
164 #define MAX_INIT_PARAMS_LENGTH (2048)
165 #define MAC_ADDRESS_OFFSET 0x200
167 #define INIT_PARAMS_1_SIGNATURE_ADDRESS EEPROM_BEGIN_NON_CIS
168 #define INIT_PARAMS_1_DATA_ADDRESS (INIT_PARAMS_1_SIGNATURE_ADDRESS+16)
169 #define INIT_PARAMS_1_MACADDRESS_ADDRESS (MAC_ADDRESS_OFFSET)
170 #define INIT_PARAMS_1_LENGTH_ADDRESS (INIT_PARAMS_1_SIGNATURE_ADDRESS+4)
172 #define INIT_PARAMS_2_SIGNATURE_ADDRESS (EEPROM_BEGIN_NON_CIS + 2048 + 16)
173 #define INIT_PARAMS_2_DATA_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 16)
174 #define INIT_PARAMS_2_MACADDRESS_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 8)
175 #define INIT_PARAMS_2_LENGTH_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 4)
177 #define EEPROM_SPI_DEV_CONFIG_REG 0x0F003000
178 #define EEPROM_SPI_Q_STATUS1_REG 0x0F003004
179 #define EEPROM_SPI_Q_STATUS1_MASK_REG 0x0F00300C
181 #define EEPROM_SPI_Q_STATUS_REG 0x0F003008
182 #define EEPROM_CMDQ_SPI_REG 0x0F003018
183 #define EEPROM_WRITE_DATAQ_REG 0x0F00301C
184 #define EEPROM_READ_DATAQ_REG 0x0F003020
185 #define SPI_FLUSH_REG 0x0F00304C
187 #define EEPROM_WRITE_ENABLE 0x06000000
188 #define EEPROM_READ_STATUS_REGISTER 0x05000000
189 #define EEPROM_16_BYTE_PAGE_WRITE 0xFA000000
190 #define EEPROM_WRITE_QUEUE_EMPTY 0x00001000
191 #define EEPROM_WRITE_QUEUE_AVAIL 0x00002000
192 #define EEPROM_WRITE_QUEUE_FULL 0x00004000
193 #define EEPROM_16_BYTE_PAGE_READ 0xFB000000
194 #define EEPROM_4_BYTE_PAGE_READ 0x3B000000
196 #define EEPROM_CMD_QUEUE_FLUSH 0x00000001
197 #define EEPROM_WRITE_QUEUE_FLUSH 0x00000002
198 #define EEPROM_READ_QUEUE_FLUSH 0x00000004
199 #define EEPROM_ETH_QUEUE_FLUSH 0x00000008
200 #define EEPROM_ALL_QUEUE_FLUSH 0x0000000f
201 #define EEPROM_READ_ENABLE 0x06000000
202 #define EEPROM_16_BYTE_PAGE_WRITE 0xFA000000
203 #define EEPROM_READ_DATA_FULL 0x00000010
204 #define EEPROM_READ_DATA_AVAIL 0x00000020
205 #define EEPROM_READ_QUEUE_EMPTY 0x00000002
206 #define EEPROM_CMD_QUEUE_EMPTY 0x00000100
207 #define EEPROM_CMD_QUEUE_AVAIL 0x00000200
208 #define EEPROM_CMD_QUEUE_FULL 0x00000400
210 /* Most EEPROM status register bit 0 indicates if the EEPROM is busy
211 * with a write if set 1. See the details of the EEPROM Status Register
212 * in the EEPROM data sheet.
214 #define EEPROM_STATUS_REG_WRITE_BUSY 0x00000001
216 /* We will have 1 mSec for every RETRIES_PER_DELAY count and have a max attempts of MAX_EEPROM_RETRIES
217 * This will give us 80 mSec minimum of delay = 80mSecs
219 #define MAX_EEPROM_RETRIES 80
220 #define RETRIES_PER_DELAY 64
221 #define MAX_RW_SIZE 0x10
222 #define MAX_READ_SIZE 0x10
223 #define MAX_SECTOR_SIZE (512 * 1024)
224 #define MIN_SECTOR_SIZE (1024)
225 #define FLASH_SECTOR_SIZE_OFFSET 0xEFFFC
226 #define FLASH_SECTOR_SIZE_SIG_OFFSET 0xEFFF8
227 #define FLASH_SECTOR_SIZE_SIG 0xCAFEBABE
228 #define FLASH_CS_INFO_START_ADDR 0xFF0000
229 #define FLASH_CONTROL_STRUCT_SIGNATURE 0xBECEF1A5
230 #define SCSI_FIRMWARE_MAJOR_VERSION 0x1
231 #define SCSI_FIRMWARE_MINOR_VERSION 0x5
232 #define BYTE_WRITE_SUPPORT 0x1
233 #define FLASH_AUTO_INIT_BASE_ADDR 0xF00000
234 #define FLASH_CONTIGIOUS_START_ADDR_AFTER_INIT 0x1C000000
235 #define FLASH_CONTIGIOUS_START_ADDR_BEFORE_INIT 0x1F000000
236 #define FLASH_CONTIGIOUS_START_ADDR_BCS350 0x08000000
237 #define FLASH_CONTIGIOUS_END_ADDR_BCS350 0x08FFFFFF
238 #define FLASH_SIZE_ADDR 0xFFFFEC
239 #define FLASH_SPI_CMDQ_REG 0xAF003040
240 #define FLASH_SPI_WRITEQ_REG 0xAF003044
241 #define FLASH_SPI_READQ_REG 0xAF003048
242 #define FLASH_CONFIG_REG 0xAF003050
243 #define FLASH_GPIO_CONFIG_REG 0xAF000030
244 #define FLASH_CMD_WRITE_ENABLE 0x06
245 #define FLASH_CMD_READ_ENABLE 0x03
246 #define FLASH_CMD_RESET_WRITE_ENABLE 0x04
247 #define FLASH_CMD_STATUS_REG_READ 0x05
248 #define FLASH_CMD_STATUS_REG_WRITE 0x01
249 #define FLASH_CMD_READ_ID 0x9F
250 #define PAD_SELECT_REGISTER 0xAF000410
251 #define FLASH_PART_SST25VF080B 0xBF258E
252 #define EEPROM_CAL_DATA_INTERNAL_LOC 0xbFB00008
253 #define EEPROM_CALPARAM_START 0x200
254 #define EEPROM_SIZE_OFFSET 524
256 /* As Read/Write time vaires from 1.5 to 3.0 ms.
257 * so After Ignoring the rdm/wrm time(that is dependent on many factor like interface etc.),
258 * here time calculated meets the worst case delay, 3.0 ms
260 #define MAX_FLASH_RETRIES 4
261 #define FLASH_PER_RETRIES_DELAY 16
262 #define EEPROM_MAX_CAL_AREA_SIZE 0xF0000
263 #define BECM ntohl(0x4245434d)
264 #define FLASH_2X_MAJOR_NUMBER 0x2
265 #define DSD_IMAGE_MAGIC_NUMBER 0xBECE0D5D
266 #define ISO_IMAGE_MAGIC_NUMBER 0xBECE0150
267 #define NON_CDLESS_DEVICE_BOOT_SIG 0xBECEB007
269 #define MINOR_VERSION(x) ((x >> 16) & 0xFFFF)
270 #define MAJOR_VERSION(x) (x & 0xFFFF)
272 #define CORRUPTED_PATTERN 0x0
273 #define UNINIT_PTR_IN_CS 0xBBBBDDDD
274 #define VENDOR_PTR_IN_CS 0xAAAACCCC
275 #define FLASH2X_SECTION_PRESENT 1 << 0
276 #define FLASH2X_SECTION_VALID 1 << 1
277 #define FLASH2X_SECTION_RO 1 << 2
278 #define FLASH2X_SECTION_ACT 1 << 3
279 #define SECTOR_IS_NOT_WRITABLE STATUS_FAILURE
280 #define INVALID_OFFSET STATUS_FAILURE
281 #define INVALID_SECTION STATUS_FAILURE
282 #define SECTOR_1K 1024
283 #define SECTOR_64K (64 * SECTOR_1K)
284 #define SECTOR_128K (2 * SECTOR_64K)
285 #define SECTOR_256k (2 * SECTOR_128K)
286 #define SECTOR_512K (2 * SECTOR_256k)
287 #define FLASH_PART_SIZE (16 * 1024 * 1024)
288 #define RESET_CHIP_SELECT -1
289 #define CHIP_SELECT_BIT12 12
290 #define SECTOR_READWRITE_PERMISSION 0
291 #define SECTOR_READONLY 1
292 #define SIGNATURE_SIZE 4
293 #define DEFAULT_BUFF_SIZE 0x10000
295 #define FIELD_OFFSET_IN_HEADER(HeaderPointer, Field) ((PUCHAR)&((HeaderPointer)(NULL))->Field - (PUCHAR)(NULL))