Pileus Git - ~andy/linux/blob - drivers/staging/bcm/DDRInit.c

   1 #include "headers.h"
   2
   3
   4
   5 #define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
   6 #define MIPS_CLOCK_REG  0x0f000820
   7
   8 /* DDR INIT-133Mhz */
   9 #define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12  /* index for 0x0F007000 */
  10 static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = {  /* DPLL Clock Setting */
  11         {0x0F000800, 0x00007212},
  12         {0x0f000820, 0x07F13FFF},
  13         {0x0f000810, 0x00000F95},
  14         {0x0f000860, 0x00000000},
  15         {0x0f000880, 0x000003DD},
  16         /* Changed source for X-bar and MIPS clock to APLL */
  17         {0x0f000840, 0x0FFF1B00},
  18         {0x0f000870, 0x00000002},
  19         {0x0F00a044, 0x1fffffff},
  20         {0x0F00a040, 0x1f000000},
  21         {0x0F00a084, 0x1Cffffff},
  22         {0x0F00a080, 0x1C000000},
  23         {0x0F00a04C, 0x0000000C},
  24         /* Memcontroller Default values */
  25         {0x0F007000, 0x00010001},
  26         {0x0F007004, 0x01010100},
  27         {0x0F007008, 0x01000001},
  28         {0x0F00700c, 0x00000000},
  29         {0x0F007010, 0x01000000},
  30         {0x0F007014, 0x01000100},
  31         {0x0F007018, 0x01000000},
  32         {0x0F00701c, 0x01020001},
  33         {0x0F007020, 0x04030107},
  34         {0x0F007024, 0x02000007},
  35         {0x0F007028, 0x02020202},
  36         {0x0F00702c, 0x0206060a},
  37         {0x0F007030, 0x05000000},
  38         {0x0F007034, 0x00000003},
  39         {0x0F007038, 0x110a0200},
  40         {0x0F00703C, 0x02101010},
  41         {0x0F007040, 0x45751200},
  42         {0x0F007044, 0x110a0d00},
  43         {0x0F007048, 0x081b0306},
  44         {0x0F00704c, 0x00000000},
  45         {0x0F007050, 0x0000001c},
  46         {0x0F007054, 0x00000000},
  47         {0x0F007058, 0x00000000},
  48         {0x0F00705c, 0x00000000},
  49         {0x0F007060, 0x0010246c},
  50         {0x0F007064, 0x00000010},
  51         {0x0F007068, 0x00000000},
  52         {0x0F00706c, 0x00000001},
  53         {0x0F007070, 0x00007000},
  54         {0x0F007074, 0x00000000},
  55         {0x0F007078, 0x00000000},
  56         {0x0F00707C, 0x00000000},
  57         {0x0F007080, 0x00000000},
  58         {0x0F007084, 0x00000000},
  59         /* Enable BW improvement within memory controller */
  60         {0x0F007094, 0x00000104},
  61         /* Enable 2 ports within X-bar */
  62         {0x0F00A000, 0x00000016},
  63         /* Enable start bit within memory controller */
  64         {0x0F007018, 0x01010000}
  65 };
  66 /* 80Mhz */
  67 #define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10  /* index for 0x0F007000 */
  68 static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {  /* DPLL Clock Setting */
  69         {0x0f000810, 0x00000F95},
  70         {0x0f000820, 0x07f1ffff},
  71         {0x0f000860, 0x00000000},
  72         {0x0f000880, 0x000003DD},
  73         {0x0F00a044, 0x1fffffff},
  74         {0x0F00a040, 0x1f000000},
  75         {0x0F00a084, 0x1Cffffff},
  76         {0x0F00a080, 0x1C000000},
  77         {0x0F00a000, 0x00000016},
  78         {0x0F00a04C, 0x0000000C},
  79         /* Memcontroller Default values */
  80         {0x0F007000, 0x00010001},
  81         {0x0F007004, 0x01000000},
  82         {0x0F007008, 0x01000001},
  83         {0x0F00700c, 0x00000000},
  84         {0x0F007010, 0x01000000},
  85         {0x0F007014, 0x01000100},
  86         {0x0F007018, 0x01000000},
  87         {0x0F00701c, 0x01020000},
  88         {0x0F007020, 0x04020107},
  89         {0x0F007024, 0x00000007},
  90         {0x0F007028, 0x02020201},
  91         {0x0F00702c, 0x0204040a},
  92         {0x0F007030, 0x04000000},
  93         {0x0F007034, 0x00000002},
  94         {0x0F007038, 0x1F060200},
  95         {0x0F00703C, 0x1C22221F},
  96         {0x0F007040, 0x8A006600},
  97         {0x0F007044, 0x221a0800},
  98         {0x0F007048, 0x02690204},
  99         {0x0F00704c, 0x00000000},
 100         {0x0F007050, 0x0000001c},
 101         {0x0F007054, 0x00000000},
 102         {0x0F007058, 0x00000000},
 103         {0x0F00705c, 0x00000000},
 104         {0x0F007060, 0x000A15D6},
 105         {0x0F007064, 0x0000000A},
 106         {0x0F007068, 0x00000000},
 107         {0x0F00706c, 0x00000001},
 108         {0x0F007070, 0x00004000},
 109         {0x0F007074, 0x00000000},
 110         {0x0F007078, 0x00000000},
 111         {0x0F00707C, 0x00000000},
 112         {0x0F007080, 0x00000000},
 113         {0x0F007084, 0x00000000},
 114         {0x0F007094, 0x00000104},
 115         /* Enable start bit within memory controller */
 116         {0x0F007018, 0x01010000}
 117 };
 118 /* 100Mhz */
 119 #define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13  /* index for 0x0F007000 */
 120 static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {  /* DPLL Clock Setting */
 121         {0x0F000800, 0x00007008},
 122         {0x0f000810, 0x00000F95},
 123         {0x0f000820, 0x07F13E3F},
 124         {0x0f000860, 0x00000000},
 125         {0x0f000880, 0x000003DD},
 126         /* Changed source for X-bar and MIPS clock to APLL */
 127         {0x0f000840, 0x0FFF1B00},
 128         {0x0f000870, 0x00000002},
 129         {0x0F00a044, 0x1fffffff},
 130         {0x0F00a040, 0x1f000000},
 131         {0x0F00a084, 0x1Cffffff},
 132         {0x0F00a080, 0x1C000000},
 133         {0x0F00a04C, 0x0000000C},
 134         /* Enable 2 ports within X-bar */
 135         {0x0F00A000, 0x00000016},
 136         /* Memcontroller Default values */
 137         {0x0F007000, 0x00010001},
 138         {0x0F007004, 0x01010100},
 139         {0x0F007008, 0x01000001},
 140         {0x0F00700c, 0x00000000},
 141         {0x0F007010, 0x01000000},
 142         {0x0F007014, 0x01000100},
 143         {0x0F007018, 0x01000000},
 144         {0x0F00701c, 0x01020001},
 145         {0x0F007020, 0x04020107},
 146         {0x0F007024, 0x00000007},
 147         {0x0F007028, 0x01020201},
 148         {0x0F00702c, 0x0204040A},
 149         {0x0F007030, 0x06000000},
 150         {0x0F007034, 0x00000004},
 151         {0x0F007038, 0x20080200},
 152         {0x0F00703C, 0x02030320},
 153         {0x0F007040, 0x6E7F1200},
 154         {0x0F007044, 0x01190A00},
 155         {0x0F007048, 0x06120305},
 156         {0x0F00704c, 0x00000000},
 157         {0x0F007050, 0x0000001C},
 158         {0x0F007054, 0x00000000},
 159         {0x0F007058, 0x00000000},
 160         {0x0F00705c, 0x00000000},
 161         {0x0F007060, 0x00082ED6},
 162         {0x0F007064, 0x0000000A},
 163         {0x0F007068, 0x00000000},
 164         {0x0F00706c, 0x00000001},
 165         {0x0F007070, 0x00005000},
 166         {0x0F007074, 0x00000000},
 167         {0x0F007078, 0x00000000},
 168         {0x0F00707C, 0x00000000},
 169         {0x0F007080, 0x00000000},
 170         {0x0F007084, 0x00000000},
 171         /* Enable BW improvement within memory controller */
 172         {0x0F007094, 0x00000104},
 173         /* Enable start bit within memory controller */
 174         {0x0F007018, 0x01010000}
 175 };
 176
 177 /* Net T3B DDR Settings
 178  * DDR INIT-133Mhz
 179  */
 180 static struct bcm_ddr_setting asDPLL_266MHZ[] = {
 181         {0x0F000800, 0x00007212},
 182         {0x0f000820, 0x07F13FFF},
 183         {0x0f000810, 0x00000F95},
 184         {0x0f000860, 0x00000000},
 185         {0x0f000880, 0x000003DD},
 186         /* Changed source for X-bar and MIPS clock to APLL */
 187         {0x0f000840, 0x0FFF1B00},
 188         {0x0f000870, 0x00000002}
 189 };
 190
 191 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11  /* index for 0x0F007000 */
 192 static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {  /* DPLL Clock Setting */
 193         {0x0f000810, 0x00000F95},
 194         {0x0f000810, 0x00000F95},
 195         {0x0f000810, 0x00000F95},
 196         {0x0f000820, 0x07F13652},
 197         {0x0f000840, 0x0FFF0800},
 198         /* Changed source for X-bar and MIPS clock to APLL */
 199         {0x0f000880, 0x000003DD},
 200         {0x0f000860, 0x00000000},
 201         /* Changed source for X-bar and MIPS clock to APLL */
 202         {0x0F00a044, 0x1fffffff},
 203         {0x0F00a040, 0x1f000000},
 204         {0x0F00a084, 0x1Cffffff},
 205         {0x0F00a080, 0x1C000000},
 206         /* Enable 2 ports within X-bar */
 207         {0x0F00A000, 0x00000016},
 208         /* Memcontroller Default values */
 209         {0x0F007000, 0x00010001},
 210         {0x0F007004, 0x01010100},
 211         {0x0F007008, 0x01000001},
 212         {0x0F00700c, 0x00000000},
 213         {0x0F007010, 0x01000000},
 214         {0x0F007014, 0x01000100},
 215         {0x0F007018, 0x01000000},
 216         {0x0F00701c, 0x01020001},
 217         {0x0F007020, 0x04030107},
 218         {0x0F007024, 0x02000007},
 219         {0x0F007028, 0x02020202},
 220         {0x0F00702c, 0x0206060a},
 221         {0x0F007030, 0x05000000},
 222         {0x0F007034, 0x00000003},
 223         {0x0F007038, 0x130a0200},
 224         {0x0F00703C, 0x02101012},
 225         {0x0F007040, 0x457D1200},
 226         {0x0F007044, 0x11130d00},
 227         {0x0F007048, 0x040D0306},
 228         {0x0F00704c, 0x00000000},
 229         {0x0F007050, 0x0000001c},
 230         {0x0F007054, 0x00000000},
 231         {0x0F007058, 0x00000000},
 232         {0x0F00705c, 0x00000000},
 233         {0x0F007060, 0x0010246c},
 234         {0x0F007064, 0x00000012},
 235         {0x0F007068, 0x00000000},
 236         {0x0F00706c, 0x00000001},
 237         {0x0F007070, 0x00007000},
 238         {0x0F007074, 0x00000000},
 239         {0x0F007078, 0x00000000},
 240         {0x0F00707C, 0x00000000},
 241         {0x0F007080, 0x00000000},
 242         {0x0F007084, 0x00000000},
 243         /* Enable BW improvement within memory controller */
 244         {0x0F007094, 0x00000104},
 245         /* Enable start bit within memory controller */
 246         {0x0F007018, 0x01010000},
 247         };
 248
 249 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9  /* index for 0x0F007000 */
 250 static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {  /* DPLL Clock Setting */
 251         {0x0f000810, 0x00000F95},
 252         {0x0f000820, 0x07F13FFF},
 253         {0x0f000840, 0x0FFF1F00},
 254         {0x0f000880, 0x000003DD},
 255         {0x0f000860, 0x00000000},
 256
 257         {0x0F00a044, 0x1fffffff},
 258         {0x0F00a040, 0x1f000000},
 259         {0x0F00a084, 0x1Cffffff},
 260         {0x0F00a080, 0x1C000000},
 261         {0x0F00a000, 0x00000016},
 262         /* Memcontroller Default values */
 263         {0x0F007000, 0x00010001},
 264         {0x0F007004, 0x01000000},
 265         {0x0F007008, 0x01000001},
 266         {0x0F00700c, 0x00000000},
 267         {0x0F007010, 0x01000000},
 268         {0x0F007014, 0x01000100},
 269         {0x0F007018, 0x01000000},
 270         {0x0F00701c, 0x01020000},
 271         {0x0F007020, 0x04020107},
 272         {0x0F007024, 0x00000007},
 273         {0x0F007028, 0x02020201},
 274         {0x0F00702c, 0x0204040a},
 275         {0x0F007030, 0x04000000},
 276         {0x0F007034, 0x02000002},
 277         {0x0F007038, 0x1F060202},
 278         {0x0F00703C, 0x1C22221F},
 279         {0x0F007040, 0x8A006600},
 280         {0x0F007044, 0x221a0800},
 281         {0x0F007048, 0x02690204},
 282         {0x0F00704c, 0x00000000},
 283         {0x0F007050, 0x0100001c},
 284         {0x0F007054, 0x00000000},
 285         {0x0F007058, 0x00000000},
 286         {0x0F00705c, 0x00000000},
 287         {0x0F007060, 0x000A15D6},
 288         {0x0F007064, 0x0000000A},
 289         {0x0F007068, 0x00000000},
 290         {0x0F00706c, 0x00000001},
 291         {0x0F007070, 0x00004000},
 292         {0x0F007074, 0x00000000},
 293         {0x0F007078, 0x00000000},
 294         {0x0F00707C, 0x00000000},
 295         {0x0F007080, 0x00000000},
 296         {0x0F007084, 0x00000000},
 297         {0x0F007094, 0x00000104},
 298         /* Enable start bit within memory controller */
 299         {0x0F007018, 0x01010000}
 300 };
 301
 302 /* 100Mhz */
 303 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9  /* index for 0x0F007000 */
 304 static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {  /* DPLL Clock Setting */
 305         {0x0f000810, 0x00000F95},
 306         {0x0f000820, 0x07F1369B},
 307         {0x0f000840, 0x0FFF0800},
 308         {0x0f000880, 0x000003DD},
 309         {0x0f000860, 0x00000000},
 310         {0x0F00a044, 0x1fffffff},
 311         {0x0F00a040, 0x1f000000},
 312         {0x0F00a084, 0x1Cffffff},
 313         {0x0F00a080, 0x1C000000},
 314         /* Enable 2 ports within X-bar */
 315         {0x0F00A000, 0x00000016},
 316         /* Memcontroller Default values */
 317         {0x0F007000, 0x00010001},
 318         {0x0F007004, 0x01010100},
 319         {0x0F007008, 0x01000001},
 320         {0x0F00700c, 0x00000000},
 321         {0x0F007010, 0x01000000},
 322         {0x0F007014, 0x01000100},
 323         {0x0F007018, 0x01000000},
 324         {0x0F00701c, 0x01020000},
 325         {0x0F007020, 0x04020107},
 326         {0x0F007024, 0x00000007},
 327         {0x0F007028, 0x01020201},
 328         {0x0F00702c, 0x0204040A},
 329         {0x0F007030, 0x06000000},
 330         {0x0F007034, 0x02000004},
 331         {0x0F007038, 0x20080200},
 332         {0x0F00703C, 0x02030320},
 333         {0x0F007040, 0x6E7F1200},
 334         {0x0F007044, 0x01190A00},
 335         {0x0F007048, 0x06120305},
 336         {0x0F00704c, 0x00000000},
 337         {0x0F007050, 0x0100001C},
 338         {0x0F007054, 0x00000000},
 339         {0x0F007058, 0x00000000},
 340         {0x0F00705c, 0x00000000},
 341         {0x0F007060, 0x00082ED6},
 342         {0x0F007064, 0x0000000A},
 343         {0x0F007068, 0x00000000},
 344         {0x0F00706c, 0x00000001},
 345         {0x0F007070, 0x00005000},
 346         {0x0F007074, 0x00000000},
 347         {0x0F007078, 0x00000000},
 348         {0x0F00707C, 0x00000000},
 349         {0x0F007080, 0x00000000},
 350         {0x0F007084, 0x00000000},
 351         /* Enable BW improvement within memory controller */
 352         {0x0F007094, 0x00000104},
 353         /* Enable start bit within memory controller */
 354         {0x0F007018, 0x01010000}
 355 };
 356
 357
 358 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9  /* index for 0x0F007000 */
 359 static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = {  /* DPLL Clock Setting */
 360         {0x0f000820, 0x03F1365B},
 361         {0x0f000810, 0x00002F95},
 362         {0x0f000880, 0x000003DD},
 363         /* Changed source for X-bar and MIPS clock to APLL */
 364         {0x0f000840, 0x0FFF0000},
 365         {0x0f000860, 0x00000000},
 366         {0x0F00a044, 0x1fffffff},
 367         {0x0F00a040, 0x1f000000},
 368         {0x0F00a084, 0x1Cffffff},
 369         {0x0F00a080, 0x1C000000},
 370         {0x0F00A000, 0x00000016},
 371         /* Memcontroller Default values */
 372         {0x0F007000, 0x00010001},
 373         {0x0F007004, 0x01010100},
 374         {0x0F007008, 0x01000001},
 375         {0x0F00700c, 0x00000000},
 376         {0x0F007010, 0x01000000},
 377         {0x0F007014, 0x01000100},
 378         {0x0F007018, 0x01000000},
 379         {0x0F00701c, 0x01020001},
 380         {0x0F007020, 0x04030107},
 381         {0x0F007024, 0x02000007},
 382         {0x0F007028, 0x02020200},
 383         {0x0F00702c, 0x0206060a},
 384         {0x0F007030, 0x05000000},
 385         {0x0F007034, 0x00000003},
 386         {0x0F007038, 0x200a0200},
 387         {0x0F00703C, 0x02101020},
 388         {0x0F007040, 0x45711200},
 389         {0x0F007044, 0x110D0D00},
 390         {0x0F007048, 0x04080306},
 391         {0x0F00704c, 0x00000000},
 392         {0x0F007050, 0x0100001c},
 393         {0x0F007054, 0x00000000},
 394         {0x0F007058, 0x00000000},
 395         {0x0F00705c, 0x00000000},
 396         {0x0F007060, 0x0010245F},
 397         {0x0F007064, 0x00000010},
 398         {0x0F007068, 0x00000000},
 399         {0x0F00706c, 0x00000001},
 400         {0x0F007070, 0x00007000},
 401         {0x0F007074, 0x00000000},
 402         {0x0F007078, 0x00000000},
 403         {0x0F00707C, 0x00000000},
 404         {0x0F007080, 0x00000000},
 405         {0x0F007084, 0x00000000},
 406         {0x0F007088, 0x01000001},
 407         {0x0F00708c, 0x00000101},
 408         {0x0F007090, 0x00000000},
 409         /* Enable BW improvement within memory controller */
 410         {0x0F007094, 0x00040000},
 411         {0x0F007098, 0x00000000},
 412         {0x0F0070c8, 0x00000104},
 413         /* Enable 2 ports within X-bar */
 414         /* Enable start bit within memory controller */
 415         {0x0F007018, 0x01010000}
 416 };
 417
 418 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11  /* index for 0x0F007000 */
 419 static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = {  /* DPLL Clock Setting */
 420         {0x0f000810, 0x00002F95},
 421         {0x0f000820, 0x03F1369B},
 422         {0x0f000840, 0x0fff0000},
 423         {0x0f000860, 0x00000000},
 424         {0x0f000880, 0x000003DD},
 425         /* Changed source for X-bar and MIPS clock to APLL */
 426         {0x0f000840, 0x0FFF0000},
 427         {0x0F00a044, 0x1fffffff},
 428         {0x0F00a040, 0x1f000000},
 429         {0x0F00a084, 0x1Cffffff},
 430         {0x0F00a080, 0x1C000000},
 431         /* Memcontroller Default values */
 432         {0x0F007000, 0x00010001},
 433         {0x0F007004, 0x01010100},
 434         {0x0F007008, 0x01000001},
 435         {0x0F00700c, 0x00000000},
 436         {0x0F007010, 0x01000000},
 437         {0x0F007014, 0x01000100},
 438         {0x0F007018, 0x01000000},
 439         {0x0F00701c, 0x01020000},
 440         {0x0F007020, 0x04020107},
 441         {0x0F007024, 0x00000007},
 442         {0x0F007028, 0x01020200},
 443         {0x0F00702c, 0x0204040a},
 444         {0x0F007030, 0x06000000},
 445         {0x0F007034, 0x00000004},
 446         {0x0F007038, 0x1F080200},
 447         {0x0F00703C, 0x0203031F},
 448         {0x0F007040, 0x6e001200},
 449         {0x0F007044, 0x011a0a00},
 450         {0x0F007048, 0x03000305},
 451         {0x0F00704c, 0x00000000},
 452         {0x0F007050, 0x0100001c},
 453         {0x0F007054, 0x00000000},
 454         {0x0F007058, 0x00000000},
 455         {0x0F00705c, 0x00000000},
 456         {0x0F007060, 0x00082ED6},
 457         {0x0F007064, 0x0000000A},
 458         {0x0F007068, 0x00000000},
 459         {0x0F00706c, 0x00000001},
 460         {0x0F007070, 0x00005000},
 461         {0x0F007074, 0x00000000},
 462         {0x0F007078, 0x00000000},
 463         {0x0F00707C, 0x00000000},
 464         {0x0F007080, 0x00000000},
 465         {0x0F007084, 0x00000000},
 466         {0x0F007088, 0x01000001},
 467         {0x0F00708c, 0x00000101},
 468         {0x0F007090, 0x00000000},
 469         {0x0F007094, 0x00010000},
 470         {0x0F007098, 0x00000000},
 471         {0x0F0070C8, 0x00000104},
 472         /* Enable 2 ports within X-bar */
 473         {0x0F00A000, 0x00000016},
 474         /* Enable start bit within memory controller */
 475         {0x0F007018, 0x01010000}
 476 };
 477
 478 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9  /* index for 0x0F007000 */
 479 static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[] = {  /* DPLL Clock Setting */
 480         {0x0f000820, 0x07F13FFF},
 481         {0x0f000810, 0x00002F95},
 482         {0x0f000860, 0x00000000},
 483         {0x0f000880, 0x000003DD},
 484         {0x0f000840, 0x0FFF1F00},
 485         {0x0F00a044, 0x1fffffff},
 486         {0x0F00a040, 0x1f000000},
 487         {0x0F00a084, 0x1Cffffff},
 488         {0x0F00a080, 0x1C000000},
 489         {0x0F00A000, 0x00000016},
 490         {0x0f007000, 0x00010001},
 491         {0x0f007004, 0x01000000},
 492         {0x0f007008, 0x01000001},
 493         {0x0f00700c, 0x00000000},
 494         {0x0f007010, 0x01000000},
 495         {0x0f007014, 0x01000100},
 496         {0x0f007018, 0x01000000},
 497         {0x0f00701c, 0x01020000},
 498         {0x0f007020, 0x04020107},
 499         {0x0f007024, 0x00000007},
 500         {0x0f007028, 0x02020200},
 501         {0x0f00702c, 0x0204040a},
 502         {0x0f007030, 0x04000000},
 503         {0x0f007034, 0x00000002},
 504         {0x0f007038, 0x1d060200},
 505         {0x0f00703c, 0x1c22221d},
 506         {0x0f007040, 0x8A116600},
 507         {0x0f007044, 0x222d0800},
 508         {0x0f007048, 0x02690204},
 509         {0x0f00704c, 0x00000000},
 510         {0x0f007050, 0x0100001c},
 511         {0x0f007054, 0x00000000},
 512         {0x0f007058, 0x00000000},
 513         {0x0f00705c, 0x00000000},
 514         {0x0f007060, 0x000A15D6},
 515         {0x0f007064, 0x0000000A},
 516         {0x0f007068, 0x00000000},
 517         {0x0f00706c, 0x00000001},
 518         {0x0f007070, 0x00004000},
 519         {0x0f007074, 0x00000000},
 520         {0x0f007078, 0x00000000},
 521         {0x0f00707c, 0x00000000},
 522         {0x0f007080, 0x00000000},
 523         {0x0f007084, 0x00000000},
 524         {0x0f007088, 0x01000001},
 525         {0x0f00708c, 0x00000101},
 526         {0x0f007090, 0x00000000},
 527         {0x0f007094, 0x00010000},
 528         {0x0f007098, 0x00000000},
 529         {0x0F0070C8, 0x00000104},
 530         {0x0F007018, 0x01010000}
 531 };
 532
 533
 534
 535
 536 /* T3 LP-B (UMA-B) */
 537
 538 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7  /* index for 0x0F007000 */
 539 static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] = {  /* DPLL Clock Setting */
 540         {0x0f000820, 0x03F137DB},
 541         {0x0f000810, 0x01842795},
 542         {0x0f000860, 0x00000000},
 543         {0x0f000880, 0x000003DD},
 544         {0x0f000840, 0x0FFF0400},
 545         {0x0F00a044, 0x1fffffff},
 546         {0x0F00a040, 0x1f000000},
 547         {0x0f003050, 0x00000021},  /* this is flash/eeprom clock divisor which set the flash clock to 20 MHz */
 548         {0x0F00a084, 0x1Cffffff},  /* Now dump from her in internal memory */
 549         {0x0F00a080, 0x1C000000},
 550         {0x0F00A000, 0x00000016},
 551         {0x0f007000, 0x00010001},
 552         {0x0f007004, 0x01000001},
 553         {0x0f007008, 0x01000101},
 554         {0x0f00700c, 0x00000000},
 555         {0x0f007010, 0x01000100},
 556         {0x0f007014, 0x01000100},
 557         {0x0f007018, 0x01000000},
 558         {0x0f00701c, 0x01020000},
 559         {0x0f007020, 0x04030107},
 560         {0x0f007024, 0x02000007},
 561         {0x0f007028, 0x02020200},
 562         {0x0f00702c, 0x0206060a},
 563         {0x0f007030, 0x050d0d00},
 564         {0x0f007034, 0x00000003},
 565         {0x0f007038, 0x170a0200},
 566         {0x0f00703c, 0x02101012},
 567         {0x0f007040, 0x45161200},
 568         {0x0f007044, 0x11250c00},
 569         {0x0f007048, 0x04da0307},
 570         {0x0f00704c, 0x00000000},
 571         {0x0f007050, 0x0000001c},
 572         {0x0f007054, 0x00000000},
 573         {0x0f007058, 0x00000000},
 574         {0x0f00705c, 0x00000000},
 575         {0x0f007060, 0x00142bb6},
 576         {0x0f007064, 0x20430014},
 577         {0x0f007068, 0x00000000},
 578         {0x0f00706c, 0x00000001},
 579         {0x0f007070, 0x00009000},
 580         {0x0f007074, 0x00000000},
 581         {0x0f007078, 0x00000000},
 582         {0x0f00707c, 0x00000000},
 583         {0x0f007080, 0x00000000},
 584         {0x0f007084, 0x00000000},
 585         {0x0f007088, 0x01000001},
 586         {0x0f00708c, 0x00000101},
 587         {0x0f007090, 0x00000000},
 588         {0x0f007094, 0x00040000},
 589         {0x0f007098, 0x00000000},
 590         {0x0F0070C8, 0x00000104},
 591         {0x0F007018, 0x01010000}
 592 };
 593
 594
 595 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7  /* index for 0x0F007000 */
 596 static struct bcm_ddr_setting asT3LPB_DDRSetting133MHz[] = {  /* DPLL Clock Setting */
 597         {0x0f000820, 0x03F1365B},
 598         {0x0f000810, 0x00002F95},
 599         {0x0f000880, 0x000003DD},
 600         /* Changed source for X-bar and MIPS clock to APLL */
 601         {0x0f000840, 0x0FFF0000},
 602         {0x0f000860, 0x00000000},
 603         {0x0F00a044, 0x1fffffff},
 604         {0x0F00a040, 0x1f000000},
 605         {0x0f003050, 0x00000021},  /* flash/eeprom clock divisor which set the flash clock to 20 MHz */
 606         {0x0F00a084, 0x1Cffffff},  /* dump from here in internal memory */
 607         {0x0F00a080, 0x1C000000},
 608         {0x0F00A000, 0x00000016},
 609         /* Memcontroller Default values */
 610         {0x0F007000, 0x00010001},
 611         {0x0F007004, 0x01010100},
 612         {0x0F007008, 0x01000001},
 613         {0x0F00700c, 0x00000000},
 614         {0x0F007010, 0x01000000},
 615         {0x0F007014, 0x01000100},
 616         {0x0F007018, 0x01000000},
 617         {0x0F00701c, 0x01020001},
 618         {0x0F007020, 0x04030107},
 619         {0x0F007024, 0x02000007},
 620         {0x0F007028, 0x02020200},
 621         {0x0F00702c, 0x0206060a},
 622         {0x0F007030, 0x05000000},
 623         {0x0F007034, 0x00000003},
 624         {0x0F007038, 0x190a0200},
 625         {0x0F00703C, 0x02101017},
 626         {0x0F007040, 0x45171200},
 627         {0x0F007044, 0x11290D00},
 628         {0x0F007048, 0x04080306},
 629         {0x0F00704c, 0x00000000},
 630         {0x0F007050, 0x0100001c},
 631         {0x0F007054, 0x00000000},
 632         {0x0F007058, 0x00000000},
 633         {0x0F00705c, 0x00000000},
 634         {0x0F007060, 0x0010245F},
 635         {0x0F007064, 0x00000010},
 636         {0x0F007068, 0x00000000},
 637         {0x0F00706c, 0x00000001},
 638         {0x0F007070, 0x00007000},
 639         {0x0F007074, 0x00000000},
 640         {0x0F007078, 0x00000000},
 641         {0x0F00707C, 0x00000000},
 642         {0x0F007080, 0x00000000},
 643         {0x0F007084, 0x00000000},
 644         {0x0F007088, 0x01000001},
 645         {0x0F00708c, 0x00000101},
 646         {0x0F007090, 0x00000000},
 647         /* Enable BW improvement within memory controller */
 648         {0x0F007094, 0x00040000},
 649         {0x0F007098, 0x00000000},
 650         {0x0F0070c8, 0x00000104},
 651         /* Enable 2 ports within X-bar */
 652         /* Enable start bit within memory controller */
 653         {0x0F007018, 0x01010000}
 654 };
 655
 656 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8  /* index for 0x0F007000 */
 657 static struct bcm_ddr_setting asT3LPB_DDRSetting100MHz[] = {  /* DPLL Clock Setting */
 658         {0x0f000810, 0x00002F95},
 659         {0x0f000820, 0x03F1369B},
 660         {0x0f000840, 0x0fff0000},
 661         {0x0f000860, 0x00000000},
 662         {0x0f000880, 0x000003DD},
 663         /* Changed source for X-bar and MIPS clock to APLL */
 664         {0x0f000840, 0x0FFF0000},
 665         {0x0F00a044, 0x1fffffff},
 666         {0x0F00a040, 0x1f000000},
 667         {0x0f003050, 0x00000021},  /* flash/eeprom clock divisor which set the flash clock to 20 MHz */
 668         {0x0F00a084, 0x1Cffffff},  /* dump from here in internal memory */
 669         {0x0F00a080, 0x1C000000},
 670         /* Memcontroller Default values */
 671         {0x0F007000, 0x00010001},
 672         {0x0F007004, 0x01010100},
 673         {0x0F007008, 0x01000001},
 674         {0x0F00700c, 0x00000000},
 675         {0x0F007010, 0x01000000},
 676         {0x0F007014, 0x01000100},
 677         {0x0F007018, 0x01000000},
 678         {0x0F00701c, 0x01020000},
 679         {0x0F007020, 0x04020107},
 680         {0x0F007024, 0x00000007},
 681         {0x0F007028, 0x01020200},
 682         {0x0F00702c, 0x0204040a},
 683         {0x0F007030, 0x06000000},
 684         {0x0F007034, 0x00000004},
 685         {0x0F007038, 0x1F080200},
 686         {0x0F00703C, 0x0203031F},
 687         {0x0F007040, 0x6e001200},
 688         {0x0F007044, 0x011a0a00},
 689         {0x0F007048, 0x03000305},
 690         {0x0F00704c, 0x00000000},
 691         {0x0F007050, 0x0100001c},
 692         {0x0F007054, 0x00000000},
 693         {0x0F007058, 0x00000000},
 694         {0x0F00705c, 0x00000000},
 695         {0x0F007060, 0x00082ED6},
 696         {0x0F007064, 0x0000000A},
 697         {0x0F007068, 0x00000000},
 698         {0x0F00706c, 0x00000001},
 699         {0x0F007070, 0x00005000},
 700         {0x0F007074, 0x00000000},
 701         {0x0F007078, 0x00000000},
 702         {0x0F00707C, 0x00000000},
 703         {0x0F007080, 0x00000000},
 704         {0x0F007084, 0x00000000},
 705         {0x0F007088, 0x01000001},
 706         {0x0F00708c, 0x00000101},
 707         {0x0F007090, 0x00000000},
 708         {0x0F007094, 0x00010000},
 709         {0x0F007098, 0x00000000},
 710         {0x0F0070C8, 0x00000104},
 711         /* Enable 2 ports within X-bar */
 712         {0x0F00A000, 0x00000016},
 713         /* Enable start bit within memory controller */
 714         {0x0F007018, 0x01010000}
 715 };
 716
 717 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7  /* index for 0x0F007000 */
 718 static struct bcm_ddr_setting asT3LPB_DDRSetting80MHz[] = {  /* DPLL Clock Setting */
 719         {0x0f000820, 0x07F13FFF},
 720         {0x0f000810, 0x00002F95},
 721         {0x0f000860, 0x00000000},
 722         {0x0f000880, 0x000003DD},
 723         {0x0f000840, 0x0FFF1F00},
 724         {0x0F00a044, 0x1fffffff},
 725         {0x0F00a040, 0x1f000000},
 726         {0x0f003050, 0x00000021},  /* flash/eeprom clock divisor which set the flash clock to 20 MHz */
 727         {0x0F00a084, 0x1Cffffff},  /* dump from here in internal memory */
 728         {0x0F00a080, 0x1C000000},
 729         {0x0F00A000, 0x00000016},
 730         {0x0f007000, 0x00010001},
 731         {0x0f007004, 0x01000000},
 732         {0x0f007008, 0x01000001},
 733         {0x0f00700c, 0x00000000},
 734         {0x0f007010, 0x01000000},
 735         {0x0f007014, 0x01000100},
 736         {0x0f007018, 0x01000000},
 737         {0x0f00701c, 0x01020000},
 738         {0x0f007020, 0x04020107},
 739         {0x0f007024, 0x00000007},
 740         {0x0f007028, 0x02020200},
 741         {0x0f00702c, 0x0204040a},
 742         {0x0f007030, 0x04000000},
 743         {0x0f007034, 0x00000002},
 744         {0x0f007038, 0x1d060200},
 745         {0x0f00703c, 0x1c22221d},
 746         {0x0f007040, 0x8A116600},
 747         {0x0f007044, 0x222d0800},
 748         {0x0f007048, 0x02690204},
 749         {0x0f00704c, 0x00000000},
 750         {0x0f007050, 0x0100001c},
 751         {0x0f007054, 0x00000000},
 752         {0x0f007058, 0x00000000},
 753         {0x0f00705c, 0x00000000},
 754         {0x0f007060, 0x000A15D6},
 755         {0x0f007064, 0x0000000A},
 756         {0x0f007068, 0x00000000},
 757         {0x0f00706c, 0x00000001},
 758         {0x0f007070, 0x00004000},
 759         {0x0f007074, 0x00000000},
 760         {0x0f007078, 0x00000000},
 761         {0x0f00707c, 0x00000000},
 762         {0x0f007080, 0x00000000},
 763         {0x0f007084, 0x00000000},
 764         {0x0f007088, 0x01000001},
 765         {0x0f00708c, 0x00000101},
 766         {0x0f007090, 0x00000000},
 767         {0x0f007094, 0x00010000},
 768         {0x0f007098, 0x00000000},
 769         {0x0F0070C8, 0x00000104},
 770         {0x0F007018, 0x01010000}
 771 };
 772
 773
 774 int ddr_init(struct bcm_mini_adapter *Adapter)
 775 {
 776         struct bcm_ddr_setting *psDDRSetting = NULL;
 777         ULONG RegCount = 0;
 778         UINT value = 0;
 779         UINT  uiResetValue = 0;
 780         UINT uiClockSetting = 0;
 781         int retval = STATUS_SUCCESS;
 782
 783         switch (Adapter->chip_id) {
 784         case 0xbece3200:
 785                 switch (Adapter->DDRSetting) {
 786                 case DDR_80_MHZ:
 787                         psDDRSetting = asT3LP_DDRSetting80MHz;
 788                         RegCount = (sizeof(asT3LP_DDRSetting80MHz)/
 789                         sizeof(struct bcm_ddr_setting));
 790                         break;
 791                 case DDR_100_MHZ:
 792                         psDDRSetting = asT3LP_DDRSetting100MHz;
 793                         RegCount = (sizeof(asT3LP_DDRSetting100MHz)/
 794                         sizeof(struct bcm_ddr_setting));
 795                         break;
 796                 case DDR_133_MHZ:
 797                         psDDRSetting = asT3LP_DDRSetting133MHz;
 798                         RegCount = (sizeof(asT3LP_DDRSetting133MHz)/
 799                         sizeof(struct bcm_ddr_setting));
 800                         if (Adapter->bMipsConfig == MIPS_200_MHZ)
 801                                 uiClockSetting = 0x03F13652;
 802                         else
 803                                 uiClockSetting = 0x03F1365B;
 804                         break;
 805                 default:
 806                         return -EINVAL;
 807                 }
 808
 809                 break;
 810         case T3LPB:
 811         case BCS220_2:
 812         case BCS220_2BC:
 813         case BCS250_BC:
 814         case BCS220_3:
 815                 /* Set bit 2 and bit 6 to 1 for BBIC 2mA drive
 816                  * (please check current value and additionally set these bits)
 817                  */
 818         if ((Adapter->chip_id !=  BCS220_2) &&
 819                 (Adapter->chip_id !=  BCS220_2BC) &&
 820                 (Adapter->chip_id != BCS220_3)) {
 821                 retval = rdmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
 822                 if (retval < 0) {
 823                         BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
 824                         return retval;
 825                 }
 826                 uiResetValue |= 0x44;
 827                 retval = wrmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
 828                 if (retval < 0) {
 829                         BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
 830                         return retval;
 831                 }
 832         }
 833                 switch (Adapter->DDRSetting) {
 834
 835
 836
 837                 case DDR_80_MHZ:
 838                         psDDRSetting = asT3LPB_DDRSetting80MHz;
 839                         RegCount = (sizeof(asT3B_DDRSetting80MHz)/
 840                         sizeof(struct bcm_ddr_setting));
 841                         break;
 842                 case DDR_100_MHZ:
 843                         psDDRSetting = asT3LPB_DDRSetting100MHz;
 844                         RegCount = (sizeof(asT3B_DDRSetting100MHz)/
 845                         sizeof(struct bcm_ddr_setting));
 846                         break;
 847                 case DDR_133_MHZ:
 848                         psDDRSetting = asT3LPB_DDRSetting133MHz;
 849                         RegCount = (sizeof(asT3B_DDRSetting133MHz)/
 850                         sizeof(struct bcm_ddr_setting));
 851
 852                         if (Adapter->bMipsConfig == MIPS_200_MHZ)
 853                                 uiClockSetting = 0x03F13652;
 854                         else
 855                                 uiClockSetting = 0x03F1365B;
 856                         break;
 857
 858                 case DDR_160_MHZ:
 859                         psDDRSetting = asT3LPB_DDRSetting160MHz;
 860                         RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(struct bcm_ddr_setting);
 861
 862                         if (Adapter->bMipsConfig == MIPS_200_MHZ)
 863                                 uiClockSetting = 0x03F137D2;
 864                         else
 865                                 uiClockSetting = 0x03F137DB;
 866                 }
 867                         break;
 868
 869         case 0xbece0110:
 870         case 0xbece0120:
 871         case 0xbece0121:
 872         case 0xbece0130:
 873         case 0xbece0300:
 874         BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "DDR Setting: %x\n", Adapter->DDRSetting);
 875                 switch (Adapter->DDRSetting) {
 876                 case DDR_80_MHZ:
 877                         psDDRSetting = asT3_DDRSetting80MHz;
 878                         RegCount = (sizeof(asT3_DDRSetting80MHz)/
 879                         sizeof(struct bcm_ddr_setting));
 880                         break;
 881                 case DDR_100_MHZ:
 882                         psDDRSetting = asT3_DDRSetting100MHz;
 883                         RegCount = (sizeof(asT3_DDRSetting100MHz)/
 884                         sizeof(struct bcm_ddr_setting));
 885                         break;
 886                 case DDR_133_MHZ:
 887                         psDDRSetting = asT3_DDRSetting133MHz;
 888                         RegCount = (sizeof(asT3_DDRSetting133MHz)/
 889                         sizeof(struct bcm_ddr_setting));
 890                         break;
 891                 default:
 892                         return -EINVAL;
 893                 }
 894         case 0xbece0310:
 895         {
 896                 switch (Adapter->DDRSetting) {
 897                 case DDR_80_MHZ:
 898                         psDDRSetting = asT3B_DDRSetting80MHz;
 899                         RegCount = (sizeof(asT3B_DDRSetting80MHz)/
 900                         sizeof(struct bcm_ddr_setting));
 901                         break;
 902                 case DDR_100_MHZ:
 903                         psDDRSetting = asT3B_DDRSetting100MHz;
 904                         RegCount = (sizeof(asT3B_DDRSetting100MHz)/
 905                         sizeof(struct bcm_ddr_setting));
 906                         break;
 907                 case DDR_133_MHZ:
 908
 909                         if (Adapter->bDPLLConfig == PLL_266_MHZ) {  /* 266Mhz PLL selected. */
 910                                 memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
 911                                 sizeof(asDPLL_266MHZ));
 912                                 psDDRSetting = asT3B_DDRSetting133MHz;
 913                                 RegCount = (sizeof(asT3B_DDRSetting133MHz)/
 914                                 sizeof(struct bcm_ddr_setting));
 915                         } else {
 916                                 psDDRSetting = asT3B_DDRSetting133MHz;
 917                                 RegCount = (sizeof(asT3B_DDRSetting133MHz)/
 918                                 sizeof(struct bcm_ddr_setting));
 919                                 if (Adapter->bMipsConfig == MIPS_200_MHZ)
 920                                         uiClockSetting = 0x07F13652;
 921                                 else
 922                                         uiClockSetting = 0x07F1365B;
 923                         }
 924                         break;
 925                 default:
 926                         return -EINVAL;
 927                 }
 928                 break;
 929
 930         }
 931         default:
 932                 return -EINVAL;
 933         }
 934
 935         value = 0;
 936         BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "Register Count is =%lu\n", RegCount);
 937         while (RegCount && !retval) {
 938                 if (uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
 939                         value = uiClockSetting;
 940                 else
 941                         value = psDDRSetting->ulRegValue;
 942                 retval = wrmalt(Adapter, psDDRSetting->ulRegAddress, &value, sizeof(value));
 943                 if (STATUS_SUCCESS != retval) {
 944                         BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__);
 945                         break;
 946                 }
 947
 948                 RegCount--;
 949                 psDDRSetting++;
 950         }
 951
 952         if (Adapter->chip_id >= 0xbece3300) {
 953
 954                 mdelay(3);
 955                 if ((Adapter->chip_id != BCS220_2) &&
 956                         (Adapter->chip_id != BCS220_2BC) &&
 957                         (Adapter->chip_id != BCS220_3)) {
 958                         /* drive MDDR to half in case of UMA-B: */
 959                         uiResetValue = 0x01010001;
 960                         retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
 961                         if (retval < 0) {
 962                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
 963                                 return retval;
 964                         }
 965                         uiResetValue = 0x00040020;
 966                         retval = wrmalt(Adapter, (UINT)0x0F007094, &uiResetValue, sizeof(uiResetValue));
 967                         if (retval < 0) {
 968                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
 969                                 return retval;
 970                         }
 971                         uiResetValue = 0x01020101;
 972                         retval = wrmalt(Adapter, (UINT)0x0F00701c, &uiResetValue, sizeof(uiResetValue));
 973                         if (retval < 0) {
 974                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
 975                                 return retval;
 976                         }
 977                         uiResetValue = 0x01010000;
 978                         retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
 979                         if (retval < 0) {
 980                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
 981                                 return retval;
 982                         }
 983                 }
 984                 mdelay(3);
 985
 986                 /* DC/DC standby change...
 987                  * This is to be done only for Hybrid PMU mode.
 988                  * with the current h/w there is no way to detect this.
 989                  * and since we dont have internal PMU lets do it under UMA-B chip id.
 990                  * we will change this when we will have internal PMU.
 991                  */
 992                 if (Adapter->PmuMode == HYBRID_MODE_7C) {
 993                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
 994                         if (retval < 0) {
 995                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
 996                                 return retval;
 997                         }
 998                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
 999                         if (retval < 0) {
1000                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1001                                 return retval;
1002                         }
1003                         uiResetValue = 0x1322a8;
1004                         retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
1005                         if (retval < 0) {
1006                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1007                                 return retval;
1008                         }
1009                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1010                         if (retval < 0) {
1011                                 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1012                                 return retval;
1013                         }
1014                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1015                         if (retval < 0) {
1016                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1017                                 return retval;
1018                         }
1019                         uiResetValue = 0x132296;
1020                         retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
1021                         if (retval < 0) {
1022                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1023                                 return retval;
1024                         }
1025                 } else if (Adapter->PmuMode == HYBRID_MODE_6) {
1026
1027                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1028                         if (retval < 0) {
1029                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1030                                 return retval;
1031                         }
1032                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1033                         if (retval < 0) {
1034                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1035                                 return retval;
1036                         }
1037                         uiResetValue = 0x6003229a;
1038                         retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
1039                         if (retval < 0) {
1040                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1041                                 return retval;
1042                         }
1043                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1044                         if (retval < 0) {
1045                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1046                                 return retval;
1047                         }
1048                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1049                         if (retval < 0) {
1050                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1051                                 return retval;
1052                         }
1053                         uiResetValue = 0x1322a8;
1054                         retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
1055                         if (retval < 0) {
1056                                 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__);
1057                                 return retval;
1058                         }
1059                 }
1060
1061         }
1062         Adapter->bDDRInitDone = TRUE;
1063         return retval;
1064 }
1065
1066 int download_ddr_settings(struct bcm_mini_adapter *Adapter)
1067 {
1068         struct bcm_ddr_setting *psDDRSetting = NULL;
1069         ULONG RegCount = 0;
1070         unsigned long ul_ddr_setting_load_addr = DDR_DUMP_INTERNAL_DEVICE_MEMORY;
1071         UINT  value = 0;
1072         int retval = STATUS_SUCCESS;
1073         bool bOverrideSelfRefresh = false;
1074
1075         switch (Adapter->chip_id) {
1076         case 0xbece3200:
1077                 switch (Adapter->DDRSetting) {
1078                 case DDR_80_MHZ:
1079                         psDDRSetting = asT3LP_DDRSetting80MHz;
1080                         RegCount = ARRAY_SIZE(asT3LP_DDRSetting80MHz);
1081                         RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1082                         psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1083                         break;
1084                 case DDR_100_MHZ:
1085                         psDDRSetting = asT3LP_DDRSetting100MHz;
1086                         RegCount = ARRAY_SIZE(asT3LP_DDRSetting100MHz);
1087                         RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1088                         psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1089                         break;
1090                 case DDR_133_MHZ:
1091                         bOverrideSelfRefresh = TRUE;
1092                         psDDRSetting = asT3LP_DDRSetting133MHz;
1093                         RegCount = ARRAY_SIZE(asT3LP_DDRSetting133MHz);
1094                         RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1095                         psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1096                         break;
1097                         default:
1098                             return -EINVAL;
1099                 }
1100                 break;
1101
1102         case T3LPB:
1103         case BCS220_2:
1104         case BCS220_2BC:
1105         case BCS250_BC:
1106         case BCS220_3:
1107                 switch (Adapter->DDRSetting) {
1108                 case DDR_80_MHZ:
1109                         psDDRSetting = asT3LPB_DDRSetting80MHz;
1110                         RegCount = ARRAY_SIZE(asT3LPB_DDRSetting80MHz);
1111                         RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1112                         psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1113                         break;
1114                 case DDR_100_MHZ:
1115                         psDDRSetting = asT3LPB_DDRSetting100MHz;
1116                         RegCount = ARRAY_SIZE(asT3LPB_DDRSetting100MHz);
1117                         RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1118                         psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1119                         break;
1120                 case DDR_133_MHZ:
1121                         bOverrideSelfRefresh = TRUE;
1122                         psDDRSetting = asT3LPB_DDRSetting133MHz;
1123                         RegCount = ARRAY_SIZE(asT3LPB_DDRSetting133MHz);
1124                         RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1125                         psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1126                         break;
1127
1128                 case DDR_160_MHZ:
1129                         bOverrideSelfRefresh = TRUE;
1130                         psDDRSetting = asT3LPB_DDRSetting160MHz;
1131                         RegCount = ARRAY_SIZE(asT3LPB_DDRSetting160MHz);
1132                         RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1133                         psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1134
1135                         break;
1136                 default:
1137                         return -EINVAL;
1138                 }
1139                 break;
1140         case 0xbece0300:
1141                 switch (Adapter->DDRSetting) {
1142                 case DDR_80_MHZ:
1143                         psDDRSetting = asT3_DDRSetting80MHz;
1144                         RegCount = ARRAY_SIZE(asT3_DDRSetting80MHz);
1145                         RegCount -= T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1146                         psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1147                         break;
1148                 case DDR_100_MHZ:
1149                         psDDRSetting = asT3_DDRSetting100MHz;
1150                         RegCount = ARRAY_SIZE(asT3_DDRSetting100MHz);
1151                         RegCount -= T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1152                         psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1153                         break;
1154                 case DDR_133_MHZ:
1155                         psDDRSetting = asT3_DDRSetting133MHz;
1156                         RegCount = ARRAY_SIZE(asT3_DDRSetting133MHz);
1157                         RegCount -= T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1158                         psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1159                         break;
1160                 default:
1161                         return -EINVAL;
1162                 }
1163         break;
1164         case 0xbece0310:
1165             {
1166                 switch (Adapter->DDRSetting) {
1167                 case DDR_80_MHZ:
1168                         psDDRSetting = asT3B_DDRSetting80MHz;
1169                         RegCount = ARRAY_SIZE(asT3B_DDRSetting80MHz);
1170                         RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1171                         psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1172                         break;
1173                 case DDR_100_MHZ:
1174                         psDDRSetting = asT3B_DDRSetting100MHz;
1175                         RegCount = ARRAY_SIZE(asT3B_DDRSetting100MHz);
1176                         RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1177                         psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1178                         break;
1179                 case DDR_133_MHZ:
1180                         bOverrideSelfRefresh = TRUE;
1181                         psDDRSetting = asT3B_DDRSetting133MHz;
1182                         RegCount = ARRAY_SIZE(asT3B_DDRSetting133MHz);
1183                         RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1184                         psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1185                 break;
1186                 }
1187                 break;
1188              }
1189         default:
1190                 return -EINVAL;
1191         }
1192         /* total number of Register that has to be dumped */
1193         value = RegCount;
1194         retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1195         if (retval) {
1196                 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__);
1197
1198                 return retval;
1199         }
1200         ul_ddr_setting_load_addr += sizeof(ULONG);
1201         /* signature */
1202         value = (0x1d1e0dd0);
1203         retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1204         if (retval) {
1205                 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__);
1206                 return retval;
1207         }
1208
1209         ul_ddr_setting_load_addr += sizeof(ULONG);
1210         RegCount *= (sizeof(struct bcm_ddr_setting)/sizeof(ULONG));
1211
1212         while (RegCount && !retval) {
1213                 value = psDDRSetting->ulRegAddress;
1214                 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1215                 ul_ddr_setting_load_addr += sizeof(ULONG);
1216                 if (!retval) {
1217                         if (bOverrideSelfRefresh && (psDDRSetting->ulRegAddress == 0x0F007018)) {
1218                                 value = (psDDRSetting->ulRegValue |(1<<8));
1219                         if (STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr,
1220                                 &value, sizeof(value))) {
1221                                 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__);
1222                                 break;
1223                         }
1224                         } else {
1225                                 value =  psDDRSetting->ulRegValue;
1226
1227                                 if (STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr ,
1228                                         &value, sizeof(value))) {
1229                                         BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__);
1230                                         break;
1231                                 }
1232                         }
1233                 }
1234                 ul_ddr_setting_load_addr += sizeof(ULONG);
1235                 RegCount--;
1236                 psDDRSetting++;
1237         }
1238                 return retval;
1239 }