1 /***********************************
3 ************************************/
7 #define MAX_FRAGMENTEDIP_CLASSIFICATION_ENTRIES 256
16 typedef struct _LEADER LEADER, *PLEADER;
18 struct _PACKETTOSEND {
22 typedef struct _PACKETTOSEND PACKETTOSEND, *PPACKETTOSEND;
24 struct _CONTROL_PACKET {
27 struct _CONTROL_PACKET *next;
29 typedef struct _CONTROL_PACKET CONTROL_PACKET, *PCONTROL_PACKET;
35 typedef struct link_request LINK_REQUEST, *PLINK_REQUEST;
37 /* classification extension is added */
38 typedef struct _ADD_CONNECTION {
39 ULONG SrcIpAddressCount;
40 ULONG SrcIpAddress[MAX_CONNECTIONS];
41 ULONG SrcIpMask[MAX_CONNECTIONS];
43 ULONG DestIpAddressCount;
44 ULONG DestIpAddress[MAX_CONNECTIONS];
45 ULONG DestIpMask[MAX_CONNECTIONS];
55 } ADD_CONNECTION, *PADD_CONNECTION;
57 typedef struct _CLASSIFICATION_RULE {
59 UCHAR ucIPSrcAddr[32];
60 UCHAR ucIPDestAddrLen;
61 UCHAR ucIPDestAddr[32];
62 UCHAR ucSrcPortRangeLen;
63 UCHAR ucSrcPortRange[4];
64 UCHAR ucDestPortRangeLen;
65 UCHAR ucDestPortRange[4];
67 } CLASSIFICATION_RULE, *PCLASSIFICATION_RULE;
69 typedef struct _CLASSIFICATION_ONLY {
76 UCHAR ucDestinationAddress[16];
77 } CLASSIFICATION_ONLY, *PCLASSIFICATION_ONLY;
79 #define MAX_IP_RANGE_LENGTH 4
80 #define MAX_PORT_RANGE 4
81 #define MAX_PROTOCOL_LENGTH 32
82 #define IPV6_ADDRESS_SIZEINBYTES 0x10
84 typedef union _U_IP_ADDRESS {
86 ULONG ulIpv4Addr[MAX_IP_RANGE_LENGTH]; /* Source Ip Address Range */
87 ULONG ulIpv4Mask[MAX_IP_RANGE_LENGTH]; /* Source Ip Mask Address Range */
90 ULONG ulIpv6Addr[MAX_IP_RANGE_LENGTH * 4]; /* Source Ip Address Range */
91 ULONG ulIpv6Mask[MAX_IP_RANGE_LENGTH * 4]; /* Source Ip Mask Address Range */
94 UCHAR ucIpv4Address[MAX_IP_RANGE_LENGTH * IP_LENGTH_OF_ADDRESS];
95 UCHAR ucIpv4Mask[MAX_IP_RANGE_LENGTH * IP_LENGTH_OF_ADDRESS];
98 UCHAR ucIpv6Address[MAX_IP_RANGE_LENGTH * IPV6_ADDRESS_SIZEINBYTES];
99 UCHAR ucIpv6Mask[MAX_IP_RANGE_LENGTH * IPV6_ADDRESS_SIZEINBYTES];
104 typedef struct _S_HDR_SUPRESSION_CONTEXTINFO {
105 UCHAR ucaHdrSupressionInBuf[MAX_PHS_LENGTHS]; /* Intermediate buffer to accumulate pkt Header for PHS */
106 UCHAR ucaHdrSupressionOutBuf[MAX_PHS_LENGTHS + PHSI_LEN]; /* Intermediate buffer containing pkt Header after PHS */
107 } S_HDR_SUPRESSION_CONTEXTINFO;
109 typedef struct _S_CLASSIFIER_RULE {
112 B_UINT16 uiClassifierRuleIndex;
115 B_UINT8 u8ClassifierRulePriority; /* This field detemines the Classifier Priority */
116 U_IP_ADDRESS stSrcIpAddress;
117 UCHAR ucIPSourceAddressLength; /* Ip Source Address Length */
119 U_IP_ADDRESS stDestIpAddress;
120 UCHAR ucIPDestinationAddressLength; /* Ip Destination Address Length */
121 UCHAR ucIPTypeOfServiceLength; /* Type of service Length */
122 UCHAR ucTosLow; /* Tos Low */
123 UCHAR ucTosHigh; /* Tos High */
124 UCHAR ucTosMask; /* Tos Mask */
126 UCHAR ucProtocolLength; /* protocol Length */
127 UCHAR ucProtocol[MAX_PROTOCOL_LENGTH]; /* protocol Length */
128 USHORT usSrcPortRangeLo[MAX_PORT_RANGE];
129 USHORT usSrcPortRangeHi[MAX_PORT_RANGE];
130 UCHAR ucSrcPortRangeLength;
132 USHORT usDestPortRangeLo[MAX_PORT_RANGE];
133 USHORT usDestPortRangeHi[MAX_PORT_RANGE];
134 UCHAR ucDestPortRangeLength;
136 BOOLEAN bProtocolValid;
138 BOOLEAN bDestIpValid;
141 /* For IPv6 Addressing */
143 BOOLEAN bIpv6Protocol;
146 UCHAR u8AssociatedPHSI;
148 /* Classification fields for ETH CS */
149 UCHAR ucEthCSSrcMACLen;
150 UCHAR au8EThCSSrcMAC[MAC_ADDRESS_SIZE];
151 UCHAR au8EThCSSrcMACMask[MAC_ADDRESS_SIZE];
152 UCHAR ucEthCSDestMACLen;
153 UCHAR au8EThCSDestMAC[MAC_ADDRESS_SIZE];
154 UCHAR au8EThCSDestMACMask[MAC_ADDRESS_SIZE];
155 UCHAR ucEtherTypeLen;
156 UCHAR au8EthCSEtherType[NUM_ETHERTYPE_BYTES];
157 UCHAR usUserPriority[2];
159 USHORT usValidityBitMap;
161 /* typedef struct _S_CLASSIFIER_RULE S_CLASSIFIER_RULE; */
163 typedef struct _S_FRAGMENTED_PACKET_INFO {
165 ULONG ulSrcIpAddress;
166 USHORT usIpIdentification;
167 S_CLASSIFIER_RULE *pstMatchedClassifierEntry;
168 BOOLEAN bOutOfOrderFragment;
169 } S_FRAGMENTED_PACKET_INFO, *PS_FRAGMENTED_PACKET_INFO;
171 struct _packet_info {
172 /* classification extension Rule */
176 /* This field determines the priority of the SF Queues */
177 B_UINT8 u8TrafficPriority;
181 BOOLEAN bActivateRequestSent;
183 B_UINT8 u8QueueType; /* BE or rtPS */
185 UINT uiMaxBucketSize; /* maximum size of the bucket for the queue */
186 UINT uiCurrentQueueDepthOnTarget;
187 UINT uiCurrentBytesOnHost;
188 UINT uiCurrentPacketsOnHost;
189 UINT uiDroppedCountBytes;
190 UINT uiDroppedCountPackets;
193 UINT uiCurrentDrainRate;
194 UINT uiThisPeriodSentBytes;
195 LARGE_INTEGER liDrainCalculated;
196 UINT uiCurrentTokenCount;
197 LARGE_INTEGER liLastUpdateTokenAt;
198 UINT uiMaxAllowedRate;
199 UINT NumOfPacketsSent;
202 S_MIBS_EXTSERVICEFLOW_PARAMETERS stMibsExtServiceFlowTable;
203 UINT uiCurrentRxRate;
204 UINT uiThisPeriodRxBytes;
212 struct sk_buff *FirstTxQueue;
213 struct sk_buff *LastTxQueue;
216 struct sk_buff *ControlHead;
217 struct sk_buff *ControlTail;
221 BOOLEAN bProtocolValid;
223 BOOLEAN bDestIpValid;
227 BOOLEAN bAdmittedSet;
228 BOOLEAN bAuthorizedSet;
229 BOOLEAN bClassifierPriority;
230 UCHAR ucServiceClassName[MAX_CLASS_NAME_LENGTH];
231 BOOLEAN bHeaderSuppressionEnabled;
232 spinlock_t SFQueueLock;
233 void *pstSFIndication;
234 struct timeval stLastUpdateTokenAt;
235 atomic_t uiPerSFTxResourceCount;
240 typedef struct _packet_info PacketInfo;
242 typedef struct _PER_TARANG_DATA {
243 struct _PER_TARANG_DATA *next;
244 struct _MINI_ADAPTER *Adapter;
245 struct sk_buff *RxAppControlHead;
246 struct sk_buff *RxAppControlTail;
247 volatile INT AppCtrlQueueLen;
248 BOOLEAN MacTracingEnabled;
249 BOOLEAN bApplicationToExit;
250 S_MIBS_DROPPED_APP_CNTRL_MESSAGES stDroppedAppCntrlMsgs;
251 ULONG RxCntrlMsgBitMask;
252 } PER_TARANG_DATA, *PPER_TARANG_DATA;
255 typedef struct _TARGET_PARAMS {
256 B_UINT32 m_u32CfgVersion;
258 /* Scanning Related Params */
259 B_UINT32 m_u32CenterFrequency;
260 B_UINT32 m_u32BandAScan;
261 B_UINT32 m_u32BandBScan;
262 B_UINT32 m_u32BandCScan;
265 B_UINT32 m_u32minGrantsize; /* size of minimum grant is 0 or 6 */
266 B_UINT32 m_u32PHSEnable;
269 B_UINT32 m_u32HoEnable;
270 B_UINT32 m_u32HoReserved1;
271 B_UINT32 m_u32HoReserved2;
273 /* Power Control Params */
274 B_UINT32 m_u32MimoEnable;
275 B_UINT32 m_u32SecurityEnable;
277 * bit 1: 1 Idlemode enable;
278 * bit 2: 1 Sleepmode Enable
280 B_UINT32 m_u32PowerSavingModesEnable;
281 /* PowerSaving Mode Options:
282 * bit 0 = 1: CPE mode - to keep pcmcia if alive;
283 * bit 1 = 1: CINR reporing in Idlemode Msg
284 * bit 2 = 1: Default PSC Enable in sleepmode
286 B_UINT32 m_u32PowerSavingModeOptions;
288 B_UINT32 m_u32ArqEnable;
290 /* From Version #3, the HARQ section renamed as general */
291 B_UINT32 m_u32HarqEnable;
292 /* EEPROM Param Location */
293 B_UINT32 m_u32EEPROMFlag;
294 /* BINARY TYPE - 4th MSByte:
295 * Interface Type - 3rd MSByte:
296 * Vendor Type - 2nd MSByte
298 /* Unused - LSByte */
299 B_UINT32 m_u32Customize;
300 B_UINT32 m_u32ConfigBW; /* In Hz */
301 B_UINT32 m_u32ShutDownTimer;
302 B_UINT32 m_u32RadioParameter;
303 B_UINT32 m_u32PhyParameter1;
304 B_UINT32 m_u32PhyParameter2;
305 B_UINT32 m_u32PhyParameter3;
307 /* in eval mode only;
308 * lower 16bits = basic cid for testing;
309 * then bit 16 is test cqich,
310 * bit 17 test init rang;
311 * bit 18 test periodic rang
312 * bit 19 is test harq ack/nack
314 B_UINT32 m_u32TestOptions;
315 B_UINT32 m_u32MaxMACDataperDLFrame;
316 B_UINT32 m_u32MaxMACDataperULFrame;
317 B_UINT32 m_u32Corr2MacFlags;
319 /* adding driver params. */
320 B_UINT32 HostDrvrConfig1;
321 B_UINT32 HostDrvrConfig2;
322 B_UINT32 HostDrvrConfig3;
323 B_UINT32 HostDrvrConfig4;
324 B_UINT32 HostDrvrConfig5;
325 B_UINT32 HostDrvrConfig6;
326 B_UINT32 m_u32SegmentedPUSCenable;
328 /* BAMC enable - but 4.x does not support this feature
329 * This is added just to sync 4.x and 5.x CFGs
331 B_UINT32 m_u32BandAMCEnable;
332 } STARGETPARAMS, *PSTARGETPARAMS;
335 typedef struct _STTARGETDSXBUFFER {
336 ULONG ulTargetDsxBuffer;
339 } STTARGETDSXBUFFER, *PSTTARGETDSXBUFFER;
341 typedef INT (*FP_FLASH_WRITE)(struct _MINI_ADAPTER *, UINT, PVOID);
343 typedef INT (*FP_FLASH_WRITE_STATUS)(struct _MINI_ADAPTER *, UINT, PVOID);
346 * Driver adapter data structure
348 struct _MINI_ADAPTER {
349 struct _MINI_ADAPTER *next;
350 struct net_device *dev;
353 atomic_t ApplicationRunning;
354 volatile INT CtrlQueueLen;
355 atomic_t AppCtrlQueueLen;
356 BOOLEAN AppCtrlQueueOverFlow;
357 atomic_t CurrentApplicationCount;
358 atomic_t RegisteredApplicationCount;
359 BOOLEAN LinkUpStatus;
361 u32 StatisticsPointer;
362 struct sk_buff *RxControlHead;
363 struct sk_buff *RxControlTail;
364 struct semaphore RxAppControlQueuelock;
365 struct semaphore fw_download_sema;
366 PPER_TARANG_DATA pTarangs;
367 spinlock_t control_queue_lock;
368 wait_queue_head_t process_read_wait_queue;
370 /* the pointer to the first packet we have queued in send
371 * deserialized miniport support variables
373 atomic_t TotalPacketCount;
376 /* this to keep track of the Tx and Rx MailBox Registers. */
377 atomic_t CurrNumFreeTxDesc;
378 /* to keep track the no of byte received */
379 USHORT PrevNumRecvDescs;
380 USHORT CurrNumRecvDescs;
382 PacketInfo PackInfo[NO_OF_QUEUES];
383 S_CLASSIFIER_RULE astClassifierTable[MAX_CLASSIFIERS];
384 BOOLEAN TransferMode;
386 /*************** qos ******************/
387 BOOLEAN bETHCSEnabled;
389 ULONG rtPSBucketSize;
396 wait_queue_head_t tx_packet_wait_queue;
397 wait_queue_head_t process_rx_cntrlpkt;
398 atomic_t process_waiting;
399 BOOLEAN fw_download_done;
401 char *txctlpacket[MAX_CNTRL_PKTS];
402 atomic_t cntrlpktCnt ;
403 atomic_t index_app_read_cntrlpkt;
404 atomic_t index_wr_txcntrlpkt;
405 atomic_t index_rd_txcntrlpkt;
407 struct semaphore rdmwrmsync;
409 STTARGETDSXBUFFER astTargetDsxBuffer[MAX_TARGET_DSX_BUFFERS];
410 ULONG ulFreeTargetBufferCnt;
411 ULONG ulCurrentTargetBuffer;
412 ULONG ulTotalTargetBuffersAvailable;
413 unsigned long chip_id;
414 wait_queue_head_t lowpower_mode_wait_queue;
416 BOOLEAN bBinDownloaded;
417 BOOLEAN bCfgDownloaded;
418 BOOLEAN bSyncUpRequestSent;
419 USHORT usBestEffortQueueIndex;
420 wait_queue_head_t ioctl_fw_dnld_wait_queue;
421 BOOLEAN waiting_to_fw_download_done;
422 pid_t fw_download_process_pid;
423 PSTARGETPARAMS pstargetparams;
424 BOOLEAN device_removed;
425 BOOLEAN DeviceAccess;
426 BOOLEAN bIsAutoCorrectEnabled;
427 BOOLEAN bDDRInitDone;
429 ULONG ulPowerSaveMode;
430 spinlock_t txtransmitlock;
431 B_UINT8 txtransmit_running;
432 /* Thread for control packet handling */
433 struct task_struct *control_packet_handler;
434 /* thread for transmitting packets. */
435 struct task_struct *transmit_packet_thread;
437 /* LED Related Structures */
438 LED_INFO_STRUCT LEDInfo;
440 /* Driver State for LED Blinking */
441 LedEventInfo_t DriverState;
442 /* Interface Specific */
443 PVOID pvInterfaceAdapter;
444 int (*bcm_file_download)(PVOID,
447 int (*bcm_file_readback_from_chip)(PVOID,
450 INT (*interface_rdm)(PVOID,
454 INT (*interface_wrm)(PVOID,
458 int (*interface_transmit)(PVOID, PVOID , UINT);
460 BOOLEAN bDregRequestSentInIdleMode;
461 BOOLEAN bTriedToWakeUpFromlowPowerMode;
463 BOOLEAN bWakeUpDevice;
464 unsigned int usIdleModePattern;
465 /* BOOLEAN bTriedToWakeUpFromShutdown; */
466 BOOLEAN bLinkDownRequested;
468 PHS_DEVICE_EXTENSION stBCMPhsContext;
469 S_HDR_SUPRESSION_CONTEXTINFO stPhsTxContextInfo;
470 uint8_t ucaPHSPktRestoreBuf[2048];
475 UINT32 aTxPktSizeHist[MIBS_MAX_HIST_ENTRIES];
476 UINT32 aRxPktSizeHist[MIBS_MAX_HIST_ENTRIES];
477 S_FRAGMENTED_PACKET_INFO astFragmentedPktClassifierTable[MAX_FRAGMENTEDIP_CLASSIFICATION_ENTRIES];
482 UINT uiSectorSizeInCFG;
483 BOOLEAN bSectorSizeOverride;
484 BOOLEAN bStatusWrite;
486 UINT uiVendorExtnFlag;
487 /* it will always represent chosen DSD at any point of time.
488 * Generally it is Active DSD but in case of NVM RD/WR it might be different.
490 UINT ulFlashCalStart;
491 ULONG ulFlashControlSectionStart;
492 ULONG ulFlashWriteSize;
494 FP_FLASH_WRITE fpFlashWrite;
495 FP_FLASH_WRITE_STATUS fpFlashWriteWithStatusCheck;
497 struct semaphore NVMRdmWrmLock;
498 struct device *pstCreatedClassDevice;
500 /* BOOLEAN InterfaceUpStatus; */
501 PFLASH2X_CS_INFO psFlash2xCSInfo;
502 PFLASH_CS_INFO psFlashCSInfo;
503 PFLASH2X_VENDORSPECIFIC_INFO psFlash2xVendorInfo;
504 UINT uiFlashBaseAdd; /* Flash start address */
505 UINT uiActiveISOOffset; /* Active ISO offset chosen before f/w download */
506 FLASH2X_SECTION_VAL eActiveISO; /* Active ISO section val */
507 FLASH2X_SECTION_VAL eActiveDSD; /* Active DSD val chosen before f/w download */
508 UINT uiActiveDSDOffsetAtFwDld; /* For accessing Active DSD chosen before f/w download */
509 UINT uiFlashLayoutMajorVersion;
510 UINT uiFlashLayoutMinorVersion;
511 BOOLEAN bAllDSDWriteAllow;
512 BOOLEAN bSigCorrupted;
513 /* this should be set who so ever want to change the Headers. after Wrtie it should be reset immediately. */
514 BOOLEAN bHeaderChangeAllowed;
516 BOOLEAN bEndPointHalted;
517 /* while bFlashRawRead will be true, Driver ignore map lay out and consider flash as of without any map. */
518 BOOLEAN bFlashRawRead;
519 BOOLEAN bPreparingForLowPowerMode;
522 BOOLEAN StopAllXaction;
523 UINT32 liTimeSinceLastNetEntry; /* Used to Support extended CAPI requirements from */
524 struct semaphore LowPowerModeSync;
525 ULONG liDrainCalculated;
527 S_BCM_DEBUG_STATE stDebugState;
529 typedef struct _MINI_ADAPTER MINI_ADAPTER, *PMINI_ADAPTER;
531 #define GET_BCM_ADAPTER(net_dev) netdev_priv(net_dev)
533 struct _ETH_HEADER_STRUC {
534 UCHAR au8DestinationAddress[6];
535 UCHAR au8SourceAddress[6];
538 typedef struct _ETH_HEADER_STRUC ETH_HEADER_STRUC, *PETH_HEADER_STRUC;
540 typedef struct FirmwareInfo {
541 void __user *pvMappedFirmwareAddress;
542 ULONG u32FirmwareLength;
543 ULONG u32StartingAddress;
544 } __packed FIRMWARE_INFO, *PFIRMWARE_INFO;
546 /* holds the value of net_device structure.. */
547 extern struct net_device *gblpnetdev;
548 typedef struct _cntl_pkt {
549 PMINI_ADAPTER Adapter;
552 typedef LINK_REQUEST CONTROL_MESSAGE;
554 typedef struct _DDR_SETTING {
557 } DDR_SETTING, *PDDR_SETTING;
558 typedef DDR_SETTING DDR_SET_NODE, *PDDR_SET_NODE;
559 INT InitAdapter(PMINI_ADAPTER psAdapter);
561 /* =====================================================================
562 * Beceem vendor request codes for EP0
563 * =====================================================================
566 #define BCM_REQUEST_READ 0x2
567 #define BCM_REQUEST_WRITE 0x1
568 #define EP2_MPS_REG 0x0F0110A0
571 #define EP2_CFG_REG 0x0F0110A8
572 #define EP2_CFG_INT 0x27
573 #define EP2_CFG_BULK 0x25
575 #define EP4_MPS_REG 0x0F0110F0
578 #define EP4_CFG_REG 0x0F0110F8
580 #define ISO_MPS_REG 0x0F0110C8
581 #define ISO_MPS 0x00000000
590 typedef enum eInterface_setting {
591 DEFAULT_SETTING_0 = 0,
592 ALTERNATE_SETTING_1 = 1,
595 #endif /* __ADAPTER_H__ */