2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h>
13 #include <linux/delay.h>
14 #include <linux/ssb/ssb_embedded.h>
16 #include "ssb_private.h"
20 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
22 return ssb_read32(pc->dev, offset);
26 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
28 ssb_write32(pc->dev, offset, value);
32 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
34 return ssb_read16(pc->dev, offset);
38 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
40 ssb_write16(pc->dev, offset, value);
43 /**************************************************
44 * Code for hostmode operation.
45 **************************************************/
47 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
49 #include <asm/paccess.h>
50 /* Probe a 32bit value on the bus and catch bus exceptions.
51 * Returns nonzero on a bus exception.
52 * This is MIPS specific */
53 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
55 /* Assume one-hot slot wiring */
56 #define SSB_PCI_SLOT_MAX 16
58 /* Global lock is OK, as we won't have more than one extpci anyway. */
59 static DEFINE_SPINLOCK(cfgspace_lock);
60 /* Core to access the external PCI config space. Can only have one. */
61 static struct ssb_pcicore *extpci_core;
64 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
65 unsigned int bus, unsigned int dev,
66 unsigned int func, unsigned int off)
71 /* We do only have one cardbus device behind the bridge. */
72 if (pc->cardbusmode && (dev >= 1))
76 /* Type 0 transaction */
77 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
79 /* Slide the window */
80 tmp = SSB_PCICORE_SBTOPCI_CFG0;
81 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
82 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
83 /* Calculate the address */
85 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
89 /* Type 1 transaction */
90 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
91 SSB_PCICORE_SBTOPCI_CFG1);
92 /* Calculate the address */
103 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
104 unsigned int bus, unsigned int dev,
105 unsigned int func, unsigned int off,
112 SSB_WARN_ON(!pc->hostmode);
113 if (unlikely(len != 1 && len != 2 && len != 4))
115 addr = get_cfgspace_addr(pc, bus, dev, func, off);
119 mmio = ioremap_nocache(addr, len);
123 if (mips_busprobe32(val, mmio)) {
129 val >>= (8 * (off & 3));
133 *((u8 *)buf) = (u8)val;
136 *((u16 *)buf) = (u16)val;
139 *((u32 *)buf) = (u32)val;
149 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
150 unsigned int bus, unsigned int dev,
151 unsigned int func, unsigned int off,
152 const void *buf, int len)
158 SSB_WARN_ON(!pc->hostmode);
159 if (unlikely(len != 1 && len != 2 && len != 4))
161 addr = get_cfgspace_addr(pc, bus, dev, func, off);
165 mmio = ioremap_nocache(addr, len);
169 if (mips_busprobe32(val, mmio)) {
177 val &= ~(0xFF << (8 * (off & 3)));
178 val |= *((const u8 *)buf) << (8 * (off & 3));
182 val &= ~(0xFFFF << (8 * (off & 3)));
183 val |= *((const u16 *)buf) << (8 * (off & 3));
186 val = *((const u32 *)buf);
198 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
199 int reg, int size, u32 *val)
204 spin_lock_irqsave(&cfgspace_lock, flags);
205 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
206 PCI_FUNC(devfn), reg, val, size);
207 spin_unlock_irqrestore(&cfgspace_lock, flags);
209 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
212 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
213 int reg, int size, u32 val)
218 spin_lock_irqsave(&cfgspace_lock, flags);
219 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
220 PCI_FUNC(devfn), reg, &val, size);
221 spin_unlock_irqrestore(&cfgspace_lock, flags);
223 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
226 static struct pci_ops ssb_pcicore_pciops = {
227 .read = ssb_pcicore_read_config,
228 .write = ssb_pcicore_write_config,
231 static struct resource ssb_pcicore_mem_resource = {
232 .name = "SSB PCIcore external memory",
233 .start = SSB_PCI_DMA,
234 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
235 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
238 static struct resource ssb_pcicore_io_resource = {
239 .name = "SSB PCIcore external I/O",
242 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
245 static struct pci_controller ssb_pcicore_controller = {
246 .pci_ops = &ssb_pcicore_pciops,
247 .io_resource = &ssb_pcicore_io_resource,
248 .mem_resource = &ssb_pcicore_mem_resource,
251 /* This function is called when doing a pci_enable_device().
252 * We must first check if the device is a device on the PCI-core bridge. */
253 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
255 if (d->bus->ops != &ssb_pcicore_pciops) {
256 /* This is not a device on the PCI-core bridge. */
260 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
263 /* Fix up interrupt lines */
264 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
265 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
270 /* Early PCI fixup for a device on the PCI-core bridge. */
271 static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
275 if (dev->bus->ops != &ssb_pcicore_pciops) {
276 /* This is not a device on the PCI-core bridge. */
279 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
282 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
284 /* Enable PCI bridge bus mastering and memory space */
286 if (pcibios_enable_device(dev, ~0) < 0) {
287 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
291 /* Enable PCI bridge BAR1 prefetch and burst */
292 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
294 /* Make sure our latency is high enough to handle the devices behind us */
296 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
298 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
300 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
302 /* PCI device IRQ mapping. */
303 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
305 if (dev->bus->ops != &ssb_pcicore_pciops) {
306 /* This is not a device on the PCI-core bridge. */
309 return ssb_mips_irq(extpci_core->dev) + 2;
312 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
316 if (WARN_ON(extpci_core))
320 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
321 /* Reset devices on the external PCI bus */
322 val = SSB_PCICORE_CTL_RST_OE;
323 val |= SSB_PCICORE_CTL_CLK_OE;
324 pcicore_write32(pc, SSB_PCICORE_CTL, val);
325 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
326 pcicore_write32(pc, SSB_PCICORE_CTL, val);
327 udelay(150); /* Assertion time demanded by the PCI standard */
328 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
329 pcicore_write32(pc, SSB_PCICORE_CTL, val);
330 val = SSB_PCICORE_ARBCTL_INTERN;
331 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
332 udelay(1); /* Assertion time demanded by the PCI standard */
334 if (pc->dev->bus->has_cardbus_slot) {
335 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
337 /* GPIO 1 resets the bridge */
338 ssb_gpio_out(pc->dev->bus, 1, 1);
339 ssb_gpio_outen(pc->dev->bus, 1, 1);
340 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
341 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
345 /* 64MB I/O window */
346 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
347 SSB_PCICORE_SBTOPCI_IO);
348 /* 64MB config space */
349 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
350 SSB_PCICORE_SBTOPCI_CFG0);
351 /* 1GB memory window */
352 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
353 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
355 /* Enable PCI bridge BAR0 prefetch and burst */
356 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
357 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
358 /* Clear error conditions */
360 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
362 /* Enable PCI interrupts */
363 pcicore_write32(pc, SSB_PCICORE_IMASK,
364 SSB_PCICORE_IMASK_INTA);
366 /* Ok, ready to run, register it to the system.
367 * The following needs change, if we want to port hostmode
368 * to non-MIPS platform. */
369 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
370 set_io_port_base(ssb_pcicore_controller.io_map_base);
371 /* Give some time to the PCI controller to configure itself with the new
372 * values. Not waiting at this point causes crashes of the machine. */
374 register_pci_controller(&ssb_pcicore_controller);
377 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
379 struct ssb_bus *bus = pc->dev->bus;
383 chipid_top = (bus->chip_id & 0xFF00);
384 if (chipid_top != 0x4700 &&
385 chipid_top != 0x5300)
388 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
391 /* The 200-pin BCM4712 package does not bond out PCI. Even when
392 * PCI is bonded out, some boards may leave the pins floating. */
393 if (bus->chip_id == 0x4712) {
394 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
396 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
399 if (bus->chip_id == 0x5350)
402 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
404 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
407 /**************************************************
408 * Generic and Clientmode operation code.
409 **************************************************/
411 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
413 /* Disable PCI interrupts. */
414 ssb_write32(pc->dev, SSB_INTVEC, 0);
417 void ssb_pcicore_init(struct ssb_pcicore *pc)
419 struct ssb_device *dev = pc->dev;
423 if (!ssb_device_is_enabled(dev))
424 ssb_device_enable(dev, 0);
426 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
427 pc->hostmode = pcicore_is_in_hostmode(pc);
429 ssb_pcicore_init_hostmode(pc);
430 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
432 ssb_pcicore_init_clientmode(pc);
435 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
437 pcicore_write32(pc, 0x130, address);
438 return pcicore_read32(pc, 0x134);
441 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
443 pcicore_write32(pc, 0x130, address);
444 pcicore_write32(pc, 0x134, data);
447 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
448 u8 address, u16 data)
450 const u16 mdio_control = 0x128;
451 const u16 mdio_data = 0x12C;
455 v = 0x80; /* Enable Preamble Sequence */
456 v |= 0x2; /* MDIO Clock Divisor */
457 pcicore_write32(pc, mdio_control, v);
459 v = (1 << 30); /* Start of Transaction */
460 v |= (1 << 28); /* Write Transaction */
461 v |= (1 << 17); /* Turnaround */
462 v |= (u32)device << 22;
463 v |= (u32)address << 18;
465 pcicore_write32(pc, mdio_data, v);
466 /* Wait for the device to complete the transaction */
468 for (i = 0; i < 10; i++) {
469 v = pcicore_read32(pc, mdio_control);
470 if (v & 0x100 /* Trans complete */)
474 pcicore_write32(pc, mdio_control, 0);
477 static void ssb_broadcast_value(struct ssb_device *dev,
478 u32 address, u32 data)
480 /* This is used for both, PCI and ChipCommon core, so be careful. */
481 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
482 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
484 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
485 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
486 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
487 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
490 static void ssb_commit_settings(struct ssb_bus *bus)
492 struct ssb_device *dev;
494 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
497 /* This forces an update of the cached registers. */
498 ssb_broadcast_value(dev, 0xFD8, 0);
501 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
502 struct ssb_device *dev)
504 struct ssb_device *pdev = pc->dev;
509 if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
510 /* This SSB device is not on a PCI host-bus. So the IRQs are
511 * not routed through the PCI core.
512 * So we must not enable routing through the PCI core. */
520 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
522 /* Enable interrupts for this device. */
523 if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
526 /* Calculate the "coremask" for the device. */
527 coremask = (1 << dev->core_index);
529 SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
530 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
533 tmp |= coremask << 8;
534 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
540 intvec = ssb_read32(pdev, SSB_INTVEC);
541 tmp = ssb_read32(dev, SSB_TPSFLAG);
542 tmp &= SSB_TPSFLAG_BPFLAG;
543 intvec |= (1 << tmp);
544 ssb_write32(pdev, SSB_INTVEC, intvec);
547 /* Setup PCIcore operation. */
550 if (pdev->id.coreid == SSB_DEV_PCI) {
551 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
552 tmp |= SSB_PCICORE_SBTOPCI_PREF;
553 tmp |= SSB_PCICORE_SBTOPCI_BURST;
554 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
556 if (pdev->id.revision < 5) {
557 tmp = ssb_read32(pdev, SSB_IMCFGLO);
558 tmp &= ~SSB_IMCFGLO_SERTO;
560 tmp &= ~SSB_IMCFGLO_REQTO;
561 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
562 ssb_write32(pdev, SSB_IMCFGLO, tmp);
563 ssb_commit_settings(bus);
564 } else if (pdev->id.revision >= 11) {
565 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
566 tmp |= SSB_PCICORE_SBTOPCI_MRM;
567 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
570 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
571 //TODO: Better make defines for all these magic PCIE values.
572 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
573 /* TLP Workaround register. */
574 tmp = ssb_pcie_read(pc, 0x4);
576 ssb_pcie_write(pc, 0x4, tmp);
578 if (pdev->id.revision == 0) {
579 const u8 serdes_rx_device = 0x1F;
581 ssb_pcie_mdio_write(pc, serdes_rx_device,
582 2 /* Timer */, 0x8128);
583 ssb_pcie_mdio_write(pc, serdes_rx_device,
584 6 /* CDR */, 0x0100);
585 ssb_pcie_mdio_write(pc, serdes_rx_device,
586 7 /* CDR BW */, 0x1466);
587 } else if (pdev->id.revision == 1) {
588 /* DLLP Link Control register. */
589 tmp = ssb_pcie_read(pc, 0x100);
591 ssb_pcie_write(pc, 0x100, tmp);
598 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);