2 * Sonics Silicon Backplane
3 * Broadcom ChipCommon core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/ssb/ssb_regs.h>
13 #include <linux/pci.h>
15 #include "ssb_private.h"
21 SSB_CHIPCO_CLKSRC_PCI,
22 /* Crystal slow clock oscillator */
23 SSB_CHIPCO_CLKSRC_XTALOS,
24 /* Low power oscillator */
25 SSB_CHIPCO_CLKSRC_LOPWROS,
29 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
33 value |= chipco_read32(cc, offset) & ~mask;
34 chipco_write32(cc, offset, value);
39 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
40 enum ssb_clkmode mode)
42 struct ssb_device *ccdev = cc->dev;
49 /* chipcommon cores prior to rev6 don't support dynamic clock control */
50 if (ccdev->id.revision < 6)
52 /* chipcommon cores rev10 are a whole new ball game */
53 if (ccdev->id.revision >= 10)
55 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
59 case SSB_CLKMODE_SLOW:
60 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
61 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
62 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
64 case SSB_CLKMODE_FAST:
65 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
66 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
67 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
68 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
69 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
71 case SSB_CLKMODE_DYNAMIC:
72 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
73 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
74 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
75 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
76 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
77 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
78 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
80 /* for dynamic control, we have to release our xtal_pu "force on" */
81 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
82 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
89 /* Get the Slow Clock Source */
90 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
92 struct ssb_bus *bus = cc->dev->bus;
93 u32 uninitialized_var(tmp);
95 if (cc->dev->id.revision < 6) {
96 if (bus->bustype == SSB_BUSTYPE_SSB ||
97 bus->bustype == SSB_BUSTYPE_PCMCIA)
98 return SSB_CHIPCO_CLKSRC_XTALOS;
99 if (bus->bustype == SSB_BUSTYPE_PCI) {
100 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
102 return SSB_CHIPCO_CLKSRC_PCI;
103 return SSB_CHIPCO_CLKSRC_XTALOS;
106 if (cc->dev->id.revision < 10) {
107 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
110 return SSB_CHIPCO_CLKSRC_LOPWROS;
112 return SSB_CHIPCO_CLKSRC_XTALOS;
114 return SSB_CHIPCO_CLKSRC_PCI;
117 return SSB_CHIPCO_CLKSRC_XTALOS;
120 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
121 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
123 int uninitialized_var(limit);
124 enum ssb_clksrc clocksrc;
128 clocksrc = chipco_pctl_get_slowclksrc(cc);
129 if (cc->dev->id.revision < 6) {
131 case SSB_CHIPCO_CLKSRC_PCI:
134 case SSB_CHIPCO_CLKSRC_XTALOS:
140 } else if (cc->dev->id.revision < 10) {
142 case SSB_CHIPCO_CLKSRC_LOPWROS:
144 case SSB_CHIPCO_CLKSRC_XTALOS:
145 case SSB_CHIPCO_CLKSRC_PCI:
146 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
147 divisor = (tmp >> 16) + 1;
152 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
153 divisor = (tmp >> 16) + 1;
158 case SSB_CHIPCO_CLKSRC_LOPWROS:
164 case SSB_CHIPCO_CLKSRC_XTALOS:
170 case SSB_CHIPCO_CLKSRC_PCI:
182 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
184 struct ssb_bus *bus = cc->dev->bus;
186 if (bus->chip_id == 0x4321) {
187 if (bus->chip_rev == 0)
188 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
189 else if (bus->chip_rev == 1)
190 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
193 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
196 if (cc->dev->id.revision >= 10) {
197 /* Set Idle Power clock rate to 1Mhz */
198 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
199 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
200 0x0000FFFF) | 0x00040000);
204 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
205 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
206 (maxfreq * 150 + 999999) / 1000000);
207 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
208 (maxfreq * 15 + 999999) / 1000000);
212 /* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
213 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
215 struct ssb_bus *bus = cc->dev->bus;
217 switch (bus->chip_id) {
229 /* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
230 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
232 struct ssb_bus *bus = cc->dev->bus;
237 if (bus->bustype != SSB_BUSTYPE_PCI)
240 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
241 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
245 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
248 minfreq = chipco_pctl_clockfreqlimit(cc, 0);
249 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
250 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
251 SSB_WARN_ON(tmp & ~0xFFFF);
253 cc->fast_pwrup_delay = tmp;
256 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
259 return; /* We don't have a ChipCommon */
260 if (cc->dev->id.revision >= 11)
261 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
262 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
264 if (cc->dev->id.revision >= 20) {
265 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
266 chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
270 chipco_powercontrol_init(cc);
271 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
272 calc_fast_powerup_delay(cc);
275 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
279 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
282 void ssb_chipco_resume(struct ssb_chipcommon *cc)
286 chipco_powercontrol_init(cc);
287 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
290 /* Get the processor clock */
291 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
292 u32 *plltype, u32 *n, u32 *m)
294 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
295 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
301 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
304 /* 5350 uses m2 to control mips */
305 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
308 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
313 /* Get the bus clock */
314 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
315 u32 *plltype, u32 *n, u32 *m)
317 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
318 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
320 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
321 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
323 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
324 if (cc->dev->bus->chip_id != 0x5365) {
325 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
330 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
334 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
337 struct ssb_device *dev = cc->dev;
338 struct ssb_bus *bus = dev->bus;
341 /* set register for external IO to control LED. */
342 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
343 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
344 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
345 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */
346 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
348 /* Set timing for the flash */
349 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
350 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
351 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */
352 if ((bus->chip_id == 0x5365) ||
353 (dev->id.revision < 9))
354 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
355 if ((bus->chip_id == 0x5365) ||
356 (dev->id.revision < 9) ||
357 ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
358 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
360 if (bus->chip_id == 0x5350) {
362 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
363 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
364 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
365 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */
366 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
370 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
371 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
374 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
377 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
379 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
382 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
384 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
387 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
389 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
392 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
394 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
397 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
399 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
402 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
404 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
406 EXPORT_SYMBOL(ssb_chipco_gpio_control);
408 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
410 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
413 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
415 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
418 #ifdef CONFIG_SSB_SERIAL
419 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
420 struct ssb_serial_port *ports)
422 struct ssb_bus *bus = cc->dev->bus;
428 unsigned int ccrev = cc->dev->id.revision;
430 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
431 irq = ssb_mips_irq(cc->dev);
433 if (plltype == SSB_PLLTYPE_1) {
435 baud_base = ssb_calc_clock_rate(plltype,
436 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
437 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
441 /* BCM5354 uses constant 25MHz clock */
442 baud_base = 25000000;
444 /* Set the override bit so we don't divide it */
445 chipco_write32(cc, SSB_CHIPCO_CORECTL,
446 chipco_read32(cc, SSB_CHIPCO_CORECTL)
447 | SSB_CHIPCO_CORECTL_UARTCLK0);
448 } else if ((ccrev >= 11) && (ccrev != 15)) {
449 /* Fixed ALP clock */
450 baud_base = 20000000;
451 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
452 /* FIXME: baud_base is different for devices with a PMU */
457 /* Turn off UART clock before switching clocksource. */
458 chipco_write32(cc, SSB_CHIPCO_CORECTL,
459 chipco_read32(cc, SSB_CHIPCO_CORECTL)
460 & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
462 /* Set the override bit so we don't divide it */
463 chipco_write32(cc, SSB_CHIPCO_CORECTL,
464 chipco_read32(cc, SSB_CHIPCO_CORECTL)
465 | SSB_CHIPCO_CORECTL_UARTCLK0);
467 /* Re-enable the UART clock. */
468 chipco_write32(cc, SSB_CHIPCO_CORECTL,
469 chipco_read32(cc, SSB_CHIPCO_CORECTL)
470 | SSB_CHIPCO_CORECTL_UARTCLKEN);
472 } else if (ccrev >= 3) {
473 /* Internal backplane clock */
474 baud_base = ssb_clockspeed(bus);
475 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
476 & SSB_CHIPCO_CLKDIV_UART;
478 /* Fixed internal backplane clock */
479 baud_base = 88000000;
483 /* Clock source depends on strapping if UartClkOverride is unset */
485 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
486 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
487 SSB_CHIPCO_CAP_UARTCLK_INT) {
488 /* Internal divided backplane clock */
491 /* Assume external clock of 1.8432 MHz */
497 /* Determine the registers of the UARTs */
498 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
499 for (i = 0; i < n; i++) {
500 void __iomem *cc_mmio;
501 void __iomem *uart_regs;
503 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
504 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
505 /* Offset changed at after rev 0 */
507 uart_regs += (i * 8);
509 uart_regs += (i * 256);
512 ports[i].regs = uart_regs;
514 ports[i].baud_base = baud_base;
515 ports[i].reg_shift = 0;
520 #endif /* CONFIG_SSB_SERIAL */