2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
48 void (*write) (struct master_data *);
49 void (*read) (struct master_data *);
50 void (*duplex) (struct master_data *);
54 /* Driver model hookup */
55 struct platform_device *pdev;
57 /* SPI framework hookup */
58 struct spi_master *master;
60 /* Regs base of SPI controller */
61 void __iomem *regs_base;
63 /* Pin request list */
67 struct bfin5xx_spi_master *master_info;
69 /* Driver message queue */
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
73 struct list_head queue;
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers;
80 /* Current message transfer state info */
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
83 struct slave_data *cur_chip;
108 const struct transfer_ops *ops;
118 u8 width; /* 0 or 1 */
120 u8 bits_per_word; /* 8 or 16 */
121 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
124 u8 pio_interrupt; /* use spi data irq */
125 const struct transfer_ops *ops;
128 #define DEFINE_SPI_REG(reg, off) \
129 static inline u16 read_##reg(struct master_data *drv_data) \
130 { return bfin_read16(drv_data->regs_base + off); } \
131 static inline void write_##reg(struct master_data *drv_data, u16 v) \
132 { bfin_write16(drv_data->regs_base + off, v); }
134 DEFINE_SPI_REG(CTRL, 0x00)
135 DEFINE_SPI_REG(FLAG, 0x04)
136 DEFINE_SPI_REG(STAT, 0x08)
137 DEFINE_SPI_REG(TDBR, 0x0C)
138 DEFINE_SPI_REG(RDBR, 0x10)
139 DEFINE_SPI_REG(BAUD, 0x14)
140 DEFINE_SPI_REG(SHAW, 0x18)
142 static void bfin_spi_enable(struct master_data *drv_data)
146 cr = read_CTRL(drv_data);
147 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
150 static void bfin_spi_disable(struct master_data *drv_data)
154 cr = read_CTRL(drv_data);
155 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
158 /* Caculate the SPI_BAUD register value based on input HZ */
159 static u16 hz_to_spi_baud(u32 speed_hz)
161 u_long sclk = get_sclk();
162 u16 spi_baud = (sclk / (2 * speed_hz));
164 if ((sclk % (2 * speed_hz)) > 0)
167 if (spi_baud < MIN_SPI_BAUD_VAL)
168 spi_baud = MIN_SPI_BAUD_VAL;
173 static int bfin_spi_flush(struct master_data *drv_data)
175 unsigned long limit = loops_per_jiffy << 1;
177 /* wait for stop and clear stat */
178 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
181 write_STAT(drv_data, BIT_STAT_CLR);
186 /* Chip select operation functions for cs_change flag */
187 static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip)
189 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
190 u16 flag = read_FLAG(drv_data);
194 write_FLAG(drv_data, flag);
196 gpio_set_value(chip->cs_gpio, 0);
200 static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip)
202 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
203 u16 flag = read_FLAG(drv_data);
207 write_FLAG(drv_data, flag);
209 gpio_set_value(chip->cs_gpio, 1);
212 /* Move delay here for consistency */
213 if (chip->cs_chg_udelay)
214 udelay(chip->cs_chg_udelay);
217 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
218 static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip)
220 if (chip->chip_select_num < MAX_CTRL_CS) {
221 u16 flag = read_FLAG(drv_data);
223 flag |= (chip->flag >> 8);
225 write_FLAG(drv_data, flag);
229 static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip)
231 if (chip->chip_select_num < MAX_CTRL_CS) {
232 u16 flag = read_FLAG(drv_data);
234 flag &= ~(chip->flag >> 8);
236 write_FLAG(drv_data, flag);
240 /* stop controller and re-config current chip*/
241 static void bfin_spi_restore_state(struct master_data *drv_data)
243 struct slave_data *chip = drv_data->cur_chip;
245 /* Clear status and disable clock */
246 write_STAT(drv_data, BIT_STAT_CLR);
247 bfin_spi_disable(drv_data);
248 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
250 /* Load the registers */
251 write_CTRL(drv_data, chip->ctl_reg);
252 write_BAUD(drv_data, chip->baud);
254 bfin_spi_enable(drv_data);
255 bfin_spi_cs_active(drv_data, chip);
258 /* used to kick off transfer in rx mode and read unwanted RX data */
259 static inline void bfin_spi_dummy_read(struct master_data *drv_data)
261 (void) read_RDBR(drv_data);
264 static void bfin_spi_u8_writer(struct master_data *drv_data)
266 /* clear RXS (we check for RXS inside the loop) */
267 bfin_spi_dummy_read(drv_data);
269 while (drv_data->tx < drv_data->tx_end) {
270 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
271 /* wait until transfer finished.
272 checking SPIF or TXS may not guarantee transfer completion */
273 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
275 /* discard RX data and clear RXS */
276 bfin_spi_dummy_read(drv_data);
280 static void bfin_spi_u8_reader(struct master_data *drv_data)
282 u16 tx_val = drv_data->cur_chip->idle_tx_val;
284 /* discard old RX data and clear RXS */
285 bfin_spi_dummy_read(drv_data);
287 while (drv_data->rx < drv_data->rx_end) {
288 write_TDBR(drv_data, tx_val);
289 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
291 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
295 static void bfin_spi_u8_duplex(struct master_data *drv_data)
297 /* discard old RX data and clear RXS */
298 bfin_spi_dummy_read(drv_data);
300 while (drv_data->rx < drv_data->rx_end) {
301 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
302 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
304 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
308 static const struct transfer_ops bfin_transfer_ops_u8 = {
309 .write = bfin_spi_u8_writer,
310 .read = bfin_spi_u8_reader,
311 .duplex = bfin_spi_u8_duplex,
314 static void bfin_spi_u16_writer(struct master_data *drv_data)
316 /* clear RXS (we check for RXS inside the loop) */
317 bfin_spi_dummy_read(drv_data);
319 while (drv_data->tx < drv_data->tx_end) {
320 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
322 /* wait until transfer finished.
323 checking SPIF or TXS may not guarantee transfer completion */
324 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
326 /* discard RX data and clear RXS */
327 bfin_spi_dummy_read(drv_data);
331 static void bfin_spi_u16_reader(struct master_data *drv_data)
333 u16 tx_val = drv_data->cur_chip->idle_tx_val;
335 /* discard old RX data and clear RXS */
336 bfin_spi_dummy_read(drv_data);
338 while (drv_data->rx < drv_data->rx_end) {
339 write_TDBR(drv_data, tx_val);
340 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
342 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
347 static void bfin_spi_u16_duplex(struct master_data *drv_data)
349 /* discard old RX data and clear RXS */
350 bfin_spi_dummy_read(drv_data);
352 while (drv_data->rx < drv_data->rx_end) {
353 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
355 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
357 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
362 static const struct transfer_ops bfin_transfer_ops_u16 = {
363 .write = bfin_spi_u16_writer,
364 .read = bfin_spi_u16_reader,
365 .duplex = bfin_spi_u16_duplex,
368 /* test if ther is more transfer to be done */
369 static void *bfin_spi_next_transfer(struct master_data *drv_data)
371 struct spi_message *msg = drv_data->cur_msg;
372 struct spi_transfer *trans = drv_data->cur_transfer;
374 /* Move to next transfer */
375 if (trans->transfer_list.next != &msg->transfers) {
376 drv_data->cur_transfer =
377 list_entry(trans->transfer_list.next,
378 struct spi_transfer, transfer_list);
379 return RUNNING_STATE;
385 * caller already set message->status;
386 * dma and pio irqs are blocked give finished message back
388 static void bfin_spi_giveback(struct master_data *drv_data)
390 struct slave_data *chip = drv_data->cur_chip;
391 struct spi_transfer *last_transfer;
393 struct spi_message *msg;
395 spin_lock_irqsave(&drv_data->lock, flags);
396 msg = drv_data->cur_msg;
397 drv_data->cur_msg = NULL;
398 drv_data->cur_transfer = NULL;
399 drv_data->cur_chip = NULL;
400 queue_work(drv_data->workqueue, &drv_data->pump_messages);
401 spin_unlock_irqrestore(&drv_data->lock, flags);
403 last_transfer = list_entry(msg->transfers.prev,
404 struct spi_transfer, transfer_list);
408 if (!drv_data->cs_change)
409 bfin_spi_cs_deactive(drv_data, chip);
411 /* Not stop spi in autobuffer mode */
412 if (drv_data->tx_dma != 0xFFFF)
413 bfin_spi_disable(drv_data);
416 msg->complete(msg->context);
419 /* spi data irq handler */
420 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
422 struct master_data *drv_data = dev_id;
423 struct slave_data *chip = drv_data->cur_chip;
424 struct spi_message *msg = drv_data->cur_msg;
425 int n_bytes = drv_data->n_bytes;
427 /* wait until transfer finished. */
428 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
431 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
432 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
435 dev_dbg(&drv_data->pdev->dev, "last read\n");
437 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
438 else if (n_bytes == 1)
439 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
440 drv_data->rx += n_bytes;
443 msg->actual_length += drv_data->len_in_bytes;
444 if (drv_data->cs_change)
445 bfin_spi_cs_deactive(drv_data, chip);
446 /* Move to next transfer */
447 msg->state = bfin_spi_next_transfer(drv_data);
449 disable_irq(drv_data->spi_irq);
451 /* Schedule transfer tasklet */
452 tasklet_schedule(&drv_data->pump_transfers);
456 if (drv_data->rx && drv_data->tx) {
458 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
459 if (drv_data->n_bytes == 2) {
460 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
461 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
462 } else if (drv_data->n_bytes == 1) {
463 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
464 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
466 } else if (drv_data->rx) {
468 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
469 if (drv_data->n_bytes == 2)
470 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
471 else if (drv_data->n_bytes == 1)
472 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
473 write_TDBR(drv_data, chip->idle_tx_val);
474 } else if (drv_data->tx) {
476 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
477 bfin_spi_dummy_read(drv_data);
478 if (drv_data->n_bytes == 2)
479 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
480 else if (drv_data->n_bytes == 1)
481 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
485 drv_data->tx += n_bytes;
487 drv_data->rx += n_bytes;
492 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
494 struct master_data *drv_data = dev_id;
495 struct slave_data *chip = drv_data->cur_chip;
496 struct spi_message *msg = drv_data->cur_msg;
497 unsigned long timeout;
498 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
499 u16 spistat = read_STAT(drv_data);
501 dev_dbg(&drv_data->pdev->dev,
502 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
505 clear_dma_irqstat(drv_data->dma_channel);
508 * wait for the last transaction shifted out. HRM states:
509 * at this point there may still be data in the SPI DMA FIFO waiting
510 * to be transmitted ... software needs to poll TXS in the SPI_STAT
511 * register until it goes low for 2 successive reads
513 if (drv_data->tx != NULL) {
514 while ((read_STAT(drv_data) & BIT_STAT_TXS) ||
515 (read_STAT(drv_data) & BIT_STAT_TXS))
519 dev_dbg(&drv_data->pdev->dev,
520 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
521 dmastat, read_STAT(drv_data));
523 timeout = jiffies + HZ;
524 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
525 if (!time_before(jiffies, timeout)) {
526 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
531 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
532 msg->state = ERROR_STATE;
533 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
535 msg->actual_length += drv_data->len_in_bytes;
537 if (drv_data->cs_change)
538 bfin_spi_cs_deactive(drv_data, chip);
540 /* Move to next transfer */
541 msg->state = bfin_spi_next_transfer(drv_data);
544 /* Schedule transfer tasklet */
545 tasklet_schedule(&drv_data->pump_transfers);
547 /* free the irq handler before next transfer */
548 dev_dbg(&drv_data->pdev->dev,
549 "disable dma channel irq%d\n",
550 drv_data->dma_channel);
551 dma_disable_irq(drv_data->dma_channel);
556 static void bfin_spi_pump_transfers(unsigned long data)
558 struct master_data *drv_data = (struct master_data *)data;
559 struct spi_message *message = NULL;
560 struct spi_transfer *transfer = NULL;
561 struct spi_transfer *previous = NULL;
562 struct slave_data *chip = NULL;
564 u16 cr, dma_width, dma_config;
565 u32 tranf_success = 1;
568 /* Get current state information */
569 message = drv_data->cur_msg;
570 transfer = drv_data->cur_transfer;
571 chip = drv_data->cur_chip;
574 * if msg is error or done, report it back using complete() callback
577 /* Handle for abort */
578 if (message->state == ERROR_STATE) {
579 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
580 message->status = -EIO;
581 bfin_spi_giveback(drv_data);
585 /* Handle end of message */
586 if (message->state == DONE_STATE) {
587 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
589 bfin_spi_giveback(drv_data);
593 /* Delay if requested at end of transfer */
594 if (message->state == RUNNING_STATE) {
595 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
596 previous = list_entry(transfer->transfer_list.prev,
597 struct spi_transfer, transfer_list);
598 if (previous->delay_usecs)
599 udelay(previous->delay_usecs);
602 /* Flush any existing transfers that may be sitting in the hardware */
603 if (bfin_spi_flush(drv_data) == 0) {
604 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
605 message->status = -EIO;
606 bfin_spi_giveback(drv_data);
610 if (transfer->len == 0) {
611 /* Move to next transfer of this msg */
612 message->state = bfin_spi_next_transfer(drv_data);
613 /* Schedule next transfer tasklet */
614 tasklet_schedule(&drv_data->pump_transfers);
617 if (transfer->tx_buf != NULL) {
618 drv_data->tx = (void *)transfer->tx_buf;
619 drv_data->tx_end = drv_data->tx + transfer->len;
620 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
621 transfer->tx_buf, drv_data->tx_end);
626 if (transfer->rx_buf != NULL) {
627 full_duplex = transfer->tx_buf != NULL;
628 drv_data->rx = transfer->rx_buf;
629 drv_data->rx_end = drv_data->rx + transfer->len;
630 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
631 transfer->rx_buf, drv_data->rx_end);
636 drv_data->rx_dma = transfer->rx_dma;
637 drv_data->tx_dma = transfer->tx_dma;
638 drv_data->len_in_bytes = transfer->len;
639 drv_data->cs_change = transfer->cs_change;
641 /* Bits per word setup */
642 switch (transfer->bits_per_word) {
644 drv_data->n_bytes = 1;
645 width = CFG_SPI_WORDSIZE8;
646 drv_data->ops = &bfin_transfer_ops_u8;
650 drv_data->n_bytes = 2;
651 width = CFG_SPI_WORDSIZE16;
652 drv_data->ops = &bfin_transfer_ops_u16;
656 /* No change, the same as default setting */
657 transfer->bits_per_word = chip->bits_per_word;
658 drv_data->n_bytes = chip->n_bytes;
660 drv_data->ops = chip->ops;
663 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
665 write_CTRL(drv_data, cr);
667 if (width == CFG_SPI_WORDSIZE16) {
668 drv_data->len = (transfer->len) >> 1;
670 drv_data->len = transfer->len;
672 dev_dbg(&drv_data->pdev->dev,
673 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
674 drv_data->ops, chip->ops, &bfin_transfer_ops_u8);
676 message->state = RUNNING_STATE;
679 /* Speed setup (surely valid because already checked) */
680 if (transfer->speed_hz)
681 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
683 write_BAUD(drv_data, chip->baud);
685 write_STAT(drv_data, BIT_STAT_CLR);
686 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
687 if (drv_data->cs_change)
688 bfin_spi_cs_active(drv_data, chip);
690 dev_dbg(&drv_data->pdev->dev,
691 "now pumping a transfer: width is %d, len is %d\n",
692 width, transfer->len);
695 * Try to map dma buffer and do a dma transfer. If successful use,
696 * different way to r/w according to the enable_dma settings and if
697 * we are not doing a full duplex transfer (since the hardware does
698 * not support full duplex DMA transfers).
700 if (!full_duplex && drv_data->cur_chip->enable_dma
701 && drv_data->len > 6) {
703 unsigned long dma_start_addr, flags;
705 disable_dma(drv_data->dma_channel);
706 clear_dma_irqstat(drv_data->dma_channel);
708 /* config dma channel */
709 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
710 set_dma_x_count(drv_data->dma_channel, drv_data->len);
711 if (width == CFG_SPI_WORDSIZE16) {
712 set_dma_x_modify(drv_data->dma_channel, 2);
713 dma_width = WDSIZE_16;
715 set_dma_x_modify(drv_data->dma_channel, 1);
716 dma_width = WDSIZE_8;
719 /* poll for SPI completion before start */
720 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
723 /* dirty hack for autobuffer DMA mode */
724 if (drv_data->tx_dma == 0xFFFF) {
725 dev_dbg(&drv_data->pdev->dev,
726 "doing autobuffer DMA out.\n");
728 /* no irq in autobuffer mode */
730 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
731 set_dma_config(drv_data->dma_channel, dma_config);
732 set_dma_start_addr(drv_data->dma_channel,
733 (unsigned long)drv_data->tx);
734 enable_dma(drv_data->dma_channel);
736 /* start SPI transfer */
737 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
739 /* just return here, there can only be one transfer
743 bfin_spi_giveback(drv_data);
747 /* In dma mode, rx or tx must be NULL in one transfer */
748 dma_config = (RESTART | dma_width | DI_EN);
749 if (drv_data->rx != NULL) {
750 /* set transfer mode, and enable SPI */
751 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
752 drv_data->rx, drv_data->len_in_bytes);
754 /* invalidate caches, if needed */
755 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
756 invalidate_dcache_range((unsigned long) drv_data->rx,
757 (unsigned long) (drv_data->rx +
758 drv_data->len_in_bytes));
761 dma_start_addr = (unsigned long)drv_data->rx;
762 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
764 } else if (drv_data->tx != NULL) {
765 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
767 /* flush caches, if needed */
768 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
769 flush_dcache_range((unsigned long) drv_data->tx,
770 (unsigned long) (drv_data->tx +
771 drv_data->len_in_bytes));
773 dma_start_addr = (unsigned long)drv_data->tx;
774 cr |= BIT_CTL_TIMOD_DMA_TX;
779 /* oh man, here there be monsters ... and i dont mean the
780 * fluffy cute ones from pixar, i mean the kind that'll eat
781 * your data, kick your dog, and love it all. do *not* try
782 * and change these lines unless you (1) heavily test DMA
783 * with SPI flashes on a loaded system (e.g. ping floods),
784 * (2) know just how broken the DMA engine interaction with
785 * the SPI peripheral is, and (3) have someone else to blame
786 * when you screw it all up anyways.
788 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
789 set_dma_config(drv_data->dma_channel, dma_config);
790 local_irq_save(flags);
792 write_CTRL(drv_data, cr);
793 enable_dma(drv_data->dma_channel);
794 dma_enable_irq(drv_data->dma_channel);
795 local_irq_restore(flags);
800 if (chip->pio_interrupt) {
801 /* use write mode. spi irq should have been disabled */
802 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
803 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
805 /* discard old RX data and clear RXS */
806 bfin_spi_dummy_read(drv_data);
809 if (drv_data->tx == NULL)
810 write_TDBR(drv_data, chip->idle_tx_val);
812 if (transfer->bits_per_word == 8)
813 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
814 else if (transfer->bits_per_word == 16)
815 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
816 drv_data->tx += drv_data->n_bytes;
819 /* once TDBR is empty, interrupt is triggered */
820 enable_irq(drv_data->spi_irq);
825 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
827 /* we always use SPI_WRITE mode. SPI_READ mode
828 seems to have problems with setting up the
829 output value in TDBR prior to the transfer. */
830 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
833 /* full duplex mode */
834 BUG_ON((drv_data->tx_end - drv_data->tx) !=
835 (drv_data->rx_end - drv_data->rx));
836 dev_dbg(&drv_data->pdev->dev,
837 "IO duplex: cr is 0x%x\n", cr);
839 drv_data->ops->duplex(drv_data);
841 if (drv_data->tx != drv_data->tx_end)
843 } else if (drv_data->tx != NULL) {
844 /* write only half duplex */
845 dev_dbg(&drv_data->pdev->dev,
846 "IO write: cr is 0x%x\n", cr);
848 drv_data->ops->write(drv_data);
850 if (drv_data->tx != drv_data->tx_end)
852 } else if (drv_data->rx != NULL) {
853 /* read only half duplex */
854 dev_dbg(&drv_data->pdev->dev,
855 "IO read: cr is 0x%x\n", cr);
857 drv_data->ops->read(drv_data);
858 if (drv_data->rx != drv_data->rx_end)
862 if (!tranf_success) {
863 dev_dbg(&drv_data->pdev->dev,
864 "IO write error!\n");
865 message->state = ERROR_STATE;
867 /* Update total byte transfered */
868 message->actual_length += drv_data->len_in_bytes;
869 /* Move to next transfer of this msg */
870 message->state = bfin_spi_next_transfer(drv_data);
871 if (drv_data->cs_change)
872 bfin_spi_cs_deactive(drv_data, chip);
875 /* Schedule next transfer tasklet */
876 tasklet_schedule(&drv_data->pump_transfers);
879 /* pop a msg from queue and kick off real transfer */
880 static void bfin_spi_pump_messages(struct work_struct *work)
882 struct master_data *drv_data;
885 drv_data = container_of(work, struct master_data, pump_messages);
887 /* Lock queue and check for queue work */
888 spin_lock_irqsave(&drv_data->lock, flags);
889 if (list_empty(&drv_data->queue) || !drv_data->running) {
890 /* pumper kicked off but no work to do */
892 spin_unlock_irqrestore(&drv_data->lock, flags);
896 /* Make sure we are not already running a message */
897 if (drv_data->cur_msg) {
898 spin_unlock_irqrestore(&drv_data->lock, flags);
902 /* Extract head of queue */
903 drv_data->cur_msg = list_entry(drv_data->queue.next,
904 struct spi_message, queue);
906 /* Setup the SSP using the per chip configuration */
907 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
908 bfin_spi_restore_state(drv_data);
910 list_del_init(&drv_data->cur_msg->queue);
912 /* Initial message state */
913 drv_data->cur_msg->state = START_STATE;
914 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
915 struct spi_transfer, transfer_list);
917 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
918 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
919 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
920 drv_data->cur_chip->ctl_reg);
922 dev_dbg(&drv_data->pdev->dev,
923 "the first transfer len is %d\n",
924 drv_data->cur_transfer->len);
926 /* Mark as busy and launch transfers */
927 tasklet_schedule(&drv_data->pump_transfers);
930 spin_unlock_irqrestore(&drv_data->lock, flags);
934 * got a msg to transfer, queue it in drv_data->queue.
935 * And kick off message pumper
937 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
939 struct master_data *drv_data = spi_master_get_devdata(spi->master);
942 spin_lock_irqsave(&drv_data->lock, flags);
944 if (!drv_data->running) {
945 spin_unlock_irqrestore(&drv_data->lock, flags);
949 msg->actual_length = 0;
950 msg->status = -EINPROGRESS;
951 msg->state = START_STATE;
953 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
954 list_add_tail(&msg->queue, &drv_data->queue);
956 if (drv_data->running && !drv_data->busy)
957 queue_work(drv_data->workqueue, &drv_data->pump_messages);
959 spin_unlock_irqrestore(&drv_data->lock, flags);
964 #define MAX_SPI_SSEL 7
966 static u16 ssel[][MAX_SPI_SSEL] = {
967 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
968 P_SPI0_SSEL4, P_SPI0_SSEL5,
969 P_SPI0_SSEL6, P_SPI0_SSEL7},
971 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
972 P_SPI1_SSEL4, P_SPI1_SSEL5,
973 P_SPI1_SSEL6, P_SPI1_SSEL7},
975 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
976 P_SPI2_SSEL4, P_SPI2_SSEL5,
977 P_SPI2_SSEL6, P_SPI2_SSEL7},
980 /* setup for devices (may be called multiple times -- not just first setup) */
981 static int bfin_spi_setup(struct spi_device *spi)
983 struct bfin5xx_spi_chip *chip_info;
984 struct slave_data *chip = NULL;
985 struct master_data *drv_data = spi_master_get_devdata(spi->master);
988 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
991 /* Only alloc (or use chip_info) on first setup */
993 chip = spi_get_ctldata(spi);
995 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
997 dev_err(&spi->dev, "cannot allocate chip data\n");
1002 chip->enable_dma = 0;
1003 chip_info = spi->controller_data;
1006 /* chip_info isn't always needed */
1008 /* Make sure people stop trying to set fields via ctl_reg
1009 * when they should actually be using common SPI framework.
1010 * Currently we let through: WOM EMISO PSSE GM SZ.
1011 * Not sure if a user actually needs/uses any of these,
1012 * but let's assume (for now) they do.
1014 if (chip_info->ctl_reg & ~(BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | \
1015 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ)) {
1016 dev_err(&spi->dev, "do not set bits in ctl_reg "
1017 "that the SPI framework manages\n");
1021 chip->enable_dma = chip_info->enable_dma != 0
1022 && drv_data->master_info->enable_dma;
1023 chip->ctl_reg = chip_info->ctl_reg;
1024 chip->bits_per_word = chip_info->bits_per_word;
1025 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1026 chip->idle_tx_val = chip_info->idle_tx_val;
1027 chip->pio_interrupt = chip_info->pio_interrupt;
1030 /* translate common spi framework into our register */
1031 if (spi->mode & SPI_CPOL)
1032 chip->ctl_reg |= BIT_CTL_CPOL;
1033 if (spi->mode & SPI_CPHA)
1034 chip->ctl_reg |= BIT_CTL_CPHA;
1035 if (spi->mode & SPI_LSB_FIRST)
1036 chip->ctl_reg |= BIT_CTL_LSBF;
1037 /* we dont support running in slave mode (yet?) */
1038 chip->ctl_reg |= BIT_CTL_MASTER;
1041 * Notice: for blackfin, the speed_hz is the value of register
1042 * SPI_BAUD, not the real baudrate
1044 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1045 chip->chip_select_num = spi->chip_select;
1046 if (chip->chip_select_num < MAX_CTRL_CS)
1047 chip->flag = (1 << spi->chip_select) << 8;
1049 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1051 switch (chip->bits_per_word) {
1054 chip->width = CFG_SPI_WORDSIZE8;
1055 chip->ops = &bfin_transfer_ops_u8;
1060 chip->width = CFG_SPI_WORDSIZE16;
1061 chip->ops = &bfin_transfer_ops_u16;
1065 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1066 chip->bits_per_word);
1070 if (chip->enable_dma && chip->pio_interrupt) {
1071 dev_err(&spi->dev, "enable_dma is set, "
1072 "do not set pio_interrupt\n");
1076 * if any one SPI chip is registered and wants DMA, request the
1077 * DMA channel for it
1079 if (chip->enable_dma && !drv_data->dma_requested) {
1080 /* register dma irq handler */
1081 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1084 "Unable to request BlackFin SPI DMA channel\n");
1087 drv_data->dma_requested = 1;
1089 ret = set_dma_callback(drv_data->dma_channel,
1090 bfin_spi_dma_irq_handler, drv_data);
1092 dev_err(&spi->dev, "Unable to set dma callback\n");
1095 dma_disable_irq(drv_data->dma_channel);
1098 if (chip->pio_interrupt && !drv_data->irq_requested) {
1099 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1100 IRQF_DISABLED, "BFIN_SPI", drv_data);
1102 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1105 drv_data->irq_requested = 1;
1106 /* we use write mode, spi irq has to be disabled here */
1107 disable_irq(drv_data->spi_irq);
1110 if (chip->chip_select_num >= MAX_CTRL_CS) {
1111 ret = gpio_request(chip->cs_gpio, spi->modalias);
1113 dev_err(&spi->dev, "gpio_request() error\n");
1116 gpio_direction_output(chip->cs_gpio, 1);
1119 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1120 spi->modalias, chip->width, chip->enable_dma);
1121 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1122 chip->ctl_reg, chip->flag);
1124 spi_set_ctldata(spi, chip);
1126 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1127 if (chip->chip_select_num < MAX_CTRL_CS) {
1128 ret = peripheral_request(ssel[spi->master->bus_num]
1129 [chip->chip_select_num-1], spi->modalias);
1131 dev_err(&spi->dev, "peripheral_request() error\n");
1136 bfin_spi_cs_enable(drv_data, chip);
1137 bfin_spi_cs_deactive(drv_data, chip);
1142 if (chip->chip_select_num >= MAX_CTRL_CS)
1143 gpio_free(chip->cs_gpio);
1145 peripheral_free(ssel[spi->master->bus_num]
1146 [chip->chip_select_num - 1]);
1149 if (drv_data->dma_requested)
1150 free_dma(drv_data->dma_channel);
1151 drv_data->dma_requested = 0;
1154 /* prevent free 'chip' twice */
1155 spi_set_ctldata(spi, NULL);
1162 * callback for spi framework.
1163 * clean driver specific data
1165 static void bfin_spi_cleanup(struct spi_device *spi)
1167 struct slave_data *chip = spi_get_ctldata(spi);
1168 struct master_data *drv_data = spi_master_get_devdata(spi->master);
1173 if (chip->chip_select_num < MAX_CTRL_CS) {
1174 peripheral_free(ssel[spi->master->bus_num]
1175 [chip->chip_select_num-1]);
1176 bfin_spi_cs_disable(drv_data, chip);
1178 gpio_free(chip->cs_gpio);
1181 /* prevent free 'chip' twice */
1182 spi_set_ctldata(spi, NULL);
1185 static inline int bfin_spi_init_queue(struct master_data *drv_data)
1187 INIT_LIST_HEAD(&drv_data->queue);
1188 spin_lock_init(&drv_data->lock);
1190 drv_data->running = false;
1193 /* init transfer tasklet */
1194 tasklet_init(&drv_data->pump_transfers,
1195 bfin_spi_pump_transfers, (unsigned long)drv_data);
1197 /* init messages workqueue */
1198 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1199 drv_data->workqueue = create_singlethread_workqueue(
1200 dev_name(drv_data->master->dev.parent));
1201 if (drv_data->workqueue == NULL)
1207 static inline int bfin_spi_start_queue(struct master_data *drv_data)
1209 unsigned long flags;
1211 spin_lock_irqsave(&drv_data->lock, flags);
1213 if (drv_data->running || drv_data->busy) {
1214 spin_unlock_irqrestore(&drv_data->lock, flags);
1218 drv_data->running = true;
1219 drv_data->cur_msg = NULL;
1220 drv_data->cur_transfer = NULL;
1221 drv_data->cur_chip = NULL;
1222 spin_unlock_irqrestore(&drv_data->lock, flags);
1224 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1229 static inline int bfin_spi_stop_queue(struct master_data *drv_data)
1231 unsigned long flags;
1232 unsigned limit = 500;
1235 spin_lock_irqsave(&drv_data->lock, flags);
1238 * This is a bit lame, but is optimized for the common execution path.
1239 * A wait_queue on the drv_data->busy could be used, but then the common
1240 * execution path (pump_messages) would be required to call wake_up or
1241 * friends on every SPI message. Do this instead
1243 drv_data->running = false;
1244 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1245 spin_unlock_irqrestore(&drv_data->lock, flags);
1247 spin_lock_irqsave(&drv_data->lock, flags);
1250 if (!list_empty(&drv_data->queue) || drv_data->busy)
1253 spin_unlock_irqrestore(&drv_data->lock, flags);
1258 static inline int bfin_spi_destroy_queue(struct master_data *drv_data)
1262 status = bfin_spi_stop_queue(drv_data);
1266 destroy_workqueue(drv_data->workqueue);
1271 static int __init bfin_spi_probe(struct platform_device *pdev)
1273 struct device *dev = &pdev->dev;
1274 struct bfin5xx_spi_master *platform_info;
1275 struct spi_master *master;
1276 struct master_data *drv_data;
1277 struct resource *res;
1280 platform_info = dev->platform_data;
1282 /* Allocate master with space for drv_data */
1283 master = spi_alloc_master(dev, sizeof(*drv_data));
1285 dev_err(&pdev->dev, "can not alloc spi_master\n");
1289 drv_data = spi_master_get_devdata(master);
1290 drv_data->master = master;
1291 drv_data->master_info = platform_info;
1292 drv_data->pdev = pdev;
1293 drv_data->pin_req = platform_info->pin_req;
1295 /* the spi->mode bits supported by this driver: */
1296 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1298 master->bus_num = pdev->id;
1299 master->num_chipselect = platform_info->num_chipselect;
1300 master->cleanup = bfin_spi_cleanup;
1301 master->setup = bfin_spi_setup;
1302 master->transfer = bfin_spi_transfer;
1304 /* Find and map our resources */
1305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1307 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1309 goto out_error_get_res;
1312 drv_data->regs_base = ioremap(res->start, resource_size(res));
1313 if (drv_data->regs_base == NULL) {
1314 dev_err(dev, "Cannot map IO\n");
1316 goto out_error_ioremap;
1319 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1321 dev_err(dev, "No DMA channel specified\n");
1323 goto out_error_free_io;
1325 drv_data->dma_channel = res->start;
1327 drv_data->spi_irq = platform_get_irq(pdev, 0);
1328 if (drv_data->spi_irq < 0) {
1329 dev_err(dev, "No spi pio irq specified\n");
1331 goto out_error_free_io;
1334 /* Initial and start queue */
1335 status = bfin_spi_init_queue(drv_data);
1337 dev_err(dev, "problem initializing queue\n");
1338 goto out_error_queue_alloc;
1341 status = bfin_spi_start_queue(drv_data);
1343 dev_err(dev, "problem starting queue\n");
1344 goto out_error_queue_alloc;
1347 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1349 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1350 goto out_error_queue_alloc;
1353 /* Reset SPI registers. If these registers were used by the boot loader,
1354 * the sky may fall on your head if you enable the dma controller.
1356 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1357 write_FLAG(drv_data, 0xFF00);
1359 /* Register with the SPI framework */
1360 platform_set_drvdata(pdev, drv_data);
1361 status = spi_register_master(master);
1363 dev_err(dev, "problem registering spi master\n");
1364 goto out_error_queue_alloc;
1367 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1368 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1369 drv_data->dma_channel);
1372 out_error_queue_alloc:
1373 bfin_spi_destroy_queue(drv_data);
1375 iounmap((void *) drv_data->regs_base);
1378 spi_master_put(master);
1383 /* stop hardware and remove the driver */
1384 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1386 struct master_data *drv_data = platform_get_drvdata(pdev);
1392 /* Remove the queue */
1393 status = bfin_spi_destroy_queue(drv_data);
1397 /* Disable the SSP at the peripheral and SOC level */
1398 bfin_spi_disable(drv_data);
1401 if (drv_data->master_info->enable_dma) {
1402 if (dma_channel_active(drv_data->dma_channel))
1403 free_dma(drv_data->dma_channel);
1406 if (drv_data->irq_requested) {
1407 free_irq(drv_data->spi_irq, drv_data);
1408 drv_data->irq_requested = 0;
1411 /* Disconnect from the SPI framework */
1412 spi_unregister_master(drv_data->master);
1414 peripheral_free_list(drv_data->pin_req);
1416 /* Prevent double remove */
1417 platform_set_drvdata(pdev, NULL);
1423 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1425 struct master_data *drv_data = platform_get_drvdata(pdev);
1428 status = bfin_spi_stop_queue(drv_data);
1432 drv_data->ctrl_reg = read_CTRL(drv_data);
1433 drv_data->flag_reg = read_FLAG(drv_data);
1436 * reset SPI_CTL and SPI_FLG registers
1438 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1439 write_FLAG(drv_data, 0xFF00);
1444 static int bfin_spi_resume(struct platform_device *pdev)
1446 struct master_data *drv_data = platform_get_drvdata(pdev);
1449 write_CTRL(drv_data, drv_data->ctrl_reg);
1450 write_FLAG(drv_data, drv_data->flag_reg);
1452 /* Start the queue running */
1453 status = bfin_spi_start_queue(drv_data);
1455 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1462 #define bfin_spi_suspend NULL
1463 #define bfin_spi_resume NULL
1464 #endif /* CONFIG_PM */
1466 MODULE_ALIAS("platform:bfin-spi");
1467 static struct platform_driver bfin_spi_driver = {
1470 .owner = THIS_MODULE,
1472 .suspend = bfin_spi_suspend,
1473 .resume = bfin_spi_resume,
1474 .remove = __devexit_p(bfin_spi_remove),
1477 static int __init bfin_spi_init(void)
1479 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1481 module_init(bfin_spi_init);
1483 static void __exit bfin_spi_exit(void)
1485 platform_driver_unregister(&bfin_spi_driver);
1487 module_exit(bfin_spi_exit);