Pileus Git - ~andy/linux/blob - drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of.h>
  32 #include <linux/of_gpio.h>
  33
  34 #include <mach/dma.h>
  35 #include <linux/platform_data/spi-s3c64xx.h>
  36
  37 #define MAX_SPI_PORTS           3
  38
  39 /* Registers and bit-fields */
  40
  41 #define S3C64XX_SPI_CH_CFG              0x00
  42 #define S3C64XX_SPI_CLK_CFG             0x04
  43 #define S3C64XX_SPI_MODE_CFG    0x08
  44 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  45 #define S3C64XX_SPI_INT_EN              0x10
  46 #define S3C64XX_SPI_STATUS              0x14
  47 #define S3C64XX_SPI_TX_DATA             0x18
  48 #define S3C64XX_SPI_RX_DATA             0x1C
  49 #define S3C64XX_SPI_PACKET_CNT  0x20
  50 #define S3C64XX_SPI_PENDING_CLR 0x24
  51 #define S3C64XX_SPI_SWAP_CFG    0x28
  52 #define S3C64XX_SPI_FB_CLK              0x2C
  53
  54 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  55 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  56 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  57 #define S3C64XX_SPI_CPOL_L              (1<<3)
  58 #define S3C64XX_SPI_CPHA_B              (1<<2)
  59 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  60 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  61
  62 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  63 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  64 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  65 #define S3C64XX_SPI_PSR_MASK            0xff
  66
  67 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  68 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  69 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  70 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  71 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  72 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  73 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  74 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  75 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  76 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  77 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  78
  79 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  80 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  81
  82 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  83 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  84 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  85 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  86 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  87 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  88 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  89
  90 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  91 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  92 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  93 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  94 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  95 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  96
  97 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  98
  99 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 100 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 101 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 102 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 103 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 104
 105 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 106 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 107 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 108 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 109 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 110 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 111 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 112 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 113
 114 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 115
 116 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 117 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 118                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 121                                         FIFO_LVL_MASK(i))
 122
 123 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 124 #define S3C64XX_SPI_TRAILCNT_OFF        19
 125
 126 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 127
 128 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 129
 130 #define RXBUSY    (1<<2)
 131 #define TXBUSY    (1<<3)
 132
 133 struct s3c64xx_spi_dma_data {
 134         unsigned                ch;
 135         enum dma_transfer_direction direction;
 136         enum dma_ch     dmach;
 137 };
 138
 139 /**
 140  * struct s3c64xx_spi_info - SPI Controller hardware info
 141  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 142  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 143  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 144  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 145  * @clk_from_cmu: True, if the controller does not include a clock mux and
 146  *      prescaler unit.
 147  *
 148  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 149  * differ in some aspects such as the size of the fifo and spi bus clock
 150  * setup. Such differences are specified to the driver using this structure
 151  * which is provided as driver data to the driver.
 152  */
 153 struct s3c64xx_spi_port_config {
 154         int     fifo_lvl_mask[MAX_SPI_PORTS];
 155         int     rx_lvl_offset;
 156         int     tx_st_done;
 157         bool    high_speed;
 158         bool    clk_from_cmu;
 159 };
 160
 161 /**
 162  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 163  * @clk: Pointer to the spi clock.
 164  * @src_clk: Pointer to the clock used to generate SPI signals.
 165  * @master: Pointer to the SPI Protocol master.
 166  * @cntrlr_info: Platform specific data for the controller this driver manages.
 167  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 168  * @queue: To log SPI xfer requests.
 169  * @lock: Controller specific lock.
 170  * @state: Set of FLAGS to indicate status.
 171  * @rx_dmach: Controller's DMA channel for Rx.
 172  * @tx_dmach: Controller's DMA channel for Tx.
 173  * @sfr_start: BUS address of SPI controller regs.
 174  * @regs: Pointer to ioremap'ed controller registers.
 175  * @irq: interrupt
 176  * @xfer_completion: To indicate completion of xfer task.
 177  * @cur_mode: Stores the active configuration of the controller.
 178  * @cur_bpw: Stores the active bits per word settings.
 179  * @cur_speed: Stores the active xfer clock speed.
 180  */
 181 struct s3c64xx_spi_driver_data {
 182         void __iomem                    *regs;
 183         struct clk                      *clk;
 184         struct clk                      *src_clk;
 185         struct platform_device          *pdev;
 186         struct spi_master               *master;
 187         struct s3c64xx_spi_info  *cntrlr_info;
 188         struct spi_device               *tgl_spi;
 189         struct list_head                queue;
 190         spinlock_t                      lock;
 191         unsigned long                   sfr_start;
 192         struct completion               xfer_completion;
 193         unsigned                        state;
 194         unsigned                        cur_mode, cur_bpw;
 195         unsigned                        cur_speed;
 196         struct s3c64xx_spi_dma_data     rx_dma;
 197         struct s3c64xx_spi_dma_data     tx_dma;
 198         struct samsung_dma_ops          *ops;
 199         struct s3c64xx_spi_port_config  *port_conf;
 200         unsigned int                    port_id;
 201         unsigned long                   gpios[4];
 202 };
 203
 204 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 205         .name = "samsung-spi-dma",
 206 };
 207
 208 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 209 {
 210         void __iomem *regs = sdd->regs;
 211         unsigned long loops;
 212         u32 val;
 213
 214         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 215
 216         val = readl(regs + S3C64XX_SPI_CH_CFG);
 217         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 218         writel(val, regs + S3C64XX_SPI_CH_CFG);
 219
 220         val = readl(regs + S3C64XX_SPI_CH_CFG);
 221         val |= S3C64XX_SPI_CH_SW_RST;
 222         val &= ~S3C64XX_SPI_CH_HS_EN;
 223         writel(val, regs + S3C64XX_SPI_CH_CFG);
 224
 225         /* Flush TxFIFO*/
 226         loops = msecs_to_loops(1);
 227         do {
 228                 val = readl(regs + S3C64XX_SPI_STATUS);
 229         } while (TX_FIFO_LVL(val, sdd) && loops--);
 230
 231         if (loops == 0)
 232                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 233
 234         /* Flush RxFIFO*/
 235         loops = msecs_to_loops(1);
 236         do {
 237                 val = readl(regs + S3C64XX_SPI_STATUS);
 238                 if (RX_FIFO_LVL(val, sdd))
 239                         readl(regs + S3C64XX_SPI_RX_DATA);
 240                 else
 241                         break;
 242         } while (loops--);
 243
 244         if (loops == 0)
 245                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 246
 247         val = readl(regs + S3C64XX_SPI_CH_CFG);
 248         val &= ~S3C64XX_SPI_CH_SW_RST;
 249         writel(val, regs + S3C64XX_SPI_CH_CFG);
 250
 251         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 252         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 253         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 254 }
 255
 256 static void s3c64xx_spi_dmacb(void *data)
 257 {
 258         struct s3c64xx_spi_driver_data *sdd;
 259         struct s3c64xx_spi_dma_data *dma = data;
 260         unsigned long flags;
 261
 262         if (dma->direction == DMA_DEV_TO_MEM)
 263                 sdd = container_of(data,
 264                         struct s3c64xx_spi_driver_data, rx_dma);
 265         else
 266                 sdd = container_of(data,
 267                         struct s3c64xx_spi_driver_data, tx_dma);
 268
 269         spin_lock_irqsave(&sdd->lock, flags);
 270
 271         if (dma->direction == DMA_DEV_TO_MEM) {
 272                 sdd->state &= ~RXBUSY;
 273                 if (!(sdd->state & TXBUSY))
 274                         complete(&sdd->xfer_completion);
 275         } else {
 276                 sdd->state &= ~TXBUSY;
 277                 if (!(sdd->state & RXBUSY))
 278                         complete(&sdd->xfer_completion);
 279         }
 280
 281         spin_unlock_irqrestore(&sdd->lock, flags);
 282 }
 283
 284 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 285                                         unsigned len, dma_addr_t buf)
 286 {
 287         struct s3c64xx_spi_driver_data *sdd;
 288         struct samsung_dma_prep info;
 289         struct samsung_dma_config config;
 290
 291         if (dma->direction == DMA_DEV_TO_MEM) {
 292                 sdd = container_of((void *)dma,
 293                         struct s3c64xx_spi_driver_data, rx_dma);
 294                 config.direction = sdd->rx_dma.direction;
 295                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 296                 config.width = sdd->cur_bpw / 8;
 297                 sdd->ops->config(sdd->rx_dma.ch, &config);
 298         } else {
 299                 sdd = container_of((void *)dma,
 300                         struct s3c64xx_spi_driver_data, tx_dma);
 301                 config.direction =  sdd->tx_dma.direction;
 302                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 303                 config.width = sdd->cur_bpw / 8;
 304                 sdd->ops->config(sdd->tx_dma.ch, &config);
 305         }
 306
 307         info.cap = DMA_SLAVE;
 308         info.len = len;
 309         info.fp = s3c64xx_spi_dmacb;
 310         info.fp_param = dma;
 311         info.direction = dma->direction;
 312         info.buf = buf;
 313
 314         sdd->ops->prepare(dma->ch, &info);
 315         sdd->ops->trigger(dma->ch);
 316 }
 317
 318 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 319 {
 320         struct samsung_dma_req req;
 321         struct device *dev = &sdd->pdev->dev;
 322
 323         sdd->ops = samsung_dma_get_ops();
 324
 325         req.cap = DMA_SLAVE;
 326         req.client = &s3c64xx_spi_dma_client;
 327
 328         sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req, dev, "rx");
 329         sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req, dev, "tx");
 330
 331         return 1;
 332 }
 333
 334 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 335                                 struct spi_device *spi,
 336                                 struct spi_transfer *xfer, int dma_mode)
 337 {
 338         void __iomem *regs = sdd->regs;
 339         u32 modecfg, chcfg;
 340
 341         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 342         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 343
 344         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 345         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 346
 347         if (dma_mode) {
 348                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 349         } else {
 350                 /* Always shift in data in FIFO, even if xfer is Tx only,
 351                  * this helps setting PCKT_CNT value for generating clocks
 352                  * as exactly needed.
 353                  */
 354                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 355                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 356                                         | S3C64XX_SPI_PACKET_CNT_EN,
 357                                         regs + S3C64XX_SPI_PACKET_CNT);
 358         }
 359
 360         if (xfer->tx_buf != NULL) {
 361                 sdd->state |= TXBUSY;
 362                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 363                 if (dma_mode) {
 364                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 365                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 366                 } else {
 367                         switch (sdd->cur_bpw) {
 368                         case 32:
 369                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 370                                         xfer->tx_buf, xfer->len / 4);
 371                                 break;
 372                         case 16:
 373                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 374                                         xfer->tx_buf, xfer->len / 2);
 375                                 break;
 376                         default:
 377                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 378                                         xfer->tx_buf, xfer->len);
 379                                 break;
 380                         }
 381                 }
 382         }
 383
 384         if (xfer->rx_buf != NULL) {
 385                 sdd->state |= RXBUSY;
 386
 387                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 388                                         && !(sdd->cur_mode & SPI_CPHA))
 389                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 390
 391                 if (dma_mode) {
 392                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 393                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 394                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 395                                         | S3C64XX_SPI_PACKET_CNT_EN,
 396                                         regs + S3C64XX_SPI_PACKET_CNT);
 397                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 398                 }
 399         }
 400
 401         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 402         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 403 }
 404
 405 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 406                                                 struct spi_device *spi)
 407 {
 408         struct s3c64xx_spi_csinfo *cs;
 409
 410         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 411                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 412                         /* Deselect the last toggled device */
 413                         cs = sdd->tgl_spi->controller_data;
 414                         gpio_set_value(cs->line,
 415                                 spi->mode & SPI_CS_HIGH ? 0 : 1);
 416                 }
 417                 sdd->tgl_spi = NULL;
 418         }
 419
 420         cs = spi->controller_data;
 421         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 422 }
 423
 424 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 425                                 struct spi_transfer *xfer, int dma_mode)
 426 {
 427         void __iomem *regs = sdd->regs;
 428         unsigned long val;
 429         int ms;
 430
 431         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 432         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 433         ms += 10; /* some tolerance */
 434
 435         if (dma_mode) {
 436                 val = msecs_to_jiffies(ms) + 10;
 437                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 438         } else {
 439                 u32 status;
 440                 val = msecs_to_loops(ms);
 441                 do {
 442                         status = readl(regs + S3C64XX_SPI_STATUS);
 443                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 444         }
 445
 446         if (!val)
 447                 return -EIO;
 448
 449         if (dma_mode) {
 450                 u32 status;
 451
 452                 /*
 453                  * DmaTx returns after simply writing data in the FIFO,
 454                  * w/o waiting for real transmission on the bus to finish.
 455                  * DmaRx returns only after Dma read data from FIFO which
 456                  * needs bus transmission to finish, so we don't worry if
 457                  * Xfer involved Rx(with or without Tx).
 458                  */
 459                 if (xfer->rx_buf == NULL) {
 460                         val = msecs_to_loops(10);
 461                         status = readl(regs + S3C64XX_SPI_STATUS);
 462                         while ((TX_FIFO_LVL(status, sdd)
 463                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 464                                         && --val) {
 465                                 cpu_relax();
 466                                 status = readl(regs + S3C64XX_SPI_STATUS);
 467                         }
 468
 469                         if (!val)
 470                                 return -EIO;
 471                 }
 472         } else {
 473                 /* If it was only Tx */
 474                 if (xfer->rx_buf == NULL) {
 475                         sdd->state &= ~TXBUSY;
 476                         return 0;
 477                 }
 478
 479                 switch (sdd->cur_bpw) {
 480                 case 32:
 481                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 482                                 xfer->rx_buf, xfer->len / 4);
 483                         break;
 484                 case 16:
 485                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 486                                 xfer->rx_buf, xfer->len / 2);
 487                         break;
 488                 default:
 489                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 490                                 xfer->rx_buf, xfer->len);
 491                         break;
 492                 }
 493                 sdd->state &= ~RXBUSY;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 500                                                 struct spi_device *spi)
 501 {
 502         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 503
 504         if (sdd->tgl_spi == spi)
 505                 sdd->tgl_spi = NULL;
 506
 507         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 508 }
 509
 510 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 511 {
 512         void __iomem *regs = sdd->regs;
 513         u32 val;
 514
 515         /* Disable Clock */
 516         if (sdd->port_conf->clk_from_cmu) {
 517                 clk_disable_unprepare(sdd->src_clk);
 518         } else {
 519                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 520                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 521                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 522         }
 523
 524         /* Set Polarity and Phase */
 525         val = readl(regs + S3C64XX_SPI_CH_CFG);
 526         val &= ~(S3C64XX_SPI_CH_SLAVE |
 527                         S3C64XX_SPI_CPOL_L |
 528                         S3C64XX_SPI_CPHA_B);
 529
 530         if (sdd->cur_mode & SPI_CPOL)
 531                 val |= S3C64XX_SPI_CPOL_L;
 532
 533         if (sdd->cur_mode & SPI_CPHA)
 534                 val |= S3C64XX_SPI_CPHA_B;
 535
 536         writel(val, regs + S3C64XX_SPI_CH_CFG);
 537
 538         /* Set Channel & DMA Mode */
 539         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 540         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 541                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 542
 543         switch (sdd->cur_bpw) {
 544         case 32:
 545                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 546                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 547                 break;
 548         case 16:
 549                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 550                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 551                 break;
 552         default:
 553                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 554                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 555                 break;
 556         }
 557
 558         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 559
 560         if (sdd->port_conf->clk_from_cmu) {
 561                 /* Configure Clock */
 562                 /* There is half-multiplier before the SPI */
 563                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 564                 /* Enable Clock */
 565                 clk_prepare_enable(sdd->src_clk);
 566         } else {
 567                 /* Configure Clock */
 568                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 569                 val &= ~S3C64XX_SPI_PSR_MASK;
 570                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 571                                 & S3C64XX_SPI_PSR_MASK);
 572                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 573
 574                 /* Enable Clock */
 575                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 576                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 577                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 578         }
 579 }
 580
 581 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 582
 583 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 584                                                 struct spi_message *msg)
 585 {
 586         struct device *dev = &sdd->pdev->dev;
 587         struct spi_transfer *xfer;
 588
 589         if (msg->is_dma_mapped)
 590                 return 0;
 591
 592         /* First mark all xfer unmapped */
 593         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 594                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 595                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 596         }
 597
 598         /* Map until end or first fail */
 599         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 600
 601                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 602                         continue;
 603
 604                 if (xfer->tx_buf != NULL) {
 605                         xfer->tx_dma = dma_map_single(dev,
 606                                         (void *)xfer->tx_buf, xfer->len,
 607                                         DMA_TO_DEVICE);
 608                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 609                                 dev_err(dev, "dma_map_single Tx failed\n");
 610                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 611                                 return -ENOMEM;
 612                         }
 613                 }
 614
 615                 if (xfer->rx_buf != NULL) {
 616                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 617                                                 xfer->len, DMA_FROM_DEVICE);
 618                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 619                                 dev_err(dev, "dma_map_single Rx failed\n");
 620                                 dma_unmap_single(dev, xfer->tx_dma,
 621                                                 xfer->len, DMA_TO_DEVICE);
 622                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 623                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 624                                 return -ENOMEM;
 625                         }
 626                 }
 627         }
 628
 629         return 0;
 630 }
 631
 632 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 633                                                 struct spi_message *msg)
 634 {
 635         struct device *dev = &sdd->pdev->dev;
 636         struct spi_transfer *xfer;
 637
 638         if (msg->is_dma_mapped)
 639                 return;
 640
 641         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 642
 643                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 644                         continue;
 645
 646                 if (xfer->rx_buf != NULL
 647                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 648                         dma_unmap_single(dev, xfer->rx_dma,
 649                                                 xfer->len, DMA_FROM_DEVICE);
 650
 651                 if (xfer->tx_buf != NULL
 652                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 653                         dma_unmap_single(dev, xfer->tx_dma,
 654                                                 xfer->len, DMA_TO_DEVICE);
 655         }
 656 }
 657
 658 static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 659                                             struct spi_message *msg)
 660 {
 661         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 662         struct spi_device *spi = msg->spi;
 663         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 664         struct spi_transfer *xfer;
 665         int status = 0, cs_toggle = 0;
 666         u32 speed;
 667         u8 bpw;
 668
 669         /* If Master's(controller) state differs from that needed by Slave */
 670         if (sdd->cur_speed != spi->max_speed_hz
 671                         || sdd->cur_mode != spi->mode
 672                         || sdd->cur_bpw != spi->bits_per_word) {
 673                 sdd->cur_bpw = spi->bits_per_word;
 674                 sdd->cur_speed = spi->max_speed_hz;
 675                 sdd->cur_mode = spi->mode;
 676                 s3c64xx_spi_config(sdd);
 677         }
 678
 679         /* Map all the transfers if needed */
 680         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 681                 dev_err(&spi->dev,
 682                         "Xfer: Unable to map message buffers!\n");
 683                 status = -ENOMEM;
 684                 goto out;
 685         }
 686
 687         /* Configure feedback delay */
 688         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 689
 690         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 691
 692                 unsigned long flags;
 693                 int use_dma;
 694
 695                 INIT_COMPLETION(sdd->xfer_completion);
 696
 697                 /* Only BPW and Speed may change across transfers */
 698                 bpw = xfer->bits_per_word ? : spi->bits_per_word;
 699                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 700
 701                 if (xfer->len % (bpw / 8)) {
 702                         dev_err(&spi->dev,
 703                                 "Xfer length(%u) not a multiple of word size(%u)\n",
 704                                 xfer->len, bpw / 8);
 705                         status = -EIO;
 706                         goto out;
 707                 }
 708
 709                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 710                         sdd->cur_bpw = bpw;
 711                         sdd->cur_speed = speed;
 712                         s3c64xx_spi_config(sdd);
 713                 }
 714
 715                 /* Polling method for xfers not bigger than FIFO capacity */
 716                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 717                         use_dma = 0;
 718                 else
 719                         use_dma = 1;
 720
 721                 spin_lock_irqsave(&sdd->lock, flags);
 722
 723                 /* Pending only which is to be done */
 724                 sdd->state &= ~RXBUSY;
 725                 sdd->state &= ~TXBUSY;
 726
 727                 enable_datapath(sdd, spi, xfer, use_dma);
 728
 729                 /* Slave Select */
 730                 enable_cs(sdd, spi);
 731
 732                 /* Start the signals */
 733                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 734
 735                 spin_unlock_irqrestore(&sdd->lock, flags);
 736
 737                 status = wait_for_xfer(sdd, xfer, use_dma);
 738
 739                 /* Quiese the signals */
 740                 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 741                        sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 742
 743                 if (status) {
 744                         dev_err(&spi->dev, "I/O Error: "
 745                                 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 746                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 747                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 748                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 749                                 xfer->len);
 750
 751                         if (use_dma) {
 752                                 if (xfer->tx_buf != NULL
 753                                                 && (sdd->state & TXBUSY))
 754                                         sdd->ops->stop(sdd->tx_dma.ch);
 755                                 if (xfer->rx_buf != NULL
 756                                                 && (sdd->state & RXBUSY))
 757                                         sdd->ops->stop(sdd->rx_dma.ch);
 758                         }
 759
 760                         goto out;
 761                 }
 762
 763                 if (xfer->delay_usecs)
 764                         udelay(xfer->delay_usecs);
 765
 766                 if (xfer->cs_change) {
 767                         /* Hint that the next mssg is gonna be
 768                            for the same device */
 769                         if (list_is_last(&xfer->transfer_list,
 770                                                 &msg->transfers))
 771                                 cs_toggle = 1;
 772                 }
 773
 774                 msg->actual_length += xfer->len;
 775
 776                 flush_fifo(sdd);
 777         }
 778
 779 out:
 780         if (!cs_toggle || status)
 781                 disable_cs(sdd, spi);
 782         else
 783                 sdd->tgl_spi = spi;
 784
 785         s3c64xx_spi_unmap_mssg(sdd, msg);
 786
 787         msg->status = status;
 788
 789         spi_finalize_current_message(master);
 790
 791         return 0;
 792 }
 793
 794 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 795 {
 796         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 797
 798         /* Acquire DMA channels */
 799         while (!acquire_dma(sdd))
 800                 msleep(10);
 801
 802         pm_runtime_get_sync(&sdd->pdev->dev);
 803
 804         return 0;
 805 }
 806
 807 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 808 {
 809         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 810
 811         /* Free DMA channels */
 812         sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
 813         sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
 814
 815         pm_runtime_put(&sdd->pdev->dev);
 816
 817         return 0;
 818 }
 819
 820 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 821                                 struct s3c64xx_spi_driver_data *sdd,
 822                                 struct spi_device *spi)
 823 {
 824         struct s3c64xx_spi_csinfo *cs;
 825         struct device_node *slave_np, *data_np = NULL;
 826         u32 fb_delay = 0;
 827
 828         slave_np = spi->dev.of_node;
 829         if (!slave_np) {
 830                 dev_err(&spi->dev, "device node not found\n");
 831                 return ERR_PTR(-EINVAL);
 832         }
 833
 834         data_np = of_get_child_by_name(slave_np, "controller-data");
 835         if (!data_np) {
 836                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 837                 return ERR_PTR(-EINVAL);
 838         }
 839
 840         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 841         if (!cs) {
 842                 dev_err(&spi->dev, "could not allocate memory for controller"
 843                                         " data\n");
 844                 of_node_put(data_np);
 845                 return ERR_PTR(-ENOMEM);
 846         }
 847
 848         cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
 849         if (!gpio_is_valid(cs->line)) {
 850                 dev_err(&spi->dev, "chip select gpio is not specified or "
 851                                         "invalid\n");
 852                 kfree(cs);
 853                 of_node_put(data_np);
 854                 return ERR_PTR(-EINVAL);
 855         }
 856
 857         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 858         cs->fb_delay = fb_delay;
 859         of_node_put(data_np);
 860         return cs;
 861 }
 862
 863 /*
 864  * Here we only check the validity of requested configuration
 865  * and save the configuration in a local data-structure.
 866  * The controller is actually configured only just before we
 867  * get a message to transfer.
 868  */
 869 static int s3c64xx_spi_setup(struct spi_device *spi)
 870 {
 871         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 872         struct s3c64xx_spi_driver_data *sdd;
 873         struct s3c64xx_spi_info *sci;
 874         struct spi_message *msg;
 875         unsigned long flags;
 876         int err;
 877
 878         sdd = spi_master_get_devdata(spi->master);
 879         if (!cs && spi->dev.of_node) {
 880                 cs = s3c64xx_get_slave_ctrldata(sdd, spi);
 881                 spi->controller_data = cs;
 882         }
 883
 884         if (IS_ERR_OR_NULL(cs)) {
 885                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 886                 return -ENODEV;
 887         }
 888
 889         if (!spi_get_ctldata(spi)) {
 890                 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
 891                                        dev_name(&spi->dev));
 892                 if (err) {
 893                         dev_err(&spi->dev,
 894                                 "Failed to get /CS gpio [%d]: %d\n",
 895                                 cs->line, err);
 896                         goto err_gpio_req;
 897                 }
 898                 spi_set_ctldata(spi, cs);
 899         }
 900
 901         sci = sdd->cntrlr_info;
 902
 903         spin_lock_irqsave(&sdd->lock, flags);
 904
 905         list_for_each_entry(msg, &sdd->queue, queue) {
 906                 /* Is some mssg is already queued for this device */
 907                 if (msg->spi == spi) {
 908                         dev_err(&spi->dev,
 909                                 "setup: attempt while mssg in queue!\n");
 910                         spin_unlock_irqrestore(&sdd->lock, flags);
 911                         err = -EBUSY;
 912                         goto err_msgq;
 913                 }
 914         }
 915
 916         spin_unlock_irqrestore(&sdd->lock, flags);
 917
 918         if (spi->bits_per_word != 8
 919                         && spi->bits_per_word != 16
 920                         && spi->bits_per_word != 32) {
 921                 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
 922                                                         spi->bits_per_word);
 923                 err = -EINVAL;
 924                 goto setup_exit;
 925         }
 926
 927         pm_runtime_get_sync(&sdd->pdev->dev);
 928
 929         /* Check if we can provide the requested rate */
 930         if (!sdd->port_conf->clk_from_cmu) {
 931                 u32 psr, speed;
 932
 933                 /* Max possible */
 934                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 935
 936                 if (spi->max_speed_hz > speed)
 937                         spi->max_speed_hz = speed;
 938
 939                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 940                 psr &= S3C64XX_SPI_PSR_MASK;
 941                 if (psr == S3C64XX_SPI_PSR_MASK)
 942                         psr--;
 943
 944                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 945                 if (spi->max_speed_hz < speed) {
 946                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 947                                 psr++;
 948                         } else {
 949                                 err = -EINVAL;
 950                                 goto setup_exit;
 951                         }
 952                 }
 953
 954                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 955                 if (spi->max_speed_hz >= speed) {
 956                         spi->max_speed_hz = speed;
 957                 } else {
 958                         err = -EINVAL;
 959                         goto setup_exit;
 960                 }
 961         }
 962
 963         pm_runtime_put(&sdd->pdev->dev);
 964         disable_cs(sdd, spi);
 965         return 0;
 966
 967 setup_exit:
 968         /* setup() returns with device de-selected */
 969         disable_cs(sdd, spi);
 970
 971 err_msgq:
 972         gpio_free(cs->line);
 973         spi_set_ctldata(spi, NULL);
 974
 975 err_gpio_req:
 976         if (spi->dev.of_node)
 977                 kfree(cs);
 978
 979         return err;
 980 }
 981
 982 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 983 {
 984         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 985
 986         if (cs) {
 987                 gpio_free(cs->line);
 988                 if (spi->dev.of_node)
 989                         kfree(cs);
 990         }
 991         spi_set_ctldata(spi, NULL);
 992 }
 993
 994 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 995 {
 996         struct s3c64xx_spi_driver_data *sdd = data;
 997         struct spi_master *spi = sdd->master;
 998         unsigned int val;
 999
1000         val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
1001
1002         val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1003                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1004                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1005                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1006
1007         writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1008
1009         if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
1010                 dev_err(&spi->dev, "RX overrun\n");
1011         if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
1012                 dev_err(&spi->dev, "RX underrun\n");
1013         if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
1014                 dev_err(&spi->dev, "TX overrun\n");
1015         if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
1016                 dev_err(&spi->dev, "TX underrun\n");
1017
1018         return IRQ_HANDLED;
1019 }
1020
1021 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1022 {
1023         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1024         void __iomem *regs = sdd->regs;
1025         unsigned int val;
1026
1027         sdd->cur_speed = 0;
1028
1029         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1030
1031         /* Disable Interrupts - we use Polling if not DMA mode */
1032         writel(0, regs + S3C64XX_SPI_INT_EN);
1033
1034         if (!sdd->port_conf->clk_from_cmu)
1035                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1036                                 regs + S3C64XX_SPI_CLK_CFG);
1037         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1038         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1039
1040         /* Clear any irq pending bits */
1041         writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
1042                                 regs + S3C64XX_SPI_PENDING_CLR);
1043
1044         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1045
1046         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1047         val &= ~S3C64XX_SPI_MODE_4BURST;
1048         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1049         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1050         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1051
1052         flush_fifo(sdd);
1053 }
1054
1055 #ifdef CONFIG_OF
1056 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1057 {
1058         struct device *dev = &sdd->pdev->dev;
1059         int idx, gpio, ret;
1060
1061         /* find gpios for mosi, miso and clock lines */
1062         for (idx = 0; idx < 3; idx++) {
1063                 gpio = of_get_gpio(dev->of_node, idx);
1064                 if (!gpio_is_valid(gpio)) {
1065                         dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1066                         goto free_gpio;
1067                 }
1068                 sdd->gpios[idx] = gpio;
1069                 ret = gpio_request(gpio, "spi-bus");
1070                 if (ret) {
1071                         dev_err(dev, "gpio [%d] request failed: %d\n",
1072                                 gpio, ret);
1073                         goto free_gpio;
1074                 }
1075         }
1076         return 0;
1077
1078 free_gpio:
1079         while (--idx >= 0)
1080                 gpio_free(sdd->gpios[idx]);
1081         return -EINVAL;
1082 }
1083
1084 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1085 {
1086         unsigned int idx;
1087         for (idx = 0; idx < 3; idx++)
1088                 gpio_free(sdd->gpios[idx]);
1089 }
1090
1091 static struct s3c64xx_spi_info * s3c64xx_spi_parse_dt(
1092                                                 struct device *dev)
1093 {
1094         struct s3c64xx_spi_info *sci;
1095         u32 temp;
1096
1097         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1098         if (!sci) {
1099                 dev_err(dev, "memory allocation for spi_info failed\n");
1100                 return ERR_PTR(-ENOMEM);
1101         }
1102
1103         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1104                 dev_warn(dev, "spi bus clock parent not specified, using "
1105                                 "clock at index 0 as parent\n");
1106                 sci->src_clk_nr = 0;
1107         } else {
1108                 sci->src_clk_nr = temp;
1109         }
1110
1111         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1112                 dev_warn(dev, "number of chip select lines not specified, "
1113                                 "assuming 1 chip select line\n");
1114                 sci->num_cs = 1;
1115         } else {
1116                 sci->num_cs = temp;
1117         }
1118
1119         return sci;
1120 }
1121 #else
1122 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1123 {
1124         return dev->platform_data;
1125 }
1126
1127 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1128 {
1129         return -EINVAL;
1130 }
1131
1132 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1133 {
1134 }
1135 #endif
1136
1137 static const struct of_device_id s3c64xx_spi_dt_match[];
1138
1139 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1140                                                 struct platform_device *pdev)
1141 {
1142 #ifdef CONFIG_OF
1143         if (pdev->dev.of_node) {
1144                 const struct of_device_id *match;
1145                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1146                 return (struct s3c64xx_spi_port_config *)match->data;
1147         }
1148 #endif
1149         return (struct s3c64xx_spi_port_config *)
1150                          platform_get_device_id(pdev)->driver_data;
1151 }
1152
1153 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1154 {
1155         struct resource *mem_res;
1156         struct resource *res;
1157         struct s3c64xx_spi_driver_data *sdd;
1158         struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
1159         struct spi_master *master;
1160         int ret, irq;
1161         char clk_name[16];
1162
1163         if (!sci && pdev->dev.of_node) {
1164                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1165                 if (IS_ERR(sci))
1166                         return PTR_ERR(sci);
1167         }
1168
1169         if (!sci) {
1170                 dev_err(&pdev->dev, "platform_data missing!\n");
1171                 return -ENODEV;
1172         }
1173
1174         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1175         if (mem_res == NULL) {
1176                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1177                 return -ENXIO;
1178         }
1179
1180         irq = platform_get_irq(pdev, 0);
1181         if (irq < 0) {
1182                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1183                 return irq;
1184         }
1185
1186         master = spi_alloc_master(&pdev->dev,
1187                                 sizeof(struct s3c64xx_spi_driver_data));
1188         if (master == NULL) {
1189                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1190                 return -ENOMEM;
1191         }
1192
1193         platform_set_drvdata(pdev, master);
1194
1195         sdd = spi_master_get_devdata(master);
1196         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1197         sdd->master = master;
1198         sdd->cntrlr_info = sci;
1199         sdd->pdev = pdev;
1200         sdd->sfr_start = mem_res->start;
1201         if (pdev->dev.of_node) {
1202                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1203                 if (ret < 0) {
1204                         dev_err(&pdev->dev, "failed to get alias id, "
1205                                                 "errno %d\n", ret);
1206                         goto err0;
1207                 }
1208                 sdd->port_id = ret;
1209         } else {
1210                 sdd->port_id = pdev->id;
1211         }
1212
1213         sdd->cur_bpw = 8;
1214
1215         if (!sdd->pdev->dev.of_node) {
1216                 res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
1217                 if (!res) {
1218                         dev_err(&pdev->dev, "Unable to get SPI tx dma "
1219                                         "resource\n");
1220                         return -ENXIO;
1221                 }
1222                 sdd->tx_dma.dmach = res->start;
1223
1224                 res = platform_get_resource(pdev, IORESOURCE_DMA,  1);
1225                 if (!res) {
1226                         dev_err(&pdev->dev, "Unable to get SPI rx dma "
1227                                         "resource\n");
1228                         return -ENXIO;
1229                 }
1230                 sdd->rx_dma.dmach = res->start;
1231         }
1232
1233         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1234         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1235
1236         master->dev.of_node = pdev->dev.of_node;
1237         master->bus_num = sdd->port_id;
1238         master->setup = s3c64xx_spi_setup;
1239         master->cleanup = s3c64xx_spi_cleanup;
1240         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1241         master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1242         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1243         master->num_chipselect = sci->num_cs;
1244         master->dma_alignment = 8;
1245         /* the spi->mode bits understood by this driver: */
1246         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1247
1248         sdd->regs = devm_request_and_ioremap(&pdev->dev, mem_res);
1249         if (sdd->regs == NULL) {
1250                 dev_err(&pdev->dev, "Unable to remap IO\n");
1251                 ret = -ENXIO;
1252                 goto err1;
1253         }
1254
1255         if (!sci->cfg_gpio && pdev->dev.of_node) {
1256                 if (s3c64xx_spi_parse_dt_gpio(sdd))
1257                         return -EBUSY;
1258         } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
1259                 dev_err(&pdev->dev, "Unable to config gpio\n");
1260                 ret = -EBUSY;
1261                 goto err2;
1262         }
1263
1264         /* Setup clocks */
1265         sdd->clk = clk_get(&pdev->dev, "spi");
1266         if (IS_ERR(sdd->clk)) {
1267                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1268                 ret = PTR_ERR(sdd->clk);
1269                 goto err3;
1270         }
1271
1272         if (clk_prepare_enable(sdd->clk)) {
1273                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1274                 ret = -EBUSY;
1275                 goto err4;
1276         }
1277
1278         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1279         sdd->src_clk = clk_get(&pdev->dev, clk_name);
1280         if (IS_ERR(sdd->src_clk)) {
1281                 dev_err(&pdev->dev,
1282                         "Unable to acquire clock '%s'\n", clk_name);
1283                 ret = PTR_ERR(sdd->src_clk);
1284                 goto err5;
1285         }
1286
1287         if (clk_prepare_enable(sdd->src_clk)) {
1288                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1289                 ret = -EBUSY;
1290                 goto err6;
1291         }
1292
1293         /* Setup Deufult Mode */
1294         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1295
1296         spin_lock_init(&sdd->lock);
1297         init_completion(&sdd->xfer_completion);
1298         INIT_LIST_HEAD(&sdd->queue);
1299
1300         ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd);
1301         if (ret != 0) {
1302                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1303                         irq, ret);
1304                 goto err7;
1305         }
1306
1307         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1308                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1309                sdd->regs + S3C64XX_SPI_INT_EN);
1310
1311         if (spi_register_master(master)) {
1312                 dev_err(&pdev->dev, "cannot register SPI master\n");
1313                 ret = -EBUSY;
1314                 goto err8;
1315         }
1316
1317         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1318                                         "with %d Slaves attached\n",
1319                                         sdd->port_id, master->num_chipselect);
1320         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1321                                         mem_res->end, mem_res->start,
1322                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1323
1324         pm_runtime_enable(&pdev->dev);
1325
1326         return 0;
1327
1328 err8:
1329         free_irq(irq, sdd);
1330 err7:
1331         clk_disable_unprepare(sdd->src_clk);
1332 err6:
1333         clk_put(sdd->src_clk);
1334 err5:
1335         clk_disable_unprepare(sdd->clk);
1336 err4:
1337         clk_put(sdd->clk);
1338 err3:
1339         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1340                 s3c64xx_spi_dt_gpio_free(sdd);
1341 err2:
1342 err1:
1343 err0:
1344         platform_set_drvdata(pdev, NULL);
1345         spi_master_put(master);
1346
1347         return ret;
1348 }
1349
1350 static int s3c64xx_spi_remove(struct platform_device *pdev)
1351 {
1352         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1353         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1354
1355         pm_runtime_disable(&pdev->dev);
1356
1357         spi_unregister_master(master);
1358
1359         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1360
1361         free_irq(platform_get_irq(pdev, 0), sdd);
1362
1363         clk_disable_unprepare(sdd->src_clk);
1364         clk_put(sdd->src_clk);
1365
1366         clk_disable_unprepare(sdd->clk);
1367         clk_put(sdd->clk);
1368
1369         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1370                 s3c64xx_spi_dt_gpio_free(sdd);
1371
1372         platform_set_drvdata(pdev, NULL);
1373         spi_master_put(master);
1374
1375         return 0;
1376 }
1377
1378 #ifdef CONFIG_PM
1379 static int s3c64xx_spi_suspend(struct device *dev)
1380 {
1381         struct spi_master *master = dev_get_drvdata(dev);
1382         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1383
1384         spi_master_suspend(master);
1385
1386         /* Disable the clock */
1387         clk_disable_unprepare(sdd->src_clk);
1388         clk_disable_unprepare(sdd->clk);
1389
1390         if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1391                 s3c64xx_spi_dt_gpio_free(sdd);
1392
1393         sdd->cur_speed = 0; /* Output Clock is stopped */
1394
1395         return 0;
1396 }
1397
1398 static int s3c64xx_spi_resume(struct device *dev)
1399 {
1400         struct spi_master *master = dev_get_drvdata(dev);
1401         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1402         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1403
1404         if (!sci->cfg_gpio && dev->of_node)
1405                 s3c64xx_spi_parse_dt_gpio(sdd);
1406         else
1407                 sci->cfg_gpio();
1408
1409         /* Enable the clock */
1410         clk_prepare_enable(sdd->src_clk);
1411         clk_prepare_enable(sdd->clk);
1412
1413         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1414
1415         spi_master_resume(master);
1416
1417         return 0;
1418 }
1419 #endif /* CONFIG_PM */
1420
1421 #ifdef CONFIG_PM_RUNTIME
1422 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1423 {
1424         struct spi_master *master = dev_get_drvdata(dev);
1425         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1426
1427         clk_disable_unprepare(sdd->clk);
1428         clk_disable_unprepare(sdd->src_clk);
1429
1430         return 0;
1431 }
1432
1433 static int s3c64xx_spi_runtime_resume(struct device *dev)
1434 {
1435         struct spi_master *master = dev_get_drvdata(dev);
1436         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1437
1438         clk_prepare_enable(sdd->src_clk);
1439         clk_prepare_enable(sdd->clk);
1440
1441         return 0;
1442 }
1443 #endif /* CONFIG_PM_RUNTIME */
1444
1445 static const struct dev_pm_ops s3c64xx_spi_pm = {
1446         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1447         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1448                            s3c64xx_spi_runtime_resume, NULL)
1449 };
1450
1451 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1452         .fifo_lvl_mask  = { 0x7f },
1453         .rx_lvl_offset  = 13,
1454         .tx_st_done     = 21,
1455         .high_speed     = true,
1456 };
1457
1458 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1459         .fifo_lvl_mask  = { 0x7f, 0x7F },
1460         .rx_lvl_offset  = 13,
1461         .tx_st_done     = 21,
1462 };
1463
1464 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1465         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1466         .rx_lvl_offset  = 15,
1467         .tx_st_done     = 25,
1468 };
1469
1470 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1471         .fifo_lvl_mask  = { 0x7f, 0x7F },
1472         .rx_lvl_offset  = 13,
1473         .tx_st_done     = 21,
1474         .high_speed     = true,
1475 };
1476
1477 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1478         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1479         .rx_lvl_offset  = 15,
1480         .tx_st_done     = 25,
1481         .high_speed     = true,
1482 };
1483
1484 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1485         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1486         .rx_lvl_offset  = 15,
1487         .tx_st_done     = 25,
1488         .high_speed     = true,
1489         .clk_from_cmu   = true,
1490 };
1491
1492 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1493         {
1494                 .name           = "s3c2443-spi",
1495                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1496         }, {
1497                 .name           = "s3c6410-spi",
1498                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1499         }, {
1500                 .name           = "s5p64x0-spi",
1501                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1502         }, {
1503                 .name           = "s5pc100-spi",
1504                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1505         }, {
1506                 .name           = "s5pv210-spi",
1507                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1508         }, {
1509                 .name           = "exynos4210-spi",
1510                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1511         },
1512         { },
1513 };
1514
1515 #ifdef CONFIG_OF
1516 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1517         { .compatible = "samsung,exynos4210-spi",
1518                         .data = (void *)&exynos4_spi_port_config,
1519         },
1520         { },
1521 };
1522 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1523 #endif /* CONFIG_OF */
1524
1525 static struct platform_driver s3c64xx_spi_driver = {
1526         .driver = {
1527                 .name   = "s3c64xx-spi",
1528                 .owner = THIS_MODULE,
1529                 .pm = &s3c64xx_spi_pm,
1530                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1531         },
1532         .remove = s3c64xx_spi_remove,
1533         .id_table = s3c64xx_spi_driver_ids,
1534 };
1535 MODULE_ALIAS("platform:s3c64xx-spi");
1536
1537 static int __init s3c64xx_spi_init(void)
1538 {
1539         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1540 }
1541 subsys_initcall(s3c64xx_spi_init);
1542
1543 static void __exit s3c64xx_spi_exit(void)
1544 {
1545         platform_driver_unregister(&s3c64xx_spi_driver);
1546 }
1547 module_exit(s3c64xx_spi_exit);
1548
1549 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1550 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1551 MODULE_LICENSE("GPL");