Pileus Git - ~andy/linux/blob - drivers/spi/spi-rspi.c

   1 /*
   2  * SH RSPI driver
   3  *
   4  * Copyright (C) 2012  Renesas Solutions Corp.
   5  *
   6  * Based on spi-sh.c:
   7  * Copyright (C) 2011 Renesas Solutions Corp.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/list.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/io.h>
  33 #include <linux/clk.h>
  34 #include <linux/dmaengine.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/sh_dma.h>
  37 #include <linux/spi/spi.h>
  38 #include <linux/spi/rspi.h>
  39
  40 #define RSPI_SPCR               0x00
  41 #define RSPI_SSLP               0x01
  42 #define RSPI_SPPCR              0x02
  43 #define RSPI_SPSR               0x03
  44 #define RSPI_SPDR               0x04
  45 #define RSPI_SPSCR              0x08
  46 #define RSPI_SPSSR              0x09
  47 #define RSPI_SPBR               0x0a
  48 #define RSPI_SPDCR              0x0b
  49 #define RSPI_SPCKD              0x0c
  50 #define RSPI_SSLND              0x0d
  51 #define RSPI_SPND               0x0e
  52 #define RSPI_SPCR2              0x0f
  53 #define RSPI_SPCMD0             0x10
  54 #define RSPI_SPCMD1             0x12
  55 #define RSPI_SPCMD2             0x14
  56 #define RSPI_SPCMD3             0x16
  57 #define RSPI_SPCMD4             0x18
  58 #define RSPI_SPCMD5             0x1a
  59 #define RSPI_SPCMD6             0x1c
  60 #define RSPI_SPCMD7             0x1e
  61
  62 /*qspi only */
  63 #define QSPI_SPBFCR             0x18
  64 #define QSPI_SPBDCR             0x1a
  65 #define QSPI_SPBMUL0            0x1c
  66 #define QSPI_SPBMUL1            0x20
  67 #define QSPI_SPBMUL2            0x24
  68 #define QSPI_SPBMUL3            0x28
  69
  70 /* SPCR */
  71 #define SPCR_SPRIE              0x80
  72 #define SPCR_SPE                0x40
  73 #define SPCR_SPTIE              0x20
  74 #define SPCR_SPEIE              0x10
  75 #define SPCR_MSTR               0x08
  76 #define SPCR_MODFEN             0x04
  77 #define SPCR_TXMD               0x02
  78 #define SPCR_SPMS               0x01
  79
  80 /* SSLP */
  81 #define SSLP_SSL1P              0x02
  82 #define SSLP_SSL0P              0x01
  83
  84 /* SPPCR */
  85 #define SPPCR_MOIFE             0x20
  86 #define SPPCR_MOIFV             0x10
  87 #define SPPCR_SPOM              0x04
  88 #define SPPCR_SPLP2             0x02
  89 #define SPPCR_SPLP              0x01
  90
  91 /* SPSR */
  92 #define SPSR_SPRF               0x80
  93 #define SPSR_SPTEF              0x20
  94 #define SPSR_PERF               0x08
  95 #define SPSR_MODF               0x04
  96 #define SPSR_IDLNF              0x02
  97 #define SPSR_OVRF               0x01
  98
  99 /* SPSCR */
 100 #define SPSCR_SPSLN_MASK        0x07
 101
 102 /* SPSSR */
 103 #define SPSSR_SPECM_MASK        0x70
 104 #define SPSSR_SPCP_MASK         0x07
 105
 106 /* SPDCR */
 107 #define SPDCR_SPLW              0x20
 108 #define SPDCR_SPRDTD            0x10
 109 #define SPDCR_SLSEL1            0x08
 110 #define SPDCR_SLSEL0            0x04
 111 #define SPDCR_SLSEL_MASK        0x0c
 112 #define SPDCR_SPFC1             0x02
 113 #define SPDCR_SPFC0             0x01
 114
 115 /* SPCKD */
 116 #define SPCKD_SCKDL_MASK        0x07
 117
 118 /* SSLND */
 119 #define SSLND_SLNDL_MASK        0x07
 120
 121 /* SPND */
 122 #define SPND_SPNDL_MASK         0x07
 123
 124 /* SPCR2 */
 125 #define SPCR2_PTE               0x08
 126 #define SPCR2_SPIE              0x04
 127 #define SPCR2_SPOE              0x02
 128 #define SPCR2_SPPE              0x01
 129
 130 /* SPCMDn */
 131 #define SPCMD_SCKDEN            0x8000
 132 #define SPCMD_SLNDEN            0x4000
 133 #define SPCMD_SPNDEN            0x2000
 134 #define SPCMD_LSBF              0x1000
 135 #define SPCMD_SPB_MASK          0x0f00
 136 #define SPCMD_SPB_8_TO_16(bit)  (((bit - 1) << 8) & SPCMD_SPB_MASK)
 137 #define SPCMD_SPB_8BIT          0x0000  /* qspi only */
 138 #define SPCMD_SPB_16BIT         0x0100
 139 #define SPCMD_SPB_20BIT         0x0000
 140 #define SPCMD_SPB_24BIT         0x0100
 141 #define SPCMD_SPB_32BIT         0x0200
 142 #define SPCMD_SSLKP             0x0080
 143 #define SPCMD_SSLA_MASK         0x0030
 144 #define SPCMD_BRDV_MASK         0x000c
 145 #define SPCMD_CPOL              0x0002
 146 #define SPCMD_CPHA              0x0001
 147
 148 /* SPBFCR */
 149 #define SPBFCR_TXRST            0x80    /* qspi only */
 150 #define SPBFCR_RXRST            0x40    /* qspi only */
 151
 152 #define DUMMY_DATA              0x00
 153
 154 struct rspi_data {
 155         void __iomem *addr;
 156         u32 max_speed_hz;
 157         struct spi_master *master;
 158         struct list_head queue;
 159         struct work_struct ws;
 160         wait_queue_head_t wait;
 161         spinlock_t lock;
 162         struct clk *clk;
 163         u8 spsr;
 164         const struct spi_ops *ops;
 165
 166         /* for dmaengine */
 167         struct dma_chan *chan_tx;
 168         struct dma_chan *chan_rx;
 169         int irq;
 170
 171         unsigned dma_width_16bit:1;
 172         unsigned dma_callbacked:1;
 173 };
 174
 175 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
 176 {
 177         iowrite8(data, rspi->addr + offset);
 178 }
 179
 180 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
 181 {
 182         iowrite16(data, rspi->addr + offset);
 183 }
 184
 185 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
 186 {
 187         iowrite32(data, rspi->addr + offset);
 188 }
 189
 190 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
 191 {
 192         return ioread8(rspi->addr + offset);
 193 }
 194
 195 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
 196 {
 197         return ioread16(rspi->addr + offset);
 198 }
 199
 200 /* optional functions */
 201 struct spi_ops {
 202         int (*set_config_register)(const struct rspi_data *rspi,
 203                                    int access_size);
 204         int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg,
 205                         struct spi_transfer *t);
 206         int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
 207                            struct spi_transfer *t);
 208
 209 };
 210
 211 /*
 212  * functions for RSPI
 213  */
 214 static int rspi_set_config_register(const struct rspi_data *rspi,
 215                                     int access_size)
 216 {
 217         int spbr;
 218
 219         /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
 220         rspi_write8(rspi, 0x00, RSPI_SPPCR);
 221
 222         /* Sets transfer bit rate */
 223         spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
 224         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
 225
 226         /* Sets number of frames to be used: 1 frame */
 227         rspi_write8(rspi, 0x00, RSPI_SPDCR);
 228
 229         /* Sets RSPCK, SSL, next-access delay value */
 230         rspi_write8(rspi, 0x00, RSPI_SPCKD);
 231         rspi_write8(rspi, 0x00, RSPI_SSLND);
 232         rspi_write8(rspi, 0x00, RSPI_SPND);
 233
 234         /* Sets parity, interrupt mask */
 235         rspi_write8(rspi, 0x00, RSPI_SPCR2);
 236
 237         /* Sets SPCMD */
 238         rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
 239                      RSPI_SPCMD0);
 240
 241         /* Sets RSPI mode */
 242         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
 243
 244         return 0;
 245 }
 246
 247 /*
 248  * functions for QSPI
 249  */
 250 static int qspi_set_config_register(const struct rspi_data *rspi,
 251                                     int access_size)
 252 {
 253         u16 spcmd;
 254         int spbr;
 255
 256         /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
 257         rspi_write8(rspi, 0x00, RSPI_SPPCR);
 258
 259         /* Sets transfer bit rate */
 260         spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz);
 261         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
 262
 263         /* Sets number of frames to be used: 1 frame */
 264         rspi_write8(rspi, 0x00, RSPI_SPDCR);
 265
 266         /* Sets RSPCK, SSL, next-access delay value */
 267         rspi_write8(rspi, 0x00, RSPI_SPCKD);
 268         rspi_write8(rspi, 0x00, RSPI_SSLND);
 269         rspi_write8(rspi, 0x00, RSPI_SPND);
 270
 271         /* Data Length Setting */
 272         if (access_size == 8)
 273                 spcmd = SPCMD_SPB_8BIT;
 274         else if (access_size == 16)
 275                 spcmd = SPCMD_SPB_16BIT;
 276         else if (access_size == 32)
 277                 spcmd = SPCMD_SPB_32BIT;
 278
 279         spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SSLKP | SPCMD_SPNDEN;
 280
 281         /* Resets transfer data length */
 282         rspi_write32(rspi, 0, QSPI_SPBMUL0);
 283
 284         /* Resets transmit and receive buffer */
 285         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
 286         /* Sets buffer to allow normal operation */
 287         rspi_write8(rspi, 0x00, QSPI_SPBFCR);
 288
 289         /* Sets SPCMD */
 290         rspi_write16(rspi, spcmd, RSPI_SPCMD0);
 291
 292         /* Enables SPI function in a master mode */
 293         rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
 294
 295         return 0;
 296 }
 297
 298 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
 299
 300 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
 301 {
 302         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
 303 }
 304
 305 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
 306 {
 307         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
 308 }
 309
 310 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
 311                                    u8 enable_bit)
 312 {
 313         int ret;
 314
 315         rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
 316         rspi_enable_irq(rspi, enable_bit);
 317         ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
 318         if (ret == 0 && !(rspi->spsr & wait_mask))
 319                 return -ETIMEDOUT;
 320
 321         return 0;
 322 }
 323
 324 static void rspi_assert_ssl(const struct rspi_data *rspi)
 325 {
 326         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
 327 }
 328
 329 static void rspi_negate_ssl(const struct rspi_data *rspi)
 330 {
 331         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
 332 }
 333
 334 static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
 335                          struct spi_transfer *t)
 336 {
 337         int remain = t->len;
 338         const u8 *data = t->tx_buf;
 339         while (remain > 0) {
 340                 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
 341                             RSPI_SPCR);
 342
 343                 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
 344                         dev_err(&rspi->master->dev,
 345                                 "%s: tx empty timeout\n", __func__);
 346                         return -ETIMEDOUT;
 347                 }
 348
 349                 rspi_write16(rspi, *data, RSPI_SPDR);
 350                 data++;
 351                 remain--;
 352         }
 353
 354         /* Waiting for the last transmition */
 355         rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
 356
 357         return 0;
 358 }
 359
 360 static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
 361                          struct spi_transfer *t)
 362 {
 363         int remain = t->len;
 364         const u8 *data = t->tx_buf;
 365
 366         rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
 367         rspi_write8(rspi, 0x00, QSPI_SPBFCR);
 368
 369         while (remain > 0) {
 370
 371                 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
 372                         dev_err(&rspi->master->dev,
 373                                 "%s: tx empty timeout\n", __func__);
 374                         return -ETIMEDOUT;
 375                 }
 376                 rspi_write8(rspi, *data++, RSPI_SPDR);
 377
 378                 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
 379                         dev_err(&rspi->master->dev,
 380                                 "%s: receive timeout\n", __func__);
 381                         return -ETIMEDOUT;
 382                 }
 383                 rspi_read8(rspi, RSPI_SPDR);
 384
 385                 remain--;
 386         }
 387
 388         /* Waiting for the last transmition */
 389         rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
 390
 391         return 0;
 392 }
 393
 394 #define send_pio(spi, mesg, t) spi->ops->send_pio(spi, mesg, t)
 395
 396 static void rspi_dma_complete(void *arg)
 397 {
 398         struct rspi_data *rspi = arg;
 399
 400         rspi->dma_callbacked = 1;
 401         wake_up_interruptible(&rspi->wait);
 402 }
 403
 404 static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf,
 405                            unsigned len, struct dma_chan *chan,
 406                            enum dma_transfer_direction dir)
 407 {
 408         sg_init_table(sg, 1);
 409         sg_set_buf(sg, buf, len);
 410         sg_dma_len(sg) = len;
 411         return dma_map_sg(chan->device->dev, sg, 1, dir);
 412 }
 413
 414 static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan,
 415                               enum dma_transfer_direction dir)
 416 {
 417         dma_unmap_sg(chan->device->dev, sg, 1, dir);
 418 }
 419
 420 static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len)
 421 {
 422         u16 *dst = buf;
 423         const u8 *src = data;
 424
 425         while (len) {
 426                 *dst++ = (u16)(*src++);
 427                 len--;
 428         }
 429 }
 430
 431 static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len)
 432 {
 433         u8 *dst = buf;
 434         const u16 *src = data;
 435
 436         while (len) {
 437                 *dst++ = (u8)*src++;
 438                 len--;
 439         }
 440 }
 441
 442 static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
 443 {
 444         struct scatterlist sg;
 445         const void *buf = NULL;
 446         struct dma_async_tx_descriptor *desc;
 447         unsigned len;
 448         int ret = 0;
 449
 450         if (rspi->dma_width_16bit) {
 451                 void *tmp;
 452                 /*
 453                  * If DMAC bus width is 16-bit, the driver allocates a dummy
 454                  * buffer. And, the driver converts original data into the
 455                  * DMAC data as the following format:
 456                  *  original data: 1st byte, 2nd byte ...
 457                  *  DMAC data:     1st byte, dummy, 2nd byte, dummy ...
 458                  */
 459                 len = t->len * 2;
 460                 tmp = kmalloc(len, GFP_KERNEL);
 461                 if (!tmp)
 462                         return -ENOMEM;
 463                 rspi_memory_to_8bit(tmp, t->tx_buf, t->len);
 464                 buf = tmp;
 465         } else {
 466                 len = t->len;
 467                 buf = t->tx_buf;
 468         }
 469
 470         if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) {
 471                 ret = -EFAULT;
 472                 goto end_nomap;
 473         }
 474         desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE,
 475                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 476         if (!desc) {
 477                 ret = -EIO;
 478                 goto end;
 479         }
 480
 481         /*
 482          * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
 483          * called. So, this driver disables the IRQ while DMA transfer.
 484          */
 485         disable_irq(rspi->irq);
 486
 487         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
 488         rspi_enable_irq(rspi, SPCR_SPTIE);
 489         rspi->dma_callbacked = 0;
 490
 491         desc->callback = rspi_dma_complete;
 492         desc->callback_param = rspi;
 493         dmaengine_submit(desc);
 494         dma_async_issue_pending(rspi->chan_tx);
 495
 496         ret = wait_event_interruptible_timeout(rspi->wait,
 497                                                rspi->dma_callbacked, HZ);
 498         if (ret > 0 && rspi->dma_callbacked)
 499                 ret = 0;
 500         else if (!ret)
 501                 ret = -ETIMEDOUT;
 502         rspi_disable_irq(rspi, SPCR_SPTIE);
 503
 504         enable_irq(rspi->irq);
 505
 506 end:
 507         rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
 508 end_nomap:
 509         if (rspi->dma_width_16bit)
 510                 kfree(buf);
 511
 512         return ret;
 513 }
 514
 515 static void rspi_receive_init(const struct rspi_data *rspi)
 516 {
 517         u8 spsr;
 518
 519         spsr = rspi_read8(rspi, RSPI_SPSR);
 520         if (spsr & SPSR_SPRF)
 521                 rspi_read16(rspi, RSPI_SPDR);   /* dummy read */
 522         if (spsr & SPSR_OVRF)
 523                 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
 524                             RSPI_SPCR);
 525 }
 526
 527 static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
 528                             struct spi_transfer *t)
 529 {
 530         int remain = t->len;
 531         u8 *data;
 532
 533         rspi_receive_init(rspi);
 534
 535         data = t->rx_buf;
 536         while (remain > 0) {
 537                 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
 538                             RSPI_SPCR);
 539
 540                 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
 541                         dev_err(&rspi->master->dev,
 542                                 "%s: tx empty timeout\n", __func__);
 543                         return -ETIMEDOUT;
 544                 }
 545                 /* dummy write for generate clock */
 546                 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
 547
 548                 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
 549                         dev_err(&rspi->master->dev,
 550                                 "%s: receive timeout\n", __func__);
 551                         return -ETIMEDOUT;
 552                 }
 553                 /* SPDR allows 16 or 32-bit access only */
 554                 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
 555
 556                 data++;
 557                 remain--;
 558         }
 559
 560         return 0;
 561 }
 562
 563 static void qspi_receive_init(const struct rspi_data *rspi)
 564 {
 565         u8 spsr;
 566
 567         spsr = rspi_read8(rspi, RSPI_SPSR);
 568         if (spsr & SPSR_SPRF)
 569                 rspi_read8(rspi, RSPI_SPDR);   /* dummy read */
 570         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
 571         rspi_write8(rspi, 0x00, QSPI_SPBFCR);
 572 }
 573
 574 static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
 575                             struct spi_transfer *t)
 576 {
 577         int remain = t->len;
 578         u8 *data;
 579
 580         qspi_receive_init(rspi);
 581
 582         data = t->rx_buf;
 583         while (remain > 0) {
 584
 585                 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
 586                         dev_err(&rspi->master->dev,
 587                                 "%s: tx empty timeout\n", __func__);
 588                         return -ETIMEDOUT;
 589                 }
 590                 /* dummy write for generate clock */
 591                 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
 592
 593                 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
 594                         dev_err(&rspi->master->dev,
 595                                 "%s: receive timeout\n", __func__);
 596                         return -ETIMEDOUT;
 597                 }
 598                 /* SPDR allows 8, 16 or 32-bit access */
 599                 *data++ = rspi_read8(rspi, RSPI_SPDR);
 600                 remain--;
 601         }
 602
 603         return 0;
 604 }
 605
 606 #define receive_pio(spi, mesg, t) spi->ops->receive_pio(spi, mesg, t)
 607
 608 static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
 609 {
 610         struct scatterlist sg, sg_dummy;
 611         void *dummy = NULL, *rx_buf = NULL;
 612         struct dma_async_tx_descriptor *desc, *desc_dummy;
 613         unsigned len;
 614         int ret = 0;
 615
 616         if (rspi->dma_width_16bit) {
 617                 /*
 618                  * If DMAC bus width is 16-bit, the driver allocates a dummy
 619                  * buffer. And, finally the driver converts the DMAC data into
 620                  * actual data as the following format:
 621                  *  DMAC data:   1st byte, dummy, 2nd byte, dummy ...
 622                  *  actual data: 1st byte, 2nd byte ...
 623                  */
 624                 len = t->len * 2;
 625                 rx_buf = kmalloc(len, GFP_KERNEL);
 626                 if (!rx_buf)
 627                         return -ENOMEM;
 628          } else {
 629                 len = t->len;
 630                 rx_buf = t->rx_buf;
 631         }
 632
 633         /* prepare dummy transfer to generate SPI clocks */
 634         dummy = kzalloc(len, GFP_KERNEL);
 635         if (!dummy) {
 636                 ret = -ENOMEM;
 637                 goto end_nomap;
 638         }
 639         if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx,
 640                              DMA_TO_DEVICE)) {
 641                 ret = -EFAULT;
 642                 goto end_nomap;
 643         }
 644         desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1,
 645                         DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 646         if (!desc_dummy) {
 647                 ret = -EIO;
 648                 goto end_dummy_mapped;
 649         }
 650
 651         /* prepare receive transfer */
 652         if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx,
 653                              DMA_FROM_DEVICE)) {
 654                 ret = -EFAULT;
 655                 goto end_dummy_mapped;
 656
 657         }
 658         desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE,
 659                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 660         if (!desc) {
 661                 ret = -EIO;
 662                 goto end;
 663         }
 664
 665         rspi_receive_init(rspi);
 666
 667         /*
 668          * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
 669          * called. So, this driver disables the IRQ while DMA transfer.
 670          */
 671         disable_irq(rspi->irq);
 672
 673         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
 674         rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
 675         rspi->dma_callbacked = 0;
 676
 677         desc->callback = rspi_dma_complete;
 678         desc->callback_param = rspi;
 679         dmaengine_submit(desc);
 680         dma_async_issue_pending(rspi->chan_rx);
 681
 682         desc_dummy->callback = NULL;    /* No callback */
 683         dmaengine_submit(desc_dummy);
 684         dma_async_issue_pending(rspi->chan_tx);
 685
 686         ret = wait_event_interruptible_timeout(rspi->wait,
 687                                                rspi->dma_callbacked, HZ);
 688         if (ret > 0 && rspi->dma_callbacked)
 689                 ret = 0;
 690         else if (!ret)
 691                 ret = -ETIMEDOUT;
 692         rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
 693
 694         enable_irq(rspi->irq);
 695
 696 end:
 697         rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
 698 end_dummy_mapped:
 699         rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE);
 700 end_nomap:
 701         if (rspi->dma_width_16bit) {
 702                 if (!ret)
 703                         rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len);
 704                 kfree(rx_buf);
 705         }
 706         kfree(dummy);
 707
 708         return ret;
 709 }
 710
 711 static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
 712 {
 713         if (t->tx_buf && rspi->chan_tx)
 714                 return 1;
 715         /* If the module receives data by DMAC, it also needs TX DMAC */
 716         if (t->rx_buf && rspi->chan_tx && rspi->chan_rx)
 717                 return 1;
 718
 719         return 0;
 720 }
 721
 722 static void rspi_work(struct work_struct *work)
 723 {
 724         struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
 725         struct spi_message *mesg;
 726         struct spi_transfer *t;
 727         unsigned long flags;
 728         int ret;
 729
 730         while (1) {
 731                 spin_lock_irqsave(&rspi->lock, flags);
 732                 if (list_empty(&rspi->queue)) {
 733                         spin_unlock_irqrestore(&rspi->lock, flags);
 734                         break;
 735                 }
 736                 mesg = list_entry(rspi->queue.next, struct spi_message, queue);
 737                 list_del_init(&mesg->queue);
 738                 spin_unlock_irqrestore(&rspi->lock, flags);
 739
 740                 rspi_assert_ssl(rspi);
 741
 742                 list_for_each_entry(t, &mesg->transfers, transfer_list) {
 743                         if (t->tx_buf) {
 744                                 if (rspi_is_dma(rspi, t))
 745                                         ret = rspi_send_dma(rspi, t);
 746                                 else
 747                                         ret = send_pio(rspi, mesg, t);
 748                                 if (ret < 0)
 749                                         goto error;
 750                         }
 751                         if (t->rx_buf) {
 752                                 if (rspi_is_dma(rspi, t))
 753                                         ret = rspi_receive_dma(rspi, t);
 754                                 else
 755                                         ret = receive_pio(rspi, mesg, t);
 756                                 if (ret < 0)
 757                                         goto error;
 758                         }
 759                         mesg->actual_length += t->len;
 760                 }
 761                 rspi_negate_ssl(rspi);
 762
 763                 mesg->status = 0;
 764                 mesg->complete(mesg->context);
 765         }
 766
 767         return;
 768
 769 error:
 770         mesg->status = ret;
 771         mesg->complete(mesg->context);
 772 }
 773
 774 static int rspi_setup(struct spi_device *spi)
 775 {
 776         struct rspi_data *rspi = spi_master_get_devdata(spi->master);
 777
 778         if (!spi->bits_per_word)
 779                 spi->bits_per_word = 8;
 780         rspi->max_speed_hz = spi->max_speed_hz;
 781
 782         set_config_register(rspi, 8);
 783
 784         return 0;
 785 }
 786
 787 static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg)
 788 {
 789         struct rspi_data *rspi = spi_master_get_devdata(spi->master);
 790         unsigned long flags;
 791
 792         mesg->actual_length = 0;
 793         mesg->status = -EINPROGRESS;
 794
 795         spin_lock_irqsave(&rspi->lock, flags);
 796         list_add_tail(&mesg->queue, &rspi->queue);
 797         schedule_work(&rspi->ws);
 798         spin_unlock_irqrestore(&rspi->lock, flags);
 799
 800         return 0;
 801 }
 802
 803 static void rspi_cleanup(struct spi_device *spi)
 804 {
 805 }
 806
 807 static irqreturn_t rspi_irq(int irq, void *_sr)
 808 {
 809         struct rspi_data *rspi = _sr;
 810         u8 spsr;
 811         irqreturn_t ret = IRQ_NONE;
 812         u8 disable_irq = 0;
 813
 814         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
 815         if (spsr & SPSR_SPRF)
 816                 disable_irq |= SPCR_SPRIE;
 817         if (spsr & SPSR_SPTEF)
 818                 disable_irq |= SPCR_SPTIE;
 819
 820         if (disable_irq) {
 821                 ret = IRQ_HANDLED;
 822                 rspi_disable_irq(rspi, disable_irq);
 823                 wake_up(&rspi->wait);
 824         }
 825
 826         return ret;
 827 }
 828
 829 static int rspi_request_dma(struct rspi_data *rspi,
 830                                       struct platform_device *pdev)
 831 {
 832         const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
 833         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 834         dma_cap_mask_t mask;
 835         struct dma_slave_config cfg;
 836         int ret;
 837
 838         if (!res || !rspi_pd)
 839                 return 0;       /* The driver assumes no error. */
 840
 841         rspi->dma_width_16bit = rspi_pd->dma_width_16bit;
 842
 843         /* If the module receives data by DMAC, it also needs TX DMAC */
 844         if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) {
 845                 dma_cap_zero(mask);
 846                 dma_cap_set(DMA_SLAVE, mask);
 847                 rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter,
 848                                                     (void *)rspi_pd->dma_rx_id);
 849                 if (rspi->chan_rx) {
 850                         cfg.slave_id = rspi_pd->dma_rx_id;
 851                         cfg.direction = DMA_DEV_TO_MEM;
 852                         cfg.dst_addr = 0;
 853                         cfg.src_addr = res->start + RSPI_SPDR;
 854                         ret = dmaengine_slave_config(rspi->chan_rx, &cfg);
 855                         if (!ret)
 856                                 dev_info(&pdev->dev, "Use DMA when rx.\n");
 857                         else
 858                                 return ret;
 859                 }
 860         }
 861         if (rspi_pd->dma_tx_id) {
 862                 dma_cap_zero(mask);
 863                 dma_cap_set(DMA_SLAVE, mask);
 864                 rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter,
 865                                                     (void *)rspi_pd->dma_tx_id);
 866                 if (rspi->chan_tx) {
 867                         cfg.slave_id = rspi_pd->dma_tx_id;
 868                         cfg.direction = DMA_MEM_TO_DEV;
 869                         cfg.dst_addr = res->start + RSPI_SPDR;
 870                         cfg.src_addr = 0;
 871                         ret = dmaengine_slave_config(rspi->chan_tx, &cfg);
 872                         if (!ret)
 873                                 dev_info(&pdev->dev, "Use DMA when tx\n");
 874                         else
 875                                 return ret;
 876                 }
 877         }
 878
 879         return 0;
 880 }
 881
 882 static void rspi_release_dma(struct rspi_data *rspi)
 883 {
 884         if (rspi->chan_tx)
 885                 dma_release_channel(rspi->chan_tx);
 886         if (rspi->chan_rx)
 887                 dma_release_channel(rspi->chan_rx);
 888 }
 889
 890 static int rspi_remove(struct platform_device *pdev)
 891 {
 892         struct rspi_data *rspi = spi_master_get(platform_get_drvdata(pdev));
 893
 894         spi_unregister_master(rspi->master);
 895         rspi_release_dma(rspi);
 896         free_irq(platform_get_irq(pdev, 0), rspi);
 897         clk_put(rspi->clk);
 898         iounmap(rspi->addr);
 899         spi_master_put(rspi->master);
 900
 901         return 0;
 902 }
 903
 904 static int rspi_probe(struct platform_device *pdev)
 905 {
 906         struct resource *res;
 907         struct spi_master *master;
 908         struct rspi_data *rspi;
 909         int ret, irq;
 910         char clk_name[16];
 911         const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
 912         const struct spi_ops *ops;
 913         const struct platform_device_id *id_entry = pdev->id_entry;
 914
 915         ops = (struct spi_ops *)id_entry->driver_data;
 916         /* ops parameter check */
 917         if (!ops->set_config_register) {
 918                 dev_err(&pdev->dev, "there is no set_config_register\n");
 919                 return -ENODEV;
 920         }
 921         /* get base addr */
 922         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 923         if (unlikely(res == NULL)) {
 924                 dev_err(&pdev->dev, "invalid resource\n");
 925                 return -EINVAL;
 926         }
 927
 928         irq = platform_get_irq(pdev, 0);
 929         if (irq < 0) {
 930                 dev_err(&pdev->dev, "platform_get_irq error\n");
 931                 return -ENODEV;
 932         }
 933
 934         master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
 935         if (master == NULL) {
 936                 dev_err(&pdev->dev, "spi_alloc_master error.\n");
 937                 return -ENOMEM;
 938         }
 939
 940         rspi = spi_master_get_devdata(master);
 941         platform_set_drvdata(pdev, rspi);
 942         rspi->ops = ops;
 943         rspi->master = master;
 944         rspi->addr = ioremap(res->start, resource_size(res));
 945         if (rspi->addr == NULL) {
 946                 dev_err(&pdev->dev, "ioremap error.\n");
 947                 ret = -ENOMEM;
 948                 goto error1;
 949         }
 950
 951         snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id);
 952         rspi->clk = clk_get(&pdev->dev, clk_name);
 953         if (IS_ERR(rspi->clk)) {
 954                 dev_err(&pdev->dev, "cannot get clock\n");
 955                 ret = PTR_ERR(rspi->clk);
 956                 goto error2;
 957         }
 958         clk_enable(rspi->clk);
 959
 960         INIT_LIST_HEAD(&rspi->queue);
 961         spin_lock_init(&rspi->lock);
 962         INIT_WORK(&rspi->ws, rspi_work);
 963         init_waitqueue_head(&rspi->wait);
 964
 965         master->num_chipselect = rspi_pd->num_chipselect;
 966         if (!master->num_chipselect)
 967                 master->num_chipselect = 2; /* default */
 968
 969         master->bus_num = pdev->id;
 970         master->setup = rspi_setup;
 971         master->transfer = rspi_transfer;
 972         master->cleanup = rspi_cleanup;
 973
 974         ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
 975         if (ret < 0) {
 976                 dev_err(&pdev->dev, "request_irq error\n");
 977                 goto error3;
 978         }
 979
 980         rspi->irq = irq;
 981         ret = rspi_request_dma(rspi, pdev);
 982         if (ret < 0) {
 983                 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
 984                 goto error4;
 985         }
 986
 987         ret = spi_register_master(master);
 988         if (ret < 0) {
 989                 dev_err(&pdev->dev, "spi_register_master error.\n");
 990                 goto error4;
 991         }
 992
 993         dev_info(&pdev->dev, "probed\n");
 994
 995         return 0;
 996
 997 error4:
 998         rspi_release_dma(rspi);
 999         free_irq(irq, rspi);
1000 error3:
1001         clk_put(rspi->clk);
1002 error2:
1003         iounmap(rspi->addr);
1004 error1:
1005         spi_master_put(master);
1006
1007         return ret;
1008 }
1009
1010 static struct spi_ops rspi_ops = {
1011         .set_config_register =          rspi_set_config_register,
1012         .send_pio =                     rspi_send_pio,
1013         .receive_pio =                  rspi_receive_pio,
1014 };
1015
1016 static struct spi_ops qspi_ops = {
1017         .set_config_register =          qspi_set_config_register,
1018         .send_pio =                     qspi_send_pio,
1019         .receive_pio =                  qspi_receive_pio,
1020 };
1021
1022 static struct platform_device_id spi_driver_ids[] = {
1023         { "rspi",       (kernel_ulong_t)&rspi_ops },
1024         { "qspi",       (kernel_ulong_t)&qspi_ops },
1025         {},
1026 };
1027
1028 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1029
1030 static struct platform_driver rspi_driver = {
1031         .probe =        rspi_probe,
1032         .remove =       rspi_remove,
1033         .id_table =     spi_driver_ids,
1034         .driver         = {
1035                 .name = "renesas_spi",
1036                 .owner  = THIS_MODULE,
1037         },
1038 };
1039 module_platform_driver(rspi_driver);
1040
1041 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1042 MODULE_LICENSE("GPL v2");
1043 MODULE_AUTHOR("Yoshihiro Shimoda");
1044 MODULE_ALIAS("platform:rspi");