2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/spi/pxa2xx_spi.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/slab.h>
32 #include <linux/clk.h>
36 #include <asm/delay.h>
38 #include "spi-pxa2xx.h"
40 MODULE_AUTHOR("Stephen Street");
41 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
42 MODULE_LICENSE("GPL");
43 MODULE_ALIAS("platform:pxa2xx-spi");
47 #define TIMOUT_DFLT 1000
50 * for testing SSCR1 changes that require SSP restart, basically
51 * everything except the service and interrupt enables, the pxa270 developer
52 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
53 * list, but the PXA255 dev man says all bits without really meaning the
54 * service and interrupt enables
56 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
57 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
58 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
59 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
60 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
61 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
63 static void cs_assert(struct driver_data *drv_data)
65 struct chip_data *chip = drv_data->cur_chip;
67 if (drv_data->ssp_type == CE4100_SSP) {
68 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
72 if (chip->cs_control) {
73 chip->cs_control(PXA2XX_CS_ASSERT);
77 if (gpio_is_valid(chip->gpio_cs))
78 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
81 static void cs_deassert(struct driver_data *drv_data)
83 struct chip_data *chip = drv_data->cur_chip;
85 if (drv_data->ssp_type == CE4100_SSP)
88 if (chip->cs_control) {
89 chip->cs_control(PXA2XX_CS_DEASSERT);
93 if (gpio_is_valid(chip->gpio_cs))
94 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
97 int pxa2xx_spi_flush(struct driver_data *drv_data)
99 unsigned long limit = loops_per_jiffy << 1;
101 void __iomem *reg = drv_data->ioaddr;
104 while (read_SSSR(reg) & SSSR_RNE) {
107 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
108 write_SSSR_CS(drv_data, SSSR_ROR);
113 static int null_writer(struct driver_data *drv_data)
115 void __iomem *reg = drv_data->ioaddr;
116 u8 n_bytes = drv_data->n_bytes;
118 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
119 || (drv_data->tx == drv_data->tx_end))
123 drv_data->tx += n_bytes;
128 static int null_reader(struct driver_data *drv_data)
130 void __iomem *reg = drv_data->ioaddr;
131 u8 n_bytes = drv_data->n_bytes;
133 while ((read_SSSR(reg) & SSSR_RNE)
134 && (drv_data->rx < drv_data->rx_end)) {
136 drv_data->rx += n_bytes;
139 return drv_data->rx == drv_data->rx_end;
142 static int u8_writer(struct driver_data *drv_data)
144 void __iomem *reg = drv_data->ioaddr;
146 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
147 || (drv_data->tx == drv_data->tx_end))
150 write_SSDR(*(u8 *)(drv_data->tx), reg);
156 static int u8_reader(struct driver_data *drv_data)
158 void __iomem *reg = drv_data->ioaddr;
160 while ((read_SSSR(reg) & SSSR_RNE)
161 && (drv_data->rx < drv_data->rx_end)) {
162 *(u8 *)(drv_data->rx) = read_SSDR(reg);
166 return drv_data->rx == drv_data->rx_end;
169 static int u16_writer(struct driver_data *drv_data)
171 void __iomem *reg = drv_data->ioaddr;
173 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
174 || (drv_data->tx == drv_data->tx_end))
177 write_SSDR(*(u16 *)(drv_data->tx), reg);
183 static int u16_reader(struct driver_data *drv_data)
185 void __iomem *reg = drv_data->ioaddr;
187 while ((read_SSSR(reg) & SSSR_RNE)
188 && (drv_data->rx < drv_data->rx_end)) {
189 *(u16 *)(drv_data->rx) = read_SSDR(reg);
193 return drv_data->rx == drv_data->rx_end;
196 static int u32_writer(struct driver_data *drv_data)
198 void __iomem *reg = drv_data->ioaddr;
200 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
201 || (drv_data->tx == drv_data->tx_end))
204 write_SSDR(*(u32 *)(drv_data->tx), reg);
210 static int u32_reader(struct driver_data *drv_data)
212 void __iomem *reg = drv_data->ioaddr;
214 while ((read_SSSR(reg) & SSSR_RNE)
215 && (drv_data->rx < drv_data->rx_end)) {
216 *(u32 *)(drv_data->rx) = read_SSDR(reg);
220 return drv_data->rx == drv_data->rx_end;
223 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
225 struct spi_message *msg = drv_data->cur_msg;
226 struct spi_transfer *trans = drv_data->cur_transfer;
228 /* Move to next transfer */
229 if (trans->transfer_list.next != &msg->transfers) {
230 drv_data->cur_transfer =
231 list_entry(trans->transfer_list.next,
234 return RUNNING_STATE;
239 /* caller already set message->status; dma and pio irqs are blocked */
240 static void giveback(struct driver_data *drv_data)
242 struct spi_transfer* last_transfer;
243 struct spi_message *msg;
245 msg = drv_data->cur_msg;
246 drv_data->cur_msg = NULL;
247 drv_data->cur_transfer = NULL;
249 last_transfer = list_entry(msg->transfers.prev,
253 /* Delay if requested before any change in chip select */
254 if (last_transfer->delay_usecs)
255 udelay(last_transfer->delay_usecs);
257 /* Drop chip select UNLESS cs_change is true or we are returning
258 * a message with an error, or next message is for another chip
260 if (!last_transfer->cs_change)
261 cs_deassert(drv_data);
263 struct spi_message *next_msg;
265 /* Holding of cs was hinted, but we need to make sure
266 * the next message is for the same chip. Don't waste
267 * time with the following tests unless this was hinted.
269 * We cannot postpone this until pump_messages, because
270 * after calling msg->complete (below) the driver that
271 * sent the current message could be unloaded, which
272 * could invalidate the cs_control() callback...
275 /* get a pointer to the next message, if any */
276 next_msg = spi_get_next_queued_message(drv_data->master);
278 /* see if the next and current messages point
281 if (next_msg && next_msg->spi != msg->spi)
283 if (!next_msg || msg->state == ERROR_STATE)
284 cs_deassert(drv_data);
287 spi_finalize_current_message(drv_data->master);
288 drv_data->cur_chip = NULL;
291 static void reset_sccr1(struct driver_data *drv_data)
293 void __iomem *reg = drv_data->ioaddr;
294 struct chip_data *chip = drv_data->cur_chip;
297 sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
298 sccr1_reg &= ~SSCR1_RFT;
299 sccr1_reg |= chip->threshold;
300 write_SSCR1(sccr1_reg, reg);
303 static void int_error_stop(struct driver_data *drv_data, const char* msg)
305 void __iomem *reg = drv_data->ioaddr;
307 /* Stop and reset SSP */
308 write_SSSR_CS(drv_data, drv_data->clear_sr);
309 reset_sccr1(drv_data);
310 if (!pxa25x_ssp_comp(drv_data))
312 pxa2xx_spi_flush(drv_data);
313 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
315 dev_err(&drv_data->pdev->dev, "%s\n", msg);
317 drv_data->cur_msg->state = ERROR_STATE;
318 tasklet_schedule(&drv_data->pump_transfers);
321 static void int_transfer_complete(struct driver_data *drv_data)
323 void __iomem *reg = drv_data->ioaddr;
326 write_SSSR_CS(drv_data, drv_data->clear_sr);
327 reset_sccr1(drv_data);
328 if (!pxa25x_ssp_comp(drv_data))
331 /* Update total byte transferred return count actual bytes read */
332 drv_data->cur_msg->actual_length += drv_data->len -
333 (drv_data->rx_end - drv_data->rx);
335 /* Transfer delays and chip select release are
336 * handled in pump_transfers or giveback
339 /* Move to next transfer */
340 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
342 /* Schedule transfer tasklet */
343 tasklet_schedule(&drv_data->pump_transfers);
346 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
348 void __iomem *reg = drv_data->ioaddr;
350 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
351 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
353 u32 irq_status = read_SSSR(reg) & irq_mask;
355 if (irq_status & SSSR_ROR) {
356 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
360 if (irq_status & SSSR_TINT) {
361 write_SSSR(SSSR_TINT, reg);
362 if (drv_data->read(drv_data)) {
363 int_transfer_complete(drv_data);
368 /* Drain rx fifo, Fill tx fifo and prevent overruns */
370 if (drv_data->read(drv_data)) {
371 int_transfer_complete(drv_data);
374 } while (drv_data->write(drv_data));
376 if (drv_data->read(drv_data)) {
377 int_transfer_complete(drv_data);
381 if (drv_data->tx == drv_data->tx_end) {
385 sccr1_reg = read_SSCR1(reg);
386 sccr1_reg &= ~SSCR1_TIE;
389 * PXA25x_SSP has no timeout, set up rx threshould for the
390 * remaining RX bytes.
392 if (pxa25x_ssp_comp(drv_data)) {
394 sccr1_reg &= ~SSCR1_RFT;
396 bytes_left = drv_data->rx_end - drv_data->rx;
397 switch (drv_data->n_bytes) {
404 if (bytes_left > RX_THRESH_DFLT)
405 bytes_left = RX_THRESH_DFLT;
407 sccr1_reg |= SSCR1_RxTresh(bytes_left);
409 write_SSCR1(sccr1_reg, reg);
412 /* We did something */
416 static irqreturn_t ssp_int(int irq, void *dev_id)
418 struct driver_data *drv_data = dev_id;
419 void __iomem *reg = drv_data->ioaddr;
420 u32 sccr1_reg = read_SSCR1(reg);
421 u32 mask = drv_data->mask_sr;
424 status = read_SSSR(reg);
426 /* Ignore possible writes if we don't need to write */
427 if (!(sccr1_reg & SSCR1_TIE))
430 if (!(status & mask))
433 if (!drv_data->cur_msg) {
435 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
436 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
437 if (!pxa25x_ssp_comp(drv_data))
439 write_SSSR_CS(drv_data, drv_data->clear_sr);
441 dev_err(&drv_data->pdev->dev, "bad message state "
442 "in interrupt handler\n");
448 return drv_data->transfer_handler(drv_data);
451 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
453 unsigned long ssp_clk = drv_data->max_clk_rate;
454 const struct ssp_device *ssp = drv_data->ssp;
456 rate = min_t(int, ssp_clk, rate);
458 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
459 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
461 return ((ssp_clk / rate - 1) & 0xfff) << 8;
464 static void pump_transfers(unsigned long data)
466 struct driver_data *drv_data = (struct driver_data *)data;
467 struct spi_message *message = NULL;
468 struct spi_transfer *transfer = NULL;
469 struct spi_transfer *previous = NULL;
470 struct chip_data *chip = NULL;
471 void __iomem *reg = drv_data->ioaddr;
477 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
478 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
480 /* Get current state information */
481 message = drv_data->cur_msg;
482 transfer = drv_data->cur_transfer;
483 chip = drv_data->cur_chip;
485 /* Handle for abort */
486 if (message->state == ERROR_STATE) {
487 message->status = -EIO;
492 /* Handle end of message */
493 if (message->state == DONE_STATE) {
499 /* Delay if requested at end of transfer before CS change */
500 if (message->state == RUNNING_STATE) {
501 previous = list_entry(transfer->transfer_list.prev,
504 if (previous->delay_usecs)
505 udelay(previous->delay_usecs);
507 /* Drop chip select only if cs_change is requested */
508 if (previous->cs_change)
509 cs_deassert(drv_data);
512 /* Check if we can DMA this transfer */
513 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
515 /* reject already-mapped transfers; PIO won't always work */
516 if (message->is_dma_mapped
517 || transfer->rx_dma || transfer->tx_dma) {
518 dev_err(&drv_data->pdev->dev,
519 "pump_transfers: mapped transfer length "
520 "of %u is greater than %d\n",
521 transfer->len, MAX_DMA_LEN);
522 message->status = -EINVAL;
527 /* warn ... we force this to PIO mode */
528 if (printk_ratelimit())
529 dev_warn(&message->spi->dev, "pump_transfers: "
530 "DMA disabled for transfer length %ld "
532 (long)drv_data->len, MAX_DMA_LEN);
535 /* Setup the transfer state based on the type of transfer */
536 if (pxa2xx_spi_flush(drv_data) == 0) {
537 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
538 message->status = -EIO;
542 drv_data->n_bytes = chip->n_bytes;
543 drv_data->tx = (void *)transfer->tx_buf;
544 drv_data->tx_end = drv_data->tx + transfer->len;
545 drv_data->rx = transfer->rx_buf;
546 drv_data->rx_end = drv_data->rx + transfer->len;
547 drv_data->rx_dma = transfer->rx_dma;
548 drv_data->tx_dma = transfer->tx_dma;
549 drv_data->len = transfer->len;
550 drv_data->write = drv_data->tx ? chip->write : null_writer;
551 drv_data->read = drv_data->rx ? chip->read : null_reader;
553 /* Change speed and bit per word on a per transfer */
555 if (transfer->speed_hz || transfer->bits_per_word) {
557 bits = chip->bits_per_word;
558 speed = chip->speed_hz;
560 if (transfer->speed_hz)
561 speed = transfer->speed_hz;
563 if (transfer->bits_per_word)
564 bits = transfer->bits_per_word;
566 clk_div = ssp_get_clk_div(drv_data, speed);
569 drv_data->n_bytes = 1;
570 drv_data->read = drv_data->read != null_reader ?
571 u8_reader : null_reader;
572 drv_data->write = drv_data->write != null_writer ?
573 u8_writer : null_writer;
574 } else if (bits <= 16) {
575 drv_data->n_bytes = 2;
576 drv_data->read = drv_data->read != null_reader ?
577 u16_reader : null_reader;
578 drv_data->write = drv_data->write != null_writer ?
579 u16_writer : null_writer;
580 } else if (bits <= 32) {
581 drv_data->n_bytes = 4;
582 drv_data->read = drv_data->read != null_reader ?
583 u32_reader : null_reader;
584 drv_data->write = drv_data->write != null_writer ?
585 u32_writer : null_writer;
587 /* if bits/word is changed in dma mode, then must check the
588 * thresholds and burst also */
589 if (chip->enable_dma) {
590 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
594 if (printk_ratelimit())
595 dev_warn(&message->spi->dev,
597 "DMA burst size reduced to "
598 "match bits_per_word\n");
603 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
605 | (bits > 16 ? SSCR0_EDSS : 0);
608 message->state = RUNNING_STATE;
610 drv_data->dma_mapped = 0;
611 if (pxa2xx_spi_dma_is_possible(drv_data->len))
612 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
613 if (drv_data->dma_mapped) {
615 /* Ensure we have the correct interrupt handler */
616 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
618 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
620 /* Clear status and start DMA engine */
621 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
622 write_SSSR(drv_data->clear_sr, reg);
624 pxa2xx_spi_dma_start(drv_data);
626 /* Ensure we have the correct interrupt handler */
627 drv_data->transfer_handler = interrupt_transfer;
630 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
631 write_SSSR_CS(drv_data, drv_data->clear_sr);
634 /* see if we need to reload the config registers */
635 if ((read_SSCR0(reg) != cr0)
636 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
637 (cr1 & SSCR1_CHANGE_MASK)) {
639 /* stop the SSP, and update the other bits */
640 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
641 if (!pxa25x_ssp_comp(drv_data))
642 write_SSTO(chip->timeout, reg);
643 /* first set CR1 without interrupt and service enables */
644 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
645 /* restart the SSP */
646 write_SSCR0(cr0, reg);
649 if (!pxa25x_ssp_comp(drv_data))
650 write_SSTO(chip->timeout, reg);
655 /* after chip select, release the data by enabling service
656 * requests and interrupts, without changing any mode bits */
657 write_SSCR1(cr1, reg);
660 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
661 struct spi_message *msg)
663 struct driver_data *drv_data = spi_master_get_devdata(master);
665 drv_data->cur_msg = msg;
666 /* Initial message state*/
667 drv_data->cur_msg->state = START_STATE;
668 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
672 /* prepare to setup the SSP, in pump_transfers, using the per
673 * chip configuration */
674 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
676 /* Mark as busy and launch transfers */
677 tasklet_schedule(&drv_data->pump_transfers);
681 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
682 struct pxa2xx_spi_chip *chip_info)
686 if (chip == NULL || chip_info == NULL)
689 /* NOTE: setup() can be called multiple times, possibly with
690 * different chip_info, release previously requested GPIO
692 if (gpio_is_valid(chip->gpio_cs))
693 gpio_free(chip->gpio_cs);
695 /* If (*cs_control) is provided, ignore GPIO chip select */
696 if (chip_info->cs_control) {
697 chip->cs_control = chip_info->cs_control;
701 if (gpio_is_valid(chip_info->gpio_cs)) {
702 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
704 dev_err(&spi->dev, "failed to request chip select "
705 "GPIO%d\n", chip_info->gpio_cs);
709 chip->gpio_cs = chip_info->gpio_cs;
710 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
712 err = gpio_direction_output(chip->gpio_cs,
713 !chip->gpio_cs_inverted);
719 static int setup(struct spi_device *spi)
721 struct pxa2xx_spi_chip *chip_info = NULL;
722 struct chip_data *chip;
723 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
724 unsigned int clk_div;
725 uint tx_thres = TX_THRESH_DFLT;
726 uint rx_thres = RX_THRESH_DFLT;
728 if (!pxa25x_ssp_comp(drv_data)
729 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
730 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
731 "b/w not 4-32 for type non-PXA25x_SSP\n",
732 drv_data->ssp_type, spi->bits_per_word);
734 } else if (pxa25x_ssp_comp(drv_data)
735 && (spi->bits_per_word < 4
736 || spi->bits_per_word > 16)) {
737 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
738 "b/w not 4-16 for type PXA25x_SSP\n",
739 drv_data->ssp_type, spi->bits_per_word);
743 /* Only alloc on first setup */
744 chip = spi_get_ctldata(spi);
746 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
749 "failed setup: can't allocate chip data\n");
753 if (drv_data->ssp_type == CE4100_SSP) {
754 if (spi->chip_select > 4) {
755 dev_err(&spi->dev, "failed setup: "
756 "cs number must not be > 4.\n");
761 chip->frm = spi->chip_select;
764 chip->enable_dma = 0;
765 chip->timeout = TIMOUT_DFLT;
768 /* protocol drivers may change the chip settings, so...
769 * if chip_info exists, use it */
770 chip_info = spi->controller_data;
772 /* chip_info isn't always needed */
775 if (chip_info->timeout)
776 chip->timeout = chip_info->timeout;
777 if (chip_info->tx_threshold)
778 tx_thres = chip_info->tx_threshold;
779 if (chip_info->rx_threshold)
780 rx_thres = chip_info->rx_threshold;
781 chip->enable_dma = drv_data->master_info->enable_dma;
782 chip->dma_threshold = 0;
783 if (chip_info->enable_loopback)
784 chip->cr1 = SSCR1_LBM;
787 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
788 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
790 /* set dma burst and threshold outside of chip_info path so that if
791 * chip_info goes away after setting chip->enable_dma, the
792 * burst and threshold can still respond to changes in bits_per_word */
793 if (chip->enable_dma) {
794 /* set up legal burst and threshold for dma */
795 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
797 &chip->dma_burst_size,
798 &chip->dma_threshold)) {
799 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
800 "to match bits_per_word\n");
804 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
805 chip->speed_hz = spi->max_speed_hz;
809 | SSCR0_DataSize(spi->bits_per_word > 16 ?
810 spi->bits_per_word - 16 : spi->bits_per_word)
812 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
813 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
814 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
815 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
817 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
818 if (!pxa25x_ssp_comp(drv_data))
819 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
820 drv_data->max_clk_rate
821 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
822 chip->enable_dma ? "DMA" : "PIO");
824 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
825 drv_data->max_clk_rate / 2
826 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
827 chip->enable_dma ? "DMA" : "PIO");
829 if (spi->bits_per_word <= 8) {
831 chip->read = u8_reader;
832 chip->write = u8_writer;
833 } else if (spi->bits_per_word <= 16) {
835 chip->read = u16_reader;
836 chip->write = u16_writer;
837 } else if (spi->bits_per_word <= 32) {
838 chip->cr0 |= SSCR0_EDSS;
840 chip->read = u32_reader;
841 chip->write = u32_writer;
843 dev_err(&spi->dev, "invalid wordsize\n");
846 chip->bits_per_word = spi->bits_per_word;
848 spi_set_ctldata(spi, chip);
850 if (drv_data->ssp_type == CE4100_SSP)
853 return setup_cs(spi, chip, chip_info);
856 static void cleanup(struct spi_device *spi)
858 struct chip_data *chip = spi_get_ctldata(spi);
859 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
864 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
865 gpio_free(chip->gpio_cs);
870 static int pxa2xx_spi_probe(struct platform_device *pdev)
872 struct device *dev = &pdev->dev;
873 struct pxa2xx_spi_master *platform_info;
874 struct spi_master *master;
875 struct driver_data *drv_data;
876 struct ssp_device *ssp;
879 platform_info = dev_get_platdata(dev);
880 if (!platform_info) {
881 dev_err(&pdev->dev, "missing platform data\n");
885 ssp = pxa_ssp_request(pdev->id, pdev->name);
887 ssp = &platform_info->ssp;
889 if (!ssp->mmio_base) {
890 dev_err(&pdev->dev, "failed to get ssp\n");
894 /* Allocate master with space for drv_data and null dma buffer */
895 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
897 dev_err(&pdev->dev, "cannot alloc spi_master\n");
901 drv_data = spi_master_get_devdata(master);
902 drv_data->master = master;
903 drv_data->master_info = platform_info;
904 drv_data->pdev = pdev;
907 master->dev.parent = &pdev->dev;
908 master->dev.of_node = pdev->dev.of_node;
909 /* the spi->mode bits understood by this driver: */
910 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
912 master->bus_num = ssp->port_id;
913 master->num_chipselect = platform_info->num_chipselect;
914 master->dma_alignment = DMA_ALIGNMENT;
915 master->cleanup = cleanup;
916 master->setup = setup;
917 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
919 drv_data->ssp_type = ssp->type;
920 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
922 drv_data->ioaddr = ssp->mmio_base;
923 drv_data->ssdr_physical = ssp->phys_base + SSDR;
924 if (pxa25x_ssp_comp(drv_data)) {
925 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
926 drv_data->dma_cr1 = 0;
927 drv_data->clear_sr = SSSR_ROR;
928 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
930 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
931 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
932 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
933 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
936 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
939 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
940 goto out_error_master_alloc;
943 /* Setup DMA if requested */
944 drv_data->tx_channel = -1;
945 drv_data->rx_channel = -1;
946 if (platform_info->enable_dma) {
947 status = pxa2xx_spi_dma_setup(drv_data);
949 dev_warn(dev, "failed to setup DMA, using PIO\n");
950 platform_info->enable_dma = false;
954 /* Enable SOC clock */
955 clk_prepare_enable(ssp->clk);
957 drv_data->max_clk_rate = clk_get_rate(ssp->clk);
959 /* Load default SSP configuration */
960 write_SSCR0(0, drv_data->ioaddr);
961 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
962 SSCR1_TxTresh(TX_THRESH_DFLT),
964 write_SSCR0(SSCR0_SCR(2)
968 if (!pxa25x_ssp_comp(drv_data))
969 write_SSTO(0, drv_data->ioaddr);
970 write_SSPSP(0, drv_data->ioaddr);
972 tasklet_init(&drv_data->pump_transfers, pump_transfers,
973 (unsigned long)drv_data);
975 /* Register with the SPI framework */
976 platform_set_drvdata(pdev, drv_data);
977 status = spi_register_master(master);
979 dev_err(&pdev->dev, "problem registering spi master\n");
980 goto out_error_clock_enabled;
985 out_error_clock_enabled:
986 clk_disable_unprepare(ssp->clk);
987 pxa2xx_spi_dma_release(drv_data);
988 free_irq(ssp->irq, drv_data);
990 out_error_master_alloc:
991 spi_master_put(master);
996 static int pxa2xx_spi_remove(struct platform_device *pdev)
998 struct driver_data *drv_data = platform_get_drvdata(pdev);
999 struct ssp_device *ssp;
1003 ssp = drv_data->ssp;
1005 /* Disable the SSP at the peripheral and SOC level */
1006 write_SSCR0(0, drv_data->ioaddr);
1007 clk_disable_unprepare(ssp->clk);
1010 if (drv_data->master_info->enable_dma)
1011 pxa2xx_spi_dma_release(drv_data);
1014 free_irq(ssp->irq, drv_data);
1019 /* Disconnect from the SPI framework */
1020 spi_unregister_master(drv_data->master);
1022 /* Prevent double remove */
1023 platform_set_drvdata(pdev, NULL);
1028 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1032 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1033 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1037 static int pxa2xx_spi_suspend(struct device *dev)
1039 struct driver_data *drv_data = dev_get_drvdata(dev);
1040 struct ssp_device *ssp = drv_data->ssp;
1043 status = spi_master_suspend(drv_data->master);
1046 write_SSCR0(0, drv_data->ioaddr);
1047 clk_disable_unprepare(ssp->clk);
1052 static int pxa2xx_spi_resume(struct device *dev)
1054 struct driver_data *drv_data = dev_get_drvdata(dev);
1055 struct ssp_device *ssp = drv_data->ssp;
1058 pxa2xx_spi_dma_resume(drv_data);
1060 /* Enable the SSP clock */
1061 clk_prepare_enable(ssp->clk);
1063 /* Start the queue running */
1064 status = spi_master_resume(drv_data->master);
1066 dev_err(dev, "problem starting queue (%d)\n", status);
1073 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1074 .suspend = pxa2xx_spi_suspend,
1075 .resume = pxa2xx_spi_resume,
1079 static struct platform_driver driver = {
1081 .name = "pxa2xx-spi",
1082 .owner = THIS_MODULE,
1084 .pm = &pxa2xx_spi_pm_ops,
1087 .probe = pxa2xx_spi_probe,
1088 .remove = pxa2xx_spi_remove,
1089 .shutdown = pxa2xx_spi_shutdown,
1092 static int __init pxa2xx_spi_init(void)
1094 return platform_driver_register(&driver);
1096 subsys_initcall(pxa2xx_spi_init);
1098 static void __exit pxa2xx_spi_exit(void)
1100 platform_driver_unregister(&driver);
1102 module_exit(pxa2xx_spi_exit);