Pileus Git - ~andy/linux/blob - drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/omap-dma.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/err.h>
  35 #include <linux/clk.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/pinctrl/consumer.h>
  42 #include <linux/err.h>
  43
  44 #include <linux/spi/spi.h>
  45
  46 #include <plat/clock.h>
  47 #include <linux/platform_data/spi-omap2-mcspi.h>
  48
  49 #define OMAP2_MCSPI_MAX_FREQ            48000000
  50 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  51
  52 #define OMAP2_MCSPI_REVISION            0x00
  53 #define OMAP2_MCSPI_SYSSTATUS           0x14
  54 #define OMAP2_MCSPI_IRQSTATUS           0x18
  55 #define OMAP2_MCSPI_IRQENABLE           0x1c
  56 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  57 #define OMAP2_MCSPI_SYST                0x24
  58 #define OMAP2_MCSPI_MODULCTRL           0x28
  59
  60 /* per-channel banks, 0x14 bytes each, first is: */
  61 #define OMAP2_MCSPI_CHCONF0             0x2c
  62 #define OMAP2_MCSPI_CHSTAT0             0x30
  63 #define OMAP2_MCSPI_CHCTRL0             0x34
  64 #define OMAP2_MCSPI_TX0                 0x38
  65 #define OMAP2_MCSPI_RX0                 0x3c
  66
  67 /* per-register bitmasks: */
  68
  69 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  70 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  71 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  72
  73 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  74 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  75 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  76 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  77 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  78 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  79 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  80 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  81 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  82 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  83 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  84 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  85 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  86 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  87 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  88
  89 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  90 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  91 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  92
  93 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  94
  95 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  96
  97 /* We have 2 DMA channels per CS, one for RX and one for TX */
  98 struct omap2_mcspi_dma {
  99         struct dma_chan *dma_tx;
 100         struct dma_chan *dma_rx;
 101
 102         int dma_tx_sync_dev;
 103         int dma_rx_sync_dev;
 104
 105         struct completion dma_tx_completion;
 106         struct completion dma_rx_completion;
 107 };
 108
 109 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 110  * cache operations; better heuristics consider wordsize and bitrate.
 111  */
 112 #define DMA_MIN_BYTES                   160
 113
 114
 115 /*
 116  * Used for context save and restore, structure members to be updated whenever
 117  * corresponding registers are modified.
 118  */
 119 struct omap2_mcspi_regs {
 120         u32 modulctrl;
 121         u32 wakeupenable;
 122         struct list_head cs;
 123 };
 124
 125 struct omap2_mcspi {
 126         struct spi_master       *master;
 127         /* Virtual base address of the controller */
 128         void __iomem            *base;
 129         unsigned long           phys;
 130         /* SPI1 has 4 channels, while SPI2 has 2 */
 131         struct omap2_mcspi_dma  *dma_channels;
 132         struct device           *dev;
 133         struct omap2_mcspi_regs ctx;
 134 };
 135
 136 struct omap2_mcspi_cs {
 137         void __iomem            *base;
 138         unsigned long           phys;
 139         int                     word_len;
 140         struct list_head        node;
 141         /* Context save and restore shadow register */
 142         u32                     chconf0;
 143 };
 144
 145 static inline void mcspi_write_reg(struct spi_master *master,
 146                 int idx, u32 val)
 147 {
 148         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 149
 150         __raw_writel(val, mcspi->base + idx);
 151 }
 152
 153 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 154 {
 155         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 156
 157         return __raw_readl(mcspi->base + idx);
 158 }
 159
 160 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 161                 int idx, u32 val)
 162 {
 163         struct omap2_mcspi_cs   *cs = spi->controller_state;
 164
 165         __raw_writel(val, cs->base +  idx);
 166 }
 167
 168 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 169 {
 170         struct omap2_mcspi_cs   *cs = spi->controller_state;
 171
 172         return __raw_readl(cs->base + idx);
 173 }
 174
 175 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 176 {
 177         struct omap2_mcspi_cs *cs = spi->controller_state;
 178
 179         return cs->chconf0;
 180 }
 181
 182 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 183 {
 184         struct omap2_mcspi_cs *cs = spi->controller_state;
 185
 186         cs->chconf0 = val;
 187         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 188         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 189 }
 190
 191 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 192                 int is_read, int enable)
 193 {
 194         u32 l, rw;
 195
 196         l = mcspi_cached_chconf0(spi);
 197
 198         if (is_read) /* 1 is read, 0 write */
 199                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 200         else
 201                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 202
 203         if (enable)
 204                 l |= rw;
 205         else
 206                 l &= ~rw;
 207
 208         mcspi_write_chconf0(spi, l);
 209 }
 210
 211 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 212 {
 213         u32 l;
 214
 215         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 216         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 217         /* Flash post-writes */
 218         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 219 }
 220
 221 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 222 {
 223         u32 l;
 224
 225         l = mcspi_cached_chconf0(spi);
 226         if (cs_active)
 227                 l |= OMAP2_MCSPI_CHCONF_FORCE;
 228         else
 229                 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 230
 231         mcspi_write_chconf0(spi, l);
 232 }
 233
 234 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 235 {
 236         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 237         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 238         u32 l;
 239
 240         /*
 241          * Setup when switching from (reset default) slave mode
 242          * to single-channel master mode
 243          */
 244         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 245         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 246         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 247         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 248
 249         ctx->modulctrl = l;
 250 }
 251
 252 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 253 {
 254         struct spi_master       *spi_cntrl = mcspi->master;
 255         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 256         struct omap2_mcspi_cs   *cs;
 257
 258         /* McSPI: context restore */
 259         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 260         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 261
 262         list_for_each_entry(cs, &ctx->cs, node)
 263                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 264 }
 265
 266 static int omap2_prepare_transfer(struct spi_master *master)
 267 {
 268         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 269
 270         pm_runtime_get_sync(mcspi->dev);
 271         return 0;
 272 }
 273
 274 static int omap2_unprepare_transfer(struct spi_master *master)
 275 {
 276         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 277
 278         pm_runtime_mark_last_busy(mcspi->dev);
 279         pm_runtime_put_autosuspend(mcspi->dev);
 280         return 0;
 281 }
 282
 283 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 284 {
 285         unsigned long timeout;
 286
 287         timeout = jiffies + msecs_to_jiffies(1000);
 288         while (!(__raw_readl(reg) & bit)) {
 289                 if (time_after(jiffies, timeout))
 290                         return -1;
 291                 cpu_relax();
 292         }
 293         return 0;
 294 }
 295
 296 static void omap2_mcspi_rx_callback(void *data)
 297 {
 298         struct spi_device *spi = data;
 299         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 300         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 301
 302         complete(&mcspi_dma->dma_rx_completion);
 303
 304         /* We must disable the DMA RX request */
 305         omap2_mcspi_set_dma_req(spi, 1, 0);
 306 }
 307
 308 static void omap2_mcspi_tx_callback(void *data)
 309 {
 310         struct spi_device *spi = data;
 311         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 312         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 313
 314         complete(&mcspi_dma->dma_tx_completion);
 315
 316         /* We must disable the DMA TX request */
 317         omap2_mcspi_set_dma_req(spi, 0, 0);
 318 }
 319
 320 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 321                                 struct spi_transfer *xfer,
 322                                 struct dma_slave_config cfg)
 323 {
 324         struct omap2_mcspi      *mcspi;
 325         struct omap2_mcspi_dma  *mcspi_dma;
 326         unsigned int            count;
 327         u8                      * rx;
 328         const u8                * tx;
 329         void __iomem            *chstat_reg;
 330         struct omap2_mcspi_cs   *cs = spi->controller_state;
 331
 332         mcspi = spi_master_get_devdata(spi->master);
 333         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 334         count = xfer->len;
 335
 336         rx = xfer->rx_buf;
 337         tx = xfer->tx_buf;
 338         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 339
 340         if (mcspi_dma->dma_tx) {
 341                 struct dma_async_tx_descriptor *tx;
 342                 struct scatterlist sg;
 343
 344                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 345
 346                 sg_init_table(&sg, 1);
 347                 sg_dma_address(&sg) = xfer->tx_dma;
 348                 sg_dma_len(&sg) = xfer->len;
 349
 350                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 351                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 352                 if (tx) {
 353                         tx->callback = omap2_mcspi_tx_callback;
 354                         tx->callback_param = spi;
 355                         dmaengine_submit(tx);
 356                 } else {
 357                         /* FIXME: fall back to PIO? */
 358                 }
 359         }
 360         dma_async_issue_pending(mcspi_dma->dma_tx);
 361         omap2_mcspi_set_dma_req(spi, 0, 1);
 362
 363         wait_for_completion(&mcspi_dma->dma_tx_completion);
 364         dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
 365                          DMA_TO_DEVICE);
 366
 367         /* for TX_ONLY mode, be sure all words have shifted out */
 368         if (rx == NULL) {
 369                 if (mcspi_wait_for_reg_bit(chstat_reg,
 370                                         OMAP2_MCSPI_CHSTAT_TXS) < 0)
 371                         dev_err(&spi->dev, "TXS timed out\n");
 372                 else if (mcspi_wait_for_reg_bit(chstat_reg,
 373                                         OMAP2_MCSPI_CHSTAT_EOT) < 0)
 374                         dev_err(&spi->dev, "EOT timed out\n");
 375         }
 376 }
 377
 378 static unsigned
 379 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 380                                 struct dma_slave_config cfg,
 381                                 unsigned es)
 382 {
 383         struct omap2_mcspi      *mcspi;
 384         struct omap2_mcspi_dma  *mcspi_dma;
 385         unsigned int            count;
 386         u32                     l;
 387         int                     elements = 0;
 388         int                     word_len, element_count;
 389         struct omap2_mcspi_cs   *cs = spi->controller_state;
 390         mcspi = spi_master_get_devdata(spi->master);
 391         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 392         count = xfer->len;
 393         word_len = cs->word_len;
 394         l = mcspi_cached_chconf0(spi);
 395
 396         if (word_len <= 8)
 397                 element_count = count;
 398         else if (word_len <= 16)
 399                 element_count = count >> 1;
 400         else /* word_len <= 32 */
 401                 element_count = count >> 2;
 402
 403         if (mcspi_dma->dma_rx) {
 404                 struct dma_async_tx_descriptor *tx;
 405                 struct scatterlist sg;
 406                 size_t len = xfer->len - es;
 407
 408                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 409
 410                 if (l & OMAP2_MCSPI_CHCONF_TURBO)
 411                         len -= es;
 412
 413                 sg_init_table(&sg, 1);
 414                 sg_dma_address(&sg) = xfer->rx_dma;
 415                 sg_dma_len(&sg) = len;
 416
 417                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 418                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 419                                 DMA_CTRL_ACK);
 420                 if (tx) {
 421                         tx->callback = omap2_mcspi_rx_callback;
 422                         tx->callback_param = spi;
 423                         dmaengine_submit(tx);
 424                 } else {
 425                                 /* FIXME: fall back to PIO? */
 426                 }
 427         }
 428
 429         dma_async_issue_pending(mcspi_dma->dma_rx);
 430         omap2_mcspi_set_dma_req(spi, 1, 1);
 431
 432         wait_for_completion(&mcspi_dma->dma_rx_completion);
 433         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 434                          DMA_FROM_DEVICE);
 435         omap2_mcspi_set_enable(spi, 0);
 436
 437         elements = element_count - 1;
 438
 439         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 440                 elements--;
 441
 442                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 443                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 444                         u32 w;
 445
 446                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 447                         if (word_len <= 8)
 448                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 449                         else if (word_len <= 16)
 450                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 451                         else /* word_len <= 32 */
 452                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 453                 } else {
 454                         dev_err(&spi->dev, "DMA RX penultimate word empty");
 455                         count -= (word_len <= 8)  ? 2 :
 456                                 (word_len <= 16) ? 4 :
 457                                 /* word_len <= 32 */ 8;
 458                         omap2_mcspi_set_enable(spi, 1);
 459                         return count;
 460                 }
 461         }
 462         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 463                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 464                 u32 w;
 465
 466                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 467                 if (word_len <= 8)
 468                         ((u8 *)xfer->rx_buf)[elements] = w;
 469                 else if (word_len <= 16)
 470                         ((u16 *)xfer->rx_buf)[elements] = w;
 471                 else /* word_len <= 32 */
 472                         ((u32 *)xfer->rx_buf)[elements] = w;
 473         } else {
 474                 dev_err(&spi->dev, "DMA RX last word empty");
 475                 count -= (word_len <= 8)  ? 1 :
 476                          (word_len <= 16) ? 2 :
 477                        /* word_len <= 32 */ 4;
 478         }
 479         omap2_mcspi_set_enable(spi, 1);
 480         return count;
 481 }
 482
 483 static unsigned
 484 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 485 {
 486         struct omap2_mcspi      *mcspi;
 487         struct omap2_mcspi_cs   *cs = spi->controller_state;
 488         struct omap2_mcspi_dma  *mcspi_dma;
 489         unsigned int            count;
 490         u32                     l;
 491         u8                      *rx;
 492         const u8                *tx;
 493         struct dma_slave_config cfg;
 494         enum dma_slave_buswidth width;
 495         unsigned es;
 496
 497         mcspi = spi_master_get_devdata(spi->master);
 498         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 499         l = mcspi_cached_chconf0(spi);
 500
 501
 502         if (cs->word_len <= 8) {
 503                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 504                 es = 1;
 505         } else if (cs->word_len <= 16) {
 506                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 507                 es = 2;
 508         } else {
 509                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 510                 es = 4;
 511         }
 512
 513         memset(&cfg, 0, sizeof(cfg));
 514         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 515         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 516         cfg.src_addr_width = width;
 517         cfg.dst_addr_width = width;
 518         cfg.src_maxburst = 1;
 519         cfg.dst_maxburst = 1;
 520
 521         rx = xfer->rx_buf;
 522         tx = xfer->tx_buf;
 523
 524         count = xfer->len;
 525
 526         if (tx != NULL)
 527                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 528
 529         if (rx != NULL)
 530                 return omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 531
 532         return count;
 533 }
 534
 535 static unsigned
 536 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 537 {
 538         struct omap2_mcspi      *mcspi;
 539         struct omap2_mcspi_cs   *cs = spi->controller_state;
 540         unsigned int            count, c;
 541         u32                     l;
 542         void __iomem            *base = cs->base;
 543         void __iomem            *tx_reg;
 544         void __iomem            *rx_reg;
 545         void __iomem            *chstat_reg;
 546         int                     word_len;
 547
 548         mcspi = spi_master_get_devdata(spi->master);
 549         count = xfer->len;
 550         c = count;
 551         word_len = cs->word_len;
 552
 553         l = mcspi_cached_chconf0(spi);
 554
 555         /* We store the pre-calculated register addresses on stack to speed
 556          * up the transfer loop. */
 557         tx_reg          = base + OMAP2_MCSPI_TX0;
 558         rx_reg          = base + OMAP2_MCSPI_RX0;
 559         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 560
 561         if (c < (word_len>>3))
 562                 return 0;
 563
 564         if (word_len <= 8) {
 565                 u8              *rx;
 566                 const u8        *tx;
 567
 568                 rx = xfer->rx_buf;
 569                 tx = xfer->tx_buf;
 570
 571                 do {
 572                         c -= 1;
 573                         if (tx != NULL) {
 574                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 575                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 576                                         dev_err(&spi->dev, "TXS timed out\n");
 577                                         goto out;
 578                                 }
 579                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 580                                                 word_len, *tx);
 581                                 __raw_writel(*tx++, tx_reg);
 582                         }
 583                         if (rx != NULL) {
 584                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 585                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 586                                         dev_err(&spi->dev, "RXS timed out\n");
 587                                         goto out;
 588                                 }
 589
 590                                 if (c == 1 && tx == NULL &&
 591                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 592                                         omap2_mcspi_set_enable(spi, 0);
 593                                         *rx++ = __raw_readl(rx_reg);
 594                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 595                                                     word_len, *(rx - 1));
 596                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 597                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 598                                                 dev_err(&spi->dev,
 599                                                         "RXS timed out\n");
 600                                                 goto out;
 601                                         }
 602                                         c = 0;
 603                                 } else if (c == 0 && tx == NULL) {
 604                                         omap2_mcspi_set_enable(spi, 0);
 605                                 }
 606
 607                                 *rx++ = __raw_readl(rx_reg);
 608                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 609                                                 word_len, *(rx - 1));
 610                         }
 611                 } while (c);
 612         } else if (word_len <= 16) {
 613                 u16             *rx;
 614                 const u16       *tx;
 615
 616                 rx = xfer->rx_buf;
 617                 tx = xfer->tx_buf;
 618                 do {
 619                         c -= 2;
 620                         if (tx != NULL) {
 621                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 622                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 623                                         dev_err(&spi->dev, "TXS timed out\n");
 624                                         goto out;
 625                                 }
 626                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 627                                                 word_len, *tx);
 628                                 __raw_writel(*tx++, tx_reg);
 629                         }
 630                         if (rx != NULL) {
 631                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 632                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 633                                         dev_err(&spi->dev, "RXS timed out\n");
 634                                         goto out;
 635                                 }
 636
 637                                 if (c == 2 && tx == NULL &&
 638                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 639                                         omap2_mcspi_set_enable(spi, 0);
 640                                         *rx++ = __raw_readl(rx_reg);
 641                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 642                                                     word_len, *(rx - 1));
 643                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 644                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 645                                                 dev_err(&spi->dev,
 646                                                         "RXS timed out\n");
 647                                                 goto out;
 648                                         }
 649                                         c = 0;
 650                                 } else if (c == 0 && tx == NULL) {
 651                                         omap2_mcspi_set_enable(spi, 0);
 652                                 }
 653
 654                                 *rx++ = __raw_readl(rx_reg);
 655                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 656                                                 word_len, *(rx - 1));
 657                         }
 658                 } while (c >= 2);
 659         } else if (word_len <= 32) {
 660                 u32             *rx;
 661                 const u32       *tx;
 662
 663                 rx = xfer->rx_buf;
 664                 tx = xfer->tx_buf;
 665                 do {
 666                         c -= 4;
 667                         if (tx != NULL) {
 668                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 669                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 670                                         dev_err(&spi->dev, "TXS timed out\n");
 671                                         goto out;
 672                                 }
 673                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 674                                                 word_len, *tx);
 675                                 __raw_writel(*tx++, tx_reg);
 676                         }
 677                         if (rx != NULL) {
 678                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 679                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 680                                         dev_err(&spi->dev, "RXS timed out\n");
 681                                         goto out;
 682                                 }
 683
 684                                 if (c == 4 && tx == NULL &&
 685                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 686                                         omap2_mcspi_set_enable(spi, 0);
 687                                         *rx++ = __raw_readl(rx_reg);
 688                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 689                                                     word_len, *(rx - 1));
 690                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 691                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 692                                                 dev_err(&spi->dev,
 693                                                         "RXS timed out\n");
 694                                                 goto out;
 695                                         }
 696                                         c = 0;
 697                                 } else if (c == 0 && tx == NULL) {
 698                                         omap2_mcspi_set_enable(spi, 0);
 699                                 }
 700
 701                                 *rx++ = __raw_readl(rx_reg);
 702                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 703                                                 word_len, *(rx - 1));
 704                         }
 705                 } while (c >= 4);
 706         }
 707
 708         /* for TX_ONLY mode, be sure all words have shifted out */
 709         if (xfer->rx_buf == NULL) {
 710                 if (mcspi_wait_for_reg_bit(chstat_reg,
 711                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 712                         dev_err(&spi->dev, "TXS timed out\n");
 713                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 714                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 715                         dev_err(&spi->dev, "EOT timed out\n");
 716
 717                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 718                  * otherwise these rx datas will affect the direct following
 719                  * RX_ONLY transfer.
 720                  */
 721                 omap2_mcspi_set_enable(spi, 0);
 722         }
 723 out:
 724         omap2_mcspi_set_enable(spi, 1);
 725         return count - c;
 726 }
 727
 728 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 729 {
 730         u32 div;
 731
 732         for (div = 0; div < 15; div++)
 733                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 734                         return div;
 735
 736         return 15;
 737 }
 738
 739 /* called only when no transfer is active to this device */
 740 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 741                 struct spi_transfer *t)
 742 {
 743         struct omap2_mcspi_cs *cs = spi->controller_state;
 744         struct omap2_mcspi *mcspi;
 745         struct spi_master *spi_cntrl;
 746         u32 l = 0, div = 0;
 747         u8 word_len = spi->bits_per_word;
 748         u32 speed_hz = spi->max_speed_hz;
 749
 750         mcspi = spi_master_get_devdata(spi->master);
 751         spi_cntrl = mcspi->master;
 752
 753         if (t != NULL && t->bits_per_word)
 754                 word_len = t->bits_per_word;
 755
 756         cs->word_len = word_len;
 757
 758         if (t && t->speed_hz)
 759                 speed_hz = t->speed_hz;
 760
 761         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 762         div = omap2_mcspi_calc_divisor(speed_hz);
 763
 764         l = mcspi_cached_chconf0(spi);
 765
 766         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 767          * REVISIT: this controller could support SPI_3WIRE mode.
 768          */
 769         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
 770         l |= OMAP2_MCSPI_CHCONF_DPE0;
 771
 772         /* wordlength */
 773         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 774         l |= (word_len - 1) << 7;
 775
 776         /* set chipselect polarity; manage with FORCE */
 777         if (!(spi->mode & SPI_CS_HIGH))
 778                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 779         else
 780                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 781
 782         /* set clock divisor */
 783         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 784         l |= div << 2;
 785
 786         /* set SPI mode 0..3 */
 787         if (spi->mode & SPI_CPOL)
 788                 l |= OMAP2_MCSPI_CHCONF_POL;
 789         else
 790                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 791         if (spi->mode & SPI_CPHA)
 792                 l |= OMAP2_MCSPI_CHCONF_PHA;
 793         else
 794                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 795
 796         mcspi_write_chconf0(spi, l);
 797
 798         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 799                         OMAP2_MCSPI_MAX_FREQ >> div,
 800                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 801                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 802
 803         return 0;
 804 }
 805
 806 static int omap2_mcspi_request_dma(struct spi_device *spi)
 807 {
 808         struct spi_master       *master = spi->master;
 809         struct omap2_mcspi      *mcspi;
 810         struct omap2_mcspi_dma  *mcspi_dma;
 811         dma_cap_mask_t mask;
 812         unsigned sig;
 813
 814         mcspi = spi_master_get_devdata(master);
 815         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 816
 817         init_completion(&mcspi_dma->dma_rx_completion);
 818         init_completion(&mcspi_dma->dma_tx_completion);
 819
 820         dma_cap_zero(mask);
 821         dma_cap_set(DMA_SLAVE, mask);
 822         sig = mcspi_dma->dma_rx_sync_dev;
 823         mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 824         if (!mcspi_dma->dma_rx) {
 825                 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
 826                 return -EAGAIN;
 827         }
 828
 829         sig = mcspi_dma->dma_tx_sync_dev;
 830         mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 831         if (!mcspi_dma->dma_tx) {
 832                 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
 833                 dma_release_channel(mcspi_dma->dma_rx);
 834                 mcspi_dma->dma_rx = NULL;
 835                 return -EAGAIN;
 836         }
 837
 838         return 0;
 839 }
 840
 841 static int omap2_mcspi_setup(struct spi_device *spi)
 842 {
 843         int                     ret;
 844         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 845         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 846         struct omap2_mcspi_dma  *mcspi_dma;
 847         struct omap2_mcspi_cs   *cs = spi->controller_state;
 848
 849         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 850                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 851                         spi->bits_per_word);
 852                 return -EINVAL;
 853         }
 854
 855         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 856
 857         if (!cs) {
 858                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 859                 if (!cs)
 860                         return -ENOMEM;
 861                 cs->base = mcspi->base + spi->chip_select * 0x14;
 862                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 863                 cs->chconf0 = 0;
 864                 spi->controller_state = cs;
 865                 /* Link this to context save list */
 866                 list_add_tail(&cs->node, &ctx->cs);
 867         }
 868
 869         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
 870                 ret = omap2_mcspi_request_dma(spi);
 871                 if (ret < 0)
 872                         return ret;
 873         }
 874
 875         ret = pm_runtime_get_sync(mcspi->dev);
 876         if (ret < 0)
 877                 return ret;
 878
 879         ret = omap2_mcspi_setup_transfer(spi, NULL);
 880         pm_runtime_mark_last_busy(mcspi->dev);
 881         pm_runtime_put_autosuspend(mcspi->dev);
 882
 883         return ret;
 884 }
 885
 886 static void omap2_mcspi_cleanup(struct spi_device *spi)
 887 {
 888         struct omap2_mcspi      *mcspi;
 889         struct omap2_mcspi_dma  *mcspi_dma;
 890         struct omap2_mcspi_cs   *cs;
 891
 892         mcspi = spi_master_get_devdata(spi->master);
 893
 894         if (spi->controller_state) {
 895                 /* Unlink controller state from context save list */
 896                 cs = spi->controller_state;
 897                 list_del(&cs->node);
 898
 899                 kfree(cs);
 900         }
 901
 902         if (spi->chip_select < spi->master->num_chipselect) {
 903                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 904
 905                 if (mcspi_dma->dma_rx) {
 906                         dma_release_channel(mcspi_dma->dma_rx);
 907                         mcspi_dma->dma_rx = NULL;
 908                 }
 909                 if (mcspi_dma->dma_tx) {
 910                         dma_release_channel(mcspi_dma->dma_tx);
 911                         mcspi_dma->dma_tx = NULL;
 912                 }
 913         }
 914 }
 915
 916 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
 917 {
 918
 919         /* We only enable one channel at a time -- the one whose message is
 920          * -- although this controller would gladly
 921          * arbitrate among multiple channels.  This corresponds to "single
 922          * channel" master mode.  As a side effect, we need to manage the
 923          * chipselect with the FORCE bit ... CS != channel enable.
 924          */
 925
 926         struct spi_device               *spi;
 927         struct spi_transfer             *t = NULL;
 928         int                             cs_active = 0;
 929         struct omap2_mcspi_cs           *cs;
 930         struct omap2_mcspi_device_config *cd;
 931         int                             par_override = 0;
 932         int                             status = 0;
 933         u32                             chconf;
 934
 935         spi = m->spi;
 936         cs = spi->controller_state;
 937         cd = spi->controller_data;
 938
 939         omap2_mcspi_set_enable(spi, 1);
 940         list_for_each_entry(t, &m->transfers, transfer_list) {
 941                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 942                         status = -EINVAL;
 943                         break;
 944                 }
 945                 if (par_override || t->speed_hz || t->bits_per_word) {
 946                         par_override = 1;
 947                         status = omap2_mcspi_setup_transfer(spi, t);
 948                         if (status < 0)
 949                                 break;
 950                         if (!t->speed_hz && !t->bits_per_word)
 951                                 par_override = 0;
 952                 }
 953
 954                 if (!cs_active) {
 955                         omap2_mcspi_force_cs(spi, 1);
 956                         cs_active = 1;
 957                 }
 958
 959                 chconf = mcspi_cached_chconf0(spi);
 960                 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 961                 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
 962
 963                 if (t->tx_buf == NULL)
 964                         chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 965                 else if (t->rx_buf == NULL)
 966                         chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 967
 968                 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
 969                         /* Turbo mode is for more than one word */
 970                         if (t->len > ((cs->word_len + 7) >> 3))
 971                                 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
 972                 }
 973
 974                 mcspi_write_chconf0(spi, chconf);
 975
 976                 if (t->len) {
 977                         unsigned        count;
 978
 979                         /* RX_ONLY mode needs dummy data in TX reg */
 980                         if (t->tx_buf == NULL)
 981                                 __raw_writel(0, cs->base
 982                                                 + OMAP2_MCSPI_TX0);
 983
 984                         if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
 985                                 count = omap2_mcspi_txrx_dma(spi, t);
 986                         else
 987                                 count = omap2_mcspi_txrx_pio(spi, t);
 988                         m->actual_length += count;
 989
 990                         if (count != t->len) {
 991                                 status = -EIO;
 992                                 break;
 993                         }
 994                 }
 995
 996                 if (t->delay_usecs)
 997                         udelay(t->delay_usecs);
 998
 999                 /* ignore the "leave it on after last xfer" hint */
1000                 if (t->cs_change) {
1001                         omap2_mcspi_force_cs(spi, 0);
1002                         cs_active = 0;
1003                 }
1004         }
1005         /* Restore defaults if they were overriden */
1006         if (par_override) {
1007                 par_override = 0;
1008                 status = omap2_mcspi_setup_transfer(spi, NULL);
1009         }
1010
1011         if (cs_active)
1012                 omap2_mcspi_force_cs(spi, 0);
1013
1014         omap2_mcspi_set_enable(spi, 0);
1015
1016         m->status = status;
1017
1018 }
1019
1020 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1021                                                 struct spi_message *m)
1022 {
1023         struct omap2_mcspi      *mcspi;
1024         struct spi_transfer     *t;
1025
1026         mcspi = spi_master_get_devdata(master);
1027         m->actual_length = 0;
1028         m->status = 0;
1029
1030         /* reject invalid messages and transfers */
1031         if (list_empty(&m->transfers))
1032                 return -EINVAL;
1033         list_for_each_entry(t, &m->transfers, transfer_list) {
1034                 const void      *tx_buf = t->tx_buf;
1035                 void            *rx_buf = t->rx_buf;
1036                 unsigned        len = t->len;
1037
1038                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1039                                 || (len && !(rx_buf || tx_buf))
1040                                 || (t->bits_per_word &&
1041                                         (  t->bits_per_word < 4
1042                                         || t->bits_per_word > 32))) {
1043                         dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1044                                         t->speed_hz,
1045                                         len,
1046                                         tx_buf ? "tx" : "",
1047                                         rx_buf ? "rx" : "",
1048                                         t->bits_per_word);
1049                         return -EINVAL;
1050                 }
1051                 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1052                         dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1053                                 t->speed_hz,
1054                                 OMAP2_MCSPI_MAX_FREQ >> 15);
1055                         return -EINVAL;
1056                 }
1057
1058                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1059                         continue;
1060
1061                 if (tx_buf != NULL) {
1062                         t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1063                                         len, DMA_TO_DEVICE);
1064                         if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1065                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1066                                                 'T', len);
1067                                 return -EINVAL;
1068                         }
1069                 }
1070                 if (rx_buf != NULL) {
1071                         t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1072                                         DMA_FROM_DEVICE);
1073                         if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1074                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1075                                                 'R', len);
1076                                 if (tx_buf != NULL)
1077                                         dma_unmap_single(mcspi->dev, t->tx_dma,
1078                                                         len, DMA_TO_DEVICE);
1079                                 return -EINVAL;
1080                         }
1081                 }
1082         }
1083
1084         omap2_mcspi_work(mcspi, m);
1085         spi_finalize_current_message(master);
1086         return 0;
1087 }
1088
1089 static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1090 {
1091         struct spi_master       *master = mcspi->master;
1092         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1093         int                     ret = 0;
1094
1095         ret = pm_runtime_get_sync(mcspi->dev);
1096         if (ret < 0)
1097                 return ret;
1098
1099         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1100                                 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1101         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1102
1103         omap2_mcspi_set_master_mode(master);
1104         pm_runtime_mark_last_busy(mcspi->dev);
1105         pm_runtime_put_autosuspend(mcspi->dev);
1106         return 0;
1107 }
1108
1109 static int omap_mcspi_runtime_resume(struct device *dev)
1110 {
1111         struct omap2_mcspi      *mcspi;
1112         struct spi_master       *master;
1113
1114         master = dev_get_drvdata(dev);
1115         mcspi = spi_master_get_devdata(master);
1116         omap2_mcspi_restore_ctx(mcspi);
1117
1118         return 0;
1119 }
1120
1121 static struct omap2_mcspi_platform_config omap2_pdata = {
1122         .regs_offset = 0,
1123 };
1124
1125 static struct omap2_mcspi_platform_config omap4_pdata = {
1126         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1127 };
1128
1129 static const struct of_device_id omap_mcspi_of_match[] = {
1130         {
1131                 .compatible = "ti,omap2-mcspi",
1132                 .data = &omap2_pdata,
1133         },
1134         {
1135                 .compatible = "ti,omap4-mcspi",
1136                 .data = &omap4_pdata,
1137         },
1138         { },
1139 };
1140 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1141
1142 static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1143 {
1144         struct spi_master       *master;
1145         const struct omap2_mcspi_platform_config *pdata;
1146         struct omap2_mcspi      *mcspi;
1147         struct resource         *r;
1148         int                     status = 0, i;
1149         u32                     regs_offset = 0;
1150         static int              bus_num = 1;
1151         struct device_node      *node = pdev->dev.of_node;
1152         const struct of_device_id *match;
1153         struct pinctrl *pinctrl;
1154
1155         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1156         if (master == NULL) {
1157                 dev_dbg(&pdev->dev, "master allocation failed\n");
1158                 return -ENOMEM;
1159         }
1160
1161         /* the spi->mode bits understood by this driver: */
1162         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1163
1164         master->setup = omap2_mcspi_setup;
1165         master->prepare_transfer_hardware = omap2_prepare_transfer;
1166         master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1167         master->transfer_one_message = omap2_mcspi_transfer_one_message;
1168         master->cleanup = omap2_mcspi_cleanup;
1169         master->dev.of_node = node;
1170
1171         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1172         if (match) {
1173                 u32 num_cs = 1; /* default number of chipselect */
1174                 pdata = match->data;
1175
1176                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1177                 master->num_chipselect = num_cs;
1178                 master->bus_num = bus_num++;
1179         } else {
1180                 pdata = pdev->dev.platform_data;
1181                 master->num_chipselect = pdata->num_cs;
1182                 if (pdev->id != -1)
1183                         master->bus_num = pdev->id;
1184         }
1185         regs_offset = pdata->regs_offset;
1186
1187         dev_set_drvdata(&pdev->dev, master);
1188
1189         mcspi = spi_master_get_devdata(master);
1190         mcspi->master = master;
1191
1192         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1193         if (r == NULL) {
1194                 status = -ENODEV;
1195                 goto free_master;
1196         }
1197
1198         r->start += regs_offset;
1199         r->end += regs_offset;
1200         mcspi->phys = r->start;
1201
1202         mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
1203         if (!mcspi->base) {
1204                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1205                 status = -ENOMEM;
1206                 goto free_master;
1207         }
1208
1209         mcspi->dev = &pdev->dev;
1210
1211         INIT_LIST_HEAD(&mcspi->ctx.cs);
1212
1213         mcspi->dma_channels = kcalloc(master->num_chipselect,
1214                         sizeof(struct omap2_mcspi_dma),
1215                         GFP_KERNEL);
1216
1217         if (mcspi->dma_channels == NULL)
1218                 goto free_master;
1219
1220         for (i = 0; i < master->num_chipselect; i++) {
1221                 char dma_ch_name[14];
1222                 struct resource *dma_res;
1223
1224                 sprintf(dma_ch_name, "rx%d", i);
1225                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1226                                                         dma_ch_name);
1227                 if (!dma_res) {
1228                         dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1229                         status = -ENODEV;
1230                         break;
1231                 }
1232
1233                 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1234                 sprintf(dma_ch_name, "tx%d", i);
1235                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1236                                                         dma_ch_name);
1237                 if (!dma_res) {
1238                         dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1239                         status = -ENODEV;
1240                         break;
1241                 }
1242
1243                 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1244         }
1245
1246         if (status < 0)
1247                 goto dma_chnl_free;
1248
1249         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1250         if (IS_ERR(pinctrl))
1251                 dev_warn(&pdev->dev,
1252                         "pins are not configured from the driver\n");
1253
1254         pm_runtime_use_autosuspend(&pdev->dev);
1255         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1256         pm_runtime_enable(&pdev->dev);
1257
1258         if (status || omap2_mcspi_master_setup(mcspi) < 0)
1259                 goto disable_pm;
1260
1261         status = spi_register_master(master);
1262         if (status < 0)
1263                 goto disable_pm;
1264
1265         return status;
1266
1267 disable_pm:
1268         pm_runtime_disable(&pdev->dev);
1269 dma_chnl_free:
1270         kfree(mcspi->dma_channels);
1271 free_master:
1272         spi_master_put(master);
1273         return status;
1274 }
1275
1276 static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
1277 {
1278         struct spi_master       *master;
1279         struct omap2_mcspi      *mcspi;
1280         struct omap2_mcspi_dma  *dma_channels;
1281
1282         master = dev_get_drvdata(&pdev->dev);
1283         mcspi = spi_master_get_devdata(master);
1284         dma_channels = mcspi->dma_channels;
1285
1286         pm_runtime_put_sync(mcspi->dev);
1287         pm_runtime_disable(&pdev->dev);
1288
1289         spi_unregister_master(master);
1290         kfree(dma_channels);
1291
1292         return 0;
1293 }
1294
1295 /* work with hotplug and coldplug */
1296 MODULE_ALIAS("platform:omap2_mcspi");
1297
1298 #ifdef  CONFIG_SUSPEND
1299 /*
1300  * When SPI wake up from off-mode, CS is in activate state. If it was in
1301  * unactive state when driver was suspend, then force it to unactive state at
1302  * wake up.
1303  */
1304 static int omap2_mcspi_resume(struct device *dev)
1305 {
1306         struct spi_master       *master = dev_get_drvdata(dev);
1307         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1308         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1309         struct omap2_mcspi_cs   *cs;
1310
1311         pm_runtime_get_sync(mcspi->dev);
1312         list_for_each_entry(cs, &ctx->cs, node) {
1313                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1314                         /*
1315                          * We need to toggle CS state for OMAP take this
1316                          * change in account.
1317                          */
1318                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1319                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1320                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1321                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1322                 }
1323         }
1324         pm_runtime_mark_last_busy(mcspi->dev);
1325         pm_runtime_put_autosuspend(mcspi->dev);
1326         return 0;
1327 }
1328 #else
1329 #define omap2_mcspi_resume      NULL
1330 #endif
1331
1332 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1333         .resume = omap2_mcspi_resume,
1334         .runtime_resume = omap_mcspi_runtime_resume,
1335 };
1336
1337 static struct platform_driver omap2_mcspi_driver = {
1338         .driver = {
1339                 .name =         "omap2_mcspi",
1340                 .owner =        THIS_MODULE,
1341                 .pm =           &omap2_mcspi_pm_ops,
1342                 .of_match_table = omap_mcspi_of_match,
1343         },
1344         .probe =        omap2_mcspi_probe,
1345         .remove =       __devexit_p(omap2_mcspi_remove),
1346 };
1347
1348 module_platform_driver(omap2_mcspi_driver);
1349 MODULE_LICENSE("GPL");