2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
40 #include <linux/of_device.h>
41 #include <linux/pinctrl/consumer.h>
43 #include <linux/spi/spi.h>
45 #include <linux/platform_data/spi-omap2-mcspi.h>
47 #define OMAP2_MCSPI_MAX_FREQ 48000000
48 #define SPI_AUTOSUSPEND_TIMEOUT 2000
50 #define OMAP2_MCSPI_REVISION 0x00
51 #define OMAP2_MCSPI_SYSSTATUS 0x14
52 #define OMAP2_MCSPI_IRQSTATUS 0x18
53 #define OMAP2_MCSPI_IRQENABLE 0x1c
54 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
55 #define OMAP2_MCSPI_SYST 0x24
56 #define OMAP2_MCSPI_MODULCTRL 0x28
58 /* per-channel banks, 0x14 bytes each, first is: */
59 #define OMAP2_MCSPI_CHCONF0 0x2c
60 #define OMAP2_MCSPI_CHSTAT0 0x30
61 #define OMAP2_MCSPI_CHCTRL0 0x34
62 #define OMAP2_MCSPI_TX0 0x38
63 #define OMAP2_MCSPI_RX0 0x3c
65 /* per-register bitmasks: */
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
71 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
84 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
87 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
88 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
89 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
91 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
93 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
95 /* We have 2 DMA channels per CS, one for RX and one for TX */
96 struct omap2_mcspi_dma {
97 struct dma_chan *dma_tx;
98 struct dma_chan *dma_rx;
103 struct completion dma_tx_completion;
104 struct completion dma_rx_completion;
107 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
108 * cache operations; better heuristics consider wordsize and bitrate.
110 #define DMA_MIN_BYTES 160
114 * Used for context save and restore, structure members to be updated whenever
115 * corresponding registers are modified.
117 struct omap2_mcspi_regs {
124 struct spi_master *master;
125 /* Virtual base address of the controller */
128 /* SPI1 has 4 channels, while SPI2 has 2 */
129 struct omap2_mcspi_dma *dma_channels;
131 struct omap2_mcspi_regs ctx;
132 unsigned int pin_dir:1;
135 struct omap2_mcspi_cs {
139 struct list_head node;
140 /* Context save and restore shadow register */
144 static inline void mcspi_write_reg(struct spi_master *master,
147 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
149 __raw_writel(val, mcspi->base + idx);
152 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
156 return __raw_readl(mcspi->base + idx);
159 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
162 struct omap2_mcspi_cs *cs = spi->controller_state;
164 __raw_writel(val, cs->base + idx);
167 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
169 struct omap2_mcspi_cs *cs = spi->controller_state;
171 return __raw_readl(cs->base + idx);
174 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
176 struct omap2_mcspi_cs *cs = spi->controller_state;
181 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
183 struct omap2_mcspi_cs *cs = spi->controller_state;
186 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
187 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
190 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
191 int is_read, int enable)
195 l = mcspi_cached_chconf0(spi);
197 if (is_read) /* 1 is read, 0 write */
198 rw = OMAP2_MCSPI_CHCONF_DMAR;
200 rw = OMAP2_MCSPI_CHCONF_DMAW;
207 mcspi_write_chconf0(spi, l);
210 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
214 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
215 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
216 /* Flash post-writes */
217 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
220 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
224 l = mcspi_cached_chconf0(spi);
226 l |= OMAP2_MCSPI_CHCONF_FORCE;
228 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
230 mcspi_write_chconf0(spi, l);
233 static void omap2_mcspi_set_master_mode(struct spi_master *master)
235 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
236 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
240 * Setup when switching from (reset default) slave mode
241 * to single-channel master mode
243 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
244 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
245 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
246 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
251 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
253 struct spi_master *spi_cntrl = mcspi->master;
254 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
255 struct omap2_mcspi_cs *cs;
257 /* McSPI: context restore */
258 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
261 list_for_each_entry(cs, &ctx->cs, node)
262 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
265 static int omap2_prepare_transfer(struct spi_master *master)
267 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
269 pm_runtime_get_sync(mcspi->dev);
273 static int omap2_unprepare_transfer(struct spi_master *master)
275 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
277 pm_runtime_mark_last_busy(mcspi->dev);
278 pm_runtime_put_autosuspend(mcspi->dev);
282 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
284 unsigned long timeout;
286 timeout = jiffies + msecs_to_jiffies(1000);
287 while (!(__raw_readl(reg) & bit)) {
288 if (time_after(jiffies, timeout)) {
289 if (!(__raw_readl(reg) & bit))
299 static void omap2_mcspi_rx_callback(void *data)
301 struct spi_device *spi = data;
302 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
303 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
305 /* We must disable the DMA RX request */
306 omap2_mcspi_set_dma_req(spi, 1, 0);
308 complete(&mcspi_dma->dma_rx_completion);
311 static void omap2_mcspi_tx_callback(void *data)
313 struct spi_device *spi = data;
314 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
315 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
317 /* We must disable the DMA TX request */
318 omap2_mcspi_set_dma_req(spi, 0, 0);
320 complete(&mcspi_dma->dma_tx_completion);
323 static void omap2_mcspi_tx_dma(struct spi_device *spi,
324 struct spi_transfer *xfer,
325 struct dma_slave_config cfg)
327 struct omap2_mcspi *mcspi;
328 struct omap2_mcspi_dma *mcspi_dma;
331 mcspi = spi_master_get_devdata(spi->master);
332 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
335 if (mcspi_dma->dma_tx) {
336 struct dma_async_tx_descriptor *tx;
337 struct scatterlist sg;
339 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
341 sg_init_table(&sg, 1);
342 sg_dma_address(&sg) = xfer->tx_dma;
343 sg_dma_len(&sg) = xfer->len;
345 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
346 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
348 tx->callback = omap2_mcspi_tx_callback;
349 tx->callback_param = spi;
350 dmaengine_submit(tx);
352 /* FIXME: fall back to PIO? */
355 dma_async_issue_pending(mcspi_dma->dma_tx);
356 omap2_mcspi_set_dma_req(spi, 0, 1);
361 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
362 struct dma_slave_config cfg,
365 struct omap2_mcspi *mcspi;
366 struct omap2_mcspi_dma *mcspi_dma;
370 int word_len, element_count;
371 struct omap2_mcspi_cs *cs = spi->controller_state;
372 mcspi = spi_master_get_devdata(spi->master);
373 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
375 word_len = cs->word_len;
376 l = mcspi_cached_chconf0(spi);
379 element_count = count;
380 else if (word_len <= 16)
381 element_count = count >> 1;
382 else /* word_len <= 32 */
383 element_count = count >> 2;
385 if (mcspi_dma->dma_rx) {
386 struct dma_async_tx_descriptor *tx;
387 struct scatterlist sg;
388 size_t len = xfer->len - es;
390 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
392 if (l & OMAP2_MCSPI_CHCONF_TURBO)
395 sg_init_table(&sg, 1);
396 sg_dma_address(&sg) = xfer->rx_dma;
397 sg_dma_len(&sg) = len;
399 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
400 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
403 tx->callback = omap2_mcspi_rx_callback;
404 tx->callback_param = spi;
405 dmaengine_submit(tx);
407 /* FIXME: fall back to PIO? */
411 dma_async_issue_pending(mcspi_dma->dma_rx);
412 omap2_mcspi_set_dma_req(spi, 1, 1);
414 wait_for_completion(&mcspi_dma->dma_rx_completion);
415 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
417 omap2_mcspi_set_enable(spi, 0);
419 elements = element_count - 1;
421 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
424 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
425 & OMAP2_MCSPI_CHSTAT_RXS)) {
428 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
430 ((u8 *)xfer->rx_buf)[elements++] = w;
431 else if (word_len <= 16)
432 ((u16 *)xfer->rx_buf)[elements++] = w;
433 else /* word_len <= 32 */
434 ((u32 *)xfer->rx_buf)[elements++] = w;
436 dev_err(&spi->dev, "DMA RX penultimate word empty");
437 count -= (word_len <= 8) ? 2 :
438 (word_len <= 16) ? 4 :
439 /* word_len <= 32 */ 8;
440 omap2_mcspi_set_enable(spi, 1);
444 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
445 & OMAP2_MCSPI_CHSTAT_RXS)) {
448 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
450 ((u8 *)xfer->rx_buf)[elements] = w;
451 else if (word_len <= 16)
452 ((u16 *)xfer->rx_buf)[elements] = w;
453 else /* word_len <= 32 */
454 ((u32 *)xfer->rx_buf)[elements] = w;
456 dev_err(&spi->dev, "DMA RX last word empty");
457 count -= (word_len <= 8) ? 1 :
458 (word_len <= 16) ? 2 :
459 /* word_len <= 32 */ 4;
461 omap2_mcspi_set_enable(spi, 1);
466 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
468 struct omap2_mcspi *mcspi;
469 struct omap2_mcspi_cs *cs = spi->controller_state;
470 struct omap2_mcspi_dma *mcspi_dma;
475 struct dma_slave_config cfg;
476 enum dma_slave_buswidth width;
478 void __iomem *chstat_reg;
480 mcspi = spi_master_get_devdata(spi->master);
481 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
482 l = mcspi_cached_chconf0(spi);
485 if (cs->word_len <= 8) {
486 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
488 } else if (cs->word_len <= 16) {
489 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
492 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
496 memset(&cfg, 0, sizeof(cfg));
497 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
498 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
499 cfg.src_addr_width = width;
500 cfg.dst_addr_width = width;
501 cfg.src_maxburst = 1;
502 cfg.dst_maxburst = 1;
510 omap2_mcspi_tx_dma(spi, xfer, cfg);
513 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
516 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
517 wait_for_completion(&mcspi_dma->dma_tx_completion);
518 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
521 /* for TX_ONLY mode, be sure all words have shifted out */
523 if (mcspi_wait_for_reg_bit(chstat_reg,
524 OMAP2_MCSPI_CHSTAT_TXS) < 0)
525 dev_err(&spi->dev, "TXS timed out\n");
526 else if (mcspi_wait_for_reg_bit(chstat_reg,
527 OMAP2_MCSPI_CHSTAT_EOT) < 0)
528 dev_err(&spi->dev, "EOT timed out\n");
535 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
537 struct omap2_mcspi *mcspi;
538 struct omap2_mcspi_cs *cs = spi->controller_state;
539 unsigned int count, c;
541 void __iomem *base = cs->base;
542 void __iomem *tx_reg;
543 void __iomem *rx_reg;
544 void __iomem *chstat_reg;
547 mcspi = spi_master_get_devdata(spi->master);
550 word_len = cs->word_len;
552 l = mcspi_cached_chconf0(spi);
554 /* We store the pre-calculated register addresses on stack to speed
555 * up the transfer loop. */
556 tx_reg = base + OMAP2_MCSPI_TX0;
557 rx_reg = base + OMAP2_MCSPI_RX0;
558 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
560 if (c < (word_len>>3))
573 if (mcspi_wait_for_reg_bit(chstat_reg,
574 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
575 dev_err(&spi->dev, "TXS timed out\n");
578 dev_vdbg(&spi->dev, "write-%d %02x\n",
580 __raw_writel(*tx++, tx_reg);
583 if (mcspi_wait_for_reg_bit(chstat_reg,
584 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
585 dev_err(&spi->dev, "RXS timed out\n");
589 if (c == 1 && tx == NULL &&
590 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
591 omap2_mcspi_set_enable(spi, 0);
592 *rx++ = __raw_readl(rx_reg);
593 dev_vdbg(&spi->dev, "read-%d %02x\n",
594 word_len, *(rx - 1));
595 if (mcspi_wait_for_reg_bit(chstat_reg,
596 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
602 } else if (c == 0 && tx == NULL) {
603 omap2_mcspi_set_enable(spi, 0);
606 *rx++ = __raw_readl(rx_reg);
607 dev_vdbg(&spi->dev, "read-%d %02x\n",
608 word_len, *(rx - 1));
611 } else if (word_len <= 16) {
620 if (mcspi_wait_for_reg_bit(chstat_reg,
621 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
622 dev_err(&spi->dev, "TXS timed out\n");
625 dev_vdbg(&spi->dev, "write-%d %04x\n",
627 __raw_writel(*tx++, tx_reg);
630 if (mcspi_wait_for_reg_bit(chstat_reg,
631 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
632 dev_err(&spi->dev, "RXS timed out\n");
636 if (c == 2 && tx == NULL &&
637 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
638 omap2_mcspi_set_enable(spi, 0);
639 *rx++ = __raw_readl(rx_reg);
640 dev_vdbg(&spi->dev, "read-%d %04x\n",
641 word_len, *(rx - 1));
642 if (mcspi_wait_for_reg_bit(chstat_reg,
643 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
649 } else if (c == 0 && tx == NULL) {
650 omap2_mcspi_set_enable(spi, 0);
653 *rx++ = __raw_readl(rx_reg);
654 dev_vdbg(&spi->dev, "read-%d %04x\n",
655 word_len, *(rx - 1));
658 } else if (word_len <= 32) {
667 if (mcspi_wait_for_reg_bit(chstat_reg,
668 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
669 dev_err(&spi->dev, "TXS timed out\n");
672 dev_vdbg(&spi->dev, "write-%d %08x\n",
674 __raw_writel(*tx++, tx_reg);
677 if (mcspi_wait_for_reg_bit(chstat_reg,
678 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
679 dev_err(&spi->dev, "RXS timed out\n");
683 if (c == 4 && tx == NULL &&
684 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
685 omap2_mcspi_set_enable(spi, 0);
686 *rx++ = __raw_readl(rx_reg);
687 dev_vdbg(&spi->dev, "read-%d %08x\n",
688 word_len, *(rx - 1));
689 if (mcspi_wait_for_reg_bit(chstat_reg,
690 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
696 } else if (c == 0 && tx == NULL) {
697 omap2_mcspi_set_enable(spi, 0);
700 *rx++ = __raw_readl(rx_reg);
701 dev_vdbg(&spi->dev, "read-%d %08x\n",
702 word_len, *(rx - 1));
707 /* for TX_ONLY mode, be sure all words have shifted out */
708 if (xfer->rx_buf == NULL) {
709 if (mcspi_wait_for_reg_bit(chstat_reg,
710 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
711 dev_err(&spi->dev, "TXS timed out\n");
712 } else if (mcspi_wait_for_reg_bit(chstat_reg,
713 OMAP2_MCSPI_CHSTAT_EOT) < 0)
714 dev_err(&spi->dev, "EOT timed out\n");
716 /* disable chan to purge rx datas received in TX_ONLY transfer,
717 * otherwise these rx datas will affect the direct following
720 omap2_mcspi_set_enable(spi, 0);
723 omap2_mcspi_set_enable(spi, 1);
727 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
731 for (div = 0; div < 15; div++)
732 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
738 /* called only when no transfer is active to this device */
739 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
740 struct spi_transfer *t)
742 struct omap2_mcspi_cs *cs = spi->controller_state;
743 struct omap2_mcspi *mcspi;
744 struct spi_master *spi_cntrl;
746 u8 word_len = spi->bits_per_word;
747 u32 speed_hz = spi->max_speed_hz;
749 mcspi = spi_master_get_devdata(spi->master);
750 spi_cntrl = mcspi->master;
752 if (t != NULL && t->bits_per_word)
753 word_len = t->bits_per_word;
755 cs->word_len = word_len;
757 if (t && t->speed_hz)
758 speed_hz = t->speed_hz;
760 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
761 div = omap2_mcspi_calc_divisor(speed_hz);
763 l = mcspi_cached_chconf0(spi);
765 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
766 * REVISIT: this controller could support SPI_3WIRE mode.
768 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
769 l &= ~OMAP2_MCSPI_CHCONF_IS;
770 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
771 l |= OMAP2_MCSPI_CHCONF_DPE0;
773 l |= OMAP2_MCSPI_CHCONF_IS;
774 l |= OMAP2_MCSPI_CHCONF_DPE1;
775 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
779 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
780 l |= (word_len - 1) << 7;
782 /* set chipselect polarity; manage with FORCE */
783 if (!(spi->mode & SPI_CS_HIGH))
784 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
786 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
788 /* set clock divisor */
789 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
792 /* set SPI mode 0..3 */
793 if (spi->mode & SPI_CPOL)
794 l |= OMAP2_MCSPI_CHCONF_POL;
796 l &= ~OMAP2_MCSPI_CHCONF_POL;
797 if (spi->mode & SPI_CPHA)
798 l |= OMAP2_MCSPI_CHCONF_PHA;
800 l &= ~OMAP2_MCSPI_CHCONF_PHA;
802 mcspi_write_chconf0(spi, l);
804 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
805 OMAP2_MCSPI_MAX_FREQ >> div,
806 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
807 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
813 * Note that we currently allow DMA only if we get a channel
814 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
816 static int omap2_mcspi_request_dma(struct spi_device *spi)
818 struct spi_master *master = spi->master;
819 struct omap2_mcspi *mcspi;
820 struct omap2_mcspi_dma *mcspi_dma;
824 mcspi = spi_master_get_devdata(master);
825 mcspi_dma = mcspi->dma_channels + spi->chip_select;
827 init_completion(&mcspi_dma->dma_rx_completion);
828 init_completion(&mcspi_dma->dma_tx_completion);
831 dma_cap_set(DMA_SLAVE, mask);
832 sig = mcspi_dma->dma_rx_sync_dev;
833 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
834 if (!mcspi_dma->dma_rx)
837 sig = mcspi_dma->dma_tx_sync_dev;
838 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
839 if (!mcspi_dma->dma_tx) {
840 dma_release_channel(mcspi_dma->dma_rx);
841 mcspi_dma->dma_rx = NULL;
848 dev_warn(&spi->dev, "not using DMA for McSPI\n");
852 static int omap2_mcspi_setup(struct spi_device *spi)
855 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
856 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
857 struct omap2_mcspi_dma *mcspi_dma;
858 struct omap2_mcspi_cs *cs = spi->controller_state;
860 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
863 cs = kzalloc(sizeof *cs, GFP_KERNEL);
866 cs->base = mcspi->base + spi->chip_select * 0x14;
867 cs->phys = mcspi->phys + spi->chip_select * 0x14;
869 spi->controller_state = cs;
870 /* Link this to context save list */
871 list_add_tail(&cs->node, &ctx->cs);
874 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
875 ret = omap2_mcspi_request_dma(spi);
876 if (ret < 0 && ret != -EAGAIN)
880 ret = pm_runtime_get_sync(mcspi->dev);
884 ret = omap2_mcspi_setup_transfer(spi, NULL);
885 pm_runtime_mark_last_busy(mcspi->dev);
886 pm_runtime_put_autosuspend(mcspi->dev);
891 static void omap2_mcspi_cleanup(struct spi_device *spi)
893 struct omap2_mcspi *mcspi;
894 struct omap2_mcspi_dma *mcspi_dma;
895 struct omap2_mcspi_cs *cs;
897 mcspi = spi_master_get_devdata(spi->master);
899 if (spi->controller_state) {
900 /* Unlink controller state from context save list */
901 cs = spi->controller_state;
907 if (spi->chip_select < spi->master->num_chipselect) {
908 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
910 if (mcspi_dma->dma_rx) {
911 dma_release_channel(mcspi_dma->dma_rx);
912 mcspi_dma->dma_rx = NULL;
914 if (mcspi_dma->dma_tx) {
915 dma_release_channel(mcspi_dma->dma_tx);
916 mcspi_dma->dma_tx = NULL;
921 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
924 /* We only enable one channel at a time -- the one whose message is
925 * -- although this controller would gladly
926 * arbitrate among multiple channels. This corresponds to "single
927 * channel" master mode. As a side effect, we need to manage the
928 * chipselect with the FORCE bit ... CS != channel enable.
931 struct spi_device *spi;
932 struct spi_transfer *t = NULL;
933 struct spi_master *master;
934 struct omap2_mcspi_dma *mcspi_dma;
936 struct omap2_mcspi_cs *cs;
937 struct omap2_mcspi_device_config *cd;
938 int par_override = 0;
943 master = spi->master;
944 mcspi_dma = mcspi->dma_channels + spi->chip_select;
945 cs = spi->controller_state;
946 cd = spi->controller_data;
948 omap2_mcspi_set_enable(spi, 1);
949 list_for_each_entry(t, &m->transfers, transfer_list) {
950 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
954 if (par_override || t->speed_hz || t->bits_per_word) {
956 status = omap2_mcspi_setup_transfer(spi, t);
959 if (!t->speed_hz && !t->bits_per_word)
962 if (cd && cd->cs_per_word) {
963 chconf = mcspi->ctx.modulctrl;
964 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
965 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
966 mcspi->ctx.modulctrl =
967 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
972 omap2_mcspi_force_cs(spi, 1);
976 chconf = mcspi_cached_chconf0(spi);
977 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
978 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
980 if (t->tx_buf == NULL)
981 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
982 else if (t->rx_buf == NULL)
983 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
985 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
986 /* Turbo mode is for more than one word */
987 if (t->len > ((cs->word_len + 7) >> 3))
988 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
991 mcspi_write_chconf0(spi, chconf);
996 /* RX_ONLY mode needs dummy data in TX reg */
997 if (t->tx_buf == NULL)
998 __raw_writel(0, cs->base
1001 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1002 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1003 count = omap2_mcspi_txrx_dma(spi, t);
1005 count = omap2_mcspi_txrx_pio(spi, t);
1006 m->actual_length += count;
1008 if (count != t->len) {
1015 udelay(t->delay_usecs);
1017 /* ignore the "leave it on after last xfer" hint */
1019 omap2_mcspi_force_cs(spi, 0);
1023 /* Restore defaults if they were overriden */
1026 status = omap2_mcspi_setup_transfer(spi, NULL);
1030 omap2_mcspi_force_cs(spi, 0);
1032 if (cd && cd->cs_per_word) {
1033 chconf = mcspi->ctx.modulctrl;
1034 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1035 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1036 mcspi->ctx.modulctrl =
1037 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1040 omap2_mcspi_set_enable(spi, 0);
1046 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1047 struct spi_message *m)
1049 struct spi_device *spi;
1050 struct omap2_mcspi *mcspi;
1051 struct omap2_mcspi_dma *mcspi_dma;
1052 struct spi_transfer *t;
1055 mcspi = spi_master_get_devdata(master);
1056 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1057 m->actual_length = 0;
1060 /* reject invalid messages and transfers */
1061 if (list_empty(&m->transfers))
1063 list_for_each_entry(t, &m->transfers, transfer_list) {
1064 const void *tx_buf = t->tx_buf;
1065 void *rx_buf = t->rx_buf;
1066 unsigned len = t->len;
1068 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1069 || (len && !(rx_buf || tx_buf))) {
1070 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1078 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1079 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1081 OMAP2_MCSPI_MAX_FREQ >> 15);
1085 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1088 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1089 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1090 len, DMA_TO_DEVICE);
1091 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1092 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1097 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1098 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1100 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1101 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1104 dma_unmap_single(mcspi->dev, t->tx_dma,
1105 len, DMA_TO_DEVICE);
1111 omap2_mcspi_work(mcspi, m);
1112 spi_finalize_current_message(master);
1116 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1118 struct spi_master *master = mcspi->master;
1119 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1122 ret = pm_runtime_get_sync(mcspi->dev);
1126 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1127 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1128 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1130 omap2_mcspi_set_master_mode(master);
1131 pm_runtime_mark_last_busy(mcspi->dev);
1132 pm_runtime_put_autosuspend(mcspi->dev);
1136 static int omap_mcspi_runtime_resume(struct device *dev)
1138 struct omap2_mcspi *mcspi;
1139 struct spi_master *master;
1141 master = dev_get_drvdata(dev);
1142 mcspi = spi_master_get_devdata(master);
1143 omap2_mcspi_restore_ctx(mcspi);
1148 static struct omap2_mcspi_platform_config omap2_pdata = {
1152 static struct omap2_mcspi_platform_config omap4_pdata = {
1153 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1156 static const struct of_device_id omap_mcspi_of_match[] = {
1158 .compatible = "ti,omap2-mcspi",
1159 .data = &omap2_pdata,
1162 .compatible = "ti,omap4-mcspi",
1163 .data = &omap4_pdata,
1167 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1169 static int omap2_mcspi_probe(struct platform_device *pdev)
1171 struct spi_master *master;
1172 const struct omap2_mcspi_platform_config *pdata;
1173 struct omap2_mcspi *mcspi;
1176 u32 regs_offset = 0;
1177 static int bus_num = 1;
1178 struct device_node *node = pdev->dev.of_node;
1179 const struct of_device_id *match;
1180 struct pinctrl *pinctrl;
1182 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1183 if (master == NULL) {
1184 dev_dbg(&pdev->dev, "master allocation failed\n");
1188 /* the spi->mode bits understood by this driver: */
1189 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1190 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1191 master->setup = omap2_mcspi_setup;
1192 master->prepare_transfer_hardware = omap2_prepare_transfer;
1193 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1194 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1195 master->cleanup = omap2_mcspi_cleanup;
1196 master->dev.of_node = node;
1198 dev_set_drvdata(&pdev->dev, master);
1200 mcspi = spi_master_get_devdata(master);
1201 mcspi->master = master;
1203 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1205 u32 num_cs = 1; /* default number of chipselect */
1206 pdata = match->data;
1208 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1209 master->num_chipselect = num_cs;
1210 master->bus_num = bus_num++;
1211 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1212 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1214 pdata = pdev->dev.platform_data;
1215 master->num_chipselect = pdata->num_cs;
1217 master->bus_num = pdev->id;
1218 mcspi->pin_dir = pdata->pin_dir;
1220 regs_offset = pdata->regs_offset;
1222 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1228 r->start += regs_offset;
1229 r->end += regs_offset;
1230 mcspi->phys = r->start;
1232 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1233 if (IS_ERR(mcspi->base)) {
1234 status = PTR_ERR(mcspi->base);
1238 mcspi->dev = &pdev->dev;
1240 INIT_LIST_HEAD(&mcspi->ctx.cs);
1242 mcspi->dma_channels = kcalloc(master->num_chipselect,
1243 sizeof(struct omap2_mcspi_dma),
1246 if (mcspi->dma_channels == NULL)
1249 for (i = 0; i < master->num_chipselect; i++) {
1250 char dma_ch_name[14];
1251 struct resource *dma_res;
1253 sprintf(dma_ch_name, "rx%d", i);
1254 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1257 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1262 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1263 sprintf(dma_ch_name, "tx%d", i);
1264 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1267 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1272 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1278 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1279 if (IS_ERR(pinctrl))
1280 dev_warn(&pdev->dev,
1281 "pins are not configured from the driver\n");
1283 pm_runtime_use_autosuspend(&pdev->dev);
1284 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1285 pm_runtime_enable(&pdev->dev);
1287 status = omap2_mcspi_master_setup(mcspi);
1291 status = spi_register_master(master);
1298 pm_runtime_disable(&pdev->dev);
1300 kfree(mcspi->dma_channels);
1302 spi_master_put(master);
1306 static int omap2_mcspi_remove(struct platform_device *pdev)
1308 struct spi_master *master;
1309 struct omap2_mcspi *mcspi;
1310 struct omap2_mcspi_dma *dma_channels;
1312 master = dev_get_drvdata(&pdev->dev);
1313 mcspi = spi_master_get_devdata(master);
1314 dma_channels = mcspi->dma_channels;
1316 pm_runtime_put_sync(mcspi->dev);
1317 pm_runtime_disable(&pdev->dev);
1319 spi_unregister_master(master);
1320 kfree(dma_channels);
1325 /* work with hotplug and coldplug */
1326 MODULE_ALIAS("platform:omap2_mcspi");
1328 #ifdef CONFIG_SUSPEND
1330 * When SPI wake up from off-mode, CS is in activate state. If it was in
1331 * unactive state when driver was suspend, then force it to unactive state at
1334 static int omap2_mcspi_resume(struct device *dev)
1336 struct spi_master *master = dev_get_drvdata(dev);
1337 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1338 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1339 struct omap2_mcspi_cs *cs;
1341 pm_runtime_get_sync(mcspi->dev);
1342 list_for_each_entry(cs, &ctx->cs, node) {
1343 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1345 * We need to toggle CS state for OMAP take this
1346 * change in account.
1348 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1349 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1350 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1351 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1354 pm_runtime_mark_last_busy(mcspi->dev);
1355 pm_runtime_put_autosuspend(mcspi->dev);
1359 #define omap2_mcspi_resume NULL
1362 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1363 .resume = omap2_mcspi_resume,
1364 .runtime_resume = omap_mcspi_runtime_resume,
1367 static struct platform_driver omap2_mcspi_driver = {
1369 .name = "omap2_mcspi",
1370 .owner = THIS_MODULE,
1371 .pm = &omap2_mcspi_pm_ops,
1372 .of_match_table = omap_mcspi_of_match,
1374 .probe = omap2_mcspi_probe,
1375 .remove = omap2_mcspi_remove,
1378 module_platform_driver(omap2_mcspi_driver);
1379 MODULE_LICENSE("GPL");