Pileus Git - ~andy/linux/blob - drivers/sh/pfc.c

   1 /*
   2  * SuperH Pin Function Controller support.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sh_pfc.h>
  16 #include <linux/module.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/bitops.h>
  20 #include <linux/slab.h>
  21 #include <linux/ioport.h>
  22
  23 static struct sh_pfc *sh_pfc __read_mostly;
  24
  25 static inline bool sh_pfc_initialized(void)
  26 {
  27         return !!sh_pfc;
  28 }
  29
  30 static void pfc_iounmap(struct sh_pfc *pfc)
  31 {
  32         int k;
  33
  34         for (k = 0; k < pfc->num_resources; k++)
  35                 if (pfc->window[k].virt)
  36                         iounmap(pfc->window[k].virt);
  37
  38         kfree(pfc->window);
  39         pfc->window = NULL;
  40 }
  41
  42 static int pfc_ioremap(struct sh_pfc *pfc)
  43 {
  44         struct resource *res;
  45         int k;
  46
  47         if (!pfc->num_resources)
  48                 return 0;
  49
  50         pfc->window = kzalloc(pfc->num_resources * sizeof(*pfc->window),
  51                               GFP_NOWAIT);
  52         if (!pfc->window)
  53                 goto err1;
  54
  55         for (k = 0; k < pfc->num_resources; k++) {
  56                 res = pfc->resource + k;
  57                 WARN_ON(resource_type(res) != IORESOURCE_MEM);
  58                 pfc->window[k].phys = res->start;
  59                 pfc->window[k].size = resource_size(res);
  60                 pfc->window[k].virt = ioremap_nocache(res->start,
  61                                                          resource_size(res));
  62                 if (!pfc->window[k].virt)
  63                         goto err2;
  64         }
  65
  66         return 0;
  67
  68 err2:
  69         pfc_iounmap(pfc);
  70 err1:
  71         return -1;
  72 }
  73
  74 static void __iomem *pfc_phys_to_virt(struct sh_pfc *pfc,
  75                                       unsigned long address)
  76 {
  77         struct pfc_window *window;
  78         int k;
  79
  80         /* scan through physical windows and convert address */
  81         for (k = 0; k < pfc->num_resources; k++) {
  82                 window = pfc->window + k;
  83
  84                 if (address < window->phys)
  85                         continue;
  86
  87                 if (address >= (window->phys + window->size))
  88                         continue;
  89
  90                 return window->virt + (address - window->phys);
  91         }
  92
  93         /* no windows defined, register must be 1:1 mapped virt:phys */
  94         return (void __iomem *)address;
  95 }
  96
  97 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
  98 {
  99         if (enum_id < r->begin)
 100                 return 0;
 101
 102         if (enum_id > r->end)
 103                 return 0;
 104
 105         return 1;
 106 }
 107
 108 static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
 109                                        unsigned long reg_width)
 110 {
 111         switch (reg_width) {
 112         case 8:
 113                 return ioread8(mapped_reg);
 114         case 16:
 115                 return ioread16(mapped_reg);
 116         case 32:
 117                 return ioread32(mapped_reg);
 118         }
 119
 120         BUG();
 121         return 0;
 122 }
 123
 124 static void gpio_write_raw_reg(void __iomem *mapped_reg,
 125                                unsigned long reg_width,
 126                                unsigned long data)
 127 {
 128         switch (reg_width) {
 129         case 8:
 130                 iowrite8(data, mapped_reg);
 131                 return;
 132         case 16:
 133                 iowrite16(data, mapped_reg);
 134                 return;
 135         case 32:
 136                 iowrite32(data, mapped_reg);
 137                 return;
 138         }
 139
 140         BUG();
 141 }
 142
 143 int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
 144 {
 145         unsigned long pos;
 146
 147         pos = dr->reg_width - (in_pos + 1);
 148
 149         pr_debug("read_bit: addr = %lx, pos = %ld, "
 150                  "r_width = %ld\n", dr->reg, pos, dr->reg_width);
 151
 152         return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
 153 }
 154 EXPORT_SYMBOL_GPL(sh_pfc_read_bit);
 155
 156 void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
 157                       unsigned long value)
 158 {
 159         unsigned long pos;
 160
 161         pos = dr->reg_width - (in_pos + 1);
 162
 163         pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
 164                  "r_width = %ld\n",
 165                  dr->reg, !!value, pos, dr->reg_width);
 166
 167         if (value)
 168                 set_bit(pos, &dr->reg_shadow);
 169         else
 170                 clear_bit(pos, &dr->reg_shadow);
 171
 172         gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
 173 }
 174 EXPORT_SYMBOL_GPL(sh_pfc_write_bit);
 175
 176 static void config_reg_helper(struct sh_pfc *pfc,
 177                               struct pinmux_cfg_reg *crp,
 178                               unsigned long in_pos,
 179                               void __iomem **mapped_regp,
 180                               unsigned long *maskp,
 181                               unsigned long *posp)
 182 {
 183         int k;
 184
 185         *mapped_regp = pfc_phys_to_virt(pfc, crp->reg);
 186
 187         if (crp->field_width) {
 188                 *maskp = (1 << crp->field_width) - 1;
 189                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 190         } else {
 191                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 192                 *posp = crp->reg_width;
 193                 for (k = 0; k <= in_pos; k++)
 194                         *posp -= crp->var_field_width[k];
 195         }
 196 }
 197
 198 static int read_config_reg(struct sh_pfc *pfc,
 199                            struct pinmux_cfg_reg *crp,
 200                            unsigned long field)
 201 {
 202         void __iomem *mapped_reg;
 203         unsigned long mask, pos;
 204
 205         config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 206
 207         pr_debug("read_reg: addr = %lx, field = %ld, "
 208                  "r_width = %ld, f_width = %ld\n",
 209                  crp->reg, field, crp->reg_width, crp->field_width);
 210
 211         return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
 212 }
 213
 214 static void write_config_reg(struct sh_pfc *pfc,
 215                              struct pinmux_cfg_reg *crp,
 216                              unsigned long field, unsigned long value)
 217 {
 218         void __iomem *mapped_reg;
 219         unsigned long mask, pos, data;
 220
 221         config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 222
 223         pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
 224                  "r_width = %ld, f_width = %ld\n",
 225                  crp->reg, value, field, crp->reg_width, crp->field_width);
 226
 227         mask = ~(mask << pos);
 228         value = value << pos;
 229
 230         data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
 231         data &= mask;
 232         data |= value;
 233
 234         if (pfc->unlock_reg)
 235                 gpio_write_raw_reg(pfc_phys_to_virt(pfc, pfc->unlock_reg),
 236                                    32, ~data);
 237
 238         gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
 239 }
 240
 241 static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
 242 {
 243         struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
 244         struct pinmux_data_reg *data_reg;
 245         int k, n;
 246
 247         if (!enum_in_range(gpiop->enum_id, &pfc->data))
 248                 return -1;
 249
 250         k = 0;
 251         while (1) {
 252                 data_reg = pfc->data_regs + k;
 253
 254                 if (!data_reg->reg_width)
 255                         break;
 256
 257                 data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg);
 258
 259                 for (n = 0; n < data_reg->reg_width; n++) {
 260                         if (data_reg->enum_ids[n] == gpiop->enum_id) {
 261                                 gpiop->flags &= ~PINMUX_FLAG_DREG;
 262                                 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
 263                                 gpiop->flags &= ~PINMUX_FLAG_DBIT;
 264                                 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
 265                                 return 0;
 266                         }
 267                 }
 268                 k++;
 269         }
 270
 271         BUG();
 272
 273         return -1;
 274 }
 275
 276 static void setup_data_regs(struct sh_pfc *pfc)
 277 {
 278         struct pinmux_data_reg *drp;
 279         int k;
 280
 281         for (k = pfc->first_gpio; k <= pfc->last_gpio; k++)
 282                 setup_data_reg(pfc, k);
 283
 284         k = 0;
 285         while (1) {
 286                 drp = pfc->data_regs + k;
 287
 288                 if (!drp->reg_width)
 289                         break;
 290
 291                 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
 292                                                     drp->reg_width);
 293                 k++;
 294         }
 295 }
 296
 297 int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
 298                         struct pinmux_data_reg **drp, int *bitp)
 299 {
 300         struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
 301         int k, n;
 302
 303         if (!enum_in_range(gpiop->enum_id, &pfc->data))
 304                 return -1;
 305
 306         k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
 307         n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
 308         *drp = pfc->data_regs + k;
 309         *bitp = n;
 310         return 0;
 311 }
 312 EXPORT_SYMBOL_GPL(sh_pfc_get_data_reg);
 313
 314 static int get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
 315                           struct pinmux_cfg_reg **crp,
 316                           int *fieldp, int *valuep,
 317                           unsigned long **cntp)
 318 {
 319         struct pinmux_cfg_reg *config_reg;
 320         unsigned long r_width, f_width, curr_width, ncomb;
 321         int k, m, n, pos, bit_pos;
 322
 323         k = 0;
 324         while (1) {
 325                 config_reg = pfc->cfg_regs + k;
 326
 327                 r_width = config_reg->reg_width;
 328                 f_width = config_reg->field_width;
 329
 330                 if (!r_width)
 331                         break;
 332
 333                 pos = 0;
 334                 m = 0;
 335                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 336                         if (f_width)
 337                                 curr_width = f_width;
 338                         else
 339                                 curr_width = config_reg->var_field_width[m];
 340
 341                         ncomb = 1 << curr_width;
 342                         for (n = 0; n < ncomb; n++) {
 343                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 344                                         *crp = config_reg;
 345                                         *fieldp = m;
 346                                         *valuep = n;
 347                                         *cntp = &config_reg->cnt[m];
 348                                         return 0;
 349                                 }
 350                         }
 351                         pos += ncomb;
 352                         m++;
 353                 }
 354                 k++;
 355         }
 356
 357         return -1;
 358 }
 359
 360 int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
 361                         pinmux_enum_t *enum_idp)
 362 {
 363         pinmux_enum_t enum_id = pfc->gpios[gpio].enum_id;
 364         pinmux_enum_t *data = pfc->gpio_data;
 365         int k;
 366
 367         if (!enum_in_range(enum_id, &pfc->data)) {
 368                 if (!enum_in_range(enum_id, &pfc->mark)) {
 369                         pr_err("non data/mark enum_id for gpio %d\n", gpio);
 370                         return -1;
 371                 }
 372         }
 373
 374         if (pos) {
 375                 *enum_idp = data[pos + 1];
 376                 return pos + 1;
 377         }
 378
 379         for (k = 0; k < pfc->gpio_data_size; k++) {
 380                 if (data[k] == enum_id) {
 381                         *enum_idp = data[k + 1];
 382                         return k + 1;
 383                 }
 384         }
 385
 386         pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
 387         return -1;
 388 }
 389 EXPORT_SYMBOL_GPL(sh_pfc_gpio_to_enum);
 390
 391 int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
 392                        int cfg_mode)
 393 {
 394         struct pinmux_cfg_reg *cr = NULL;
 395         pinmux_enum_t enum_id;
 396         struct pinmux_range *range;
 397         int in_range, pos, field, value;
 398         unsigned long *cntp;
 399
 400         switch (pinmux_type) {
 401
 402         case PINMUX_TYPE_FUNCTION:
 403                 range = NULL;
 404                 break;
 405
 406         case PINMUX_TYPE_OUTPUT:
 407                 range = &pfc->output;
 408                 break;
 409
 410         case PINMUX_TYPE_INPUT:
 411                 range = &pfc->input;
 412                 break;
 413
 414         case PINMUX_TYPE_INPUT_PULLUP:
 415                 range = &pfc->input_pu;
 416                 break;
 417
 418         case PINMUX_TYPE_INPUT_PULLDOWN:
 419                 range = &pfc->input_pd;
 420                 break;
 421
 422         default:
 423                 goto out_err;
 424         }
 425
 426         pos = 0;
 427         enum_id = 0;
 428         field = 0;
 429         value = 0;
 430         while (1) {
 431                 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
 432                 if (pos <= 0)
 433                         goto out_err;
 434
 435                 if (!enum_id)
 436                         break;
 437
 438                 /* first check if this is a function enum */
 439                 in_range = enum_in_range(enum_id, &pfc->function);
 440                 if (!in_range) {
 441                         /* not a function enum */
 442                         if (range) {
 443                                 /*
 444                                  * other range exists, so this pin is
 445                                  * a regular GPIO pin that now is being
 446                                  * bound to a specific direction.
 447                                  *
 448                                  * for this case we only allow function enums
 449                                  * and the enums that match the other range.
 450                                  */
 451                                 in_range = enum_in_range(enum_id, range);
 452
 453                                 /*
 454                                  * special case pass through for fixed
 455                                  * input-only or output-only pins without
 456                                  * function enum register association.
 457                                  */
 458                                 if (in_range && enum_id == range->force)
 459                                         continue;
 460                         } else {
 461                                 /*
 462                                  * no other range exists, so this pin
 463                                  * must then be of the function type.
 464                                  *
 465                                  * allow function type pins to select
 466                                  * any combination of function/in/out
 467                                  * in their MARK lists.
 468                                  */
 469                                 in_range = 1;
 470                         }
 471                 }
 472
 473                 if (!in_range)
 474                         continue;
 475
 476                 if (get_config_reg(pfc, enum_id, &cr,
 477                                    &field, &value, &cntp) != 0)
 478                         goto out_err;
 479
 480                 switch (cfg_mode) {
 481                 case GPIO_CFG_DRYRUN:
 482                         if (!*cntp ||
 483                             (read_config_reg(pfc, cr, field) != value))
 484                                 continue;
 485                         break;
 486
 487                 case GPIO_CFG_REQ:
 488                         write_config_reg(pfc, cr, field, value);
 489                         *cntp = *cntp + 1;
 490                         break;
 491
 492                 case GPIO_CFG_FREE:
 493                         *cntp = *cntp - 1;
 494                         break;
 495                 }
 496         }
 497
 498         return 0;
 499  out_err:
 500         return -1;
 501 }
 502 EXPORT_SYMBOL_GPL(sh_pfc_config_gpio);
 503
 504 int sh_pfc_set_direction(struct sh_pfc *pfc, unsigned gpio,
 505                          int new_pinmux_type)
 506 {
 507         int pinmux_type;
 508         int ret = -EINVAL;
 509
 510         if (!pfc)
 511                 goto err_out;
 512
 513         pinmux_type = pfc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
 514
 515         switch (pinmux_type) {
 516         case PINMUX_TYPE_GPIO:
 517                 break;
 518         case PINMUX_TYPE_OUTPUT:
 519         case PINMUX_TYPE_INPUT:
 520         case PINMUX_TYPE_INPUT_PULLUP:
 521         case PINMUX_TYPE_INPUT_PULLDOWN:
 522                 sh_pfc_config_gpio(pfc, gpio, pinmux_type, GPIO_CFG_FREE);
 523                 break;
 524         default:
 525                 goto err_out;
 526         }
 527
 528         if (sh_pfc_config_gpio(pfc, gpio,
 529                                new_pinmux_type,
 530                                GPIO_CFG_DRYRUN) != 0)
 531                 goto err_out;
 532
 533         if (sh_pfc_config_gpio(pfc, gpio,
 534                                new_pinmux_type,
 535                                GPIO_CFG_REQ) != 0)
 536                 BUG();
 537
 538         pfc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
 539         pfc->gpios[gpio].flags |= new_pinmux_type;
 540
 541         ret = 0;
 542  err_out:
 543         return ret;
 544 }
 545 EXPORT_SYMBOL_GPL(sh_pfc_set_direction);
 546
 547 int register_sh_pfc(struct sh_pfc *pfc)
 548 {
 549         int (*initroutine)(struct sh_pfc *) = NULL;
 550         int ret;
 551
 552         /*
 553          * Ensure that the type encoding fits
 554          */
 555         BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
 556
 557         if (sh_pfc)
 558                 return -EBUSY;
 559
 560         ret = pfc_ioremap(pfc);
 561         if (unlikely(ret < 0))
 562                 return ret;
 563
 564         spin_lock_init(&pfc->lock);
 565
 566         setup_data_regs(pfc);
 567
 568         sh_pfc = pfc;
 569         pr_info("%s support registered\n", pfc->name);
 570
 571         initroutine = symbol_request(sh_pfc_register_gpiochip);
 572         if (initroutine) {
 573                 (*initroutine)(pfc);
 574                 symbol_put_addr(initroutine);
 575         }
 576
 577         return 0;
 578 }