Pileus Git - ~andy/linux/blob - drivers/sh/pfc/core.c

   1 /*
   2  * SuperH Pin Function Controller support.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #define pr_fmt(fmt) "sh_pfc " KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sh_pfc.h>
  16 #include <linux/module.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/bitops.h>
  20 #include <linux/slab.h>
  21 #include <linux/ioport.h>
  22 #include <linux/pinctrl/machine.h>
  23
  24 static struct sh_pfc *sh_pfc __read_mostly;
  25
  26 static inline bool sh_pfc_initialized(void)
  27 {
  28         return !!sh_pfc;
  29 }
  30
  31 static void pfc_iounmap(struct sh_pfc *pfc)
  32 {
  33         int k;
  34
  35         for (k = 0; k < pfc->num_resources; k++)
  36                 if (pfc->window[k].virt)
  37                         iounmap(pfc->window[k].virt);
  38
  39         kfree(pfc->window);
  40         pfc->window = NULL;
  41 }
  42
  43 static int pfc_ioremap(struct sh_pfc *pfc)
  44 {
  45         struct resource *res;
  46         int k;
  47
  48         if (!pfc->num_resources)
  49                 return 0;
  50
  51         pfc->window = kzalloc(pfc->num_resources * sizeof(*pfc->window),
  52                               GFP_NOWAIT);
  53         if (!pfc->window)
  54                 goto err1;
  55
  56         for (k = 0; k < pfc->num_resources; k++) {
  57                 res = pfc->resource + k;
  58                 WARN_ON(resource_type(res) != IORESOURCE_MEM);
  59                 pfc->window[k].phys = res->start;
  60                 pfc->window[k].size = resource_size(res);
  61                 pfc->window[k].virt = ioremap_nocache(res->start,
  62                                                          resource_size(res));
  63                 if (!pfc->window[k].virt)
  64                         goto err2;
  65         }
  66
  67         return 0;
  68
  69 err2:
  70         pfc_iounmap(pfc);
  71 err1:
  72         return -1;
  73 }
  74
  75 static void __iomem *pfc_phys_to_virt(struct sh_pfc *pfc,
  76                                       unsigned long address)
  77 {
  78         struct pfc_window *window;
  79         int k;
  80
  81         /* scan through physical windows and convert address */
  82         for (k = 0; k < pfc->num_resources; k++) {
  83                 window = pfc->window + k;
  84
  85                 if (address < window->phys)
  86                         continue;
  87
  88                 if (address >= (window->phys + window->size))
  89                         continue;
  90
  91                 return window->virt + (address - window->phys);
  92         }
  93
  94         /* no windows defined, register must be 1:1 mapped virt:phys */
  95         return (void __iomem *)address;
  96 }
  97
  98 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
  99 {
 100         if (enum_id < r->begin)
 101                 return 0;
 102
 103         if (enum_id > r->end)
 104                 return 0;
 105
 106         return 1;
 107 }
 108
 109 static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
 110                                        unsigned long reg_width)
 111 {
 112         switch (reg_width) {
 113         case 8:
 114                 return ioread8(mapped_reg);
 115         case 16:
 116                 return ioread16(mapped_reg);
 117         case 32:
 118                 return ioread32(mapped_reg);
 119         }
 120
 121         BUG();
 122         return 0;
 123 }
 124
 125 static void gpio_write_raw_reg(void __iomem *mapped_reg,
 126                                unsigned long reg_width,
 127                                unsigned long data)
 128 {
 129         switch (reg_width) {
 130         case 8:
 131                 iowrite8(data, mapped_reg);
 132                 return;
 133         case 16:
 134                 iowrite16(data, mapped_reg);
 135                 return;
 136         case 32:
 137                 iowrite32(data, mapped_reg);
 138                 return;
 139         }
 140
 141         BUG();
 142 }
 143
 144 int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
 145 {
 146         unsigned long pos;
 147
 148         pos = dr->reg_width - (in_pos + 1);
 149
 150         pr_debug("read_bit: addr = %lx, pos = %ld, "
 151                  "r_width = %ld\n", dr->reg, pos, dr->reg_width);
 152
 153         return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
 154 }
 155 EXPORT_SYMBOL_GPL(sh_pfc_read_bit);
 156
 157 void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
 158                       unsigned long value)
 159 {
 160         unsigned long pos;
 161
 162         pos = dr->reg_width - (in_pos + 1);
 163
 164         pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
 165                  "r_width = %ld\n",
 166                  dr->reg, !!value, pos, dr->reg_width);
 167
 168         if (value)
 169                 set_bit(pos, &dr->reg_shadow);
 170         else
 171                 clear_bit(pos, &dr->reg_shadow);
 172
 173         gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
 174 }
 175 EXPORT_SYMBOL_GPL(sh_pfc_write_bit);
 176
 177 static void config_reg_helper(struct sh_pfc *pfc,
 178                               struct pinmux_cfg_reg *crp,
 179                               unsigned long in_pos,
 180                               void __iomem **mapped_regp,
 181                               unsigned long *maskp,
 182                               unsigned long *posp)
 183 {
 184         int k;
 185
 186         *mapped_regp = pfc_phys_to_virt(pfc, crp->reg);
 187
 188         if (crp->field_width) {
 189                 *maskp = (1 << crp->field_width) - 1;
 190                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 191         } else {
 192                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 193                 *posp = crp->reg_width;
 194                 for (k = 0; k <= in_pos; k++)
 195                         *posp -= crp->var_field_width[k];
 196         }
 197 }
 198
 199 static int read_config_reg(struct sh_pfc *pfc,
 200                            struct pinmux_cfg_reg *crp,
 201                            unsigned long field)
 202 {
 203         void __iomem *mapped_reg;
 204         unsigned long mask, pos;
 205
 206         config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 207
 208         pr_debug("read_reg: addr = %lx, field = %ld, "
 209                  "r_width = %ld, f_width = %ld\n",
 210                  crp->reg, field, crp->reg_width, crp->field_width);
 211
 212         return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
 213 }
 214
 215 static void write_config_reg(struct sh_pfc *pfc,
 216                              struct pinmux_cfg_reg *crp,
 217                              unsigned long field, unsigned long value)
 218 {
 219         void __iomem *mapped_reg;
 220         unsigned long mask, pos, data;
 221
 222         config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 223
 224         pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
 225                  "r_width = %ld, f_width = %ld\n",
 226                  crp->reg, value, field, crp->reg_width, crp->field_width);
 227
 228         mask = ~(mask << pos);
 229         value = value << pos;
 230
 231         data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
 232         data &= mask;
 233         data |= value;
 234
 235         if (pfc->unlock_reg)
 236                 gpio_write_raw_reg(pfc_phys_to_virt(pfc, pfc->unlock_reg),
 237                                    32, ~data);
 238
 239         gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
 240 }
 241
 242 static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
 243 {
 244         struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
 245         struct pinmux_data_reg *data_reg;
 246         int k, n;
 247
 248         if (!enum_in_range(gpiop->enum_id, &pfc->data))
 249                 return -1;
 250
 251         k = 0;
 252         while (1) {
 253                 data_reg = pfc->data_regs + k;
 254
 255                 if (!data_reg->reg_width)
 256                         break;
 257
 258                 data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg);
 259
 260                 for (n = 0; n < data_reg->reg_width; n++) {
 261                         if (data_reg->enum_ids[n] == gpiop->enum_id) {
 262                                 gpiop->flags &= ~PINMUX_FLAG_DREG;
 263                                 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
 264                                 gpiop->flags &= ~PINMUX_FLAG_DBIT;
 265                                 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
 266                                 return 0;
 267                         }
 268                 }
 269                 k++;
 270         }
 271
 272         BUG();
 273
 274         return -1;
 275 }
 276
 277 static void setup_data_regs(struct sh_pfc *pfc)
 278 {
 279         struct pinmux_data_reg *drp;
 280         int k;
 281
 282         for (k = pfc->first_gpio; k <= pfc->last_gpio; k++)
 283                 setup_data_reg(pfc, k);
 284
 285         k = 0;
 286         while (1) {
 287                 drp = pfc->data_regs + k;
 288
 289                 if (!drp->reg_width)
 290                         break;
 291
 292                 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
 293                                                     drp->reg_width);
 294                 k++;
 295         }
 296 }
 297
 298 int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
 299                         struct pinmux_data_reg **drp, int *bitp)
 300 {
 301         struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
 302         int k, n;
 303
 304         if (!enum_in_range(gpiop->enum_id, &pfc->data))
 305                 return -1;
 306
 307         k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
 308         n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
 309         *drp = pfc->data_regs + k;
 310         *bitp = n;
 311         return 0;
 312 }
 313 EXPORT_SYMBOL_GPL(sh_pfc_get_data_reg);
 314
 315 static int get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
 316                           struct pinmux_cfg_reg **crp,
 317                           int *fieldp, int *valuep,
 318                           unsigned long **cntp)
 319 {
 320         struct pinmux_cfg_reg *config_reg;
 321         unsigned long r_width, f_width, curr_width, ncomb;
 322         int k, m, n, pos, bit_pos;
 323
 324         k = 0;
 325         while (1) {
 326                 config_reg = pfc->cfg_regs + k;
 327
 328                 r_width = config_reg->reg_width;
 329                 f_width = config_reg->field_width;
 330
 331                 if (!r_width)
 332                         break;
 333
 334                 pos = 0;
 335                 m = 0;
 336                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 337                         if (f_width)
 338                                 curr_width = f_width;
 339                         else
 340                                 curr_width = config_reg->var_field_width[m];
 341
 342                         ncomb = 1 << curr_width;
 343                         for (n = 0; n < ncomb; n++) {
 344                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 345                                         *crp = config_reg;
 346                                         *fieldp = m;
 347                                         *valuep = n;
 348                                         *cntp = &config_reg->cnt[m];
 349                                         return 0;
 350                                 }
 351                         }
 352                         pos += ncomb;
 353                         m++;
 354                 }
 355                 k++;
 356         }
 357
 358         return -1;
 359 }
 360
 361 int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
 362                         pinmux_enum_t *enum_idp)
 363 {
 364         pinmux_enum_t enum_id = pfc->gpios[gpio].enum_id;
 365         pinmux_enum_t *data = pfc->gpio_data;
 366         int k;
 367
 368         if (!enum_in_range(enum_id, &pfc->data)) {
 369                 if (!enum_in_range(enum_id, &pfc->mark)) {
 370                         pr_err("non data/mark enum_id for gpio %d\n", gpio);
 371                         return -1;
 372                 }
 373         }
 374
 375         if (pos) {
 376                 *enum_idp = data[pos + 1];
 377                 return pos + 1;
 378         }
 379
 380         for (k = 0; k < pfc->gpio_data_size; k++) {
 381                 if (data[k] == enum_id) {
 382                         *enum_idp = data[k + 1];
 383                         return k + 1;
 384                 }
 385         }
 386
 387         pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
 388         return -1;
 389 }
 390 EXPORT_SYMBOL_GPL(sh_pfc_gpio_to_enum);
 391
 392 int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
 393                        int cfg_mode)
 394 {
 395         struct pinmux_cfg_reg *cr = NULL;
 396         pinmux_enum_t enum_id;
 397         struct pinmux_range *range;
 398         int in_range, pos, field, value;
 399         unsigned long *cntp;
 400
 401         switch (pinmux_type) {
 402
 403         case PINMUX_TYPE_FUNCTION:
 404                 range = NULL;
 405                 break;
 406
 407         case PINMUX_TYPE_OUTPUT:
 408                 range = &pfc->output;
 409                 break;
 410
 411         case PINMUX_TYPE_INPUT:
 412                 range = &pfc->input;
 413                 break;
 414
 415         case PINMUX_TYPE_INPUT_PULLUP:
 416                 range = &pfc->input_pu;
 417                 break;
 418
 419         case PINMUX_TYPE_INPUT_PULLDOWN:
 420                 range = &pfc->input_pd;
 421                 break;
 422
 423         default:
 424                 goto out_err;
 425         }
 426
 427         pos = 0;
 428         enum_id = 0;
 429         field = 0;
 430         value = 0;
 431         while (1) {
 432                 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
 433                 if (pos <= 0)
 434                         goto out_err;
 435
 436                 if (!enum_id)
 437                         break;
 438
 439                 /* first check if this is a function enum */
 440                 in_range = enum_in_range(enum_id, &pfc->function);
 441                 if (!in_range) {
 442                         /* not a function enum */
 443                         if (range) {
 444                                 /*
 445                                  * other range exists, so this pin is
 446                                  * a regular GPIO pin that now is being
 447                                  * bound to a specific direction.
 448                                  *
 449                                  * for this case we only allow function enums
 450                                  * and the enums that match the other range.
 451                                  */
 452                                 in_range = enum_in_range(enum_id, range);
 453
 454                                 /*
 455                                  * special case pass through for fixed
 456                                  * input-only or output-only pins without
 457                                  * function enum register association.
 458                                  */
 459                                 if (in_range && enum_id == range->force)
 460                                         continue;
 461                         } else {
 462                                 /*
 463                                  * no other range exists, so this pin
 464                                  * must then be of the function type.
 465                                  *
 466                                  * allow function type pins to select
 467                                  * any combination of function/in/out
 468                                  * in their MARK lists.
 469                                  */
 470                                 in_range = 1;
 471                         }
 472                 }
 473
 474                 if (!in_range)
 475                         continue;
 476
 477                 if (get_config_reg(pfc, enum_id, &cr,
 478                                    &field, &value, &cntp) != 0)
 479                         goto out_err;
 480
 481                 switch (cfg_mode) {
 482                 case GPIO_CFG_DRYRUN:
 483                         if (!*cntp ||
 484                             (read_config_reg(pfc, cr, field) != value))
 485                                 continue;
 486                         break;
 487
 488                 case GPIO_CFG_REQ:
 489                         write_config_reg(pfc, cr, field, value);
 490                         *cntp = *cntp + 1;
 491                         break;
 492
 493                 case GPIO_CFG_FREE:
 494                         *cntp = *cntp - 1;
 495                         break;
 496                 }
 497         }
 498
 499         return 0;
 500  out_err:
 501         return -1;
 502 }
 503 EXPORT_SYMBOL_GPL(sh_pfc_config_gpio);
 504
 505 int register_sh_pfc(struct sh_pfc *pfc)
 506 {
 507         int (*initroutine)(struct sh_pfc *) = NULL;
 508         int ret;
 509
 510         /*
 511          * Ensure that the type encoding fits
 512          */
 513         BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
 514
 515         if (sh_pfc)
 516                 return -EBUSY;
 517
 518         ret = pfc_ioremap(pfc);
 519         if (unlikely(ret < 0))
 520                 return ret;
 521
 522         spin_lock_init(&pfc->lock);
 523
 524         pinctrl_provide_dummies();
 525         setup_data_regs(pfc);
 526
 527         sh_pfc = pfc;
 528
 529         /*
 530          * Initialize pinctrl bindings first
 531          */
 532         initroutine = symbol_request(sh_pfc_register_pinctrl);
 533         if (initroutine) {
 534                 ret = (*initroutine)(pfc);
 535                 symbol_put_addr(initroutine);
 536
 537                 if (unlikely(ret != 0))
 538                         goto err;
 539         } else {
 540                 pr_err("failed to initialize pinctrl bindings\n");
 541                 goto err;
 542         }
 543
 544         /*
 545          * Then the GPIO chip
 546          */
 547         initroutine = symbol_request(sh_pfc_register_gpiochip);
 548         if (initroutine) {
 549                 ret = (*initroutine)(pfc);
 550                 symbol_put_addr(initroutine);
 551
 552                 /*
 553                  * If the GPIO chip fails to come up we still leave the
 554                  * PFC state as it is, given that there are already
 555                  * extant users of it that have succeeded by this point.
 556                  */
 557                 if (unlikely(ret != 0)) {
 558                         pr_notice("failed to init GPIO chip, ignoring...\n");
 559                         ret = 0;
 560                 }
 561         }
 562
 563         pr_info("%s support registered\n", pfc->name);
 564
 565         return 0;
 566
 567 err:
 568         pfc_iounmap(pfc);
 569         sh_pfc = NULL;
 570
 571         return ret;
 572 }