2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/dmapool.h>
21 #include <linux/mempool.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/aer.h>
28 #include <linux/bsg-lib.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/scsi_device.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <scsi/scsi_transport.h>
36 #include <scsi/scsi_transport_iscsi.h>
37 #include <scsi/scsi_bsg_iscsi.h>
38 #include <scsi/scsi_netlink.h>
39 #include <scsi/libiscsi.h>
44 #include "ql4_nvram.h"
46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
47 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
51 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
55 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
59 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
62 #define ISP4XXX_PCI_FN_1 0x1
63 #define ISP4XXX_PCI_FN_2 0x3
69 * Data bit definitions
87 #define BIT_16 0x10000
88 #define BIT_17 0x20000
89 #define BIT_18 0x40000
90 #define BIT_19 0x80000
91 #define BIT_20 0x100000
92 #define BIT_21 0x200000
93 #define BIT_22 0x400000
94 #define BIT_23 0x800000
95 #define BIT_24 0x1000000
96 #define BIT_25 0x2000000
97 #define BIT_26 0x4000000
98 #define BIT_27 0x8000000
99 #define BIT_28 0x10000000
100 #define BIT_29 0x20000000
101 #define BIT_30 0x40000000
102 #define BIT_31 0x80000000
105 * Macros to help code, maintain, etc.
107 #define ql4_printk(level, ha, format, arg...) \
108 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
112 * Host adapter default definitions
113 ***********************************/
116 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
117 #define MAX_LUNS 0xffff
118 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
119 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
120 #define MAX_PDU_ENTRIES 32
121 #define INVALID_ENTRY 0xFFFF
122 #define MAX_CMDS_TO_RISC 1024
123 #define MAX_SRBS MAX_CMDS_TO_RISC
124 #define MBOX_AEN_REG_COUNT 8
125 #define MAX_INIT_RETRIES 5
130 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
131 #define RESPONSE_QUEUE_DEPTH 64
132 #define QUEUE_SIZE 64
133 #define DMA_BUFFER_SIZE 512
138 #define MAC_ADDR_LEN 6 /* in bytes */
139 #define IP_ADDR_LEN 4 /* in bytes */
140 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
141 #define DRIVER_NAME "qla4xxx"
143 #define MAX_LINKED_CMDS_PER_LUN 3
144 #define MAX_REQS_SERVICED_PER_INTR 1
146 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
147 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
148 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
150 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */
151 /* recovery timeout */
153 #define LSDW(x) ((u32)((u64)(x)))
154 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
157 * Retry & Timeout Values
160 #define SOFT_RESET_TOV 30
161 #define RESET_INTR_TOV 3
162 #define SEMAPHORE_TOV 10
163 #define ADAPTER_INIT_TOV 30
164 #define ADAPTER_RESET_TOV 180
165 #define EXTEND_CMD_TOV 60
166 #define WAIT_CMD_TOV 30
167 #define EH_WAIT_CMD_TOV 120
168 #define FIRMWARE_UP_TOV 60
169 #define RESET_FIRMWARE_TOV 30
170 #define LOGOUT_TOV 10
171 #define IOCB_TOV_MARGIN 10
172 #define RELOGIN_TOV 18
173 #define ISNS_DEREG_TOV 5
174 #define HBA_ONLINE_TOV 30
175 #define DISABLE_ACB_TOV 30
176 #define IP_CONFIG_TOV 30
179 #define MAX_RESET_HA_RETRIES 2
180 #define FW_ALIVE_WAIT_TOV 3
182 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
185 * SCSI Request Block structure (srb) that is placed
186 * on cmd->SCp location of every I/O [We have 22 bytes available]
189 struct list_head list; /* (8) */
190 struct scsi_qla_host *ha; /* HA the SP is queued on */
191 struct ddb_entry *ddb;
192 uint16_t flags; /* (1) Status flags. */
194 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
195 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
196 uint8_t state; /* (1) Status flags. */
198 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
199 #define SRB_FREE_STATE 1
200 #define SRB_ACTIVE_STATE 3
201 #define SRB_ACTIVE_TIMEOUT_STATE 4
202 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
204 struct scsi_cmnd *cmd; /* (4) SCSI command block */
205 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
206 struct kref srb_ref; /* reference count for this srb */
207 uint8_t err_id; /* error id */
208 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
209 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
210 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
211 #define SRB_ERR_OTHER 4
215 uint16_t iocb_cnt; /* Number of used iocbs */
218 /* Used for extended sense / status continuation */
219 uint8_t *req_sense_ptr;
220 uint16_t req_sense_len;
225 * Asynchronous Event Queue structure
228 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
233 struct aen entry[MAX_AEN_ENTRIES];
237 * Device Database (DDB) structure
240 struct scsi_qla_host *ha;
241 struct iscsi_cls_session *sess;
242 struct iscsi_cls_conn *conn;
244 uint16_t fw_ddb_index; /* DDB firmware index */
245 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
247 #define FLASH_DDB 0x01
249 struct dev_db_entry fw_ddb_entry;
250 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
251 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
252 struct ddb_entry *ddb_entry, uint32_t state);
254 /* Driver Re-login */
255 unsigned long flags; /* DDB Flags */
256 uint16_t default_relogin_timeout; /* Max time to wait for
257 * relogin to complete */
258 atomic_t retry_relogin_timer; /* Min Time between relogins
260 atomic_t relogin_timer; /* Max Time to wait for
261 * relogin to complete */
262 atomic_t relogin_retry_count; /* Num of times relogin has been
264 uint32_t default_time2wait; /* Default Min time between
265 * relogins (+aens) */
269 struct qla_ddb_index {
270 struct list_head list;
272 struct dev_db_entry fw_ddb;
275 #define DDB_IPADDR_LEN 64
277 struct ql4_tuple_ddb {
280 char ip_addr[DDB_IPADDR_LEN];
281 char iscsi_name[ISCSI_NAME_SIZE];
283 #define DDB_OPT_IPV6 0x0e0e
284 #define DDB_OPT_IPV4 0x0f0f
290 #define DDB_STATE_DEAD 0 /* We can no longer talk to
292 #define DDB_STATE_ONLINE 1 /* Device ready to accept
294 #define DDB_STATE_MISSING 2 /* Device logged off, trying
300 #define DF_RELOGIN 0 /* Relogin to device */
301 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
302 #define DF_FO_MASKED 3
306 struct ql82xx_hw_data {
307 /* Offsets for flash/nvram access (set to ~0 if not used). */
308 uint32_t flash_conf_off;
309 uint32_t flash_data_off;
311 uint32_t fdt_wrt_disable;
312 uint32_t fdt_erase_cmd;
313 uint32_t fdt_block_size;
314 uint32_t fdt_unprotect_sec_cmd;
315 uint32_t fdt_protect_sec_cmd;
317 uint32_t flt_region_flt;
318 uint32_t flt_region_fdt;
319 uint32_t flt_region_boot;
320 uint32_t flt_region_bootload;
321 uint32_t flt_region_fw;
323 uint32_t flt_iscsi_param;
324 uint32_t flt_region_chap;
325 uint32_t flt_chap_size;
328 struct qla4_8xxx_legacy_intr_set {
329 uint32_t int_vec_bit;
330 uint32_t tgt_status_reg;
331 uint32_t tgt_mask_reg;
332 uint32_t pci_int_reg;
337 #define QLA_MSIX_DEFAULT 0x00
338 #define QLA_MSIX_RSP_Q 0x01
340 #define QLA_MSIX_ENTRIES 2
341 #define QLA_MIDX_DEFAULT 0
342 #define QLA_MIDX_RSP_Q 1
344 struct ql4_msix_entry {
346 uint16_t msix_vector;
353 struct isp_operations {
354 int (*iospace_config) (struct scsi_qla_host *ha);
355 void (*pci_config) (struct scsi_qla_host *);
356 void (*disable_intrs) (struct scsi_qla_host *);
357 void (*enable_intrs) (struct scsi_qla_host *);
358 int (*start_firmware) (struct scsi_qla_host *);
359 irqreturn_t (*intr_handler) (int , void *);
360 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
361 int (*reset_chip) (struct scsi_qla_host *);
362 int (*reset_firmware) (struct scsi_qla_host *);
363 void (*queue_iocb) (struct scsi_qla_host *);
364 void (*complete_iocb) (struct scsi_qla_host *);
365 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
366 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
367 int (*get_sys_info) (struct scsi_qla_host *);
370 /*qla4xxx ipaddress configuration details */
371 struct ipaddress_config {
372 uint16_t ipv4_options;
373 uint16_t tcp_options;
374 uint16_t ipv4_vlan_tag;
375 uint8_t ipv4_addr_state;
376 uint8_t ip_address[IP_ADDR_LEN];
377 uint8_t subnet_mask[IP_ADDR_LEN];
378 uint8_t gateway[IP_ADDR_LEN];
379 uint32_t ipv6_options;
380 uint32_t ipv6_addl_options;
381 uint8_t ipv6_link_local_state;
382 uint8_t ipv6_addr0_state;
383 uint8_t ipv6_addr1_state;
384 uint8_t ipv6_default_router_state;
385 uint16_t ipv6_vlan_tag;
386 struct in6_addr ipv6_link_local_addr;
387 struct in6_addr ipv6_addr0;
388 struct in6_addr ipv6_addr1;
389 struct in6_addr ipv6_default_router_addr;
390 uint16_t eth_mtu_size;
395 #define QL4_CHAP_MAX_NAME_LEN 256
396 #define QL4_CHAP_MAX_SECRET_LEN 100
400 struct ql4_chap_format {
401 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
402 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
403 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
404 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
405 u16 intr_chap_name_length;
406 u16 intr_secret_length;
407 u16 target_chap_name_length;
408 u16 target_secret_length;
411 struct ip_address_format {
416 struct ql4_conn_info {
418 struct ip_address_format dest_ipaddr;
419 struct ql4_chap_format chap;
422 struct ql4_boot_session_info {
424 struct ql4_conn_info conn_list[1];
427 struct ql4_boot_tgt_info {
428 struct ql4_boot_session_info boot_pri_sess;
429 struct ql4_boot_session_info boot_sec_sess;
433 * Linux Host Adapter structure
435 struct scsi_qla_host {
436 /* Linux adapter configuration data */
439 #define AF_ONLINE 0 /* 0x00000001 */
440 #define AF_INIT_DONE 1 /* 0x00000002 */
441 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
442 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
443 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
444 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
445 #define AF_LINK_UP 8 /* 0x00000100 */
446 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
447 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
448 #define AF_HA_REMOVAL 12 /* 0x00001000 */
449 #define AF_INTx_ENABLED 15 /* 0x00008000 */
450 #define AF_MSI_ENABLED 16 /* 0x00010000 */
451 #define AF_MSIX_ENABLED 17 /* 0x00020000 */
452 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
453 #define AF_FW_RECOVERY 19 /* 0x00080000 */
454 #define AF_EEH_BUSY 20 /* 0x00100000 */
455 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
456 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
457 unsigned long dpc_flags;
459 #define DPC_RESET_HA 1 /* 0x00000002 */
460 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
461 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
462 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
463 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
464 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
465 #define DPC_AEN 9 /* 0x00000200 */
466 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
467 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
468 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
469 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
470 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
473 struct Scsi_Host *host; /* pointer to host data */
479 #define SRB_MIN_REQ 128
480 mempool_t *srb_mempool;
482 /* pci information */
483 struct pci_dev *pdev;
485 struct isp_reg __iomem *reg; /* Base I/O address */
486 unsigned long pio_address;
487 unsigned long pio_length;
488 #define MIN_IOBASE_LEN 0x100
490 uint16_t req_q_count;
492 unsigned long host_no;
494 /* NVRAM registers */
495 struct eeprom_data *nvram;
496 spinlock_t hardware_lock ____cacheline_aligned;
497 uint32_t eeprom_cmd_data;
499 /* Counters for general statistics */
501 uint64_t adapter_error_count;
502 uint64_t device_error_count;
503 uint64_t total_io_count;
504 uint64_t total_mbytes_xferred;
505 uint64_t link_failure_count;
506 uint64_t invalid_crc_count;
507 uint32_t bytes_xfered;
508 uint32_t spurious_int_count;
509 uint32_t aborted_io_count;
510 uint32_t io_timeout_count;
511 uint32_t mailbox_timeout_count;
512 uint32_t seconds_since_last_intr;
513 uint32_t seconds_since_last_heartbeat;
516 /* Info Needed for Management App */
517 /* --- From GetFwVersion --- */
518 uint32_t firmware_version[2];
519 uint32_t patch_number;
520 uint32_t build_number;
523 /* --- From Init_FW --- */
524 /* init_cb_t *init_cb; */
525 uint16_t firmware_options;
527 uint8_t name_string[256];
528 uint8_t heartbeat_interval;
530 /* --- From FlashSysInfo --- */
531 uint8_t my_mac[MAC_ADDR_LEN];
532 uint8_t serial_number[16];
534 /* --- From GetFwState --- */
535 uint32_t firmware_state;
536 uint32_t addl_fw_state;
538 /* Linux kernel thread */
539 struct workqueue_struct *dpc_thread;
540 struct work_struct dpc_work;
542 /* Linux timer thread */
543 struct timer_list timer;
544 uint32_t timer_active;
546 /* Recovery Timers */
547 atomic_t check_relogin_timeouts;
548 uint32_t retry_reset_ha_cnt;
549 uint32_t isp_reset_timer; /* reset test timer */
550 uint32_t nic_reset_timer; /* simulated nic reset test timer */
552 struct list_head free_srb_q;
553 uint16_t free_srb_q_count;
554 uint16_t num_srbs_allocated;
556 /* DMA Memory Block */
558 dma_addr_t queues_dma;
559 unsigned long queues_len;
561 #define MEM_ALIGN_VALUE \
562 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
563 sizeof(struct queue_entry))
564 /* request and response queue variables */
565 dma_addr_t request_dma;
566 struct queue_entry *request_ring;
567 struct queue_entry *request_ptr;
568 dma_addr_t response_dma;
569 struct queue_entry *response_ring;
570 struct queue_entry *response_ptr;
571 dma_addr_t shadow_regs_dma;
572 struct shadow_regs *shadow_regs;
573 uint16_t request_in; /* Current indexes. */
574 uint16_t request_out;
575 uint16_t response_in;
576 uint16_t response_out;
578 /* aen queue variables */
579 uint16_t aen_q_count; /* Number of available aen_q entries */
580 uint16_t aen_in; /* Current indexes */
582 struct aen aen_q[MAX_AEN_ENTRIES];
584 struct ql4_aen_log aen_log;/* tracks all aens */
586 /* This mutex protects several threads to do mailbox commands
589 struct mutex mbox_sem;
591 /* temporary mailbox status registers */
592 volatile uint8_t mbox_status_count;
593 volatile uint32_t mbox_status[MBOX_REG_COUNT];
595 /* FW ddb index map */
596 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
598 /* Saved srb for status continuation entry processing */
599 struct srb *status_srb;
603 /* qla82xx specific fields */
604 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */
605 unsigned long nx_pcibase; /* Base I/O address */
606 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
607 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
608 unsigned long first_page_group_start;
609 unsigned long first_page_group_end;
612 uint32_t curr_window;
613 uint32_t ddr_mn_window;
614 unsigned long mn_win_crb;
615 unsigned long ms_win_crb;
621 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
625 uint32_t fw_heartbeat_counter;
627 struct isp_operations *isp_ops;
628 struct ql82xx_hw_data hw;
630 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
632 uint32_t nx_dev_init_timeout;
633 uint32_t nx_reset_timeout;
635 struct completion mbx_intr_comp;
637 struct ipaddress_config ip_config;
638 struct iscsi_iface *iface_ipv4;
639 struct iscsi_iface *iface_ipv6_0;
640 struct iscsi_iface *iface_ipv6_1;
642 /* --- From About Firmware --- */
643 uint16_t iscsi_major;
644 uint16_t iscsi_minor;
645 uint16_t bootload_major;
646 uint16_t bootload_minor;
647 uint16_t bootload_patch;
648 uint16_t bootload_build;
649 uint16_t def_timeout; /* Default login timeout */
651 uint32_t flash_state;
652 #define QLFLASH_WAITING 0
653 #define QLFLASH_READING 1
654 #define QLFLASH_WRITING 2
655 struct dma_pool *chap_dma_pool;
656 uint8_t *chap_list; /* CHAP table cache */
657 struct mutex chap_sem;
658 #define CHAP_DMA_BLOCK_SIZE 512
659 struct workqueue_struct *task_wq;
660 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
661 #define SYSFS_FLAG_FW_SEL_BOOT 2
662 struct iscsi_boot_kset *boot_kset;
663 struct ql4_boot_tgt_info boot_tgt;
664 uint16_t phy_port_num;
665 uint16_t phy_port_cnt;
666 uint16_t iscsi_pci_func_cnt;
667 uint8_t model_name[16];
668 struct completion disable_acb_comp;
669 struct dma_pool *fw_ddb_dma_pool;
670 #define DDB_DMA_BLOCK_SIZE 512
671 uint16_t pri_ddb_idx;
672 uint16_t sec_ddb_idx;
676 struct ql4_task_data {
677 struct scsi_qla_host *ha;
678 uint8_t iocb_req_cnt;
686 struct iscsi_task *task;
687 struct passthru_status sts;
688 struct work_struct task_work;
691 struct qla_endpoint {
692 struct Scsi_Host *host;
693 struct sockaddr dst_addr;
697 struct qla_endpoint *qla_ep;
700 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
702 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
705 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
707 return ((ha->ip_config.ipv6_options &
708 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
711 static inline int is_qla4010(struct scsi_qla_host *ha)
713 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
716 static inline int is_qla4022(struct scsi_qla_host *ha)
718 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
721 static inline int is_qla4032(struct scsi_qla_host *ha)
723 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
726 static inline int is_qla40XX(struct scsi_qla_host *ha)
728 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
731 static inline int is_qla8022(struct scsi_qla_host *ha)
733 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
736 /* Note: Currently AER/EEH is now supported only for 8022 cards
737 * This function needs to be updated when AER/EEH is enabled
740 static inline int is_aer_supported(struct scsi_qla_host *ha)
742 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
745 static inline int adapter_up(struct scsi_qla_host *ha)
747 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
748 (test_bit(AF_LINK_UP, &ha->flags) != 0);
751 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
753 return (struct scsi_qla_host *)iscsi_host_priv(shost);
756 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
758 return (is_qla4010(ha) ?
759 &ha->reg->u1.isp4010.nvram :
760 &ha->reg->u1.isp4022.semaphore);
763 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
765 return (is_qla4010(ha) ?
766 &ha->reg->u1.isp4010.nvram :
767 &ha->reg->u1.isp4022.nvram);
770 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
772 return (is_qla4010(ha) ?
773 &ha->reg->u2.isp4010.ext_hw_conf :
774 &ha->reg->u2.isp4022.p0.ext_hw_conf);
777 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
779 return (is_qla4010(ha) ?
780 &ha->reg->u2.isp4010.port_status :
781 &ha->reg->u2.isp4022.p0.port_status);
784 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
786 return (is_qla4010(ha) ?
787 &ha->reg->u2.isp4010.port_ctrl :
788 &ha->reg->u2.isp4022.p0.port_ctrl);
791 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
793 return (is_qla4010(ha) ?
794 &ha->reg->u2.isp4010.port_err_status :
795 &ha->reg->u2.isp4022.p0.port_err_status);
798 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
800 return (is_qla4010(ha) ?
801 &ha->reg->u2.isp4010.gp_out :
802 &ha->reg->u2.isp4022.p0.gp_out);
805 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
807 return (is_qla4010(ha) ?
808 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
809 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
812 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
813 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
814 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
816 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
819 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
820 QL4010_FLASH_SEM_BITS);
822 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
823 (QL4022_RESOURCE_BITS_BASE_CODE |
824 (a->mac_index)) << 13);
827 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
830 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
832 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
835 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
838 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
839 QL4010_NVRAM_SEM_BITS);
841 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
842 (QL4022_RESOURCE_BITS_BASE_CODE |
843 (a->mac_index)) << 10);
846 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
849 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
851 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
854 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
857 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
858 QL4010_DRVR_SEM_BITS);
860 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
861 (QL4022_RESOURCE_BITS_BASE_CODE |
862 (a->mac_index)) << 1);
865 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
868 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
870 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
873 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
875 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
876 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
877 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
878 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
879 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
880 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
883 /*---------------------------------------------------------------------------*/
885 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
887 #define INIT_ADAPTER 0
888 #define RESET_ADAPTER 1
890 #define PRESERVE_DDB_LIST 0
891 #define REBUILD_DDB_LIST 1
893 /* Defines for process_aen() */
894 #define PROCESS_ALL_AENS 0
895 #define FLUSH_DDB_CHANGED_AENS 1
897 #endif /*_QLA4XXX_H */