Pileus Git - ~andy/linux/blob - drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2011 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/slab.h>
  11 #include <linux/vmalloc.h>
  12 #include <asm/uaccess.h>
  13
  14 /*
  15  * NVRAM support routines
  16  */
  17
  18 /**
  19  * qla2x00_lock_nvram_access() -
  20  * @ha: HA context
  21  */
  22 static void
  23 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  24 {
  25         uint16_t data;
  26         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  27
  28         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  29                 data = RD_REG_WORD(&reg->nvram);
  30                 while (data & NVR_BUSY) {
  31                         udelay(100);
  32                         data = RD_REG_WORD(&reg->nvram);
  33                 }
  34
  35                 /* Lock resource */
  36                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  37                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  38                 udelay(5);
  39                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  40                 while ((data & BIT_0) == 0) {
  41                         /* Lock failed */
  42                         udelay(100);
  43                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  44                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  45                         udelay(5);
  46                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  47                 }
  48         }
  49 }
  50
  51 /**
  52  * qla2x00_unlock_nvram_access() -
  53  * @ha: HA context
  54  */
  55 static void
  56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  57 {
  58         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  59
  60         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  61                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  62                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  63         }
  64 }
  65
  66 /**
  67  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  68  * @ha: HA context
  69  * @data: Serial interface selector
  70  */
  71 static void
  72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  73 {
  74         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  75
  76         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  77         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  78         NVRAM_DELAY();
  79         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  80             NVR_WRT_ENABLE);
  81         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  82         NVRAM_DELAY();
  83         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  84         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  85         NVRAM_DELAY();
  86 }
  87
  88 /**
  89  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  90  *      NVRAM.
  91  * @ha: HA context
  92  * @nv_cmd: NVRAM command
  93  *
  94  * Bit definitions for NVRAM command:
  95  *
  96  *      Bit 26     = start bit
  97  *      Bit 25, 24 = opcode
  98  *      Bit 23-16  = address
  99  *      Bit 15-0   = write data
 100  *
 101  * Returns the word read from nvram @addr.
 102  */
 103 static uint16_t
 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 105 {
 106         uint8_t         cnt;
 107         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 108         uint16_t        data = 0;
 109         uint16_t        reg_data;
 110
 111         /* Send command to NVRAM. */
 112         nv_cmd <<= 5;
 113         for (cnt = 0; cnt < 11; cnt++) {
 114                 if (nv_cmd & BIT_31)
 115                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 116                 else
 117                         qla2x00_nv_write(ha, 0);
 118                 nv_cmd <<= 1;
 119         }
 120
 121         /* Read data from NVRAM. */
 122         for (cnt = 0; cnt < 16; cnt++) {
 123                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 124                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 125                 NVRAM_DELAY();
 126                 data <<= 1;
 127                 reg_data = RD_REG_WORD(&reg->nvram);
 128                 if (reg_data & NVR_DATA_IN)
 129                         data |= BIT_0;
 130                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 131                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 132                 NVRAM_DELAY();
 133         }
 134
 135         /* Deselect chip. */
 136         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 137         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 138         NVRAM_DELAY();
 139
 140         return data;
 141 }
 142
 143
 144 /**
 145  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 146  *      request routine to get the word from NVRAM.
 147  * @ha: HA context
 148  * @addr: Address in NVRAM to read
 149  *
 150  * Returns the word read from nvram @addr.
 151  */
 152 static uint16_t
 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 154 {
 155         uint16_t        data;
 156         uint32_t        nv_cmd;
 157
 158         nv_cmd = addr << 16;
 159         nv_cmd |= NV_READ_OP;
 160         data = qla2x00_nvram_request(ha, nv_cmd);
 161
 162         return (data);
 163 }
 164
 165 /**
 166  * qla2x00_nv_deselect() - Deselect NVRAM operations.
 167  * @ha: HA context
 168  */
 169 static void
 170 qla2x00_nv_deselect(struct qla_hw_data *ha)
 171 {
 172         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 173
 174         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 175         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 176         NVRAM_DELAY();
 177 }
 178
 179 /**
 180  * qla2x00_write_nvram_word() - Write NVRAM data.
 181  * @ha: HA context
 182  * @addr: Address in NVRAM to write
 183  * @data: word to program
 184  */
 185 static void
 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 187 {
 188         int count;
 189         uint16_t word;
 190         uint32_t nv_cmd, wait_cnt;
 191         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 192         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 193
 194         qla2x00_nv_write(ha, NVR_DATA_OUT);
 195         qla2x00_nv_write(ha, 0);
 196         qla2x00_nv_write(ha, 0);
 197
 198         for (word = 0; word < 8; word++)
 199                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 200
 201         qla2x00_nv_deselect(ha);
 202
 203         /* Write data */
 204         nv_cmd = (addr << 16) | NV_WRITE_OP;
 205         nv_cmd |= data;
 206         nv_cmd <<= 5;
 207         for (count = 0; count < 27; count++) {
 208                 if (nv_cmd & BIT_31)
 209                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 210                 else
 211                         qla2x00_nv_write(ha, 0);
 212
 213                 nv_cmd <<= 1;
 214         }
 215
 216         qla2x00_nv_deselect(ha);
 217
 218         /* Wait for NVRAM to become ready */
 219         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 220         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 221         wait_cnt = NVR_WAIT_CNT;
 222         do {
 223                 if (!--wait_cnt) {
 224                         ql_dbg(ql_dbg_user, vha, 0x708d,
 225                             "NVRAM didn't go ready...\n");
 226                         break;
 227                 }
 228                 NVRAM_DELAY();
 229                 word = RD_REG_WORD(&reg->nvram);
 230         } while ((word & NVR_DATA_IN) == 0);
 231
 232         qla2x00_nv_deselect(ha);
 233
 234         /* Disable writes */
 235         qla2x00_nv_write(ha, NVR_DATA_OUT);
 236         for (count = 0; count < 10; count++)
 237                 qla2x00_nv_write(ha, 0);
 238
 239         qla2x00_nv_deselect(ha);
 240 }
 241
 242 static int
 243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 244         uint16_t data, uint32_t tmo)
 245 {
 246         int ret, count;
 247         uint16_t word;
 248         uint32_t nv_cmd;
 249         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 250
 251         ret = QLA_SUCCESS;
 252
 253         qla2x00_nv_write(ha, NVR_DATA_OUT);
 254         qla2x00_nv_write(ha, 0);
 255         qla2x00_nv_write(ha, 0);
 256
 257         for (word = 0; word < 8; word++)
 258                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 259
 260         qla2x00_nv_deselect(ha);
 261
 262         /* Write data */
 263         nv_cmd = (addr << 16) | NV_WRITE_OP;
 264         nv_cmd |= data;
 265         nv_cmd <<= 5;
 266         for (count = 0; count < 27; count++) {
 267                 if (nv_cmd & BIT_31)
 268                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 269                 else
 270                         qla2x00_nv_write(ha, 0);
 271
 272                 nv_cmd <<= 1;
 273         }
 274
 275         qla2x00_nv_deselect(ha);
 276
 277         /* Wait for NVRAM to become ready */
 278         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 279         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 280         do {
 281                 NVRAM_DELAY();
 282                 word = RD_REG_WORD(&reg->nvram);
 283                 if (!--tmo) {
 284                         ret = QLA_FUNCTION_FAILED;
 285                         break;
 286                 }
 287         } while ((word & NVR_DATA_IN) == 0);
 288
 289         qla2x00_nv_deselect(ha);
 290
 291         /* Disable writes */
 292         qla2x00_nv_write(ha, NVR_DATA_OUT);
 293         for (count = 0; count < 10; count++)
 294                 qla2x00_nv_write(ha, 0);
 295
 296         qla2x00_nv_deselect(ha);
 297
 298         return ret;
 299 }
 300
 301 /**
 302  * qla2x00_clear_nvram_protection() -
 303  * @ha: HA context
 304  */
 305 static int
 306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 307 {
 308         int ret, stat;
 309         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 310         uint32_t word, wait_cnt;
 311         uint16_t wprot, wprot_old;
 312         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 313
 314         /* Clear NVRAM write protection. */
 315         ret = QLA_FUNCTION_FAILED;
 316
 317         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 319             __constant_cpu_to_le16(0x1234), 100000);
 320         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 321         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 322                 /* Write enable. */
 323                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 324                 qla2x00_nv_write(ha, 0);
 325                 qla2x00_nv_write(ha, 0);
 326                 for (word = 0; word < 8; word++)
 327                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 328
 329                 qla2x00_nv_deselect(ha);
 330
 331                 /* Enable protection register. */
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 334                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 335                 for (word = 0; word < 8; word++)
 336                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 337
 338                 qla2x00_nv_deselect(ha);
 339
 340                 /* Clear protection register (ffff is cleared). */
 341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 344                 for (word = 0; word < 8; word++)
 345                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 346
 347                 qla2x00_nv_deselect(ha);
 348
 349                 /* Wait for NVRAM to become ready. */
 350                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 351                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 352                 wait_cnt = NVR_WAIT_CNT;
 353                 do {
 354                         if (!--wait_cnt) {
 355                                 ql_dbg(ql_dbg_user, vha, 0x708e,
 356                                     "NVRAM didn't go ready...\n");
 357                                 break;
 358                         }
 359                         NVRAM_DELAY();
 360                         word = RD_REG_WORD(&reg->nvram);
 361                 } while ((word & NVR_DATA_IN) == 0);
 362
 363                 if (wait_cnt)
 364                         ret = QLA_SUCCESS;
 365         } else
 366                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 367
 368         return ret;
 369 }
 370
 371 static void
 372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 373 {
 374         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 375         uint32_t word, wait_cnt;
 376         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 377
 378         if (stat != QLA_SUCCESS)
 379                 return;
 380
 381         /* Set NVRAM write protection. */
 382         /* Write enable. */
 383         qla2x00_nv_write(ha, NVR_DATA_OUT);
 384         qla2x00_nv_write(ha, 0);
 385         qla2x00_nv_write(ha, 0);
 386         for (word = 0; word < 8; word++)
 387                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 388
 389         qla2x00_nv_deselect(ha);
 390
 391         /* Enable protection register. */
 392         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 393         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 394         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 395         for (word = 0; word < 8; word++)
 396                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 397
 398         qla2x00_nv_deselect(ha);
 399
 400         /* Enable protection register. */
 401         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 402         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 404         for (word = 0; word < 8; word++)
 405                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 406
 407         qla2x00_nv_deselect(ha);
 408
 409         /* Wait for NVRAM to become ready. */
 410         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 411         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 412         wait_cnt = NVR_WAIT_CNT;
 413         do {
 414                 if (!--wait_cnt) {
 415                         ql_dbg(ql_dbg_user, vha, 0x708f,
 416                             "NVRAM didn't go ready...\n");
 417                         break;
 418                 }
 419                 NVRAM_DELAY();
 420                 word = RD_REG_WORD(&reg->nvram);
 421         } while ((word & NVR_DATA_IN) == 0);
 422 }
 423
 424
 425 /*****************************************************************************/
 426 /* Flash Manipulation Routines                                               */
 427 /*****************************************************************************/
 428
 429 static inline uint32_t
 430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 431 {
 432         return ha->flash_conf_off | faddr;
 433 }
 434
 435 static inline uint32_t
 436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 437 {
 438         return ha->flash_data_off | faddr;
 439 }
 440
 441 static inline uint32_t
 442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 443 {
 444         return ha->nvram_conf_off | naddr;
 445 }
 446
 447 static inline uint32_t
 448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 449 {
 450         return ha->nvram_data_off | naddr;
 451 }
 452
 453 static uint32_t
 454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 455 {
 456         int rval;
 457         uint32_t cnt, data;
 458         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 459
 460         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 461         /* Wait for READ cycle to complete. */
 462         rval = QLA_SUCCESS;
 463         for (cnt = 3000;
 464             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 465             rval == QLA_SUCCESS; cnt--) {
 466                 if (cnt)
 467                         udelay(10);
 468                 else
 469                         rval = QLA_FUNCTION_TIMEOUT;
 470                 cond_resched();
 471         }
 472
 473         /* TODO: What happens if we time out? */
 474         data = 0xDEADDEAD;
 475         if (rval == QLA_SUCCESS)
 476                 data = RD_REG_DWORD(&reg->flash_data);
 477
 478         return data;
 479 }
 480
 481 uint32_t *
 482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 483     uint32_t dwords)
 484 {
 485         uint32_t i;
 486         struct qla_hw_data *ha = vha->hw;
 487
 488         /* Dword reads to flash. */
 489         for (i = 0; i < dwords; i++, faddr++)
 490                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 491                     flash_data_addr(ha, faddr)));
 492
 493         return dwptr;
 494 }
 495
 496 static int
 497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 498 {
 499         int rval;
 500         uint32_t cnt;
 501         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 502
 503         WRT_REG_DWORD(&reg->flash_data, data);
 504         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 505         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 506         /* Wait for Write cycle to complete. */
 507         rval = QLA_SUCCESS;
 508         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 509             rval == QLA_SUCCESS; cnt--) {
 510                 if (cnt)
 511                         udelay(10);
 512                 else
 513                         rval = QLA_FUNCTION_TIMEOUT;
 514                 cond_resched();
 515         }
 516         return rval;
 517 }
 518
 519 static void
 520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 521     uint8_t *flash_id)
 522 {
 523         uint32_t ids;
 524
 525         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 526         *man_id = LSB(ids);
 527         *flash_id = MSB(ids);
 528
 529         /* Check if man_id and flash_id are valid. */
 530         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 531                 /* Read information using 0x9f opcode
 532                  * Device ID, Mfg ID would be read in the format:
 533                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 534                  * Example: ATMEL 0x00 01 45 1F
 535                  * Extract MFG and Dev ID from last two bytes.
 536                  */
 537                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 538                 *man_id = LSB(ids);
 539                 *flash_id = MSB(ids);
 540         }
 541 }
 542
 543 static int
 544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 545 {
 546         const char *loc, *locations[] = { "DEF", "PCI" };
 547         uint32_t pcihdr, pcids;
 548         uint32_t *dcode;
 549         uint8_t *buf, *bcode, last_image;
 550         uint16_t cnt, chksum, *wptr;
 551         struct qla_flt_location *fltl;
 552         struct qla_hw_data *ha = vha->hw;
 553         struct req_que *req = ha->req_q_map[0];
 554
 555         /*
 556          * FLT-location structure resides after the last PCI region.
 557          */
 558
 559         /* Begin with sane defaults. */
 560         loc = locations[0];
 561         *start = 0;
 562         if (IS_QLA24XX_TYPE(ha))
 563                 *start = FA_FLASH_LAYOUT_ADDR_24;
 564         else if (IS_QLA25XX(ha))
 565                 *start = FA_FLASH_LAYOUT_ADDR;
 566         else if (IS_QLA81XX(ha))
 567                 *start = FA_FLASH_LAYOUT_ADDR_81;
 568         else if (IS_QLA82XX(ha)) {
 569                 *start = FA_FLASH_LAYOUT_ADDR_82;
 570                 goto end;
 571         }
 572         /* Begin with first PCI expansion ROM header. */
 573         buf = (uint8_t *)req->ring;
 574         dcode = (uint32_t *)req->ring;
 575         pcihdr = 0;
 576         last_image = 1;
 577         do {
 578                 /* Verify PCI expansion ROM header. */
 579                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 580                 bcode = buf + (pcihdr % 4);
 581                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 582                         goto end;
 583
 584                 /* Locate PCI data structure. */
 585                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 586                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 587                 bcode = buf + (pcihdr % 4);
 588
 589                 /* Validate signature of PCI data structure. */
 590                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 591                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 592                         goto end;
 593
 594                 last_image = bcode[0x15] & BIT_7;
 595
 596                 /* Locate next PCI expansion ROM. */
 597                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 598         } while (!last_image);
 599
 600         /* Now verify FLT-location structure. */
 601         fltl = (struct qla_flt_location *)req->ring;
 602         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 603             sizeof(struct qla_flt_location) >> 2);
 604         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 605             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 606                 goto end;
 607
 608         wptr = (uint16_t *)req->ring;
 609         cnt = sizeof(struct qla_flt_location) >> 1;
 610         for (chksum = 0; cnt; cnt--)
 611                 chksum += le16_to_cpu(*wptr++);
 612         if (chksum) {
 613                 ql_log(ql_log_fatal, vha, 0x0045,
 614                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 615                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
 616                     buf, sizeof(struct qla_flt_location));
 617                 return QLA_FUNCTION_FAILED;
 618         }
 619
 620         /* Good data.  Use specified location. */
 621         loc = locations[1];
 622         *start = (le16_to_cpu(fltl->start_hi) << 16 |
 623             le16_to_cpu(fltl->start_lo)) >> 2;
 624 end:
 625         ql_dbg(ql_dbg_init, vha, 0x0046,
 626             "FLTL[%s] = 0x%x.\n",
 627             loc, *start);
 628         return QLA_SUCCESS;
 629 }
 630
 631 static void
 632 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 633 {
 634         const char *loc, *locations[] = { "DEF", "FLT" };
 635         const uint32_t def_fw[] =
 636                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 637         const uint32_t def_boot[] =
 638                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 639         const uint32_t def_vpd_nvram[] =
 640                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 641         const uint32_t def_vpd0[] =
 642                 { 0, 0, FA_VPD0_ADDR_81 };
 643         const uint32_t def_vpd1[] =
 644                 { 0, 0, FA_VPD1_ADDR_81 };
 645         const uint32_t def_nvram0[] =
 646                 { 0, 0, FA_NVRAM0_ADDR_81 };
 647         const uint32_t def_nvram1[] =
 648                 { 0, 0, FA_NVRAM1_ADDR_81 };
 649         const uint32_t def_fdt[] =
 650                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 651                         FA_FLASH_DESCR_ADDR_81 };
 652         const uint32_t def_npiv_conf0[] =
 653                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 654                         FA_NPIV_CONF0_ADDR_81 };
 655         const uint32_t def_npiv_conf1[] =
 656                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 657                         FA_NPIV_CONF1_ADDR_81 };
 658         const uint32_t fcp_prio_cfg0[] =
 659                 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
 660                         0 };
 661         const uint32_t fcp_prio_cfg1[] =
 662                 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
 663                         0 };
 664         uint32_t def;
 665         uint16_t *wptr;
 666         uint16_t cnt, chksum;
 667         uint32_t start;
 668         struct qla_flt_header *flt;
 669         struct qla_flt_region *region;
 670         struct qla_hw_data *ha = vha->hw;
 671         struct req_que *req = ha->req_q_map[0];
 672
 673         def = 0;
 674         if (IS_QLA25XX(ha))
 675                 def = 1;
 676         else if (IS_QLA81XX(ha))
 677                 def = 2;
 678
 679         /* Assign FCP prio region since older adapters may not have FLT, or
 680            FCP prio region in it's FLT.
 681          */
 682         ha->flt_region_fcp_prio = ha->flags.port0 ?
 683             fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
 684
 685         ha->flt_region_flt = flt_addr;
 686         wptr = (uint16_t *)req->ring;
 687         flt = (struct qla_flt_header *)req->ring;
 688         region = (struct qla_flt_region *)&flt[1];
 689         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 690             flt_addr << 2, OPTROM_BURST_SIZE);
 691         if (*wptr == __constant_cpu_to_le16(0xffff))
 692                 goto no_flash_data;
 693         if (flt->version != __constant_cpu_to_le16(1)) {
 694                 ql_log(ql_log_warn, vha, 0x0047,
 695                     "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
 696                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 697                     le16_to_cpu(flt->checksum));
 698                 goto no_flash_data;
 699         }
 700
 701         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 702         for (chksum = 0; cnt; cnt--)
 703                 chksum += le16_to_cpu(*wptr++);
 704         if (chksum) {
 705                 ql_log(ql_log_fatal, vha, 0x0048,
 706                     "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
 707                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 708                     le16_to_cpu(flt->checksum));
 709                 goto no_flash_data;
 710         }
 711
 712         loc = locations[1];
 713         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 714         for ( ; cnt; cnt--, region++) {
 715                 /* Store addresses as DWORD offsets. */
 716                 start = le32_to_cpu(region->start) >> 2;
 717                 ql_dbg(ql_dbg_init, vha, 0x0049,
 718                     "FLT[%02x]: start=0x%x "
 719                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code),
 720                     start, le32_to_cpu(region->end) >> 2,
 721                     le32_to_cpu(region->size));
 722
 723                 switch (le32_to_cpu(region->code) & 0xff) {
 724                 case FLT_REG_FW:
 725                         ha->flt_region_fw = start;
 726                         break;
 727                 case FLT_REG_BOOT_CODE:
 728                         ha->flt_region_boot = start;
 729                         break;
 730                 case FLT_REG_VPD_0:
 731                         ha->flt_region_vpd_nvram = start;
 732                         if (IS_QLA82XX(ha))
 733                                 break;
 734                         if (ha->flags.port0)
 735                                 ha->flt_region_vpd = start;
 736                         break;
 737                 case FLT_REG_VPD_1:
 738                         if (IS_QLA82XX(ha))
 739                                 break;
 740                         if (!ha->flags.port0)
 741                                 ha->flt_region_vpd = start;
 742                         break;
 743                 case FLT_REG_NVRAM_0:
 744                         if (ha->flags.port0)
 745                                 ha->flt_region_nvram = start;
 746                         break;
 747                 case FLT_REG_NVRAM_1:
 748                         if (!ha->flags.port0)
 749                                 ha->flt_region_nvram = start;
 750                         break;
 751                 case FLT_REG_FDT:
 752                         ha->flt_region_fdt = start;
 753                         break;
 754                 case FLT_REG_NPIV_CONF_0:
 755                         if (ha->flags.port0)
 756                                 ha->flt_region_npiv_conf = start;
 757                         break;
 758                 case FLT_REG_NPIV_CONF_1:
 759                         if (!ha->flags.port0)
 760                                 ha->flt_region_npiv_conf = start;
 761                         break;
 762                 case FLT_REG_GOLD_FW:
 763                         ha->flt_region_gold_fw = start;
 764                         break;
 765                 case FLT_REG_FCP_PRIO_0:
 766                         if (ha->flags.port0)
 767                                 ha->flt_region_fcp_prio = start;
 768                         break;
 769                 case FLT_REG_FCP_PRIO_1:
 770                         if (!ha->flags.port0)
 771                                 ha->flt_region_fcp_prio = start;
 772                         break;
 773                 case FLT_REG_BOOT_CODE_82XX:
 774                         ha->flt_region_boot = start;
 775                         break;
 776                 case FLT_REG_FW_82XX:
 777                         ha->flt_region_fw = start;
 778                         break;
 779                 case FLT_REG_GOLD_FW_82XX:
 780                         ha->flt_region_gold_fw = start;
 781                         break;
 782                 case FLT_REG_BOOTLOAD_82XX:
 783                         ha->flt_region_bootload = start;
 784                         break;
 785                 case FLT_REG_VPD_82XX:
 786                         ha->flt_region_vpd = start;
 787                         break;
 788                 }
 789         }
 790         goto done;
 791
 792 no_flash_data:
 793         /* Use hardcoded defaults. */
 794         loc = locations[0];
 795         ha->flt_region_fw = def_fw[def];
 796         ha->flt_region_boot = def_boot[def];
 797         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 798         ha->flt_region_vpd = ha->flags.port0 ?
 799             def_vpd0[def] : def_vpd1[def];
 800         ha->flt_region_nvram = ha->flags.port0 ?
 801             def_nvram0[def] : def_nvram1[def];
 802         ha->flt_region_fdt = def_fdt[def];
 803         ha->flt_region_npiv_conf = ha->flags.port0 ?
 804             def_npiv_conf0[def] : def_npiv_conf1[def];
 805 done:
 806         ql_dbg(ql_dbg_init, vha, 0x004a,
 807             "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x.\n",
 808             loc, ha->flt_region_boot,
 809             ha->flt_region_fw, ha->flt_region_vpd_nvram,
 810             ha->flt_region_vpd);
 811         ql_dbg(ql_dbg_init, vha, 0x004b,
 812             "nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
 813             ha->flt_region_nvram,
 814             ha->flt_region_fdt, ha->flt_region_flt,
 815             ha->flt_region_npiv_conf, ha->flt_region_fcp_prio);
 816 }
 817
 818 static void
 819 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 820 {
 821 #define FLASH_BLK_SIZE_4K       0x1000
 822 #define FLASH_BLK_SIZE_32K      0x8000
 823 #define FLASH_BLK_SIZE_64K      0x10000
 824         const char *loc, *locations[] = { "MID", "FDT" };
 825         uint16_t cnt, chksum;
 826         uint16_t *wptr;
 827         struct qla_fdt_layout *fdt;
 828         uint8_t man_id, flash_id;
 829         uint16_t mid = 0, fid = 0;
 830         struct qla_hw_data *ha = vha->hw;
 831         struct req_que *req = ha->req_q_map[0];
 832
 833         wptr = (uint16_t *)req->ring;
 834         fdt = (struct qla_fdt_layout *)req->ring;
 835         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 836             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 837         if (*wptr == __constant_cpu_to_le16(0xffff))
 838                 goto no_flash_data;
 839         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 840             fdt->sig[3] != 'D')
 841                 goto no_flash_data;
 842
 843         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 844             cnt++)
 845                 chksum += le16_to_cpu(*wptr++);
 846         if (chksum) {
 847                 ql_dbg(ql_dbg_init, vha, 0x004c,
 848                     "Inconsistent FDT detected:"
 849                     " checksum=0x%x id=%c version0x%x.\n", chksum,
 850                     fdt->sig[0], le16_to_cpu(fdt->version));
 851                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
 852                     (uint8_t *)fdt, sizeof(*fdt));
 853                 goto no_flash_data;
 854         }
 855
 856         loc = locations[1];
 857         mid = le16_to_cpu(fdt->man_id);
 858         fid = le16_to_cpu(fdt->id);
 859         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 860         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 861         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 862         if (fdt->unprotect_sec_cmd) {
 863                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 864                     fdt->unprotect_sec_cmd);
 865                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 866                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 867                     flash_conf_addr(ha, 0x0336);
 868         }
 869         goto done;
 870 no_flash_data:
 871         loc = locations[0];
 872         if (IS_QLA82XX(ha)) {
 873                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 874                 goto done;
 875         }
 876         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 877         mid = man_id;
 878         fid = flash_id;
 879         ha->fdt_wrt_disable = 0x9c;
 880         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 881         switch (man_id) {
 882         case 0xbf: /* STT flash. */
 883                 if (flash_id == 0x8e)
 884                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 885                 else
 886                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 887
 888                 if (flash_id == 0x80)
 889                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 890                 break;
 891         case 0x13: /* ST M25P80. */
 892                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 893                 break;
 894         case 0x1f: /* Atmel 26DF081A. */
 895                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 896                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 897                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 898                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 899                 break;
 900         default:
 901                 /* Default to 64 kb sector size. */
 902                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 903                 break;
 904         }
 905 done:
 906         ql_dbg(ql_dbg_init, vha, 0x004d,
 907             "FDT[%s]: (0x%x/0x%x) erase=0x%x "
 908             "pr=%x wrtd=0x%x blk=0x%x.\n",
 909             loc, mid, fid,
 910             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 911             ha->fdt_wrt_disable, ha->fdt_block_size);
 912
 913 }
 914
 915 static void
 916 qla2xxx_get_idc_param(scsi_qla_host_t *vha)
 917 {
 918 #define QLA82XX_IDC_PARAM_ADDR       0x003e885c
 919         uint32_t *wptr;
 920         struct qla_hw_data *ha = vha->hw;
 921         struct req_que *req = ha->req_q_map[0];
 922
 923         if (!IS_QLA82XX(ha))
 924                 return;
 925
 926         wptr = (uint32_t *)req->ring;
 927         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 928                 QLA82XX_IDC_PARAM_ADDR , 8);
 929
 930         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
 931                 ha->nx_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
 932                 ha->nx_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
 933         } else {
 934                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
 935                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
 936         }
 937         ql_dbg(ql_dbg_init, vha, 0x004e,
 938             "nx_dev_init_timeout=%d "
 939             "nx_reset_timeout=%d.\n", ha->nx_dev_init_timeout,
 940             ha->nx_reset_timeout);
 941         return;
 942 }
 943
 944 int
 945 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
 946 {
 947         int ret;
 948         uint32_t flt_addr;
 949         struct qla_hw_data *ha = vha->hw;
 950
 951         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha))
 952                 return QLA_SUCCESS;
 953
 954         ret = qla2xxx_find_flt_start(vha, &flt_addr);
 955         if (ret != QLA_SUCCESS)
 956                 return ret;
 957
 958         qla2xxx_get_flt_info(vha, flt_addr);
 959         qla2xxx_get_fdt_info(vha);
 960         qla2xxx_get_idc_param(vha);
 961
 962         return QLA_SUCCESS;
 963 }
 964
 965 void
 966 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
 967 {
 968 #define NPIV_CONFIG_SIZE        (16*1024)
 969         void *data;
 970         uint16_t *wptr;
 971         uint16_t cnt, chksum;
 972         int i;
 973         struct qla_npiv_header hdr;
 974         struct qla_npiv_entry *entry;
 975         struct qla_hw_data *ha = vha->hw;
 976
 977         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha))
 978                 return;
 979
 980         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
 981             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
 982         if (hdr.version == __constant_cpu_to_le16(0xffff))
 983                 return;
 984         if (hdr.version != __constant_cpu_to_le16(1)) {
 985                 ql_dbg(ql_dbg_user, vha, 0x7090,
 986                     "Unsupported NPIV-Config "
 987                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 988                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 989                     le16_to_cpu(hdr.checksum));
 990                 return;
 991         }
 992
 993         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
 994         if (!data) {
 995                 ql_log(ql_log_warn, vha, 0x7091,
 996                     "Unable to allocate memory for data.\n");
 997                 return;
 998         }
 999
1000         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1001             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1002
1003         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
1004             sizeof(struct qla_npiv_entry)) >> 1;
1005         for (wptr = data, chksum = 0; cnt; cnt--)
1006                 chksum += le16_to_cpu(*wptr++);
1007         if (chksum) {
1008                 ql_dbg(ql_dbg_user, vha, 0x7092,
1009                     "Inconsistent NPIV-Config "
1010                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1011                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1012                     le16_to_cpu(hdr.checksum));
1013                 goto done;
1014         }
1015
1016         entry = data + sizeof(struct qla_npiv_header);
1017         cnt = le16_to_cpu(hdr.entries);
1018         for (i = 0; cnt; cnt--, entry++, i++) {
1019                 uint16_t flags;
1020                 struct fc_vport_identifiers vid;
1021                 struct fc_vport *vport;
1022
1023                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1024
1025                 flags = le16_to_cpu(entry->flags);
1026                 if (flags == 0xffff)
1027                         continue;
1028                 if ((flags & BIT_0) == 0)
1029                         continue;
1030
1031                 memset(&vid, 0, sizeof(vid));
1032                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1033                 vid.vport_type = FC_PORTTYPE_NPIV;
1034                 vid.disable = false;
1035                 vid.port_name = wwn_to_u64(entry->port_name);
1036                 vid.node_name = wwn_to_u64(entry->node_name);
1037
1038                 ql_dbg(ql_dbg_user, vha, 0x7093,
1039                     "NPIV[%02x]: wwpn=%llx "
1040                     "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1041                     (unsigned long long)vid.port_name,
1042                     (unsigned long long)vid.node_name,
1043                     le16_to_cpu(entry->vf_id),
1044                     entry->q_qos, entry->f_qos);
1045
1046                 if (i < QLA_PRECONFIG_VPORTS) {
1047                         vport = fc_vport_create(vha->host, 0, &vid);
1048                         if (!vport)
1049                                 ql_log(ql_log_warn, vha, 0x7094,
1050                                     "NPIV-Config Failed to create vport [%02x]: "
1051                                     "wwpn=%llx wwnn=%llx.\n", cnt,
1052                                     (unsigned long long)vid.port_name,
1053                                     (unsigned long long)vid.node_name);
1054                 }
1055         }
1056 done:
1057         kfree(data);
1058 }
1059
1060 static int
1061 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1062 {
1063         struct qla_hw_data *ha = vha->hw;
1064         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1065
1066         if (ha->flags.fac_supported)
1067                 return qla81xx_fac_do_write_enable(vha, 1);
1068
1069         /* Enable flash write. */
1070         WRT_REG_DWORD(&reg->ctrl_status,
1071             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1072         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1073
1074         if (!ha->fdt_wrt_disable)
1075                 goto done;
1076
1077         /* Disable flash write-protection, first clear SR protection bit */
1078         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1079         /* Then write zero again to clear remaining SR bits.*/
1080         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1081 done:
1082         return QLA_SUCCESS;
1083 }
1084
1085 static int
1086 qla24xx_protect_flash(scsi_qla_host_t *vha)
1087 {
1088         uint32_t cnt;
1089         struct qla_hw_data *ha = vha->hw;
1090         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1091
1092         if (ha->flags.fac_supported)
1093                 return qla81xx_fac_do_write_enable(vha, 0);
1094
1095         if (!ha->fdt_wrt_disable)
1096                 goto skip_wrt_protect;
1097
1098         /* Enable flash write-protection and wait for completion. */
1099         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1100             ha->fdt_wrt_disable);
1101         for (cnt = 300; cnt &&
1102             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1103             cnt--) {
1104                 udelay(10);
1105         }
1106
1107 skip_wrt_protect:
1108         /* Disable flash write. */
1109         WRT_REG_DWORD(&reg->ctrl_status,
1110             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1111         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1112
1113         return QLA_SUCCESS;
1114 }
1115
1116 static int
1117 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1118 {
1119         struct qla_hw_data *ha = vha->hw;
1120         uint32_t start, finish;
1121
1122         if (ha->flags.fac_supported) {
1123                 start = fdata >> 2;
1124                 finish = start + (ha->fdt_block_size >> 2) - 1;
1125                 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1126                     start), flash_data_addr(ha, finish));
1127         }
1128
1129         return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1130             (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1131             ((fdata >> 16) & 0xff));
1132 }
1133
1134 static int
1135 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1136     uint32_t dwords)
1137 {
1138         int ret;
1139         uint32_t liter;
1140         uint32_t sec_mask, rest_addr;
1141         uint32_t fdata;
1142         dma_addr_t optrom_dma;
1143         void *optrom = NULL;
1144         struct qla_hw_data *ha = vha->hw;
1145
1146         /* Prepare burst-capable write on supported ISPs. */
1147         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1148             dwords > OPTROM_BURST_DWORDS) {
1149                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1150                     &optrom_dma, GFP_KERNEL);
1151                 if (!optrom) {
1152                         ql_log(ql_log_warn, vha, 0x7095,
1153                             "Unable to allocate "
1154                             "memory for optrom burst write (%x KB).\n",
1155                             OPTROM_BURST_SIZE / 1024);
1156                 }
1157         }
1158
1159         rest_addr = (ha->fdt_block_size >> 2) - 1;
1160         sec_mask = ~rest_addr;
1161
1162         ret = qla24xx_unprotect_flash(vha);
1163         if (ret != QLA_SUCCESS) {
1164                 ql_log(ql_log_warn, vha, 0x7096,
1165                     "Unable to unprotect flash for update.\n");
1166                 goto done;
1167         }
1168
1169         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1170                 fdata = (faddr & sec_mask) << 2;
1171
1172                 /* Are we at the beginning of a sector? */
1173                 if ((faddr & rest_addr) == 0) {
1174                         /* Do sector unprotect. */
1175                         if (ha->fdt_unprotect_sec_cmd)
1176                                 qla24xx_write_flash_dword(ha,
1177                                     ha->fdt_unprotect_sec_cmd,
1178                                     (fdata & 0xff00) | ((fdata << 16) &
1179                                     0xff0000) | ((fdata >> 16) & 0xff));
1180                         ret = qla24xx_erase_sector(vha, fdata);
1181                         if (ret != QLA_SUCCESS) {
1182                                 ql_dbg(ql_dbg_user, vha, 0x7007,
1183                                     "Unable to erase erase sector: address=%x.\n",
1184                                     faddr);
1185                                 break;
1186                         }
1187                 }
1188
1189                 /* Go with burst-write. */
1190                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1191                         /* Copy data to DMA'ble buffer. */
1192                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1193
1194                         ret = qla2x00_load_ram(vha, optrom_dma,
1195                             flash_data_addr(ha, faddr),
1196                             OPTROM_BURST_DWORDS);
1197                         if (ret != QLA_SUCCESS) {
1198                                 ql_log(ql_log_warn, vha, 0x7097,
1199                                     "Unable to burst-write optrom segment "
1200                                     "(%x/%x/%llx).\n", ret,
1201                                     flash_data_addr(ha, faddr),
1202                                     (unsigned long long)optrom_dma);
1203                                 ql_log(ql_log_warn, vha, 0x7098,
1204                                     "Reverting to slow-write.\n");
1205
1206                                 dma_free_coherent(&ha->pdev->dev,
1207                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1208                                 optrom = NULL;
1209                         } else {
1210                                 liter += OPTROM_BURST_DWORDS - 1;
1211                                 faddr += OPTROM_BURST_DWORDS - 1;
1212                                 dwptr += OPTROM_BURST_DWORDS - 1;
1213                                 continue;
1214                         }
1215                 }
1216
1217                 ret = qla24xx_write_flash_dword(ha,
1218                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1219                 if (ret != QLA_SUCCESS) {
1220                         ql_dbg(ql_dbg_user, vha, 0x7006,
1221                             "Unable to program flash address=%x data=%x.\n",
1222                             faddr, *dwptr);
1223                         break;
1224                 }
1225
1226                 /* Do sector protect. */
1227                 if (ha->fdt_unprotect_sec_cmd &&
1228                     ((faddr & rest_addr) == rest_addr))
1229                         qla24xx_write_flash_dword(ha,
1230                             ha->fdt_protect_sec_cmd,
1231                             (fdata & 0xff00) | ((fdata << 16) &
1232                             0xff0000) | ((fdata >> 16) & 0xff));
1233         }
1234
1235         ret = qla24xx_protect_flash(vha);
1236         if (ret != QLA_SUCCESS)
1237                 ql_log(ql_log_warn, vha, 0x7099,
1238                     "Unable to protect flash after update.\n");
1239 done:
1240         if (optrom)
1241                 dma_free_coherent(&ha->pdev->dev,
1242                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1243
1244         return ret;
1245 }
1246
1247 uint8_t *
1248 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1249     uint32_t bytes)
1250 {
1251         uint32_t i;
1252         uint16_t *wptr;
1253         struct qla_hw_data *ha = vha->hw;
1254
1255         /* Word reads to NVRAM via registers. */
1256         wptr = (uint16_t *)buf;
1257         qla2x00_lock_nvram_access(ha);
1258         for (i = 0; i < bytes >> 1; i++, naddr++)
1259                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1260                     naddr));
1261         qla2x00_unlock_nvram_access(ha);
1262
1263         return buf;
1264 }
1265
1266 uint8_t *
1267 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1268     uint32_t bytes)
1269 {
1270         uint32_t i;
1271         uint32_t *dwptr;
1272         struct qla_hw_data *ha = vha->hw;
1273
1274         if (IS_QLA82XX(ha))
1275                 return  buf;
1276
1277         /* Dword reads to flash. */
1278         dwptr = (uint32_t *)buf;
1279         for (i = 0; i < bytes >> 2; i++, naddr++)
1280                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1281                     nvram_data_addr(ha, naddr)));
1282
1283         return buf;
1284 }
1285
1286 int
1287 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1288     uint32_t bytes)
1289 {
1290         int ret, stat;
1291         uint32_t i;
1292         uint16_t *wptr;
1293         unsigned long flags;
1294         struct qla_hw_data *ha = vha->hw;
1295
1296         ret = QLA_SUCCESS;
1297
1298         spin_lock_irqsave(&ha->hardware_lock, flags);
1299         qla2x00_lock_nvram_access(ha);
1300
1301         /* Disable NVRAM write-protection. */
1302         stat = qla2x00_clear_nvram_protection(ha);
1303
1304         wptr = (uint16_t *)buf;
1305         for (i = 0; i < bytes >> 1; i++, naddr++) {
1306                 qla2x00_write_nvram_word(ha, naddr,
1307                     cpu_to_le16(*wptr));
1308                 wptr++;
1309         }
1310
1311         /* Enable NVRAM write-protection. */
1312         qla2x00_set_nvram_protection(ha, stat);
1313
1314         qla2x00_unlock_nvram_access(ha);
1315         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1316
1317         return ret;
1318 }
1319
1320 int
1321 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1322     uint32_t bytes)
1323 {
1324         int ret;
1325         uint32_t i;
1326         uint32_t *dwptr;
1327         struct qla_hw_data *ha = vha->hw;
1328         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1329
1330         ret = QLA_SUCCESS;
1331
1332         if (IS_QLA82XX(ha))
1333                 return ret;
1334
1335         /* Enable flash write. */
1336         WRT_REG_DWORD(&reg->ctrl_status,
1337             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1338         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1339
1340         /* Disable NVRAM write-protection. */
1341         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1342         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1343
1344         /* Dword writes to flash. */
1345         dwptr = (uint32_t *)buf;
1346         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1347                 ret = qla24xx_write_flash_dword(ha,
1348                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1349                 if (ret != QLA_SUCCESS) {
1350                         ql_dbg(ql_dbg_user, vha, 0x709a,
1351                             "Unable to program nvram address=%x data=%x.\n",
1352                             naddr, *dwptr);
1353                         break;
1354                 }
1355         }
1356
1357         /* Enable NVRAM write-protection. */
1358         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1359
1360         /* Disable flash write. */
1361         WRT_REG_DWORD(&reg->ctrl_status,
1362             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1363         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1364
1365         return ret;
1366 }
1367
1368 uint8_t *
1369 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1370     uint32_t bytes)
1371 {
1372         uint32_t i;
1373         uint32_t *dwptr;
1374         struct qla_hw_data *ha = vha->hw;
1375
1376         /* Dword reads to flash. */
1377         dwptr = (uint32_t *)buf;
1378         for (i = 0; i < bytes >> 2; i++, naddr++)
1379                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1380                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1381
1382         return buf;
1383 }
1384
1385 int
1386 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1387     uint32_t bytes)
1388 {
1389         struct qla_hw_data *ha = vha->hw;
1390 #define RMW_BUFFER_SIZE (64 * 1024)
1391         uint8_t *dbuf;
1392
1393         dbuf = vmalloc(RMW_BUFFER_SIZE);
1394         if (!dbuf)
1395                 return QLA_MEMORY_ALLOC_FAILED;
1396         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1397             RMW_BUFFER_SIZE);
1398         memcpy(dbuf + (naddr << 2), buf, bytes);
1399         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1400             RMW_BUFFER_SIZE);
1401         vfree(dbuf);
1402
1403         return QLA_SUCCESS;
1404 }
1405
1406 static inline void
1407 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1408 {
1409         if (IS_QLA2322(ha)) {
1410                 /* Flip all colors. */
1411                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1412                         /* Turn off. */
1413                         ha->beacon_color_state = 0;
1414                         *pflags = GPIO_LED_ALL_OFF;
1415                 } else {
1416                         /* Turn on. */
1417                         ha->beacon_color_state = QLA_LED_ALL_ON;
1418                         *pflags = GPIO_LED_RGA_ON;
1419                 }
1420         } else {
1421                 /* Flip green led only. */
1422                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1423                         /* Turn off. */
1424                         ha->beacon_color_state = 0;
1425                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1426                 } else {
1427                         /* Turn on. */
1428                         ha->beacon_color_state = QLA_LED_GRN_ON;
1429                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1430                 }
1431         }
1432 }
1433
1434 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1435
1436 void
1437 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1438 {
1439         uint16_t gpio_enable;
1440         uint16_t gpio_data;
1441         uint16_t led_color = 0;
1442         unsigned long flags;
1443         struct qla_hw_data *ha = vha->hw;
1444         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1445
1446         if (IS_QLA82XX(ha))
1447                 return;
1448
1449         spin_lock_irqsave(&ha->hardware_lock, flags);
1450
1451         /* Save the Original GPIOE. */
1452         if (ha->pio_address) {
1453                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1454                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1455         } else {
1456                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1457                 gpio_data = RD_REG_WORD(&reg->gpiod);
1458         }
1459
1460         /* Set the modified gpio_enable values */
1461         gpio_enable |= GPIO_LED_MASK;
1462
1463         if (ha->pio_address) {
1464                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1465         } else {
1466                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1467                 RD_REG_WORD(&reg->gpioe);
1468         }
1469
1470         qla2x00_flip_colors(ha, &led_color);
1471
1472         /* Clear out any previously set LED color. */
1473         gpio_data &= ~GPIO_LED_MASK;
1474
1475         /* Set the new input LED color to GPIOD. */
1476         gpio_data |= led_color;
1477
1478         /* Set the modified gpio_data values */
1479         if (ha->pio_address) {
1480                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1481         } else {
1482                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1483                 RD_REG_WORD(&reg->gpiod);
1484         }
1485
1486         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1487 }
1488
1489 int
1490 qla2x00_beacon_on(struct scsi_qla_host *vha)
1491 {
1492         uint16_t gpio_enable;
1493         uint16_t gpio_data;
1494         unsigned long flags;
1495         struct qla_hw_data *ha = vha->hw;
1496         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1497
1498         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1499         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1500
1501         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1502                 ql_log(ql_log_warn, vha, 0x709b,
1503                     "Unable to update fw options (beacon on).\n");
1504                 return QLA_FUNCTION_FAILED;
1505         }
1506
1507         /* Turn off LEDs. */
1508         spin_lock_irqsave(&ha->hardware_lock, flags);
1509         if (ha->pio_address) {
1510                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1511                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1512         } else {
1513                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1514                 gpio_data = RD_REG_WORD(&reg->gpiod);
1515         }
1516         gpio_enable |= GPIO_LED_MASK;
1517
1518         /* Set the modified gpio_enable values. */
1519         if (ha->pio_address) {
1520                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1521         } else {
1522                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1523                 RD_REG_WORD(&reg->gpioe);
1524         }
1525
1526         /* Clear out previously set LED colour. */
1527         gpio_data &= ~GPIO_LED_MASK;
1528         if (ha->pio_address) {
1529                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1530         } else {
1531                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1532                 RD_REG_WORD(&reg->gpiod);
1533         }
1534         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1535
1536         /*
1537          * Let the per HBA timer kick off the blinking process based on
1538          * the following flags. No need to do anything else now.
1539          */
1540         ha->beacon_blink_led = 1;
1541         ha->beacon_color_state = 0;
1542
1543         return QLA_SUCCESS;
1544 }
1545
1546 int
1547 qla2x00_beacon_off(struct scsi_qla_host *vha)
1548 {
1549         int rval = QLA_SUCCESS;
1550         struct qla_hw_data *ha = vha->hw;
1551
1552         ha->beacon_blink_led = 0;
1553
1554         /* Set the on flag so when it gets flipped it will be off. */
1555         if (IS_QLA2322(ha))
1556                 ha->beacon_color_state = QLA_LED_ALL_ON;
1557         else
1558                 ha->beacon_color_state = QLA_LED_GRN_ON;
1559
1560         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1561
1562         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1563         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1564
1565         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1566         if (rval != QLA_SUCCESS)
1567                 ql_log(ql_log_warn, vha, 0x709c,
1568                     "Unable to update fw options (beacon off).\n");
1569         return rval;
1570 }
1571
1572
1573 static inline void
1574 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1575 {
1576         /* Flip all colors. */
1577         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1578                 /* Turn off. */
1579                 ha->beacon_color_state = 0;
1580                 *pflags = 0;
1581         } else {
1582                 /* Turn on. */
1583                 ha->beacon_color_state = QLA_LED_ALL_ON;
1584                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1585         }
1586 }
1587
1588 void
1589 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1590 {
1591         uint16_t led_color = 0;
1592         uint32_t gpio_data;
1593         unsigned long flags;
1594         struct qla_hw_data *ha = vha->hw;
1595         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1596
1597         /* Save the Original GPIOD. */
1598         spin_lock_irqsave(&ha->hardware_lock, flags);
1599         gpio_data = RD_REG_DWORD(&reg->gpiod);
1600
1601         /* Enable the gpio_data reg for update. */
1602         gpio_data |= GPDX_LED_UPDATE_MASK;
1603
1604         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1605         gpio_data = RD_REG_DWORD(&reg->gpiod);
1606
1607         /* Set the color bits. */
1608         qla24xx_flip_colors(ha, &led_color);
1609
1610         /* Clear out any previously set LED color. */
1611         gpio_data &= ~GPDX_LED_COLOR_MASK;
1612
1613         /* Set the new input LED color to GPIOD. */
1614         gpio_data |= led_color;
1615
1616         /* Set the modified gpio_data values. */
1617         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1618         gpio_data = RD_REG_DWORD(&reg->gpiod);
1619         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1620 }
1621
1622 int
1623 qla24xx_beacon_on(struct scsi_qla_host *vha)
1624 {
1625         uint32_t gpio_data;
1626         unsigned long flags;
1627         struct qla_hw_data *ha = vha->hw;
1628         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1629
1630         if (IS_QLA82XX(ha))
1631                 return QLA_SUCCESS;
1632
1633         if (ha->beacon_blink_led == 0) {
1634                 /* Enable firmware for update */
1635                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1636
1637                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1638                         return QLA_FUNCTION_FAILED;
1639
1640                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1641                     QLA_SUCCESS) {
1642                         ql_log(ql_log_warn, vha, 0x7009,
1643                             "Unable to update fw options (beacon on).\n");
1644                         return QLA_FUNCTION_FAILED;
1645                 }
1646
1647                 spin_lock_irqsave(&ha->hardware_lock, flags);
1648                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1649
1650                 /* Enable the gpio_data reg for update. */
1651                 gpio_data |= GPDX_LED_UPDATE_MASK;
1652                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1653                 RD_REG_DWORD(&reg->gpiod);
1654
1655                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1656         }
1657
1658         /* So all colors blink together. */
1659         ha->beacon_color_state = 0;
1660
1661         /* Let the per HBA timer kick off the blinking process. */
1662         ha->beacon_blink_led = 1;
1663
1664         return QLA_SUCCESS;
1665 }
1666
1667 int
1668 qla24xx_beacon_off(struct scsi_qla_host *vha)
1669 {
1670         uint32_t gpio_data;
1671         unsigned long flags;
1672         struct qla_hw_data *ha = vha->hw;
1673         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1674
1675         if (IS_QLA82XX(ha))
1676                 return QLA_SUCCESS;
1677
1678         ha->beacon_blink_led = 0;
1679         ha->beacon_color_state = QLA_LED_ALL_ON;
1680
1681         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1682
1683         /* Give control back to firmware. */
1684         spin_lock_irqsave(&ha->hardware_lock, flags);
1685         gpio_data = RD_REG_DWORD(&reg->gpiod);
1686
1687         /* Disable the gpio_data reg for update. */
1688         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1689         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1690         RD_REG_DWORD(&reg->gpiod);
1691         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1692
1693         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1694
1695         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1696                 ql_log(ql_log_warn, vha, 0x704d,
1697                     "Unable to update fw options (beacon on).\n");
1698                 return QLA_FUNCTION_FAILED;
1699         }
1700
1701         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1702                 ql_log(ql_log_warn, vha, 0x704e,
1703                     "Unable to update fw options (beacon on).\n");
1704                 return QLA_FUNCTION_FAILED;
1705         }
1706
1707         return QLA_SUCCESS;
1708 }
1709
1710
1711 /*
1712  * Flash support routines
1713  */
1714
1715 /**
1716  * qla2x00_flash_enable() - Setup flash for reading and writing.
1717  * @ha: HA context
1718  */
1719 static void
1720 qla2x00_flash_enable(struct qla_hw_data *ha)
1721 {
1722         uint16_t data;
1723         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1724
1725         data = RD_REG_WORD(&reg->ctrl_status);
1726         data |= CSR_FLASH_ENABLE;
1727         WRT_REG_WORD(&reg->ctrl_status, data);
1728         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1729 }
1730
1731 /**
1732  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1733  * @ha: HA context
1734  */
1735 static void
1736 qla2x00_flash_disable(struct qla_hw_data *ha)
1737 {
1738         uint16_t data;
1739         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1740
1741         data = RD_REG_WORD(&reg->ctrl_status);
1742         data &= ~(CSR_FLASH_ENABLE);
1743         WRT_REG_WORD(&reg->ctrl_status, data);
1744         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1745 }
1746
1747 /**
1748  * qla2x00_read_flash_byte() - Reads a byte from flash
1749  * @ha: HA context
1750  * @addr: Address in flash to read
1751  *
1752  * A word is read from the chip, but, only the lower byte is valid.
1753  *
1754  * Returns the byte read from flash @addr.
1755  */
1756 static uint8_t
1757 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1758 {
1759         uint16_t data;
1760         uint16_t bank_select;
1761         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1762
1763         bank_select = RD_REG_WORD(&reg->ctrl_status);
1764
1765         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1766                 /* Specify 64K address range: */
1767                 /*  clear out Module Select and Flash Address bits [19:16]. */
1768                 bank_select &= ~0xf8;
1769                 bank_select |= addr >> 12 & 0xf0;
1770                 bank_select |= CSR_FLASH_64K_BANK;
1771                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1772                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1773
1774                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1775                 data = RD_REG_WORD(&reg->flash_data);
1776
1777                 return (uint8_t)data;
1778         }
1779
1780         /* Setup bit 16 of flash address. */
1781         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1782                 bank_select |= CSR_FLASH_64K_BANK;
1783                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1784                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1785         } else if (((addr & BIT_16) == 0) &&
1786             (bank_select & CSR_FLASH_64K_BANK)) {
1787                 bank_select &= ~(CSR_FLASH_64K_BANK);
1788                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1789                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1790         }
1791
1792         /* Always perform IO mapped accesses to the FLASH registers. */
1793         if (ha->pio_address) {
1794                 uint16_t data2;
1795
1796                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1797                 do {
1798                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1799                         barrier();
1800                         cpu_relax();
1801                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1802                 } while (data != data2);
1803         } else {
1804                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1805                 data = qla2x00_debounce_register(&reg->flash_data);
1806         }
1807
1808         return (uint8_t)data;
1809 }
1810
1811 /**
1812  * qla2x00_write_flash_byte() - Write a byte to flash
1813  * @ha: HA context
1814  * @addr: Address in flash to write
1815  * @data: Data to write
1816  */
1817 static void
1818 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1819 {
1820         uint16_t bank_select;
1821         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1822
1823         bank_select = RD_REG_WORD(&reg->ctrl_status);
1824         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1825                 /* Specify 64K address range: */
1826                 /*  clear out Module Select and Flash Address bits [19:16]. */
1827                 bank_select &= ~0xf8;
1828                 bank_select |= addr >> 12 & 0xf0;
1829                 bank_select |= CSR_FLASH_64K_BANK;
1830                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1831                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1832
1833                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1834                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1835                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1836                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1837
1838                 return;
1839         }
1840
1841         /* Setup bit 16 of flash address. */
1842         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1843                 bank_select |= CSR_FLASH_64K_BANK;
1844                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1845                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1846         } else if (((addr & BIT_16) == 0) &&
1847             (bank_select & CSR_FLASH_64K_BANK)) {
1848                 bank_select &= ~(CSR_FLASH_64K_BANK);
1849                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1850                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1851         }
1852
1853         /* Always perform IO mapped accesses to the FLASH registers. */
1854         if (ha->pio_address) {
1855                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1856                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1857         } else {
1858                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1859                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1860                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1861                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1862         }
1863 }
1864
1865 /**
1866  * qla2x00_poll_flash() - Polls flash for completion.
1867  * @ha: HA context
1868  * @addr: Address in flash to poll
1869  * @poll_data: Data to be polled
1870  * @man_id: Flash manufacturer ID
1871  * @flash_id: Flash ID
1872  *
1873  * This function polls the device until bit 7 of what is read matches data
1874  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1875  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1876  * reading bit 5 as a 1.
1877  *
1878  * Returns 0 on success, else non-zero.
1879  */
1880 static int
1881 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1882     uint8_t man_id, uint8_t flash_id)
1883 {
1884         int status;
1885         uint8_t flash_data;
1886         uint32_t cnt;
1887
1888         status = 1;
1889
1890         /* Wait for 30 seconds for command to finish. */
1891         poll_data &= BIT_7;
1892         for (cnt = 3000000; cnt; cnt--) {
1893                 flash_data = qla2x00_read_flash_byte(ha, addr);
1894                 if ((flash_data & BIT_7) == poll_data) {
1895                         status = 0;
1896                         break;
1897                 }
1898
1899                 if (man_id != 0x40 && man_id != 0xda) {
1900                         if ((flash_data & BIT_5) && cnt > 2)
1901                                 cnt = 2;
1902                 }
1903                 udelay(10);
1904                 barrier();
1905                 cond_resched();
1906         }
1907         return status;
1908 }
1909
1910 /**
1911  * qla2x00_program_flash_address() - Programs a flash address
1912  * @ha: HA context
1913  * @addr: Address in flash to program
1914  * @data: Data to be written in flash
1915  * @man_id: Flash manufacturer ID
1916  * @flash_id: Flash ID
1917  *
1918  * Returns 0 on success, else non-zero.
1919  */
1920 static int
1921 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1922     uint8_t data, uint8_t man_id, uint8_t flash_id)
1923 {
1924         /* Write Program Command Sequence. */
1925         if (IS_OEM_001(ha)) {
1926                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1927                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1928                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1929                 qla2x00_write_flash_byte(ha, addr, data);
1930         } else {
1931                 if (man_id == 0xda && flash_id == 0xc1) {
1932                         qla2x00_write_flash_byte(ha, addr, data);
1933                         if (addr & 0x7e)
1934                                 return 0;
1935                 } else {
1936                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1937                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1938                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1939                         qla2x00_write_flash_byte(ha, addr, data);
1940                 }
1941         }
1942
1943         udelay(150);
1944
1945         /* Wait for write to complete. */
1946         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1947 }
1948
1949 /**
1950  * qla2x00_erase_flash() - Erase the flash.
1951  * @ha: HA context
1952  * @man_id: Flash manufacturer ID
1953  * @flash_id: Flash ID
1954  *
1955  * Returns 0 on success, else non-zero.
1956  */
1957 static int
1958 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1959 {
1960         /* Individual Sector Erase Command Sequence */
1961         if (IS_OEM_001(ha)) {
1962                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1963                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1964                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1965                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1966                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1967                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1968         } else {
1969                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1970                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1971                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1972                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1973                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1974                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1975         }
1976
1977         udelay(150);
1978
1979         /* Wait for erase to complete. */
1980         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1981 }
1982
1983 /**
1984  * qla2x00_erase_flash_sector() - Erase a flash sector.
1985  * @ha: HA context
1986  * @addr: Flash sector to erase
1987  * @sec_mask: Sector address mask
1988  * @man_id: Flash manufacturer ID
1989  * @flash_id: Flash ID
1990  *
1991  * Returns 0 on success, else non-zero.
1992  */
1993 static int
1994 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1995     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1996 {
1997         /* Individual Sector Erase Command Sequence */
1998         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1999         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2000         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2001         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2002         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2003         if (man_id == 0x1f && flash_id == 0x13)
2004                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2005         else
2006                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2007
2008         udelay(150);
2009
2010         /* Wait for erase to complete. */
2011         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2012 }
2013
2014 /**
2015  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2016  * @man_id: Flash manufacturer ID
2017  * @flash_id: Flash ID
2018  */
2019 static void
2020 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2021     uint8_t *flash_id)
2022 {
2023         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2024         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2025         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2026         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2027         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2028         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2029         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2030         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2031 }
2032
2033 static void
2034 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2035         uint32_t saddr, uint32_t length)
2036 {
2037         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2038         uint32_t midpoint, ilength;
2039         uint8_t data;
2040
2041         midpoint = length / 2;
2042
2043         WRT_REG_WORD(&reg->nvram, 0);
2044         RD_REG_WORD(&reg->nvram);
2045         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2046                 if (ilength == midpoint) {
2047                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2048                         RD_REG_WORD(&reg->nvram);
2049                 }
2050                 data = qla2x00_read_flash_byte(ha, saddr);
2051                 if (saddr % 100)
2052                         udelay(10);
2053                 *tmp_buf = data;
2054                 cond_resched();
2055         }
2056 }
2057
2058 static inline void
2059 qla2x00_suspend_hba(struct scsi_qla_host *vha)
2060 {
2061         int cnt;
2062         unsigned long flags;
2063         struct qla_hw_data *ha = vha->hw;
2064         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2065
2066         /* Suspend HBA. */
2067         scsi_block_requests(vha->host);
2068         ha->isp_ops->disable_intrs(ha);
2069         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2070
2071         /* Pause RISC. */
2072         spin_lock_irqsave(&ha->hardware_lock, flags);
2073         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2074         RD_REG_WORD(&reg->hccr);
2075         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2076                 for (cnt = 0; cnt < 30000; cnt++) {
2077                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2078                                 break;
2079                         udelay(100);
2080                 }
2081         } else {
2082                 udelay(10);
2083         }
2084         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2085 }
2086
2087 static inline void
2088 qla2x00_resume_hba(struct scsi_qla_host *vha)
2089 {
2090         struct qla_hw_data *ha = vha->hw;
2091
2092         /* Resume HBA. */
2093         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2094         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2095         qla2xxx_wake_dpc(vha);
2096         qla2x00_wait_for_chip_reset(vha);
2097         scsi_unblock_requests(vha->host);
2098 }
2099
2100 uint8_t *
2101 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2102     uint32_t offset, uint32_t length)
2103 {
2104         uint32_t addr, midpoint;
2105         uint8_t *data;
2106         struct qla_hw_data *ha = vha->hw;
2107         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2108
2109         /* Suspend HBA. */
2110         qla2x00_suspend_hba(vha);
2111
2112         /* Go with read. */
2113         midpoint = ha->optrom_size / 2;
2114
2115         qla2x00_flash_enable(ha);
2116         WRT_REG_WORD(&reg->nvram, 0);
2117         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
2118         for (addr = offset, data = buf; addr < length; addr++, data++) {
2119                 if (addr == midpoint) {
2120                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2121                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
2122                 }
2123
2124                 *data = qla2x00_read_flash_byte(ha, addr);
2125         }
2126         qla2x00_flash_disable(ha);
2127
2128         /* Resume HBA. */
2129         qla2x00_resume_hba(vha);
2130
2131         return buf;
2132 }
2133
2134 int
2135 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2136     uint32_t offset, uint32_t length)
2137 {
2138
2139         int rval;
2140         uint8_t man_id, flash_id, sec_number, data;
2141         uint16_t wd;
2142         uint32_t addr, liter, sec_mask, rest_addr;
2143         struct qla_hw_data *ha = vha->hw;
2144         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2145
2146         /* Suspend HBA. */
2147         qla2x00_suspend_hba(vha);
2148
2149         rval = QLA_SUCCESS;
2150         sec_number = 0;
2151
2152         /* Reset ISP chip. */
2153         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2154         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2155
2156         /* Go with write. */
2157         qla2x00_flash_enable(ha);
2158         do {    /* Loop once to provide quick error exit */
2159                 /* Structure of flash memory based on manufacturer */
2160                 if (IS_OEM_001(ha)) {
2161                         /* OEM variant with special flash part. */
2162                         man_id = flash_id = 0;
2163                         rest_addr = 0xffff;
2164                         sec_mask   = 0x10000;
2165                         goto update_flash;
2166                 }
2167                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2168                 switch (man_id) {
2169                 case 0x20: /* ST flash. */
2170                         if (flash_id == 0xd2 || flash_id == 0xe3) {
2171                                 /*
2172                                  * ST m29w008at part - 64kb sector size with
2173                                  * 32kb,8kb,8kb,16kb sectors at memory address
2174                                  * 0xf0000.
2175                                  */
2176                                 rest_addr = 0xffff;
2177                                 sec_mask = 0x10000;
2178                                 break;
2179                         }
2180                         /*
2181                          * ST m29w010b part - 16kb sector size
2182                          * Default to 16kb sectors
2183                          */
2184                         rest_addr = 0x3fff;
2185                         sec_mask = 0x1c000;
2186                         break;
2187                 case 0x40: /* Mostel flash. */
2188                         /* Mostel v29c51001 part - 512 byte sector size. */
2189                         rest_addr = 0x1ff;
2190                         sec_mask = 0x1fe00;
2191                         break;
2192                 case 0xbf: /* SST flash. */
2193                         /* SST39sf10 part - 4kb sector size. */
2194                         rest_addr = 0xfff;
2195                         sec_mask = 0x1f000;
2196                         break;
2197                 case 0xda: /* Winbond flash. */
2198                         /* Winbond W29EE011 part - 256 byte sector size. */
2199                         rest_addr = 0x7f;
2200                         sec_mask = 0x1ff80;
2201                         break;
2202                 case 0xc2: /* Macronix flash. */
2203                         /* 64k sector size. */
2204                         if (flash_id == 0x38 || flash_id == 0x4f) {
2205                                 rest_addr = 0xffff;
2206                                 sec_mask = 0x10000;
2207                                 break;
2208                         }
2209                         /* Fall through... */
2210
2211                 case 0x1f: /* Atmel flash. */
2212                         /* 512k sector size. */
2213                         if (flash_id == 0x13) {
2214                                 rest_addr = 0x7fffffff;
2215                                 sec_mask =   0x80000000;
2216                                 break;
2217                         }
2218                         /* Fall through... */
2219
2220                 case 0x01: /* AMD flash. */
2221                         if (flash_id == 0x38 || flash_id == 0x40 ||
2222                             flash_id == 0x4f) {
2223                                 /* Am29LV081 part - 64kb sector size. */
2224                                 /* Am29LV002BT part - 64kb sector size. */
2225                                 rest_addr = 0xffff;
2226                                 sec_mask = 0x10000;
2227                                 break;
2228                         } else if (flash_id == 0x3e) {
2229                                 /*
2230                                  * Am29LV008b part - 64kb sector size with
2231                                  * 32kb,8kb,8kb,16kb sector at memory address
2232                                  * h0xf0000.
2233                                  */
2234                                 rest_addr = 0xffff;
2235                                 sec_mask = 0x10000;
2236                                 break;
2237                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2238                                 /*
2239                                  * Am29LV010 part or AM29f010 - 16kb sector
2240                                  * size.
2241                                  */
2242                                 rest_addr = 0x3fff;
2243                                 sec_mask = 0x1c000;
2244                                 break;
2245                         } else if (flash_id == 0x6d) {
2246                                 /* Am29LV001 part - 8kb sector size. */
2247                                 rest_addr = 0x1fff;
2248                                 sec_mask = 0x1e000;
2249                                 break;
2250                         }
2251                 default:
2252                         /* Default to 16 kb sector size. */
2253                         rest_addr = 0x3fff;
2254                         sec_mask = 0x1c000;
2255                         break;
2256                 }
2257
2258 update_flash:
2259                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2260                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2261                                 rval = QLA_FUNCTION_FAILED;
2262                                 break;
2263                         }
2264                 }
2265
2266                 for (addr = offset, liter = 0; liter < length; liter++,
2267                     addr++) {
2268                         data = buf[liter];
2269                         /* Are we at the beginning of a sector? */
2270                         if ((addr & rest_addr) == 0) {
2271                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2272                                         if (addr >= 0x10000UL) {
2273                                                 if (((addr >> 12) & 0xf0) &&
2274                                                     ((man_id == 0x01 &&
2275                                                         flash_id == 0x3e) ||
2276                                                      (man_id == 0x20 &&
2277                                                          flash_id == 0xd2))) {
2278                                                         sec_number++;
2279                                                         if (sec_number == 1) {
2280                                                                 rest_addr =
2281                                                                     0x7fff;
2282                                                                 sec_mask =
2283                                                                     0x18000;
2284                                                         } else if (
2285                                                             sec_number == 2 ||
2286                                                             sec_number == 3) {
2287                                                                 rest_addr =
2288                                                                     0x1fff;
2289                                                                 sec_mask =
2290                                                                     0x1e000;
2291                                                         } else if (
2292                                                             sec_number == 4) {
2293                                                                 rest_addr =
2294                                                                     0x3fff;
2295                                                                 sec_mask =
2296                                                                     0x1c000;
2297                                                         }
2298                                                 }
2299                                         }
2300                                 } else if (addr == ha->optrom_size / 2) {
2301                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2302                                         RD_REG_WORD(&reg->nvram);
2303                                 }
2304
2305                                 if (flash_id == 0xda && man_id == 0xc1) {
2306                                         qla2x00_write_flash_byte(ha, 0x5555,
2307                                             0xaa);
2308                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2309                                             0x55);
2310                                         qla2x00_write_flash_byte(ha, 0x5555,
2311                                             0xa0);
2312                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2313                                         /* Then erase it */
2314                                         if (qla2x00_erase_flash_sector(ha,
2315                                             addr, sec_mask, man_id,
2316                                             flash_id)) {
2317                                                 rval = QLA_FUNCTION_FAILED;
2318                                                 break;
2319                                         }
2320                                         if (man_id == 0x01 && flash_id == 0x6d)
2321                                                 sec_number++;
2322                                 }
2323                         }
2324
2325                         if (man_id == 0x01 && flash_id == 0x6d) {
2326                                 if (sec_number == 1 &&
2327                                     addr == (rest_addr - 1)) {
2328                                         rest_addr = 0x0fff;
2329                                         sec_mask   = 0x1f000;
2330                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2331                                         rest_addr = 0x3fff;
2332                                         sec_mask   = 0x1c000;
2333                                 }
2334                         }
2335
2336                         if (qla2x00_program_flash_address(ha, addr, data,
2337                             man_id, flash_id)) {
2338                                 rval = QLA_FUNCTION_FAILED;
2339                                 break;
2340                         }
2341                         cond_resched();
2342                 }
2343         } while (0);
2344         qla2x00_flash_disable(ha);
2345
2346         /* Resume HBA. */
2347         qla2x00_resume_hba(vha);
2348
2349         return rval;
2350 }
2351
2352 uint8_t *
2353 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2354     uint32_t offset, uint32_t length)
2355 {
2356         struct qla_hw_data *ha = vha->hw;
2357
2358         /* Suspend HBA. */
2359         scsi_block_requests(vha->host);
2360         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2361
2362         /* Go with read. */
2363         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2364
2365         /* Resume HBA. */
2366         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2367         scsi_unblock_requests(vha->host);
2368
2369         return buf;
2370 }
2371
2372 int
2373 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2374     uint32_t offset, uint32_t length)
2375 {
2376         int rval;
2377         struct qla_hw_data *ha = vha->hw;
2378
2379         /* Suspend HBA. */
2380         scsi_block_requests(vha->host);
2381         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2382
2383         /* Go with write. */
2384         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2385             length >> 2);
2386
2387         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2388         scsi_unblock_requests(vha->host);
2389
2390         return rval;
2391 }
2392
2393 uint8_t *
2394 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2395     uint32_t offset, uint32_t length)
2396 {
2397         int rval;
2398         dma_addr_t optrom_dma;
2399         void *optrom;
2400         uint8_t *pbuf;
2401         uint32_t faddr, left, burst;
2402         struct qla_hw_data *ha = vha->hw;
2403
2404         if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2405                 goto try_fast;
2406         if (offset & 0xfff)
2407                 goto slow_read;
2408         if (length < OPTROM_BURST_SIZE)
2409                 goto slow_read;
2410
2411 try_fast:
2412         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2413             &optrom_dma, GFP_KERNEL);
2414         if (!optrom) {
2415                 ql_log(ql_log_warn, vha, 0x00cc,
2416                     "Unable to allocate memory for optrom burst read (%x KB).\n",
2417                     OPTROM_BURST_SIZE / 1024);
2418                 goto slow_read;
2419         }
2420
2421         pbuf = buf;
2422         faddr = offset >> 2;
2423         left = length >> 2;
2424         burst = OPTROM_BURST_DWORDS;
2425         while (left != 0) {
2426                 if (burst > left)
2427                         burst = left;
2428
2429                 rval = qla2x00_dump_ram(vha, optrom_dma,
2430                     flash_data_addr(ha, faddr), burst);
2431                 if (rval) {
2432                         ql_log(ql_log_warn, vha, 0x00f5,
2433                             "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2434                             rval, flash_data_addr(ha, faddr),
2435                             (unsigned long long)optrom_dma);
2436                         ql_log(ql_log_warn, vha, 0x00f6,
2437                             "Reverting to slow-read.\n");
2438
2439                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2440                             optrom, optrom_dma);
2441                         goto slow_read;
2442                 }
2443
2444                 memcpy(pbuf, optrom, burst * 4);
2445
2446                 left -= burst;
2447                 faddr += burst;
2448                 pbuf += burst * 4;
2449         }
2450
2451         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2452             optrom_dma);
2453
2454         return buf;
2455
2456 slow_read:
2457     return qla24xx_read_optrom_data(vha, buf, offset, length);
2458 }
2459
2460 /**
2461  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2462  * @ha: HA context
2463  * @pcids: Pointer to the FCODE PCI data structure
2464  *
2465  * The process of retrieving the FCODE version information is at best
2466  * described as interesting.
2467  *
2468  * Within the first 100h bytes of the image an ASCII string is present
2469  * which contains several pieces of information including the FCODE
2470  * version.  Unfortunately it seems the only reliable way to retrieve
2471  * the version is by scanning for another sentinel within the string,
2472  * the FCODE build date:
2473  *
2474  *      ... 2.00.02 10/17/02 ...
2475  *
2476  * Returns QLA_SUCCESS on successful retrieval of version.
2477  */
2478 static void
2479 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2480 {
2481         int ret = QLA_FUNCTION_FAILED;
2482         uint32_t istart, iend, iter, vend;
2483         uint8_t do_next, rbyte, *vbyte;
2484
2485         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2486
2487         /* Skip the PCI data structure. */
2488         istart = pcids +
2489             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2490                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2491         iend = istart + 0x100;
2492         do {
2493                 /* Scan for the sentinel date string...eeewww. */
2494                 do_next = 0;
2495                 iter = istart;
2496                 while ((iter < iend) && !do_next) {
2497                         iter++;
2498                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2499                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2500                                     '/')
2501                                         do_next++;
2502                                 else if (qla2x00_read_flash_byte(ha,
2503                                     iter + 3) == '/')
2504                                         do_next++;
2505                         }
2506                 }
2507                 if (!do_next)
2508                         break;
2509
2510                 /* Backtrack to previous ' ' (space). */
2511                 do_next = 0;
2512                 while ((iter > istart) && !do_next) {
2513                         iter--;
2514                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2515                                 do_next++;
2516                 }
2517                 if (!do_next)
2518                         break;
2519
2520                 /*
2521                  * Mark end of version tag, and find previous ' ' (space) or
2522                  * string length (recent FCODE images -- major hack ahead!!!).
2523                  */
2524                 vend = iter - 1;
2525                 do_next = 0;
2526                 while ((iter > istart) && !do_next) {
2527                         iter--;
2528                         rbyte = qla2x00_read_flash_byte(ha, iter);
2529                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2530                                 do_next++;
2531                 }
2532                 if (!do_next)
2533                         break;
2534
2535                 /* Mark beginning of version tag, and copy data. */
2536                 iter++;
2537                 if ((vend - iter) &&
2538                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2539                         vbyte = ha->fcode_revision;
2540                         while (iter <= vend) {
2541                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2542                                 iter++;
2543                         }
2544                         ret = QLA_SUCCESS;
2545                 }
2546         } while (0);
2547
2548         if (ret != QLA_SUCCESS)
2549                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2550 }
2551
2552 int
2553 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2554 {
2555         int ret = QLA_SUCCESS;
2556         uint8_t code_type, last_image;
2557         uint32_t pcihdr, pcids;
2558         uint8_t *dbyte;
2559         uint16_t *dcode;
2560         struct qla_hw_data *ha = vha->hw;
2561
2562         if (!ha->pio_address || !mbuf)
2563                 return QLA_FUNCTION_FAILED;
2564
2565         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2566         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2567         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2568         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2569
2570         qla2x00_flash_enable(ha);
2571
2572         /* Begin with first PCI expansion ROM header. */
2573         pcihdr = 0;
2574         last_image = 1;
2575         do {
2576                 /* Verify PCI expansion ROM header. */
2577                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2578                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2579                         /* No signature */
2580                         ql_log(ql_log_fatal, vha, 0x0050,
2581                             "No matching ROM signature.\n");
2582                         ret = QLA_FUNCTION_FAILED;
2583                         break;
2584                 }
2585
2586                 /* Locate PCI data structure. */
2587                 pcids = pcihdr +
2588                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2589                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2590
2591                 /* Validate signature of PCI data structure. */
2592                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2593                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2594                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2595                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2596                         /* Incorrect header. */
2597                         ql_log(ql_log_fatal, vha, 0x0051,
2598                             "PCI data struct not found pcir_adr=%x.\n", pcids);
2599                         ret = QLA_FUNCTION_FAILED;
2600                         break;
2601                 }
2602
2603                 /* Read version */
2604                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2605                 switch (code_type) {
2606                 case ROM_CODE_TYPE_BIOS:
2607                         /* Intel x86, PC-AT compatible. */
2608                         ha->bios_revision[0] =
2609                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2610                         ha->bios_revision[1] =
2611                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2612                         ql_dbg(ql_dbg_init, vha, 0x0052,
2613                             "Read BIOS %d.%d.\n",
2614                             ha->bios_revision[1], ha->bios_revision[0]);
2615                         break;
2616                 case ROM_CODE_TYPE_FCODE:
2617                         /* Open Firmware standard for PCI (FCode). */
2618                         /* Eeeewww... */
2619                         qla2x00_get_fcode_version(ha, pcids);
2620                         break;
2621                 case ROM_CODE_TYPE_EFI:
2622                         /* Extensible Firmware Interface (EFI). */
2623                         ha->efi_revision[0] =
2624                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2625                         ha->efi_revision[1] =
2626                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2627                         ql_dbg(ql_dbg_init, vha, 0x0053,
2628                             "Read EFI %d.%d.\n",
2629                             ha->efi_revision[1], ha->efi_revision[0]);
2630                         break;
2631                 default:
2632                         ql_log(ql_log_warn, vha, 0x0054,
2633                             "Unrecognized code type %x at pcids %x.\n",
2634                             code_type, pcids);
2635                         break;
2636                 }
2637
2638                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2639
2640                 /* Locate next PCI expansion ROM. */
2641                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2642                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2643         } while (!last_image);
2644
2645         if (IS_QLA2322(ha)) {
2646                 /* Read firmware image information. */
2647                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2648                 dbyte = mbuf;
2649                 memset(dbyte, 0, 8);
2650                 dcode = (uint16_t *)dbyte;
2651
2652                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2653                     8);
2654                 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2655                     "Dumping fw "
2656                     "ver from flash:.\n");
2657                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2658                     (uint8_t *)dbyte, 8);
2659
2660                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2661                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2662                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2663                     dcode[3] == 0)) {
2664                         ql_log(ql_log_warn, vha, 0x0057,
2665                             "Unrecognized fw revision at %x.\n",
2666                             ha->flt_region_fw * 4);
2667                 } else {
2668                         /* values are in big endian */
2669                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2670                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2671                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2672                         ql_dbg(ql_dbg_init, vha, 0x0058,
2673                             "FW Version: "
2674                             "%d.%d.%d.\n", ha->fw_revision[0],
2675                             ha->fw_revision[1], ha->fw_revision[2]);
2676                 }
2677         }
2678
2679         qla2x00_flash_disable(ha);
2680
2681         return ret;
2682 }
2683
2684 int
2685 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2686 {
2687         int ret = QLA_SUCCESS;
2688         uint32_t pcihdr, pcids;
2689         uint32_t *dcode;
2690         uint8_t *bcode;
2691         uint8_t code_type, last_image;
2692         int i;
2693         struct qla_hw_data *ha = vha->hw;
2694
2695         if (IS_QLA82XX(ha))
2696                 return ret;
2697
2698         if (!mbuf)
2699                 return QLA_FUNCTION_FAILED;
2700
2701         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2702         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2703         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2704         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2705
2706         dcode = mbuf;
2707
2708         /* Begin with first PCI expansion ROM header. */
2709         pcihdr = ha->flt_region_boot << 2;
2710         last_image = 1;
2711         do {
2712                 /* Verify PCI expansion ROM header. */
2713                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2714                 bcode = mbuf + (pcihdr % 4);
2715                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2716                         /* No signature */
2717                         ql_log(ql_log_fatal, vha, 0x0059,
2718                             "No matching ROM signature.\n");
2719                         ret = QLA_FUNCTION_FAILED;
2720                         break;
2721                 }
2722
2723                 /* Locate PCI data structure. */
2724                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2725
2726                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2727                 bcode = mbuf + (pcihdr % 4);
2728
2729                 /* Validate signature of PCI data structure. */
2730                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2731                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2732                         /* Incorrect header. */
2733                         ql_log(ql_log_fatal, vha, 0x005a,
2734                             "PCI data struct not found pcir_adr=%x.\n", pcids);
2735                         ret = QLA_FUNCTION_FAILED;
2736                         break;
2737                 }
2738
2739                 /* Read version */
2740                 code_type = bcode[0x14];
2741                 switch (code_type) {
2742                 case ROM_CODE_TYPE_BIOS:
2743                         /* Intel x86, PC-AT compatible. */
2744                         ha->bios_revision[0] = bcode[0x12];
2745                         ha->bios_revision[1] = bcode[0x13];
2746                         ql_dbg(ql_dbg_init, vha, 0x005b,
2747                             "Read BIOS %d.%d.\n",
2748                             ha->bios_revision[1], ha->bios_revision[0]);
2749                         break;
2750                 case ROM_CODE_TYPE_FCODE:
2751                         /* Open Firmware standard for PCI (FCode). */
2752                         ha->fcode_revision[0] = bcode[0x12];
2753                         ha->fcode_revision[1] = bcode[0x13];
2754                         ql_dbg(ql_dbg_init, vha, 0x005c,
2755                             "Read FCODE %d.%d.\n",
2756                             ha->fcode_revision[1], ha->fcode_revision[0]);
2757                         break;
2758                 case ROM_CODE_TYPE_EFI:
2759                         /* Extensible Firmware Interface (EFI). */
2760                         ha->efi_revision[0] = bcode[0x12];
2761                         ha->efi_revision[1] = bcode[0x13];
2762                         ql_dbg(ql_dbg_init, vha, 0x005d,
2763                             "Read EFI %d.%d.\n",
2764                             ha->efi_revision[1], ha->efi_revision[0]);
2765                         break;
2766                 default:
2767                         ql_log(ql_log_warn, vha, 0x005e,
2768                             "Unrecognized code type %x at pcids %x.\n",
2769                             code_type, pcids);
2770                         break;
2771                 }
2772
2773                 last_image = bcode[0x15] & BIT_7;
2774
2775                 /* Locate next PCI expansion ROM. */
2776                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2777         } while (!last_image);
2778
2779         /* Read firmware image information. */
2780         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2781         dcode = mbuf;
2782
2783         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2784         for (i = 0; i < 4; i++)
2785                 dcode[i] = be32_to_cpu(dcode[i]);
2786
2787         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2788             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2789             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2790             dcode[3] == 0)) {
2791                 ql_log(ql_log_warn, vha, 0x005f,
2792                     "Unrecognized fw revision at %x.\n",
2793                     ha->flt_region_fw * 4);
2794         } else {
2795                 ha->fw_revision[0] = dcode[0];
2796                 ha->fw_revision[1] = dcode[1];
2797                 ha->fw_revision[2] = dcode[2];
2798                 ha->fw_revision[3] = dcode[3];
2799                 ql_dbg(ql_dbg_init, vha, 0x0060,
2800                     "Firmware revision %d.%d.%d.%d.\n",
2801                     ha->fw_revision[0], ha->fw_revision[1],
2802                     ha->fw_revision[2], ha->fw_revision[3]);
2803         }
2804
2805         /* Check for golden firmware and get version if available */
2806         if (!IS_QLA81XX(ha)) {
2807                 /* Golden firmware is not present in non 81XX adapters */
2808                 return ret;
2809         }
2810
2811         memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
2812         dcode = mbuf;
2813         ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
2814             ha->flt_region_gold_fw << 2, 32);
2815
2816         if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
2817             dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
2818                 ql_log(ql_log_warn, vha, 0x0056,
2819                     "Unrecognized golden fw at 0x%x.\n",
2820                     ha->flt_region_gold_fw * 4);
2821                 return ret;
2822         }
2823
2824         for (i = 4; i < 8; i++)
2825                 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
2826
2827         return ret;
2828 }
2829
2830 static int
2831 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2832 {
2833         if (pos >= end || *pos != 0x82)
2834                 return 0;
2835
2836         pos += 3 + pos[1];
2837         if (pos >= end || *pos != 0x90)
2838                 return 0;
2839
2840         pos += 3 + pos[1];
2841         if (pos >= end || *pos != 0x78)
2842                 return 0;
2843
2844         return 1;
2845 }
2846
2847 int
2848 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2849 {
2850         struct qla_hw_data *ha = vha->hw;
2851         uint8_t *pos = ha->vpd;
2852         uint8_t *end = pos + ha->vpd_size;
2853         int len = 0;
2854
2855         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2856                 return 0;
2857
2858         while (pos < end && *pos != 0x78) {
2859                 len = (*pos == 0x82) ? pos[1] : pos[2];
2860
2861                 if (!strncmp(pos, key, strlen(key)))
2862                         break;
2863
2864                 if (*pos != 0x90 && *pos != 0x91)
2865                         pos += len;
2866
2867                 pos += 3;
2868         }
2869
2870         if (pos < end - len && *pos != 0x78)
2871                 return snprintf(str, size, "%.*s", len, pos + 3);
2872
2873         return 0;
2874 }
2875
2876 int
2877 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
2878 {
2879         int len, max_len;
2880         uint32_t fcp_prio_addr;
2881         struct qla_hw_data *ha = vha->hw;
2882
2883         if (!ha->fcp_prio_cfg) {
2884                 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
2885                 if (!ha->fcp_prio_cfg) {
2886                         ql_log(ql_log_warn, vha, 0x00d5,
2887                             "Unable to allocate memory for fcp priorty data (%x).\n",
2888                             FCP_PRIO_CFG_SIZE);
2889                         return QLA_FUNCTION_FAILED;
2890                 }
2891         }
2892         memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
2893
2894         fcp_prio_addr = ha->flt_region_fcp_prio;
2895
2896         /* first read the fcp priority data header from flash */
2897         ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
2898                         fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
2899
2900         if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
2901                 goto fail;
2902
2903         /* read remaining FCP CMD config data from flash */
2904         fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
2905         len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
2906         max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
2907
2908         ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
2909                         fcp_prio_addr << 2, (len < max_len ? len : max_len));
2910
2911         /* revalidate the entire FCP priority config data, including entries */
2912         if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
2913                 goto fail;
2914
2915         ha->flags.fcp_prio_enabled = 1;
2916         return QLA_SUCCESS;
2917 fail:
2918         vfree(ha->fcp_prio_cfg);
2919         ha->fcp_prio_cfg = NULL;
2920         return QLA_FUNCTION_FAILED;
2921 }