Pileus Git - ~andy/linux/blob - drivers/scsi/qla2xxx/qla_nx2.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/vmalloc.h>
   9
  10 #include "qla_def.h"
  11 #include "qla_gbl.h"
  12
  13 #include <linux/delay.h>
  14
  15 /* 8044 Flash Read/Write functions */
  16 uint32_t
  17 qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
  18 {
  19         return readl((void __iomem *) (ha->nx_pcibase + addr));
  20 }
  21
  22 void
  23 qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
  24 {
  25         writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
  26 }
  27
  28 int
  29 qla8044_rd_direct(struct scsi_qla_host *vha,
  30         const uint32_t crb_reg)
  31 {
  32         struct qla_hw_data *ha = vha->hw;
  33
  34         if (crb_reg < CRB_REG_INDEX_MAX)
  35                 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
  36         else
  37                 return QLA_FUNCTION_FAILED;
  38 }
  39
  40 void
  41 qla8044_wr_direct(struct scsi_qla_host *vha,
  42         const uint32_t crb_reg,
  43         const uint32_t value)
  44 {
  45         struct qla_hw_data *ha = vha->hw;
  46
  47         if (crb_reg < CRB_REG_INDEX_MAX)
  48                 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
  49 }
  50
  51 static int
  52 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
  53 {
  54         uint32_t val;
  55         int ret_val = QLA_SUCCESS;
  56         struct qla_hw_data *ha = vha->hw;
  57
  58         qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
  59         val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
  60
  61         if (val != addr) {
  62                 ql_log(ql_log_warn, vha, 0xb087,
  63                     "%s: Failed to set register window : "
  64                     "addr written 0x%x, read 0x%x!\n",
  65                     __func__, addr, val);
  66                 ret_val = QLA_FUNCTION_FAILED;
  67         }
  68         return ret_val;
  69 }
  70
  71 static int
  72 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
  73 {
  74         int ret_val = QLA_SUCCESS;
  75         struct qla_hw_data *ha = vha->hw;
  76
  77         ret_val = qla8044_set_win_base(vha, addr);
  78         if (!ret_val)
  79                 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
  80         else
  81                 ql_log(ql_log_warn, vha, 0xb088,
  82                     "%s: failed read of addr 0x%x!\n", __func__, addr);
  83         return ret_val;
  84 }
  85
  86 static int
  87 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
  88 {
  89         int ret_val = QLA_SUCCESS;
  90         struct qla_hw_data *ha = vha->hw;
  91
  92         ret_val = qla8044_set_win_base(vha, addr);
  93         if (!ret_val)
  94                 qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
  95         else
  96                 ql_log(ql_log_warn, vha, 0xb089,
  97                     "%s: failed wrt to addr 0x%x, data 0x%x\n",
  98                     __func__, addr, data);
  99         return ret_val;
 100 }
 101
 102 /*
 103  * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
 104  *
 105  * @ha : Pointer to adapter structure
 106  * @raddr : CRB address to read from
 107  * @waddr : CRB address to write to
 108  *
 109  */
 110 static void
 111 qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
 112         uint32_t raddr, uint32_t waddr)
 113 {
 114         uint32_t value;
 115
 116         qla8044_rd_reg_indirect(vha, raddr, &value);
 117         qla8044_wr_reg_indirect(vha, waddr, value);
 118 }
 119
 120 /*
 121  * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
 122  * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
 123  *
 124  * @vha : Pointer to adapter structure
 125  * @raddr : CRB address to read from
 126  * @waddr : CRB address to write to
 127  * @p_rmw_hdr : header with shift/or/xor values.
 128  *
 129  */
 130 static void
 131 qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
 132         uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
 133 {
 134         uint32_t value;
 135
 136         if (p_rmw_hdr->index_a)
 137                 value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
 138         else
 139                 qla8044_rd_reg_indirect(vha, raddr, &value);
 140         value &= p_rmw_hdr->test_mask;
 141         value <<= p_rmw_hdr->shl;
 142         value >>= p_rmw_hdr->shr;
 143         value |= p_rmw_hdr->or_value;
 144         value ^= p_rmw_hdr->xor_value;
 145         qla8044_wr_reg_indirect(vha, waddr, value);
 146         return;
 147 }
 148
 149 inline void
 150 qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
 151 {
 152         uint32_t qsnt_state;
 153         struct qla_hw_data *ha = vha->hw;
 154
 155         qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 156         qsnt_state |= (1 << ha->portnum);
 157         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
 158         ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
 159              __func__, vha->host_no, qsnt_state);
 160 }
 161
 162 void
 163 qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
 164 {
 165         uint32_t qsnt_state;
 166         struct qla_hw_data *ha = vha->hw;
 167
 168         qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 169         qsnt_state &= ~(1 << ha->portnum);
 170         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
 171         ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
 172             __func__, vha->host_no, qsnt_state);
 173 }
 174
 175 /**
 176  *
 177  * qla8044_lock_recovery - Recovers the idc_lock.
 178  * @ha : Pointer to adapter structure
 179  *
 180  * Lock Recovery Register
 181  * 5-2  Lock recovery owner: Function ID of driver doing lock recovery,
 182  *      valid if bits 1..0 are set by driver doing lock recovery.
 183  * 1-0  1 - Driver intends to force unlock the IDC lock.
 184  *      2 - Driver is moving forward to unlock the IDC lock. Driver clears
 185  *          this field after force unlocking the IDC lock.
 186  *
 187  * Lock Recovery process
 188  * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
 189  *    greater than 0, then wait for the other driver to unlock otherwise
 190  *    move to the next step.
 191  * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
 192  *    register bits 1..0 and also set the function# in bits 5..2.
 193  * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
 194  *    Wait for the other driver to perform lock recovery if the function
 195  *    number in bits 5..2 has changed, otherwise move to the next step.
 196  * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
 197  *    leaving your function# in bits 5..2.
 198  * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
 199  *    the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
 200  **/
 201 static int
 202 qla8044_lock_recovery(struct scsi_qla_host *vha)
 203 {
 204         uint32_t lock = 0, lockid;
 205         struct qla_hw_data *ha = vha->hw;
 206
 207         lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
 208
 209         /* Check for other Recovery in progress, go wait */
 210         if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
 211                 return QLA_FUNCTION_FAILED;
 212
 213         /* Intent to Recover */
 214         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
 215             (ha->portnum <<
 216              IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
 217         msleep(200);
 218
 219         /* Check Intent to Recover is advertised */
 220         lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
 221         if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
 222             IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
 223                 return QLA_FUNCTION_FAILED;
 224
 225         ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
 226             , __func__, ha->portnum);
 227
 228         /* Proceed to Recover */
 229         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
 230             (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
 231             PROCEED_TO_RECOVER);
 232
 233         /* Force Unlock() */
 234         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
 235         qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
 236
 237         /* Clear bits 0-5 in IDC_RECOVERY register*/
 238         qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
 239
 240         /* Get lock() */
 241         lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
 242         if (lock) {
 243                 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 244                 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
 245                 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
 246                 return QLA_SUCCESS;
 247         } else
 248                 return QLA_FUNCTION_FAILED;
 249 }
 250
 251 int
 252 qla8044_idc_lock(struct qla_hw_data *ha)
 253 {
 254         uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
 255         uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
 256         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 257
 258         while (status == 0) {
 259                 /* acquire semaphore5 from PCI HW block */
 260                 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
 261
 262                 if (status) {
 263                         /* Increment Counter (8-31) and update func_num (0-7) on
 264                          * getting a successful lock  */
 265                         lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 266                         lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
 267                         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
 268                         break;
 269                 }
 270
 271                 if (timeout == 0)
 272                         first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 273
 274                 if (++timeout >=
 275                     (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
 276                         tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 277                         func_num = tmo_owner & 0xFF;
 278                         lock_cnt = tmo_owner >> 8;
 279                         ql_log(ql_log_warn, vha, 0xb114,
 280                             "%s: Lock by func %d failed after 2s, lock held "
 281                             "by func %d, lock count %d, first_owner %d\n",
 282                             __func__, ha->portnum, func_num, lock_cnt,
 283                             (first_owner & 0xFF));
 284                         if (first_owner != tmo_owner) {
 285                                 /* Some other driver got lock,
 286                                  * OR same driver got lock again (counter
 287                                  * value changed), when we were waiting for
 288                                  * lock. Retry for another 2 sec */
 289                                 ql_dbg(ql_dbg_p3p, vha, 0xb115,
 290                                     "%s: %d: IDC lock failed\n",
 291                                     __func__, ha->portnum);
 292                                 timeout = 0;
 293                         } else {
 294                                 /* Same driver holding lock > 2sec.
 295                                  * Force Recovery */
 296                                 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
 297                                         /* Recovered and got lock */
 298                                         ret_val = QLA_SUCCESS;
 299                                         ql_dbg(ql_dbg_p3p, vha, 0xb116,
 300                                             "%s:IDC lock Recovery by %d"
 301                                             "successful...\n", __func__,
 302                                              ha->portnum);
 303                                 }
 304                                 /* Recovery Failed, some other function
 305                                  * has the lock, wait for 2secs
 306                                  * and retry
 307                                  */
 308                                  ql_dbg(ql_dbg_p3p, vha, 0xb08a,
 309                                      "%s: IDC lock Recovery by %d "
 310                                      "failed, Retrying timout\n", __func__,
 311                                      ha->portnum);
 312                                  timeout = 0;
 313                         }
 314                 }
 315                 msleep(QLA8044_DRV_LOCK_MSLEEP);
 316         }
 317         return ret_val;
 318 }
 319
 320 void
 321 qla8044_idc_unlock(struct qla_hw_data *ha)
 322 {
 323         int id;
 324         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 325
 326         id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
 327
 328         if ((id & 0xFF) != ha->portnum) {
 329                 ql_log(ql_log_warn, vha, 0xb118,
 330                     "%s: IDC Unlock by %d failed, lock owner is %d!\n",
 331                     __func__, ha->portnum, (id & 0xFF));
 332                 return;
 333         }
 334
 335         /* Keep lock counter value, update the ha->func_num to 0xFF */
 336         qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
 337         qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
 338 }
 339
 340 /* 8044 Flash Lock/Unlock functions */
 341 static int
 342 qla8044_flash_lock(scsi_qla_host_t *vha)
 343 {
 344         int lock_owner;
 345         int timeout = 0;
 346         uint32_t lock_status = 0;
 347         int ret_val = QLA_SUCCESS;
 348         struct qla_hw_data *ha = vha->hw;
 349
 350         while (lock_status == 0) {
 351                 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
 352                 if (lock_status)
 353                         break;
 354
 355                 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
 356                         lock_owner = qla8044_rd_reg(ha,
 357                             QLA8044_FLASH_LOCK_ID);
 358                         ql_log(ql_log_warn, vha, 0xb113,
 359                             "%s: flash lock by %d failed, held by %d\n",
 360                                 __func__, ha->portnum, lock_owner);
 361                         ret_val = QLA_FUNCTION_FAILED;
 362                         break;
 363                 }
 364                 msleep(20);
 365         }
 366         qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
 367         return ret_val;
 368 }
 369
 370 static void
 371 qla8044_flash_unlock(scsi_qla_host_t *vha)
 372 {
 373         int ret_val;
 374         struct qla_hw_data *ha = vha->hw;
 375
 376         /* Reading FLASH_UNLOCK register unlocks the Flash */
 377         qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
 378         ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
 379 }
 380
 381
 382 static
 383 void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
 384 {
 385
 386         if (qla8044_flash_lock(vha)) {
 387                 /* Someone else is holding the lock. */
 388                 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
 389         }
 390
 391         /*
 392          * Either we got the lock, or someone
 393          * else died while holding it.
 394          * In either case, unlock.
 395          */
 396         qla8044_flash_unlock(vha);
 397 }
 398
 399 /*
 400  * Address and length are byte address
 401  */
 402 static int
 403 qla8044_read_flash_data(scsi_qla_host_t *vha,  uint8_t *p_data,
 404         uint32_t flash_addr, int u32_word_count)
 405 {
 406         int i, ret_val = QLA_SUCCESS;
 407         uint32_t u32_word;
 408
 409         if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
 410                 ret_val = QLA_FUNCTION_FAILED;
 411                 goto exit_lock_error;
 412         }
 413
 414         if (flash_addr & 0x03) {
 415                 ql_log(ql_log_warn, vha, 0xb117,
 416                     "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
 417                 ret_val = QLA_FUNCTION_FAILED;
 418                 goto exit_flash_read;
 419         }
 420
 421         for (i = 0; i < u32_word_count; i++) {
 422                 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
 423                     (flash_addr & 0xFFFF0000))) {
 424                         ql_log(ql_log_warn, vha, 0xb119,
 425                             "%s: failed to write addr 0x%x to "
 426                             "FLASH_DIRECT_WINDOW\n! ",
 427                             __func__, flash_addr);
 428                         ret_val = QLA_FUNCTION_FAILED;
 429                         goto exit_flash_read;
 430                 }
 431
 432                 ret_val = qla8044_rd_reg_indirect(vha,
 433                     QLA8044_FLASH_DIRECT_DATA(flash_addr),
 434                     &u32_word);
 435                 if (ret_val != QLA_SUCCESS) {
 436                         ql_log(ql_log_warn, vha, 0xb08c,
 437                             "%s: failed to read addr 0x%x!\n",
 438                             __func__, flash_addr);
 439                         goto exit_flash_read;
 440                 }
 441
 442                 *(uint32_t *)p_data = u32_word;
 443                 p_data = p_data + 4;
 444                 flash_addr = flash_addr + 4;
 445         }
 446
 447 exit_flash_read:
 448         qla8044_flash_unlock(vha);
 449
 450 exit_lock_error:
 451         return ret_val;
 452 }
 453
 454 /*
 455  * Address and length are byte address
 456  */
 457 uint8_t *
 458 qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
 459         uint32_t offset, uint32_t length)
 460 {
 461         scsi_block_requests(vha->host);
 462         if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4)
 463             != QLA_SUCCESS) {
 464                 ql_log(ql_log_warn, vha,  0xb08d,
 465                     "%s: Failed to read from flash\n",
 466                     __func__);
 467         }
 468         scsi_unblock_requests(vha->host);
 469         return buf;
 470 }
 471
 472 inline int
 473 qla8044_need_reset(struct scsi_qla_host *vha)
 474 {
 475         uint32_t drv_state, drv_active;
 476         int rval;
 477         struct qla_hw_data *ha = vha->hw;
 478
 479         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
 480         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
 481
 482         rval = drv_state & (1 << ha->portnum);
 483
 484         if (ha->flags.eeh_busy && drv_active)
 485                 rval = 1;
 486         return rval;
 487 }
 488
 489 /*
 490  * qla8044_write_list - Write the value (p_entry->arg2) to address specified
 491  * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
 492  * entries.
 493  *
 494  * @vha : Pointer to adapter structure
 495  * @p_hdr : reset_entry header for WRITE_LIST opcode.
 496  *
 497  */
 498 static void
 499 qla8044_write_list(struct scsi_qla_host *vha,
 500         struct qla8044_reset_entry_hdr *p_hdr)
 501 {
 502         struct qla8044_entry *p_entry;
 503         uint32_t i;
 504
 505         p_entry = (struct qla8044_entry *)((char *)p_hdr +
 506             sizeof(struct qla8044_reset_entry_hdr));
 507
 508         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 509                 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
 510                 if (p_hdr->delay)
 511                         udelay((uint32_t)(p_hdr->delay));
 512         }
 513 }
 514
 515 /*
 516  * qla8044_read_write_list - Read from address specified by p_entry->arg1,
 517  * write value read to address specified by p_entry->arg2, for all entries in
 518  * header with delay of p_hdr->delay between entries.
 519  *
 520  * @vha : Pointer to adapter structure
 521  * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
 522  *
 523  */
 524 static void
 525 qla8044_read_write_list(struct scsi_qla_host *vha,
 526         struct qla8044_reset_entry_hdr *p_hdr)
 527 {
 528         struct qla8044_entry *p_entry;
 529         uint32_t i;
 530
 531         p_entry = (struct qla8044_entry *)((char *)p_hdr +
 532             sizeof(struct qla8044_reset_entry_hdr));
 533
 534         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 535                 qla8044_read_write_crb_reg(vha, p_entry->arg1,
 536                     p_entry->arg2);
 537                 if (p_hdr->delay)
 538                         udelay((uint32_t)(p_hdr->delay));
 539         }
 540 }
 541
 542 /*
 543  * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
 544  * value read ANDed with test_mask is equal to test_result.
 545  *
 546  * @ha : Pointer to adapter structure
 547  * @addr : CRB register address
 548  * @duration : Poll for total of "duration" msecs
 549  * @test_mask : Mask value read with "test_mask"
 550  * @test_result : Compare (value&test_mask) with test_result.
 551  *
 552  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
 553  */
 554 static int
 555 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
 556         int duration, uint32_t test_mask, uint32_t test_result)
 557 {
 558         uint32_t value;
 559         int timeout_error;
 560         uint8_t retries;
 561         int ret_val = QLA_SUCCESS;
 562
 563         ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
 564         if (ret_val == QLA_FUNCTION_FAILED) {
 565                 timeout_error = 1;
 566                 goto exit_poll_reg;
 567         }
 568
 569         /* poll every 1/10 of the total duration */
 570         retries = duration/10;
 571
 572         do {
 573                 if ((value & test_mask) != test_result) {
 574                         timeout_error = 1;
 575                         msleep(duration/10);
 576                         ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
 577                         if (ret_val == QLA_FUNCTION_FAILED) {
 578                                 timeout_error = 1;
 579                                 goto exit_poll_reg;
 580                         }
 581                 } else {
 582                         timeout_error = 0;
 583                         break;
 584                 }
 585         } while (retries--);
 586
 587 exit_poll_reg:
 588         if (timeout_error) {
 589                 vha->reset_tmplt.seq_error++;
 590                 ql_log(ql_log_fatal, vha, 0xb090,
 591                     "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
 592                     __func__, value, test_mask, test_result);
 593         }
 594
 595         return timeout_error;
 596 }
 597
 598 /*
 599  * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
 600  * register specified by p_entry->arg1 and compare (value AND test_mask) with
 601  * test_result to validate it. Wait for p_hdr->delay between processing entries.
 602  *
 603  * @ha : Pointer to adapter structure
 604  * @p_hdr : reset_entry header for POLL_LIST opcode.
 605  *
 606  */
 607 static void
 608 qla8044_poll_list(struct scsi_qla_host *vha,
 609         struct qla8044_reset_entry_hdr *p_hdr)
 610 {
 611         long delay;
 612         struct qla8044_entry *p_entry;
 613         struct qla8044_poll *p_poll;
 614         uint32_t i;
 615         uint32_t value;
 616
 617         p_poll = (struct qla8044_poll *)
 618                 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
 619
 620         /* Entries start after 8 byte qla8044_poll, poll header contains
 621          * the test_mask, test_value.
 622          */
 623         p_entry = (struct qla8044_entry *)((char *)p_poll +
 624             sizeof(struct qla8044_poll));
 625
 626         delay = (long)p_hdr->delay;
 627
 628         if (!delay) {
 629                 for (i = 0; i < p_hdr->count; i++, p_entry++)
 630                         qla8044_poll_reg(vha, p_entry->arg1,
 631                             delay, p_poll->test_mask, p_poll->test_value);
 632         } else {
 633                 for (i = 0; i < p_hdr->count; i++, p_entry++) {
 634                         if (delay) {
 635                                 if (qla8044_poll_reg(vha,
 636                                     p_entry->arg1, delay,
 637                                     p_poll->test_mask,
 638                                     p_poll->test_value)) {
 639                                         /*If
 640                                         * (data_read&test_mask != test_value)
 641                                         * read TIMEOUT_ADDR (arg1) and
 642                                         * ADDR (arg2) registers
 643                                         */
 644                                         qla8044_rd_reg_indirect(vha,
 645                                             p_entry->arg1, &value);
 646                                         qla8044_rd_reg_indirect(vha,
 647                                             p_entry->arg2, &value);
 648                                 }
 649                         }
 650                 }
 651         }
 652 }
 653
 654 /*
 655  * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
 656  * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
 657  * expires.
 658  *
 659  * @vha : Pointer to adapter structure
 660  * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
 661  *
 662  */
 663 static void
 664 qla8044_poll_write_list(struct scsi_qla_host *vha,
 665         struct qla8044_reset_entry_hdr *p_hdr)
 666 {
 667         long delay;
 668         struct qla8044_quad_entry *p_entry;
 669         struct qla8044_poll *p_poll;
 670         uint32_t i;
 671
 672         p_poll = (struct qla8044_poll *)((char *)p_hdr +
 673             sizeof(struct qla8044_reset_entry_hdr));
 674
 675         p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
 676             sizeof(struct qla8044_poll));
 677
 678         delay = (long)p_hdr->delay;
 679
 680         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 681                 qla8044_wr_reg_indirect(vha,
 682                     p_entry->dr_addr, p_entry->dr_value);
 683                 qla8044_wr_reg_indirect(vha,
 684                     p_entry->ar_addr, p_entry->ar_value);
 685                 if (delay) {
 686                         if (qla8044_poll_reg(vha,
 687                             p_entry->ar_addr, delay,
 688                             p_poll->test_mask,
 689                             p_poll->test_value)) {
 690                                 ql_dbg(ql_dbg_p3p, vha, 0xb091,
 691                                     "%s: Timeout Error: poll list, ",
 692                                     __func__);
 693                                 ql_dbg(ql_dbg_p3p, vha, 0xb092,
 694                                     "item_num %d, entry_num %d\n", i,
 695                                     vha->reset_tmplt.seq_index);
 696                         }
 697                 }
 698         }
 699 }
 700
 701 /*
 702  * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
 703  * value, write value to p_entry->arg2. Process entries with p_hdr->delay
 704  * between entries.
 705  *
 706  * @vha : Pointer to adapter structure
 707  * @p_hdr : header with shift/or/xor values.
 708  *
 709  */
 710 static void
 711 qla8044_read_modify_write(struct scsi_qla_host *vha,
 712         struct qla8044_reset_entry_hdr *p_hdr)
 713 {
 714         struct qla8044_entry *p_entry;
 715         struct qla8044_rmw *p_rmw_hdr;
 716         uint32_t i;
 717
 718         p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
 719             sizeof(struct qla8044_reset_entry_hdr));
 720
 721         p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
 722             sizeof(struct qla8044_rmw));
 723
 724         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 725                 qla8044_rmw_crb_reg(vha, p_entry->arg1,
 726                     p_entry->arg2, p_rmw_hdr);
 727                 if (p_hdr->delay)
 728                         udelay((uint32_t)(p_hdr->delay));
 729         }
 730 }
 731
 732 /*
 733  * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
 734  * two entries of a sequence.
 735  *
 736  * @vha : Pointer to adapter structure
 737  * @p_hdr : Common reset entry header.
 738  *
 739  */
 740 static
 741 void qla8044_pause(struct scsi_qla_host *vha,
 742         struct qla8044_reset_entry_hdr *p_hdr)
 743 {
 744         if (p_hdr->delay)
 745                 mdelay((uint32_t)((long)p_hdr->delay));
 746 }
 747
 748 /*
 749  * qla8044_template_end - Indicates end of reset sequence processing.
 750  *
 751  * @vha : Pointer to adapter structure
 752  * @p_hdr : Common reset entry header.
 753  *
 754  */
 755 static void
 756 qla8044_template_end(struct scsi_qla_host *vha,
 757         struct qla8044_reset_entry_hdr *p_hdr)
 758 {
 759         vha->reset_tmplt.template_end = 1;
 760
 761         if (vha->reset_tmplt.seq_error == 0) {
 762                 ql_dbg(ql_dbg_p3p, vha, 0xb093,
 763                     "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
 764         } else {
 765                 ql_log(ql_log_fatal, vha, 0xb094,
 766                     "%s: Reset sequence completed with some timeout "
 767                     "errors.\n", __func__);
 768         }
 769 }
 770
 771 /*
 772  * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
 773  * if (value & test_mask != test_value) re-read till timeout value expires,
 774  * read dr_addr register and assign to reset_tmplt.array.
 775  *
 776  * @vha : Pointer to adapter structure
 777  * @p_hdr : Common reset entry header.
 778  *
 779  */
 780 static void
 781 qla8044_poll_read_list(struct scsi_qla_host *vha,
 782         struct qla8044_reset_entry_hdr *p_hdr)
 783 {
 784         long delay;
 785         int index;
 786         struct qla8044_quad_entry *p_entry;
 787         struct qla8044_poll *p_poll;
 788         uint32_t i;
 789         uint32_t value;
 790
 791         p_poll = (struct qla8044_poll *)
 792                 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
 793
 794         p_entry = (struct qla8044_quad_entry *)
 795                 ((char *)p_poll + sizeof(struct qla8044_poll));
 796
 797         delay = (long)p_hdr->delay;
 798
 799         for (i = 0; i < p_hdr->count; i++, p_entry++) {
 800                 qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
 801                     p_entry->ar_value);
 802                 if (delay) {
 803                         if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
 804                             p_poll->test_mask, p_poll->test_value)) {
 805                                 ql_dbg(ql_dbg_p3p, vha, 0xb095,
 806                                     "%s: Timeout Error: poll "
 807                                     "list, ", __func__);
 808                                 ql_dbg(ql_dbg_p3p, vha, 0xb096,
 809                                     "Item_num %d, "
 810                                     "entry_num %d\n", i,
 811                                     vha->reset_tmplt.seq_index);
 812                         } else {
 813                                 index = vha->reset_tmplt.array_index;
 814                                 qla8044_rd_reg_indirect(vha,
 815                                     p_entry->dr_addr, &value);
 816                                 vha->reset_tmplt.array[index++] = value;
 817                                 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
 818                                         vha->reset_tmplt.array_index = 1;
 819                         }
 820                 }
 821         }
 822 }
 823
 824 /*
 825  * qla8031_process_reset_template - Process all entries in reset template
 826  * till entry with SEQ_END opcode, which indicates end of the reset template
 827  * processing. Each entry has a Reset Entry header, entry opcode/command, with
 828  * size of the entry, number of entries in sub-sequence and delay in microsecs
 829  * or timeout in millisecs.
 830  *
 831  * @ha : Pointer to adapter structure
 832  * @p_buff : Common reset entry header.
 833  *
 834  */
 835 static void
 836 qla8044_process_reset_template(struct scsi_qla_host *vha,
 837         char *p_buff)
 838 {
 839         int index, entries;
 840         struct qla8044_reset_entry_hdr *p_hdr;
 841         char *p_entry = p_buff;
 842
 843         vha->reset_tmplt.seq_end = 0;
 844         vha->reset_tmplt.template_end = 0;
 845         entries = vha->reset_tmplt.hdr->entries;
 846         index = vha->reset_tmplt.seq_index;
 847
 848         for (; (!vha->reset_tmplt.seq_end) && (index  < entries); index++) {
 849                 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
 850                 switch (p_hdr->cmd) {
 851                 case OPCODE_NOP:
 852                         break;
 853                 case OPCODE_WRITE_LIST:
 854                         qla8044_write_list(vha, p_hdr);
 855                         break;
 856                 case OPCODE_READ_WRITE_LIST:
 857                         qla8044_read_write_list(vha, p_hdr);
 858                         break;
 859                 case OPCODE_POLL_LIST:
 860                         qla8044_poll_list(vha, p_hdr);
 861                         break;
 862                 case OPCODE_POLL_WRITE_LIST:
 863                         qla8044_poll_write_list(vha, p_hdr);
 864                         break;
 865                 case OPCODE_READ_MODIFY_WRITE:
 866                         qla8044_read_modify_write(vha, p_hdr);
 867                         break;
 868                 case OPCODE_SEQ_PAUSE:
 869                         qla8044_pause(vha, p_hdr);
 870                         break;
 871                 case OPCODE_SEQ_END:
 872                         vha->reset_tmplt.seq_end = 1;
 873                         break;
 874                 case OPCODE_TMPL_END:
 875                         qla8044_template_end(vha, p_hdr);
 876                         break;
 877                 case OPCODE_POLL_READ_LIST:
 878                         qla8044_poll_read_list(vha, p_hdr);
 879                         break;
 880                 default:
 881                         ql_log(ql_log_fatal, vha, 0xb097,
 882                             "%s: Unknown command ==> 0x%04x on "
 883                             "entry = %d\n", __func__, p_hdr->cmd, index);
 884                         break;
 885                 }
 886                 /*
 887                  *Set pointer to next entry in the sequence.
 888                 */
 889                 p_entry += p_hdr->size;
 890         }
 891         vha->reset_tmplt.seq_index = index;
 892 }
 893
 894 static void
 895 qla8044_process_init_seq(struct scsi_qla_host *vha)
 896 {
 897         qla8044_process_reset_template(vha,
 898             vha->reset_tmplt.init_offset);
 899         if (vha->reset_tmplt.seq_end != 1)
 900                 ql_log(ql_log_fatal, vha, 0xb098,
 901                     "%s: Abrupt INIT Sub-Sequence end.\n",
 902                     __func__);
 903 }
 904
 905 static void
 906 qla8044_process_stop_seq(struct scsi_qla_host *vha)
 907 {
 908         vha->reset_tmplt.seq_index = 0;
 909         qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
 910         if (vha->reset_tmplt.seq_end != 1)
 911                 ql_log(ql_log_fatal, vha, 0xb099,
 912                     "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
 913 }
 914
 915 static void
 916 qla8044_process_start_seq(struct scsi_qla_host *vha)
 917 {
 918         qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
 919         if (vha->reset_tmplt.template_end != 1)
 920                 ql_log(ql_log_fatal, vha, 0xb09a,
 921                     "%s: Abrupt START Sub-Sequence end.\n",
 922                     __func__);
 923 }
 924
 925 static int
 926 qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
 927         uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
 928 {
 929         uint32_t i;
 930         uint32_t u32_word;
 931         uint32_t flash_offset;
 932         uint32_t addr = flash_addr;
 933         int ret_val = QLA_SUCCESS;
 934
 935         flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
 936
 937         if (addr & 0x3) {
 938                 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
 939                     __func__, addr);
 940                 ret_val = QLA_FUNCTION_FAILED;
 941                 goto exit_lockless_read;
 942         }
 943
 944         ret_val = qla8044_wr_reg_indirect(vha,
 945             QLA8044_FLASH_DIRECT_WINDOW, (addr));
 946
 947         if (ret_val != QLA_SUCCESS) {
 948                 ql_log(ql_log_fatal, vha, 0xb09c,
 949                     "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
 950                     __func__, addr);
 951                 goto exit_lockless_read;
 952         }
 953
 954         /* Check if data is spread across multiple sectors  */
 955         if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
 956             (QLA8044_FLASH_SECTOR_SIZE - 1)) {
 957                 /* Multi sector read */
 958                 for (i = 0; i < u32_word_count; i++) {
 959                         ret_val = qla8044_rd_reg_indirect(vha,
 960                             QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
 961                         if (ret_val != QLA_SUCCESS) {
 962                                 ql_log(ql_log_fatal, vha, 0xb09d,
 963                                     "%s: failed to read addr 0x%x!\n",
 964                                     __func__, addr);
 965                                 goto exit_lockless_read;
 966                         }
 967                         *(uint32_t *)p_data  = u32_word;
 968                         p_data = p_data + 4;
 969                         addr = addr + 4;
 970                         flash_offset = flash_offset + 4;
 971                         if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
 972                                 /* This write is needed once for each sector */
 973                                 ret_val = qla8044_wr_reg_indirect(vha,
 974                                     QLA8044_FLASH_DIRECT_WINDOW, (addr));
 975                                 if (ret_val != QLA_SUCCESS) {
 976                                         ql_log(ql_log_fatal, vha, 0xb09f,
 977                                             "%s: failed to write addr "
 978                                             "0x%x to FLASH_DIRECT_WINDOW!\n",
 979                                             __func__, addr);
 980                                         goto exit_lockless_read;
 981                                 }
 982                                 flash_offset = 0;
 983                         }
 984                 }
 985         } else {
 986                 /* Single sector read */
 987                 for (i = 0; i < u32_word_count; i++) {
 988                         ret_val = qla8044_rd_reg_indirect(vha,
 989                             QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
 990                         if (ret_val != QLA_SUCCESS) {
 991                                 ql_log(ql_log_fatal, vha, 0xb0a0,
 992                                     "%s: failed to read addr 0x%x!\n",
 993                                     __func__, addr);
 994                                 goto exit_lockless_read;
 995                         }
 996                         *(uint32_t *)p_data = u32_word;
 997                         p_data = p_data + 4;
 998                         addr = addr + 4;
 999                 }
1000         }
1001
1002 exit_lockless_read:
1003         return ret_val;
1004 }
1005
1006 /*
1007  * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1008  *
1009  * @vha : Pointer to adapter structure
1010  * addr : Flash address to write to
1011  * data : Data to be written
1012  * count : word_count to be written
1013  *
1014  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1015  */
1016 static int
1017 qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
1018         uint64_t addr, uint32_t *data, uint32_t count)
1019 {
1020         int i, j, ret_val = QLA_SUCCESS;
1021         uint32_t agt_ctrl;
1022         unsigned long flags;
1023         struct qla_hw_data *ha = vha->hw;
1024
1025         /* Only 128-bit aligned access */
1026         if (addr & 0xF) {
1027                 ret_val = QLA_FUNCTION_FAILED;
1028                 goto exit_ms_mem_write;
1029         }
1030         write_lock_irqsave(&ha->hw_lock, flags);
1031
1032         /* Write address */
1033         ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1034         if (ret_val == QLA_FUNCTION_FAILED) {
1035                 ql_log(ql_log_fatal, vha, 0xb0a1,
1036                     "%s: write to AGT_ADDR_HI failed!\n", __func__);
1037                 goto exit_ms_mem_write_unlock;
1038         }
1039
1040         for (i = 0; i < count; i++, addr += 16) {
1041                 if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET,
1042                     QLA8044_ADDR_QDR_NET_MAX)) ||
1043                     (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET,
1044                         QLA8044_ADDR_DDR_NET_MAX)))) {
1045                         ret_val = QLA_FUNCTION_FAILED;
1046                         goto exit_ms_mem_write_unlock;
1047                 }
1048
1049                 ret_val = qla8044_wr_reg_indirect(vha,
1050                     MD_MIU_TEST_AGT_ADDR_LO, addr);
1051
1052                 /* Write data */
1053                 ret_val += qla8044_wr_reg_indirect(vha,
1054                     MD_MIU_TEST_AGT_WRDATA_LO, *data++);
1055                 ret_val += qla8044_wr_reg_indirect(vha,
1056                     MD_MIU_TEST_AGT_WRDATA_HI, *data++);
1057                 ret_val += qla8044_wr_reg_indirect(vha,
1058                     MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
1059                 ret_val += qla8044_wr_reg_indirect(vha,
1060                     MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
1061                 if (ret_val == QLA_FUNCTION_FAILED) {
1062                         ql_log(ql_log_fatal, vha, 0xb0a2,
1063                             "%s: write to AGT_WRDATA failed!\n",
1064                             __func__);
1065                         goto exit_ms_mem_write_unlock;
1066                 }
1067
1068                 /* Check write status */
1069                 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1070                     MIU_TA_CTL_WRITE_ENABLE);
1071                 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1072                     MIU_TA_CTL_WRITE_START);
1073                 if (ret_val == QLA_FUNCTION_FAILED) {
1074                         ql_log(ql_log_fatal, vha, 0xb0a3,
1075                             "%s: write to AGT_CTRL failed!\n", __func__);
1076                         goto exit_ms_mem_write_unlock;
1077                 }
1078
1079                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1080                         ret_val = qla8044_rd_reg_indirect(vha,
1081                             MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
1082                         if (ret_val == QLA_FUNCTION_FAILED) {
1083                                 ql_log(ql_log_fatal, vha, 0xb0a4,
1084                                     "%s: failed to read "
1085                                     "MD_MIU_TEST_AGT_CTRL!\n", __func__);
1086                                 goto exit_ms_mem_write_unlock;
1087                         }
1088                         if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1089                                 break;
1090                 }
1091
1092                 /* Status check failed */
1093                 if (j >= MAX_CTL_CHECK) {
1094                         ql_log(ql_log_fatal, vha, 0xb0a5,
1095                             "%s: MS memory write failed!\n",
1096                            __func__);
1097                         ret_val = QLA_FUNCTION_FAILED;
1098                         goto exit_ms_mem_write_unlock;
1099                 }
1100         }
1101
1102 exit_ms_mem_write_unlock:
1103         write_unlock_irqrestore(&ha->hw_lock, flags);
1104
1105 exit_ms_mem_write:
1106         return ret_val;
1107 }
1108
1109 static int
1110 qla8044_copy_bootloader(struct scsi_qla_host *vha)
1111 {
1112         uint8_t *p_cache;
1113         uint32_t src, count, size;
1114         uint64_t dest;
1115         int ret_val = QLA_SUCCESS;
1116         struct qla_hw_data *ha = vha->hw;
1117
1118         src = QLA8044_BOOTLOADER_FLASH_ADDR;
1119         dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
1120         size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
1121
1122         /* 128 bit alignment check */
1123         if (size & 0xF)
1124                 size = (size + 16) & ~0xF;
1125
1126         /* 16 byte count */
1127         count = size/16;
1128
1129         p_cache = vmalloc(size);
1130         if (p_cache == NULL) {
1131                 ql_log(ql_log_fatal, vha, 0xb0a6,
1132                     "%s: Failed to allocate memory for "
1133                     "boot loader cache\n", __func__);
1134                 ret_val = QLA_FUNCTION_FAILED;
1135                 goto exit_copy_bootloader;
1136         }
1137
1138         ret_val = qla8044_lockless_flash_read_u32(vha, src,
1139             p_cache, size/sizeof(uint32_t));
1140         if (ret_val == QLA_FUNCTION_FAILED) {
1141                 ql_log(ql_log_fatal, vha, 0xb0a7,
1142                     "%s: Error reading F/W from flash!!!\n", __func__);
1143                 goto exit_copy_error;
1144         }
1145         ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
1146             __func__);
1147
1148         /* 128 bit/16 byte write to MS memory */
1149         ret_val = qla8044_ms_mem_write_128b(vha, dest,
1150             (uint32_t *)p_cache, count);
1151         if (ret_val == QLA_FUNCTION_FAILED) {
1152                 ql_log(ql_log_fatal, vha, 0xb0a9,
1153                     "%s: Error writing F/W to MS !!!\n", __func__);
1154                 goto exit_copy_error;
1155         }
1156         ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
1157             "%s: Wrote F/W (size %d) to MS !!!\n",
1158             __func__, size);
1159
1160 exit_copy_error:
1161         vfree(p_cache);
1162
1163 exit_copy_bootloader:
1164         return ret_val;
1165 }
1166
1167 static int
1168 qla8044_restart(struct scsi_qla_host *vha)
1169 {
1170         int ret_val = QLA_SUCCESS;
1171         struct qla_hw_data *ha = vha->hw;
1172
1173         qla8044_process_stop_seq(vha);
1174
1175         /* Collect minidump */
1176         if (ql2xmdenable)
1177                 qla8044_get_minidump(vha);
1178         else
1179                 ql_log(ql_log_fatal, vha, 0xb14c,
1180                     "Minidump disabled.\n");
1181
1182         qla8044_process_init_seq(vha);
1183
1184         if (qla8044_copy_bootloader(vha)) {
1185                 ql_log(ql_log_fatal, vha, 0xb0ab,
1186                     "%s: Copy bootloader, firmware restart failed!\n",
1187                     __func__);
1188                 ret_val = QLA_FUNCTION_FAILED;
1189                 goto exit_restart;
1190         }
1191
1192         /*
1193          *  Loads F/W from flash
1194          */
1195         qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
1196
1197         qla8044_process_start_seq(vha);
1198
1199 exit_restart:
1200         return ret_val;
1201 }
1202
1203 /*
1204  * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1205  * initialized.
1206  *
1207  * @ha : Pointer to adapter structure
1208  *
1209  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1210  */
1211 static int
1212 qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
1213 {
1214         uint32_t val, ret_val = QLA_FUNCTION_FAILED;
1215         int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
1216         struct qla_hw_data *ha = vha->hw;
1217
1218         do {
1219                 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
1220                 if (val == PHAN_INITIALIZE_COMPLETE) {
1221                         ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
1222                             "%s: Command Peg initialization "
1223                             "complete! state=0x%x\n", __func__, val);
1224                         ret_val = QLA_SUCCESS;
1225                         break;
1226                 }
1227                 msleep(CRB_CMDPEG_CHECK_DELAY);
1228         } while (--retries);
1229
1230         return ret_val;
1231 }
1232
1233 static int
1234 qla8044_start_firmware(struct scsi_qla_host *vha)
1235 {
1236         int ret_val = QLA_SUCCESS;
1237
1238         if (qla8044_restart(vha)) {
1239                 ql_log(ql_log_fatal, vha, 0xb0ad,
1240                     "%s: Restart Error!!!, Need Reset!!!\n",
1241                     __func__);
1242                 ret_val = QLA_FUNCTION_FAILED;
1243                 goto exit_start_fw;
1244         } else
1245                 ql_dbg(ql_dbg_p3p, vha, 0xb0af,
1246                     "%s: Restart done!\n", __func__);
1247
1248         ret_val = qla8044_check_cmd_peg_status(vha);
1249         if (ret_val) {
1250                 ql_log(ql_log_fatal, vha, 0xb0b0,
1251                     "%s: Peg not initialized!\n", __func__);
1252                 ret_val = QLA_FUNCTION_FAILED;
1253         }
1254
1255 exit_start_fw:
1256         return ret_val;
1257 }
1258
1259 void
1260 qla8044_clear_drv_active(struct qla_hw_data *ha)
1261 {
1262         uint32_t drv_active;
1263         struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
1264
1265         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1266         drv_active &= ~(1 << (ha->portnum));
1267
1268         ql_log(ql_log_info, vha, 0xb0b1,
1269             "%s(%ld): drv_active: 0x%08x\n",
1270             __func__, vha->host_no, drv_active);
1271
1272         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1273 }
1274
1275 /*
1276  * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1277  * @ha: pointer to adapter structure
1278  *
1279  * Note: IDC lock must be held upon entry
1280  **/
1281 static int
1282 qla8044_device_bootstrap(struct scsi_qla_host *vha)
1283 {
1284         int rval = QLA_FUNCTION_FAILED;
1285         int i;
1286         uint32_t old_count = 0, count = 0;
1287         int need_reset = 0;
1288         uint32_t idc_ctrl;
1289         struct qla_hw_data *ha = vha->hw;
1290
1291         need_reset = qla8044_need_reset(vha);
1292
1293         if (!need_reset) {
1294                 old_count = qla8044_rd_direct(vha,
1295                     QLA8044_PEG_ALIVE_COUNTER_INDEX);
1296
1297                 for (i = 0; i < 10; i++) {
1298                         msleep(200);
1299
1300                         count = qla8044_rd_direct(vha,
1301                             QLA8044_PEG_ALIVE_COUNTER_INDEX);
1302                         if (count != old_count) {
1303                                 rval = QLA_SUCCESS;
1304                                 goto dev_ready;
1305                         }
1306                 }
1307                 qla8044_flash_lock_recovery(vha);
1308         } else {
1309                 /* We are trying to perform a recovery here. */
1310                 if (ha->flags.isp82xx_fw_hung)
1311                         qla8044_flash_lock_recovery(vha);
1312         }
1313
1314         /* set to DEV_INITIALIZING */
1315         ql_log(ql_log_info, vha, 0xb0b2,
1316             "%s: HW State: INITIALIZING\n", __func__);
1317         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1318             QLA8XXX_DEV_INITIALIZING);
1319
1320         qla8044_idc_unlock(ha);
1321         rval = qla8044_start_firmware(vha);
1322         qla8044_idc_lock(ha);
1323
1324         if (rval != QLA_SUCCESS) {
1325                 ql_log(ql_log_info, vha, 0xb0b3,
1326                      "%s: HW State: FAILED\n", __func__);
1327                 qla8044_clear_drv_active(ha);
1328                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1329                     QLA8XXX_DEV_FAILED);
1330                 return rval;
1331         }
1332
1333         /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
1334          * device goes to INIT state. */
1335         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1336         if (idc_ctrl & GRACEFUL_RESET_BIT1) {
1337                 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
1338                     (idc_ctrl & ~GRACEFUL_RESET_BIT1));
1339                 ha->fw_dumped = 0;
1340         }
1341
1342 dev_ready:
1343         ql_log(ql_log_info, vha, 0xb0b4,
1344             "%s: HW State: READY\n", __func__);
1345         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
1346
1347         return rval;
1348 }
1349
1350 /*-------------------------Reset Sequence Functions-----------------------*/
1351 static void
1352 qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
1353 {
1354         u8 *phdr;
1355
1356         if (!vha->reset_tmplt.buff) {
1357                 ql_log(ql_log_fatal, vha, 0xb0b5,
1358                     "%s: Error Invalid reset_seq_template\n", __func__);
1359                 return;
1360         }
1361
1362         phdr = vha->reset_tmplt.buff;
1363         ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
1364             "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
1365             "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
1366             "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
1367             *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
1368             *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
1369             *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
1370             *(phdr+13), *(phdr+14), *(phdr+15));
1371 }
1372
1373 /*
1374  * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1375  *
1376  * @ha : Pointer to adapter structure
1377  *
1378  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1379  */
1380 static int
1381 qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
1382 {
1383         uint32_t sum =  0;
1384         uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
1385         int u16_count =  vha->reset_tmplt.hdr->size / sizeof(uint16_t);
1386
1387         while (u16_count-- > 0)
1388                 sum += *buff++;
1389
1390         while (sum >> 16)
1391                 sum = (sum & 0xFFFF) +  (sum >> 16);
1392
1393         /* checksum of 0 indicates a valid template */
1394         if (~sum) {
1395                 return QLA_SUCCESS;
1396         } else {
1397                 ql_log(ql_log_fatal, vha, 0xb0b7,
1398                     "%s: Reset seq checksum failed\n", __func__);
1399                 return QLA_FUNCTION_FAILED;
1400         }
1401 }
1402
1403 /*
1404  * qla8044_read_reset_template - Read Reset Template from Flash, validate
1405  * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1406  *
1407  * @ha : Pointer to adapter structure
1408  */
1409 void
1410 qla8044_read_reset_template(struct scsi_qla_host *vha)
1411 {
1412         uint8_t *p_buff;
1413         uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
1414
1415         vha->reset_tmplt.seq_error = 0;
1416         vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
1417         if (vha->reset_tmplt.buff == NULL) {
1418                 ql_log(ql_log_fatal, vha, 0xb0b8,
1419                     "%s: Failed to allocate reset template resources\n",
1420                     __func__);
1421                 goto exit_read_reset_template;
1422         }
1423
1424         p_buff = vha->reset_tmplt.buff;
1425         addr = QLA8044_RESET_TEMPLATE_ADDR;
1426
1427         tmplt_hdr_def_size =
1428             sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
1429
1430         ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
1431             "%s: Read template hdr size %d from Flash\n",
1432             __func__, tmplt_hdr_def_size);
1433
1434         /* Copy template header from flash */
1435         if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1436                 ql_log(ql_log_fatal, vha, 0xb0ba,
1437                     "%s: Failed to read reset template\n", __func__);
1438                 goto exit_read_template_error;
1439         }
1440
1441         vha->reset_tmplt.hdr =
1442          (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
1443
1444         /* Validate the template header size and signature */
1445         tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
1446         if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
1447             (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
1448                 ql_log(ql_log_fatal, vha, 0xb0bb,
1449                     "%s: Template Header size invalid %d "
1450                     "tmplt_hdr_def_size %d!!!\n", __func__,
1451                     tmplt_hdr_size, tmplt_hdr_def_size);
1452                 goto exit_read_template_error;
1453         }
1454
1455         addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1456         p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
1457         tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
1458             vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
1459
1460         ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
1461             "%s: Read rest of the template size %d\n",
1462             __func__, vha->reset_tmplt.hdr->size);
1463
1464         /* Copy rest of the template */
1465         if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1466                 ql_log(ql_log_fatal, vha, 0xb0bd,
1467                     "%s: Failed to read reset tempelate\n", __func__);
1468                 goto exit_read_template_error;
1469         }
1470
1471         /* Integrity check */
1472         if (qla8044_reset_seq_checksum_test(vha)) {
1473                 ql_log(ql_log_fatal, vha, 0xb0be,
1474                     "%s: Reset Seq checksum failed!\n", __func__);
1475                 goto exit_read_template_error;
1476         }
1477
1478         ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
1479             "%s: Reset Seq checksum passed! Get stop, "
1480             "start and init seq offsets\n", __func__);
1481
1482         /* Get STOP, START, INIT sequence offsets */
1483         vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
1484             vha->reset_tmplt.hdr->init_seq_offset;
1485
1486         vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
1487             vha->reset_tmplt.hdr->start_seq_offset;
1488
1489         vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
1490             vha->reset_tmplt.hdr->hdr_size;
1491
1492         qla8044_dump_reset_seq_hdr(vha);
1493
1494         goto exit_read_reset_template;
1495
1496 exit_read_template_error:
1497         vfree(vha->reset_tmplt.buff);
1498
1499 exit_read_reset_template:
1500         return;
1501 }
1502
1503 void
1504 qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
1505 {
1506         uint32_t idc_ctrl;
1507         struct qla_hw_data *ha = vha->hw;
1508
1509         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1510         idc_ctrl |= DONTRESET_BIT0;
1511         ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
1512             "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
1513         qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1514 }
1515
1516 inline void
1517 qla8044_set_rst_ready(struct scsi_qla_host *vha)
1518 {
1519         uint32_t drv_state;
1520         struct qla_hw_data *ha = vha->hw;
1521
1522         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1523
1524         /* For ISP8044, drv_active register has 1 bit per function,
1525          * shift 1 by func_num to set a bit for the function.*/
1526         drv_state |= (1 << ha->portnum);
1527
1528         ql_log(ql_log_info, vha, 0xb0c1,
1529             "%s(%ld): drv_state: 0x%08x\n",
1530             __func__, vha->host_no, drv_state);
1531         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
1532 }
1533
1534 /**
1535  * qla8044_need_reset_handler - Code to start reset sequence
1536  * @ha: pointer to adapter structure
1537  *
1538  * Note: IDC lock must be held upon entry
1539  **/
1540 static void
1541 qla8044_need_reset_handler(struct scsi_qla_host *vha)
1542 {
1543         uint32_t dev_state = 0, drv_state, drv_active;
1544         unsigned long reset_timeout, dev_init_timeout;
1545         struct qla_hw_data *ha = vha->hw;
1546
1547         ql_log(ql_log_fatal, vha, 0xb0c2,
1548             "%s: Performing ISP error recovery\n", __func__);
1549
1550         if (vha->flags.online) {
1551                 qla8044_idc_unlock(ha);
1552                 qla2x00_abort_isp_cleanup(vha);
1553                 ha->isp_ops->get_flash_version(vha, vha->req->ring);
1554                 ha->isp_ops->nvram_config(vha);
1555                 qla8044_idc_lock(ha);
1556         }
1557
1558         drv_state = qla8044_rd_direct(vha,
1559             QLA8044_CRB_DRV_STATE_INDEX);
1560         drv_active = qla8044_rd_direct(vha,
1561             QLA8044_CRB_DRV_ACTIVE_INDEX);
1562
1563         ql_log(ql_log_info, vha, 0xb0c5,
1564             "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1565             __func__, vha->host_no, drv_state, drv_active);
1566
1567         if (!ha->flags.nic_core_reset_owner) {
1568                 ql_dbg(ql_dbg_p3p, vha, 0xb0c3,
1569                     "%s(%ld): reset acknowledged\n",
1570                     __func__, vha->host_no);
1571                 qla8044_set_rst_ready(vha);
1572
1573                 /* Non-reset owners ACK Reset and wait for device INIT state
1574                  * as part of Reset Recovery by Reset Owner
1575                  */
1576                 dev_init_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1577
1578                 do {
1579                         if (time_after_eq(jiffies, dev_init_timeout)) {
1580                                 ql_log(ql_log_info, vha, 0xb0c4,
1581                                     "%s: Non Reset owner DEV INIT "
1582                                     "TIMEOUT!\n", __func__);
1583                                 break;
1584                         }
1585
1586                         qla8044_idc_unlock(ha);
1587                         msleep(1000);
1588                         qla8044_idc_lock(ha);
1589
1590                         dev_state = qla8044_rd_direct(vha,
1591                                         QLA8044_CRB_DEV_STATE_INDEX);
1592                 } while (((drv_state & drv_active) != drv_active) &&
1593                     (dev_state == QLA8XXX_DEV_NEED_RESET));
1594         } else {
1595                 qla8044_set_rst_ready(vha);
1596
1597                 /* wait for 10 seconds for reset ack from all functions */
1598                 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1599
1600                 while ((drv_state & drv_active) != drv_active) {
1601                         if (time_after_eq(jiffies, reset_timeout)) {
1602                                 ql_log(ql_log_info, vha, 0xb0c6,
1603                                     "%s: RESET TIMEOUT!"
1604                                     "drv_state: 0x%08x, drv_active: 0x%08x\n",
1605                                     QLA2XXX_DRIVER_NAME, drv_state, drv_active);
1606                                 break;
1607                         }
1608
1609                         qla8044_idc_unlock(ha);
1610                         msleep(1000);
1611                         qla8044_idc_lock(ha);
1612
1613                         drv_state = qla8044_rd_direct(vha,
1614                             QLA8044_CRB_DRV_STATE_INDEX);
1615                         drv_active = qla8044_rd_direct(vha,
1616                             QLA8044_CRB_DRV_ACTIVE_INDEX);
1617                 }
1618
1619                 if (drv_state != drv_active) {
1620                         ql_log(ql_log_info, vha, 0xb0c7,
1621                             "%s(%ld): Reset_owner turning off drv_active "
1622                             "of non-acking function 0x%x\n", __func__,
1623                             vha->host_no, (drv_active ^ drv_state));
1624                         drv_active = drv_active & drv_state;
1625                         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
1626                             drv_active);
1627                 }
1628
1629                 /*
1630                 * Clear RESET OWNER, will be set at next reset
1631                 * by next RST_OWNER
1632                 */
1633                 ha->flags.nic_core_reset_owner = 0;
1634
1635                 /* Start Reset Recovery */
1636                 qla8044_device_bootstrap(vha);
1637         }
1638 }
1639
1640 static void
1641 qla8044_set_drv_active(struct scsi_qla_host *vha)
1642 {
1643         uint32_t drv_active;
1644         struct qla_hw_data *ha = vha->hw;
1645
1646         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1647
1648         /* For ISP8044, drv_active register has 1 bit per function,
1649          * shift 1 by func_num to set a bit for the function.*/
1650         drv_active |= (1 << ha->portnum);
1651
1652         ql_log(ql_log_info, vha, 0xb0c8,
1653             "%s(%ld): drv_active: 0x%08x\n",
1654             __func__, vha->host_no, drv_active);
1655         qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1656 }
1657
1658 static void
1659 qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
1660 {
1661         uint32_t idc_ctrl;
1662         struct qla_hw_data *ha = vha->hw;
1663
1664         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1665         idc_ctrl &= ~DONTRESET_BIT0;
1666         ql_log(ql_log_info, vha, 0xb0c9,
1667             "%s: idc_ctrl = %d\n", __func__,
1668             idc_ctrl);
1669         qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1670 }
1671
1672 static int
1673 qla8044_set_idc_ver(struct scsi_qla_host *vha)
1674 {
1675         int idc_ver;
1676         uint32_t drv_active;
1677         int rval = QLA_SUCCESS;
1678         struct qla_hw_data *ha = vha->hw;
1679
1680         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1681         if (drv_active == (1 << ha->portnum)) {
1682                 idc_ver = qla8044_rd_direct(vha,
1683                     QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1684                 idc_ver &= (~0xFF);
1685                 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
1686                 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
1687                     idc_ver);
1688                 ql_log(ql_log_info, vha, 0xb0ca,
1689                     "%s: IDC version updated to %d\n",
1690                     __func__, idc_ver);
1691         } else {
1692                 idc_ver = qla8044_rd_direct(vha,
1693                     QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1694                 idc_ver &= 0xFF;
1695                 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
1696                         ql_log(ql_log_info, vha, 0xb0cb,
1697                             "%s: qla4xxx driver IDC version %d "
1698                             "is not compatible with IDC version %d "
1699                             "of other drivers!\n",
1700                             __func__, QLA8044_IDC_VER_MAJ_VALUE,
1701                             idc_ver);
1702                         rval = QLA_FUNCTION_FAILED;
1703                         goto exit_set_idc_ver;
1704                 }
1705         }
1706
1707         /* Update IDC_MINOR_VERSION */
1708         idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
1709         idc_ver &= ~(0x03 << (ha->portnum * 2));
1710         idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
1711         qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
1712
1713 exit_set_idc_ver:
1714         return rval;
1715 }
1716
1717 static int
1718 qla8044_update_idc_reg(struct scsi_qla_host *vha)
1719 {
1720         uint32_t drv_active;
1721         int rval = QLA_SUCCESS;
1722         struct qla_hw_data *ha = vha->hw;
1723
1724         if (vha->flags.init_done)
1725                 goto exit_update_idc_reg;
1726
1727         qla8044_idc_lock(ha);
1728         qla8044_set_drv_active(vha);
1729
1730         drv_active = qla8044_rd_direct(vha,
1731             QLA8044_CRB_DRV_ACTIVE_INDEX);
1732
1733         /* If we are the first driver to load and
1734          * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
1735         if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
1736                 qla8044_clear_idc_dontreset(vha);
1737
1738         rval = qla8044_set_idc_ver(vha);
1739         if (rval == QLA_FUNCTION_FAILED)
1740                 qla8044_clear_drv_active(ha);
1741         qla8044_idc_unlock(ha);
1742
1743 exit_update_idc_reg:
1744         return rval;
1745 }
1746
1747 /**
1748  * qla8044_need_qsnt_handler - Code to start qsnt
1749  * @ha: pointer to adapter structure
1750  **/
1751 static void
1752 qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
1753 {
1754         unsigned long qsnt_timeout;
1755         uint32_t drv_state, drv_active, dev_state;
1756         struct qla_hw_data *ha = vha->hw;
1757
1758         if (vha->flags.online)
1759                 qla2x00_quiesce_io(vha);
1760         else
1761                 return;
1762
1763         qla8044_set_qsnt_ready(vha);
1764
1765         /* Wait for 30 secs for all functions to ack qsnt mode */
1766         qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
1767         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1768         drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1769
1770         /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
1771            position is at bit 1 and drv active is at bit 0 */
1772         drv_active = drv_active << 1;
1773
1774         while (drv_state != drv_active) {
1775                 if (time_after_eq(jiffies, qsnt_timeout)) {
1776                         /* Other functions did not ack, changing state to
1777                          * DEV_READY
1778                          */
1779                         clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1780                         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1781                                             QLA8XXX_DEV_READY);
1782                         qla8044_clear_qsnt_ready(vha);
1783                         ql_log(ql_log_info, vha, 0xb0cc,
1784                             "Timeout waiting for quiescent ack!!!\n");
1785                         return;
1786                 }
1787                 qla8044_idc_unlock(ha);
1788                 msleep(1000);
1789                 qla8044_idc_lock(ha);
1790
1791                 drv_state = qla8044_rd_direct(vha,
1792                     QLA8044_CRB_DRV_STATE_INDEX);
1793                 drv_active = qla8044_rd_direct(vha,
1794                     QLA8044_CRB_DRV_ACTIVE_INDEX);
1795                 drv_active = drv_active << 1;
1796         }
1797
1798         /* All functions have Acked. Set quiescent state */
1799         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1800
1801         if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
1802                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1803                     QLA8XXX_DEV_QUIESCENT);
1804                 ql_log(ql_log_info, vha, 0xb0cd,
1805                     "%s: HW State: QUIESCENT\n", __func__);
1806         }
1807 }
1808
1809 /*
1810  * qla8044_device_state_handler - Adapter state machine
1811  * @ha: pointer to host adapter structure.
1812  *
1813  * Note: IDC lock must be UNLOCKED upon entry
1814  **/
1815 int
1816 qla8044_device_state_handler(struct scsi_qla_host *vha)
1817 {
1818         uint32_t dev_state;
1819         int rval = QLA_SUCCESS;
1820         unsigned long dev_init_timeout;
1821         struct qla_hw_data *ha = vha->hw;
1822
1823         rval = qla8044_update_idc_reg(vha);
1824         if (rval == QLA_FUNCTION_FAILED)
1825                 goto exit_error;
1826
1827         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1828         ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
1829             "Device state is 0x%x = %s\n",
1830             dev_state, dev_state < MAX_STATES ?
1831             qdev_state(dev_state) : "Unknown");
1832
1833         /* wait for 30 seconds for device to go ready */
1834         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
1835
1836         qla8044_idc_lock(ha);
1837
1838         while (1) {
1839                 if (time_after_eq(jiffies, dev_init_timeout)) {
1840                         ql_log(ql_log_warn, vha, 0xb0cf,
1841                             "%s: Device Init Failed 0x%x = %s\n",
1842                             QLA2XXX_DRIVER_NAME, dev_state,
1843                             dev_state < MAX_STATES ?
1844                             qdev_state(dev_state) : "Unknown");
1845
1846                         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1847                             QLA8XXX_DEV_FAILED);
1848                 }
1849
1850                 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1851                 ql_log(ql_log_info, vha, 0xb0d0,
1852                     "Device state is 0x%x = %s\n",
1853                     dev_state, dev_state < MAX_STATES ?
1854                     qdev_state(dev_state) : "Unknown");
1855
1856                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1857                 switch (dev_state) {
1858                 case QLA8XXX_DEV_READY:
1859                         ha->flags.nic_core_reset_owner = 0;
1860                         goto exit;
1861                 case QLA8XXX_DEV_COLD:
1862                         rval = qla8044_device_bootstrap(vha);
1863                         break;
1864                 case QLA8XXX_DEV_INITIALIZING:
1865                         qla8044_idc_unlock(ha);
1866                         msleep(1000);
1867                         qla8044_idc_lock(ha);
1868                         break;
1869                 case QLA8XXX_DEV_NEED_RESET:
1870                         /* For ISP8044, if NEED_RESET is set by any driver,
1871                          * it should be honored, irrespective of IDC_CTRL
1872                          * DONTRESET_BIT0 */
1873                         qla8044_need_reset_handler(vha);
1874                         break;
1875                 case QLA8XXX_DEV_NEED_QUIESCENT:
1876                         /* idc locked/unlocked in handler */
1877                         qla8044_need_qsnt_handler(vha);
1878
1879                         /* Reset the init timeout after qsnt handler */
1880                         dev_init_timeout = jiffies +
1881                             (ha->fcoe_reset_timeout * HZ);
1882                         break;
1883                 case QLA8XXX_DEV_QUIESCENT:
1884                         ql_log(ql_log_info, vha, 0xb0d1,
1885                             "HW State: QUIESCENT\n");
1886
1887                         qla8044_idc_unlock(ha);
1888                         msleep(1000);
1889                         qla8044_idc_lock(ha);
1890
1891                         /* Reset the init timeout after qsnt handler */
1892                         dev_init_timeout = jiffies +
1893                             (ha->fcoe_reset_timeout * HZ);
1894                         break;
1895                 case QLA8XXX_DEV_FAILED:
1896                         ha->flags.nic_core_reset_owner = 0;
1897                         qla8044_idc_unlock(ha);
1898                         qla8xxx_dev_failed_handler(vha);
1899                         rval = QLA_FUNCTION_FAILED;
1900                         qla8044_idc_lock(ha);
1901                         goto exit;
1902                 default:
1903                         qla8044_idc_unlock(ha);
1904                         qla8xxx_dev_failed_handler(vha);
1905                         rval = QLA_FUNCTION_FAILED;
1906                         qla8044_idc_lock(ha);
1907                         goto exit;
1908                 }
1909         }
1910 exit:
1911         qla8044_idc_unlock(ha);
1912
1913 exit_error:
1914         return rval;
1915 }
1916
1917 /**
1918  * qla4_8xxx_check_temp - Check the ISP82XX temperature.
1919  * @ha: adapter block pointer.
1920  *
1921  * Note: The caller should not hold the idc lock.
1922  **/
1923 static int
1924 qla8044_check_temp(struct scsi_qla_host *vha)
1925 {
1926         uint32_t temp, temp_state, temp_val;
1927         int status = QLA_SUCCESS;
1928
1929         temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
1930         temp_state = qla82xx_get_temp_state(temp);
1931         temp_val = qla82xx_get_temp_val(temp);
1932
1933         if (temp_state == QLA82XX_TEMP_PANIC) {
1934                 ql_log(ql_log_warn, vha, 0xb0d2,
1935                     "Device temperature %d degrees C"
1936                     " exceeds maximum allowed. Hardware has been shut"
1937                     " down\n", temp_val);
1938                 status = QLA_FUNCTION_FAILED;
1939                 return status;
1940         } else if (temp_state == QLA82XX_TEMP_WARN) {
1941                 ql_log(ql_log_warn, vha, 0xb0d3,
1942                     "Device temperature %d"
1943                     " degrees C exceeds operating range."
1944                     " Immediate action needed.\n", temp_val);
1945         }
1946         return 0;
1947 }
1948
1949 int qla8044_read_temperature(scsi_qla_host_t *vha)
1950 {
1951         uint32_t temp;
1952
1953         temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
1954         return qla82xx_get_temp_val(temp);
1955 }
1956
1957 /**
1958  * qla8044_check_fw_alive  - Check firmware health
1959  * @ha: Pointer to host adapter structure.
1960  *
1961  * Context: Interrupt
1962  **/
1963 int
1964 qla8044_check_fw_alive(struct scsi_qla_host *vha)
1965 {
1966         uint32_t fw_heartbeat_counter;
1967         uint32_t halt_status1, halt_status2;
1968         int status = QLA_SUCCESS;
1969
1970         fw_heartbeat_counter = qla8044_rd_direct(vha,
1971             QLA8044_PEG_ALIVE_COUNTER_INDEX);
1972
1973         /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
1974         if (fw_heartbeat_counter == 0xffffffff) {
1975                 ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
1976                     "scsi%ld: %s: Device in frozen "
1977                     "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
1978                     vha->host_no, __func__);
1979                 return status;
1980         }
1981
1982         if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
1983                 vha->seconds_since_last_heartbeat++;
1984                 /* FW not alive after 2 seconds */
1985                 if (vha->seconds_since_last_heartbeat == 2) {
1986                         vha->seconds_since_last_heartbeat = 0;
1987                         halt_status1 = qla8044_rd_direct(vha,
1988                             QLA8044_PEG_HALT_STATUS1_INDEX);
1989                         halt_status2 = qla8044_rd_direct(vha,
1990                             QLA8044_PEG_HALT_STATUS2_INDEX);
1991
1992                         ql_log(ql_log_info, vha, 0xb0d5,
1993                             "scsi(%ld): %s, ISP8044 "
1994                             "Dumping hw/fw registers:\n"
1995                             " PEG_HALT_STATUS1: 0x%x, "
1996                             "PEG_HALT_STATUS2: 0x%x,\n",
1997                             vha->host_no, __func__, halt_status1,
1998                             halt_status2);
1999                         status = QLA_FUNCTION_FAILED;
2000                 }
2001         } else
2002                 vha->seconds_since_last_heartbeat = 0;
2003
2004         vha->fw_heartbeat_counter = fw_heartbeat_counter;
2005         return status;
2006 }
2007
2008 void
2009 qla8044_watchdog(struct scsi_qla_host *vha)
2010 {
2011         uint32_t dev_state, halt_status;
2012         int halt_status_unrecoverable = 0;
2013         struct qla_hw_data *ha = vha->hw;
2014
2015         /* don't poll if reset is going on or FW hang in quiescent state */
2016         if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
2017             test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
2018             test_bit(ISP_ABORT_RETRY, &vha->dpc_flags) ||
2019             test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
2020                 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
2021
2022                 if (qla8044_check_temp(vha)) {
2023                         set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
2024                         ha->flags.isp82xx_fw_hung = 1;
2025                         qla2xxx_wake_dpc(vha);
2026                 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
2027                            !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
2028                         ql_log(ql_log_info, vha, 0xb0d6,
2029                             "%s: HW State: NEED RESET!\n",
2030                             __func__);
2031                         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2032                         qla2xxx_wake_dpc(vha);
2033                 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
2034                     !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
2035                         ql_log(ql_log_info, vha, 0xb0d7,
2036                             "%s: HW State: NEED QUIES detected!\n",
2037                             __func__);
2038                         set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
2039                         qla2xxx_wake_dpc(vha);
2040                 } else  {
2041                         /* Check firmware health */
2042                         if (qla8044_check_fw_alive(vha)) {
2043                                 halt_status = qla8044_rd_direct(vha,
2044                                         QLA8044_PEG_HALT_STATUS1_INDEX);
2045                                 if (halt_status &
2046                                     QLA8044_HALT_STATUS_FW_RESET) {
2047                                         ql_log(ql_log_fatal, vha,
2048                                             0xb0d8, "%s: Firmware "
2049                                             "error detected device "
2050                                             "is being reset\n",
2051                                             __func__);
2052                                 } else if (halt_status &
2053                                             QLA8044_HALT_STATUS_UNRECOVERABLE) {
2054                                                 halt_status_unrecoverable = 1;
2055                                 }
2056
2057                                 /* Since we cannot change dev_state in interrupt
2058                                  * context, set appropriate DPC flag then wakeup
2059                                  *  DPC */
2060                                 if (halt_status_unrecoverable) {
2061                                         set_bit(ISP_UNRECOVERABLE,
2062                                             &vha->dpc_flags);
2063                                 } else {
2064                                         if (dev_state ==
2065                                             QLA8XXX_DEV_QUIESCENT) {
2066                                                 set_bit(FCOE_CTX_RESET_NEEDED,
2067                                                     &vha->dpc_flags);
2068                                                 ql_log(ql_log_info, vha, 0xb0d9,
2069                                                     "%s: FW CONTEXT Reset "
2070                                                     "needed!\n", __func__);
2071                                         } else {
2072                                                 ql_log(ql_log_info, vha,
2073                                                     0xb0da, "%s: "
2074                                                     "detect abort needed\n",
2075                                                     __func__);
2076                                                 set_bit(ISP_ABORT_NEEDED,
2077                                                     &vha->dpc_flags);
2078                                                 qla82xx_clear_pending_mbx(vha);
2079                                         }
2080                                 }
2081                                 ha->flags.isp82xx_fw_hung = 1;
2082                                 ql_log(ql_log_warn, vha, 0xb10a,
2083                                     "Firmware hung.\n");
2084                                 qla2xxx_wake_dpc(vha);
2085                         }
2086                 }
2087
2088         }
2089 }
2090
2091 static int
2092 qla8044_minidump_process_control(struct scsi_qla_host *vha,
2093                                  struct qla8044_minidump_entry_hdr *entry_hdr)
2094 {
2095         struct qla8044_minidump_entry_crb *crb_entry;
2096         uint32_t read_value, opcode, poll_time, addr, index;
2097         uint32_t crb_addr, rval = QLA_SUCCESS;
2098         unsigned long wtime;
2099         struct qla8044_minidump_template_hdr *tmplt_hdr;
2100         int i;
2101         struct qla_hw_data *ha = vha->hw;
2102
2103         ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
2104         tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2105                 ha->md_tmplt_hdr;
2106         crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
2107
2108         crb_addr = crb_entry->addr;
2109         for (i = 0; i < crb_entry->op_count; i++) {
2110                 opcode = crb_entry->crb_ctrl.opcode;
2111
2112                 if (opcode & QLA82XX_DBG_OPCODE_WR) {
2113                         qla8044_wr_reg_indirect(vha, crb_addr,
2114                             crb_entry->value_1);
2115                         opcode &= ~QLA82XX_DBG_OPCODE_WR;
2116                 }
2117
2118                 if (opcode & QLA82XX_DBG_OPCODE_RW) {
2119                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2120                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2121                         opcode &= ~QLA82XX_DBG_OPCODE_RW;
2122                 }
2123
2124                 if (opcode & QLA82XX_DBG_OPCODE_AND) {
2125                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2126                         read_value &= crb_entry->value_2;
2127                         opcode &= ~QLA82XX_DBG_OPCODE_AND;
2128                         if (opcode & QLA82XX_DBG_OPCODE_OR) {
2129                                 read_value |= crb_entry->value_3;
2130                                 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2131                         }
2132                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2133                 }
2134                 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2135                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2136                         read_value |= crb_entry->value_3;
2137                         qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2138                         opcode &= ~QLA82XX_DBG_OPCODE_OR;
2139                 }
2140                 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
2141                         poll_time = crb_entry->crb_strd.poll_timeout;
2142                         wtime = jiffies + poll_time;
2143                         qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2144
2145                         do {
2146                                 if ((read_value & crb_entry->value_2) ==
2147                                     crb_entry->value_1) {
2148                                         break;
2149                                 } else if (time_after_eq(jiffies, wtime)) {
2150                                         /* capturing dump failed */
2151                                         rval = QLA_FUNCTION_FAILED;
2152                                         break;
2153                                 } else {
2154                                         qla8044_rd_reg_indirect(vha,
2155                                             crb_addr, &read_value);
2156                                 }
2157                         } while (1);
2158                         opcode &= ~QLA82XX_DBG_OPCODE_POLL;
2159                 }
2160
2161                 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
2162                         if (crb_entry->crb_strd.state_index_a) {
2163                                 index = crb_entry->crb_strd.state_index_a;
2164                                 addr = tmplt_hdr->saved_state_array[index];
2165                         } else {
2166                                 addr = crb_addr;
2167                         }
2168
2169                         qla8044_rd_reg_indirect(vha, addr, &read_value);
2170                         index = crb_entry->crb_ctrl.state_index_v;
2171                         tmplt_hdr->saved_state_array[index] = read_value;
2172                         opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
2173                 }
2174
2175                 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
2176                         if (crb_entry->crb_strd.state_index_a) {
2177                                 index = crb_entry->crb_strd.state_index_a;
2178                                 addr = tmplt_hdr->saved_state_array[index];
2179                         } else {
2180                                 addr = crb_addr;
2181                         }
2182
2183                         if (crb_entry->crb_ctrl.state_index_v) {
2184                                 index = crb_entry->crb_ctrl.state_index_v;
2185                                 read_value =
2186                                     tmplt_hdr->saved_state_array[index];
2187                         } else {
2188                                 read_value = crb_entry->value_1;
2189                         }
2190
2191                         qla8044_wr_reg_indirect(vha, addr, read_value);
2192                         opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
2193                 }
2194
2195                 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
2196                         index = crb_entry->crb_ctrl.state_index_v;
2197                         read_value = tmplt_hdr->saved_state_array[index];
2198                         read_value <<= crb_entry->crb_ctrl.shl;
2199                         read_value >>= crb_entry->crb_ctrl.shr;
2200                         if (crb_entry->value_2)
2201                                 read_value &= crb_entry->value_2;
2202                         read_value |= crb_entry->value_3;
2203                         read_value += crb_entry->value_1;
2204                         tmplt_hdr->saved_state_array[index] = read_value;
2205                         opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
2206                 }
2207                 crb_addr += crb_entry->crb_strd.addr_stride;
2208         }
2209         return rval;
2210 }
2211
2212 static void
2213 qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
2214         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2215 {
2216         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2217         struct qla8044_minidump_entry_crb *crb_hdr;
2218         uint32_t *data_ptr = *d_ptr;
2219
2220         ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
2221         crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
2222         r_addr = crb_hdr->addr;
2223         r_stride = crb_hdr->crb_strd.addr_stride;
2224         loop_cnt = crb_hdr->op_count;
2225
2226         for (i = 0; i < loop_cnt; i++) {
2227                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2228                 *data_ptr++ = r_addr;
2229                 *data_ptr++ = r_value;
2230                 r_addr += r_stride;
2231         }
2232         *d_ptr = data_ptr;
2233 }
2234
2235 static int
2236 qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
2237         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2238 {
2239         uint32_t r_addr, r_value, r_data;
2240         uint32_t i, j, loop_cnt;
2241         struct qla8044_minidump_entry_rdmem *m_hdr;
2242         unsigned long flags;
2243         uint32_t *data_ptr = *d_ptr;
2244         struct qla_hw_data *ha = vha->hw;
2245
2246         ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
2247         m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
2248         r_addr = m_hdr->read_addr;
2249         loop_cnt = m_hdr->read_data_size/16;
2250
2251         ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
2252             "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2253             __func__, r_addr, m_hdr->read_data_size);
2254
2255         if (r_addr & 0xf) {
2256                 ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
2257                     "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2258                     __func__, r_addr);
2259                 return QLA_FUNCTION_FAILED;
2260         }
2261
2262         if (m_hdr->read_data_size % 16) {
2263                 ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
2264                     "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2265                     __func__, m_hdr->read_data_size);
2266                 return QLA_FUNCTION_FAILED;
2267         }
2268
2269         ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
2270             "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2271             __func__, r_addr, m_hdr->read_data_size, loop_cnt);
2272
2273         write_lock_irqsave(&ha->hw_lock, flags);
2274         for (i = 0; i < loop_cnt; i++) {
2275                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
2276                 r_value = 0;
2277                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
2278                 r_value = MIU_TA_CTL_ENABLE;
2279                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2280                 r_value = MIU_TA_CTL_START_ENABLE;
2281                 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2282
2283                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2284                         qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
2285                             &r_value);
2286                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2287                                 break;
2288                 }
2289
2290                 if (j >= MAX_CTL_CHECK) {
2291                         printk_ratelimited(KERN_ERR
2292                             "%s: failed to read through agent\n", __func__);
2293                         write_unlock_irqrestore(&ha->hw_lock, flags);
2294                         return QLA_SUCCESS;
2295                 }
2296
2297                 for (j = 0; j < 4; j++) {
2298                         qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
2299                             &r_data);
2300                         *data_ptr++ = r_data;
2301                 }
2302
2303                 r_addr += 16;
2304         }
2305         write_unlock_irqrestore(&ha->hw_lock, flags);
2306
2307         ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
2308             "Leaving fn: %s datacount: 0x%x\n",
2309              __func__, (loop_cnt * 16));
2310
2311         *d_ptr = data_ptr;
2312         return QLA_SUCCESS;
2313 }
2314
2315 /* ISP83xx flash read for _RDROM _BOARD */
2316 static uint32_t
2317 qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
2318         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2319 {
2320         uint32_t fl_addr, u32_count, rval;
2321         struct qla8044_minidump_entry_rdrom *rom_hdr;
2322         uint32_t *data_ptr = *d_ptr;
2323
2324         rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
2325         fl_addr = rom_hdr->read_addr;
2326         u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
2327
2328         ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2329             __func__, fl_addr, u32_count);
2330
2331         rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
2332             (u8 *)(data_ptr), u32_count);
2333
2334         if (rval != QLA_SUCCESS) {
2335                 ql_log(ql_log_fatal, vha, 0xb0f6,
2336                     "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
2337                 return QLA_FUNCTION_FAILED;
2338         } else {
2339                 data_ptr += u32_count;
2340                 *d_ptr = data_ptr;
2341                 return QLA_SUCCESS;
2342         }
2343 }
2344
2345 static void
2346 qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
2347         struct qla8044_minidump_entry_hdr *entry_hdr, int index)
2348 {
2349         entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2350
2351         ql_log(ql_log_info, vha, 0xb0f7,
2352             "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2353             vha->host_no, index, entry_hdr->entry_type,
2354             entry_hdr->d_ctrl.entry_capture_mask);
2355 }
2356
2357 static int
2358 qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
2359         struct qla8044_minidump_entry_hdr *entry_hdr,
2360                                  uint32_t **d_ptr)
2361 {
2362         uint32_t addr, r_addr, c_addr, t_r_addr;
2363         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2364         unsigned long p_wait, w_time, p_mask;
2365         uint32_t c_value_w, c_value_r;
2366         struct qla8044_minidump_entry_cache *cache_hdr;
2367         int rval = QLA_FUNCTION_FAILED;
2368         uint32_t *data_ptr = *d_ptr;
2369
2370         ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
2371         cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2372
2373         loop_count = cache_hdr->op_count;
2374         r_addr = cache_hdr->read_addr;
2375         c_addr = cache_hdr->control_addr;
2376         c_value_w = cache_hdr->cache_ctrl.write_value;
2377
2378         t_r_addr = cache_hdr->tag_reg_addr;
2379         t_value = cache_hdr->addr_ctrl.init_tag_value;
2380         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2381         p_wait = cache_hdr->cache_ctrl.poll_wait;
2382         p_mask = cache_hdr->cache_ctrl.poll_mask;
2383
2384         for (i = 0; i < loop_count; i++) {
2385                 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2386                 if (c_value_w)
2387                         qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2388
2389                 if (p_mask) {
2390                         w_time = jiffies + p_wait;
2391                         do {
2392                                 qla8044_rd_reg_indirect(vha, c_addr,
2393                                     &c_value_r);
2394                                 if ((c_value_r & p_mask) == 0) {
2395                                         break;
2396                                 } else if (time_after_eq(jiffies, w_time)) {
2397                                         /* capturing dump failed */
2398                                         return rval;
2399                                 }
2400                         } while (1);
2401                 }
2402
2403                 addr = r_addr;
2404                 for (k = 0; k < r_cnt; k++) {
2405                         qla8044_rd_reg_indirect(vha, addr, &r_value);
2406                         *data_ptr++ = r_value;
2407                         addr += cache_hdr->read_ctrl.read_addr_stride;
2408                 }
2409                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2410         }
2411         *d_ptr = data_ptr;
2412         return QLA_SUCCESS;
2413 }
2414
2415 static void
2416 qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
2417         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2418 {
2419         uint32_t addr, r_addr, c_addr, t_r_addr;
2420         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2421         uint32_t c_value_w;
2422         struct qla8044_minidump_entry_cache *cache_hdr;
2423         uint32_t *data_ptr = *d_ptr;
2424
2425         cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2426         loop_count = cache_hdr->op_count;
2427         r_addr = cache_hdr->read_addr;
2428         c_addr = cache_hdr->control_addr;
2429         c_value_w = cache_hdr->cache_ctrl.write_value;
2430
2431         t_r_addr = cache_hdr->tag_reg_addr;
2432         t_value = cache_hdr->addr_ctrl.init_tag_value;
2433         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2434
2435         for (i = 0; i < loop_count; i++) {
2436                 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2437                 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2438                 addr = r_addr;
2439                 for (k = 0; k < r_cnt; k++) {
2440                         qla8044_rd_reg_indirect(vha, addr, &r_value);
2441                         *data_ptr++ = r_value;
2442                         addr += cache_hdr->read_ctrl.read_addr_stride;
2443                 }
2444                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2445         }
2446         *d_ptr = data_ptr;
2447 }
2448
2449 static void
2450 qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
2451         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2452 {
2453         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2454         struct qla8044_minidump_entry_rdocm *ocm_hdr;
2455         uint32_t *data_ptr = *d_ptr;
2456         struct qla_hw_data *ha = vha->hw;
2457
2458         ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
2459
2460         ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
2461         r_addr = ocm_hdr->read_addr;
2462         r_stride = ocm_hdr->read_addr_stride;
2463         loop_cnt = ocm_hdr->op_count;
2464
2465         ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
2466             "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2467             __func__, r_addr, r_stride, loop_cnt);
2468
2469         for (i = 0; i < loop_cnt; i++) {
2470                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2471                 *data_ptr++ = r_value;
2472                 r_addr += r_stride;
2473         }
2474         ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2475             __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
2476
2477         *d_ptr = data_ptr;
2478 }
2479
2480 static void
2481 qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
2482         struct qla8044_minidump_entry_hdr *entry_hdr,
2483         uint32_t **d_ptr)
2484 {
2485         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2486         struct qla8044_minidump_entry_mux *mux_hdr;
2487         uint32_t *data_ptr = *d_ptr;
2488
2489         ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
2490
2491         mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
2492         r_addr = mux_hdr->read_addr;
2493         s_addr = mux_hdr->select_addr;
2494         s_stride = mux_hdr->select_value_stride;
2495         s_value = mux_hdr->select_value;
2496         loop_cnt = mux_hdr->op_count;
2497
2498         for (i = 0; i < loop_cnt; i++) {
2499                 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2500                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2501                 *data_ptr++ = s_value;
2502                 *data_ptr++ = r_value;
2503                 s_value += s_stride;
2504         }
2505         *d_ptr = data_ptr;
2506 }
2507
2508 static void
2509 qla8044_minidump_process_queue(struct scsi_qla_host *vha,
2510         struct qla8044_minidump_entry_hdr *entry_hdr,
2511         uint32_t **d_ptr)
2512 {
2513         uint32_t s_addr, r_addr;
2514         uint32_t r_stride, r_value, r_cnt, qid = 0;
2515         uint32_t i, k, loop_cnt;
2516         struct qla8044_minidump_entry_queue *q_hdr;
2517         uint32_t *data_ptr = *d_ptr;
2518
2519         ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
2520         q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
2521         s_addr = q_hdr->select_addr;
2522         r_cnt = q_hdr->rd_strd.read_addr_cnt;
2523         r_stride = q_hdr->rd_strd.read_addr_stride;
2524         loop_cnt = q_hdr->op_count;
2525
2526         for (i = 0; i < loop_cnt; i++) {
2527                 qla8044_wr_reg_indirect(vha, s_addr, qid);
2528                 r_addr = q_hdr->read_addr;
2529                 for (k = 0; k < r_cnt; k++) {
2530                         qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2531                         *data_ptr++ = r_value;
2532                         r_addr += r_stride;
2533                 }
2534                 qid += q_hdr->q_strd.queue_id_stride;
2535         }
2536         *d_ptr = data_ptr;
2537 }
2538
2539 /* ISP83xx functions to process new minidump entries... */
2540 static uint32_t
2541 qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
2542         struct qla8044_minidump_entry_hdr *entry_hdr,
2543         uint32_t **d_ptr)
2544 {
2545         uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2546         uint16_t s_stride, i;
2547         struct qla8044_minidump_entry_pollrd *pollrd_hdr;
2548         uint32_t *data_ptr = *d_ptr;
2549
2550         pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
2551         s_addr = pollrd_hdr->select_addr;
2552         r_addr = pollrd_hdr->read_addr;
2553         s_value = pollrd_hdr->select_value;
2554         s_stride = pollrd_hdr->select_value_stride;
2555
2556         poll_wait = pollrd_hdr->poll_wait;
2557         poll_mask = pollrd_hdr->poll_mask;
2558
2559         for (i = 0; i < pollrd_hdr->op_count; i++) {
2560                 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2561                 poll_wait = pollrd_hdr->poll_wait;
2562                 while (1) {
2563                         qla8044_rd_reg_indirect(vha, s_addr, &r_value);
2564                         if ((r_value & poll_mask) != 0) {
2565                                 break;
2566                         } else {
2567                                 usleep_range(1000, 1100);
2568                                 if (--poll_wait == 0) {
2569                                         ql_log(ql_log_fatal, vha, 0xb0fe,
2570                                             "%s: TIMEOUT\n", __func__);
2571                                         goto error;
2572                                 }
2573                         }
2574                 }
2575                 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2576                 *data_ptr++ = s_value;
2577                 *data_ptr++ = r_value;
2578
2579                 s_value += s_stride;
2580         }
2581         *d_ptr = data_ptr;
2582         return QLA_SUCCESS;
2583
2584 error:
2585         return QLA_FUNCTION_FAILED;
2586 }
2587
2588 static void
2589 qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
2590         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2591 {
2592         uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2593         uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2594         struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
2595         uint32_t *data_ptr = *d_ptr;
2596
2597         rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
2598         sel_val1 = rdmux2_hdr->select_value_1;
2599         sel_val2 = rdmux2_hdr->select_value_2;
2600         sel_addr1 = rdmux2_hdr->select_addr_1;
2601         sel_addr2 = rdmux2_hdr->select_addr_2;
2602         sel_val_mask = rdmux2_hdr->select_value_mask;
2603         read_addr = rdmux2_hdr->read_addr;
2604
2605         for (i = 0; i < rdmux2_hdr->op_count; i++) {
2606                 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
2607                 t_sel_val = sel_val1 & sel_val_mask;
2608                 *data_ptr++ = t_sel_val;
2609
2610                 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2611                 qla8044_rd_reg_indirect(vha, read_addr, &data);
2612
2613                 *data_ptr++ = data;
2614
2615                 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
2616                 t_sel_val = sel_val2 & sel_val_mask;
2617                 *data_ptr++ = t_sel_val;
2618
2619                 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2620                 qla8044_rd_reg_indirect(vha, read_addr, &data);
2621
2622                 *data_ptr++ = data;
2623
2624                 sel_val1 += rdmux2_hdr->select_value_stride;
2625                 sel_val2 += rdmux2_hdr->select_value_stride;
2626         }
2627
2628         *d_ptr = data_ptr;
2629 }
2630
2631 static uint32_t
2632 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
2633         struct qla8044_minidump_entry_hdr *entry_hdr,
2634         uint32_t **d_ptr)
2635 {
2636         uint32_t poll_wait, poll_mask, r_value, data;
2637         uint32_t addr_1, addr_2, value_1, value_2;
2638         struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
2639         uint32_t *data_ptr = *d_ptr;
2640
2641         poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
2642         addr_1 = poll_hdr->addr_1;
2643         addr_2 = poll_hdr->addr_2;
2644         value_1 = poll_hdr->value_1;
2645         value_2 = poll_hdr->value_2;
2646         poll_mask = poll_hdr->poll_mask;
2647
2648         qla8044_wr_reg_indirect(vha, addr_1, value_1);
2649
2650         poll_wait = poll_hdr->poll_wait;
2651         while (1) {
2652                 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2653
2654                 if ((r_value & poll_mask) != 0) {
2655                         break;
2656                 } else {
2657                         usleep_range(1000, 1100);
2658                         if (--poll_wait == 0) {
2659                                 ql_log(ql_log_fatal, vha, 0xb0ff,
2660                                     "%s: TIMEOUT\n", __func__);
2661                                 goto error;
2662                         }
2663                 }
2664         }
2665
2666         qla8044_rd_reg_indirect(vha, addr_2, &data);
2667         data &= poll_hdr->modify_mask;
2668         qla8044_wr_reg_indirect(vha, addr_2, data);
2669         qla8044_wr_reg_indirect(vha, addr_1, value_2);
2670
2671         poll_wait = poll_hdr->poll_wait;
2672         while (1) {
2673                 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2674
2675                 if ((r_value & poll_mask) != 0) {
2676                         break;
2677                 } else {
2678                         usleep_range(1000, 1100);
2679                         if (--poll_wait == 0) {
2680                                 ql_log(ql_log_fatal, vha, 0xb100,
2681                                     "%s: TIMEOUT2\n", __func__);
2682                                 goto error;
2683                         }
2684                 }
2685         }
2686
2687         *data_ptr++ = addr_2;
2688         *data_ptr++ = data;
2689
2690         *d_ptr = data_ptr;
2691
2692         return QLA_SUCCESS;
2693
2694 error:
2695         return QLA_FUNCTION_FAILED;
2696 }
2697
2698 #define ISP8044_PEX_DMA_ENGINE_INDEX            8
2699 #define ISP8044_PEX_DMA_BASE_ADDRESS            0x77320000
2700 #define ISP8044_PEX_DMA_NUM_OFFSET              0x10000
2701 #define ISP8044_PEX_DMA_CMD_ADDR_LOW            0x0
2702 #define ISP8044_PEX_DMA_CMD_ADDR_HIGH           0x04
2703 #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL       0x08
2704
2705 #define ISP8044_PEX_DMA_READ_SIZE       (16 * 1024)
2706 #define ISP8044_PEX_DMA_MAX_WAIT        (100 * 100) /* Max wait of 100 msecs */
2707
2708 static int
2709 qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
2710 {
2711         struct qla_hw_data *ha = vha->hw;
2712         int rval = QLA_SUCCESS;
2713         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2714         uint64_t dma_base_addr = 0;
2715         struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2716
2717         tmplt_hdr = ha->md_tmplt_hdr;
2718         dma_eng_num =
2719             tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2720         dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2721                 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2722
2723         /* Read the pex-dma's command-status-and-control register. */
2724         rval = qla8044_rd_reg_indirect(vha,
2725             (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2726             &cmd_sts_and_cntrl);
2727         if (rval)
2728                 return QLA_FUNCTION_FAILED;
2729
2730         /* Check if requested pex-dma engine is available. */
2731         if (cmd_sts_and_cntrl & BIT_31)
2732                 return QLA_SUCCESS;
2733
2734         return QLA_FUNCTION_FAILED;
2735 }
2736
2737 static int
2738 qla8044_start_pex_dma(struct scsi_qla_host *vha,
2739         struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
2740 {
2741         struct qla_hw_data *ha = vha->hw;
2742         int rval = QLA_SUCCESS, wait = 0;
2743         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2744         uint64_t dma_base_addr = 0;
2745         struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2746
2747         tmplt_hdr = ha->md_tmplt_hdr;
2748         dma_eng_num =
2749             tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2750         dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2751                 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2752
2753         rval = qla8044_wr_reg_indirect(vha,
2754             dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
2755             m_hdr->desc_card_addr);
2756         if (rval)
2757                 goto error_exit;
2758
2759         rval = qla8044_wr_reg_indirect(vha,
2760             dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
2761         if (rval)
2762                 goto error_exit;
2763
2764         rval = qla8044_wr_reg_indirect(vha,
2765             dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
2766             m_hdr->start_dma_cmd);
2767         if (rval)
2768                 goto error_exit;
2769
2770         /* Wait for dma operation to complete. */
2771         for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
2772                 rval = qla8044_rd_reg_indirect(vha,
2773                     (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2774                     &cmd_sts_and_cntrl);
2775                 if (rval)
2776                         goto error_exit;
2777
2778                 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2779                         break;
2780
2781                 udelay(10);
2782         }
2783
2784         /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2785         if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
2786                 rval = QLA_FUNCTION_FAILED;
2787                 goto error_exit;
2788         }
2789
2790 error_exit:
2791         return rval;
2792 }
2793
2794 static int
2795 qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
2796         struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2797 {
2798         struct qla_hw_data *ha = vha->hw;
2799         int rval = QLA_SUCCESS;
2800         struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2801         uint32_t chunk_size, read_size;
2802         uint8_t *data_ptr = (uint8_t *)*d_ptr;
2803         void *rdmem_buffer = NULL;
2804         dma_addr_t rdmem_dma;
2805         struct qla8044_pex_dma_descriptor dma_desc;
2806
2807         rval = qla8044_check_dma_engine_state(vha);
2808         if (rval != QLA_SUCCESS) {
2809                 ql_dbg(ql_dbg_p3p, vha, 0xb147,
2810                     "DMA engine not available. Fallback to rdmem-read.\n");
2811                 return QLA_FUNCTION_FAILED;
2812         }
2813
2814         m_hdr = (void *)entry_hdr;
2815
2816         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2817             ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
2818         if (!rdmem_buffer) {
2819                 ql_dbg(ql_dbg_p3p, vha, 0xb148,
2820                     "Unable to allocate rdmem dma buffer\n");
2821                 return QLA_FUNCTION_FAILED;
2822         }
2823
2824         /* Prepare pex-dma descriptor to be written to MS memory. */
2825         /* dma-desc-cmd layout:
2826          *              0-3: dma-desc-cmd 0-3
2827          *              4-7: pcid function number
2828          *              8-15: dma-desc-cmd 8-15
2829          * dma_bus_addr: dma buffer address
2830          * cmd.read_data_size: amount of data-chunk to be read.
2831          */
2832         dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2833         dma_desc.cmd.dma_desc_cmd |=
2834             ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2835
2836         dma_desc.dma_bus_addr = rdmem_dma;
2837         dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
2838         read_size = 0;
2839
2840         /*
2841          * Perform rdmem operation using pex-dma.
2842          * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
2843          */
2844         while (read_size < m_hdr->read_data_size) {
2845                 if (m_hdr->read_data_size - read_size <
2846                     ISP8044_PEX_DMA_READ_SIZE) {
2847                         chunk_size = (m_hdr->read_data_size - read_size);
2848                         dma_desc.cmd.read_data_size = chunk_size;
2849                 }
2850
2851                 dma_desc.src_addr = m_hdr->read_addr + read_size;
2852
2853                 /* Prepare: Write pex-dma descriptor to MS memory. */
2854                 rval = qla8044_ms_mem_write_128b(vha,
2855                     m_hdr->desc_card_addr, (void *)&dma_desc,
2856                     (sizeof(struct qla8044_pex_dma_descriptor)/16));
2857                 if (rval) {
2858                         ql_log(ql_log_warn, vha, 0xb14a,
2859                             "%s: Error writing rdmem-dma-init to MS !!!\n",
2860                             __func__);
2861                         goto error_exit;
2862                 }
2863                 ql_dbg(ql_dbg_p3p, vha, 0xb14b,
2864                     "%s: Dma-descriptor: Instruct for rdmem dma "
2865                     "(chunk_size 0x%x).\n", __func__, chunk_size);
2866
2867                 /* Execute: Start pex-dma operation. */
2868                 rval = qla8044_start_pex_dma(vha, m_hdr);
2869                 if (rval)
2870                         goto error_exit;
2871
2872                 memcpy(data_ptr, rdmem_buffer, chunk_size);
2873                 data_ptr += chunk_size;
2874                 read_size += chunk_size;
2875         }
2876
2877         *d_ptr = (void *)data_ptr;
2878
2879 error_exit:
2880         if (rdmem_buffer)
2881                 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
2882                     rdmem_buffer, rdmem_dma);
2883
2884         return rval;
2885 }
2886
2887 /*
2888  *
2889  * qla8044_collect_md_data - Retrieve firmware minidump data.
2890  * @ha: pointer to adapter structure
2891  **/
2892 int
2893 qla8044_collect_md_data(struct scsi_qla_host *vha)
2894 {
2895         int num_entry_hdr = 0;
2896         struct qla8044_minidump_entry_hdr *entry_hdr;
2897         struct qla8044_minidump_template_hdr *tmplt_hdr;
2898         uint32_t *data_ptr;
2899         uint32_t data_collected = 0, f_capture_mask;
2900         int i, rval = QLA_FUNCTION_FAILED;
2901         uint64_t now;
2902         uint32_t timestamp, idc_control;
2903         struct qla_hw_data *ha = vha->hw;
2904
2905         if (!ha->md_dump) {
2906                 ql_log(ql_log_info, vha, 0xb101,
2907                     "%s(%ld) No buffer to dump\n",
2908                     __func__, vha->host_no);
2909                 return rval;
2910         }
2911
2912         if (ha->fw_dumped) {
2913                 ql_log(ql_log_warn, vha, 0xb10d,
2914                     "Firmware has been previously dumped (%p) "
2915                     "-- ignoring request.\n", ha->fw_dump);
2916                 goto md_failed;
2917         }
2918
2919         ha->fw_dumped = 0;
2920
2921         if (!ha->md_tmplt_hdr || !ha->md_dump) {
2922                 ql_log(ql_log_warn, vha, 0xb10e,
2923                     "Memory not allocated for minidump capture\n");
2924                 goto md_failed;
2925         }
2926
2927         qla8044_idc_lock(ha);
2928         idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
2929         if (idc_control & GRACEFUL_RESET_BIT1) {
2930                 ql_log(ql_log_warn, vha, 0xb112,
2931                     "Forced reset from application, "
2932                     "ignore minidump capture\n");
2933                 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
2934                     (idc_control & ~GRACEFUL_RESET_BIT1));
2935                 qla8044_idc_unlock(ha);
2936
2937                 goto md_failed;
2938         }
2939         qla8044_idc_unlock(ha);
2940
2941         if (qla82xx_validate_template_chksum(vha)) {
2942                 ql_log(ql_log_info, vha, 0xb109,
2943                     "Template checksum validation error\n");
2944                 goto md_failed;
2945         }
2946
2947         tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2948                 ha->md_tmplt_hdr;
2949         data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
2950         num_entry_hdr = tmplt_hdr->num_of_entries;
2951
2952         ql_dbg(ql_dbg_p3p, vha, 0xb11a,
2953             "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
2954
2955         f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
2956
2957         /* Validate whether required debug level is set */
2958         if ((f_capture_mask & 0x3) != 0x3) {
2959                 ql_log(ql_log_warn, vha, 0xb10f,
2960                     "Minimum required capture mask[0x%x] level not set\n",
2961                     f_capture_mask);
2962
2963         }
2964         tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
2965         ql_log(ql_log_info, vha, 0xb102,
2966             "[%s]: starting data ptr: %p\n",
2967            __func__, data_ptr);
2968         ql_log(ql_log_info, vha, 0xb10b,
2969            "[%s]: no of entry headers in Template: 0x%x\n",
2970            __func__, num_entry_hdr);
2971         ql_log(ql_log_info, vha, 0xb10c,
2972             "[%s]: Total_data_size 0x%x, %d obtained\n",
2973            __func__, ha->md_dump_size, ha->md_dump_size);
2974
2975         /* Update current timestamp before taking dump */
2976         now = get_jiffies_64();
2977         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2978         tmplt_hdr->driver_timestamp = timestamp;
2979
2980         entry_hdr = (struct qla8044_minidump_entry_hdr *)
2981                 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
2982         tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
2983             tmplt_hdr->ocm_window_reg[ha->portnum];
2984
2985         /* Walk through the entry headers - validate/perform required action */
2986         for (i = 0; i < num_entry_hdr; i++) {
2987                 if (data_collected > ha->md_dump_size) {
2988                         ql_log(ql_log_info, vha, 0xb103,
2989                             "Data collected: [0x%x], "
2990                             "Total Dump size: [0x%x]\n",
2991                             data_collected, ha->md_dump_size);
2992                         return rval;
2993                 }
2994
2995                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2996                       ql2xmdcapmask)) {
2997                         entry_hdr->d_ctrl.driver_flags |=
2998                             QLA82XX_DBG_SKIPPED_FLAG;
2999                         goto skip_nxt_entry;
3000                 }
3001
3002                 ql_dbg(ql_dbg_p3p, vha, 0xb104,
3003                     "Data collected: [0x%x], Dump size left:[0x%x]\n",
3004                     data_collected,
3005                     (ha->md_dump_size - data_collected));
3006
3007                 /* Decode the entry type and take required action to capture
3008                  * debug data
3009                  */
3010                 switch (entry_hdr->entry_type) {
3011                 case QLA82XX_RDEND:
3012                         qla8044_mark_entry_skipped(vha, entry_hdr, i);
3013                         break;
3014                 case QLA82XX_CNTRL:
3015                         rval = qla8044_minidump_process_control(vha,
3016                             entry_hdr);
3017                         if (rval != QLA_SUCCESS) {
3018                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3019                                 goto md_failed;
3020                         }
3021                         break;
3022                 case QLA82XX_RDCRB:
3023                         qla8044_minidump_process_rdcrb(vha,
3024                             entry_hdr, &data_ptr);
3025                         break;
3026                 case QLA82XX_RDMEM:
3027                         rval = qla8044_minidump_pex_dma_read(vha,
3028                             entry_hdr, &data_ptr);
3029                         if (rval != QLA_SUCCESS) {
3030                                 rval = qla8044_minidump_process_rdmem(vha,
3031                                     entry_hdr, &data_ptr);
3032                                 if (rval != QLA_SUCCESS) {
3033                                         qla8044_mark_entry_skipped(vha,
3034                                             entry_hdr, i);
3035                                         goto md_failed;
3036                                 }
3037                         }
3038                         break;
3039                 case QLA82XX_BOARD:
3040                 case QLA82XX_RDROM:
3041                         rval = qla8044_minidump_process_rdrom(vha,
3042                             entry_hdr, &data_ptr);
3043                         if (rval != QLA_SUCCESS) {
3044                                 qla8044_mark_entry_skipped(vha,
3045                                     entry_hdr, i);
3046                         }
3047                         break;
3048                 case QLA82XX_L2DTG:
3049                 case QLA82XX_L2ITG:
3050                 case QLA82XX_L2DAT:
3051                 case QLA82XX_L2INS:
3052                         rval = qla8044_minidump_process_l2tag(vha,
3053                             entry_hdr, &data_ptr);
3054                         if (rval != QLA_SUCCESS) {
3055                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3056                                 goto md_failed;
3057                         }
3058                         break;
3059                 case QLA8044_L1DTG:
3060                 case QLA8044_L1ITG:
3061                 case QLA82XX_L1DAT:
3062                 case QLA82XX_L1INS:
3063                         qla8044_minidump_process_l1cache(vha,
3064                             entry_hdr, &data_ptr);
3065                         break;
3066                 case QLA82XX_RDOCM:
3067                         qla8044_minidump_process_rdocm(vha,
3068                             entry_hdr, &data_ptr);
3069                         break;
3070                 case QLA82XX_RDMUX:
3071                         qla8044_minidump_process_rdmux(vha,
3072                             entry_hdr, &data_ptr);
3073                         break;
3074                 case QLA82XX_QUEUE:
3075                         qla8044_minidump_process_queue(vha,
3076                             entry_hdr, &data_ptr);
3077                         break;
3078                 case QLA8044_POLLRD:
3079                         rval = qla8044_minidump_process_pollrd(vha,
3080                             entry_hdr, &data_ptr);
3081                         if (rval != QLA_SUCCESS)
3082                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3083                         break;
3084                 case QLA8044_RDMUX2:
3085                         qla8044_minidump_process_rdmux2(vha,
3086                             entry_hdr, &data_ptr);
3087                         break;
3088                 case QLA8044_POLLRDMWR:
3089                         rval = qla8044_minidump_process_pollrdmwr(vha,
3090                             entry_hdr, &data_ptr);
3091                         if (rval != QLA_SUCCESS)
3092                                 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3093                         break;
3094                 case QLA82XX_RDNOP:
3095                 default:
3096                         qla8044_mark_entry_skipped(vha, entry_hdr, i);
3097                         break;
3098                 }
3099
3100                 data_collected = (uint8_t *)data_ptr -
3101                     (uint8_t *)((uint8_t *)ha->md_dump);
3102 skip_nxt_entry:
3103                 /*
3104                  * next entry in the template
3105                  */
3106                 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3107                     (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
3108         }
3109
3110         if (data_collected != ha->md_dump_size) {
3111                 ql_log(ql_log_info, vha, 0xb105,
3112                     "Dump data mismatch: Data collected: "
3113                     "[0x%x], total_data_size:[0x%x]\n",
3114                     data_collected, ha->md_dump_size);
3115                 goto md_failed;
3116         }
3117
3118         ql_log(ql_log_info, vha, 0xb110,
3119             "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
3120             vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3121         ha->fw_dumped = 1;
3122         qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
3123
3124
3125         ql_log(ql_log_info, vha, 0xb106,
3126             "Leaving fn: %s Last entry: 0x%x\n",
3127             __func__, i);
3128 md_failed:
3129         return rval;
3130 }
3131
3132 void
3133 qla8044_get_minidump(struct scsi_qla_host *vha)
3134 {
3135         struct qla_hw_data *ha = vha->hw;
3136
3137         if (!qla8044_collect_md_data(vha)) {
3138                 ha->fw_dumped = 1;
3139         } else {
3140                 ql_log(ql_log_fatal, vha, 0xb0db,
3141                     "%s: Unable to collect minidump\n",
3142                     __func__);
3143         }
3144 }
3145
3146 static int
3147 qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
3148 {
3149         uint32_t flash_status;
3150         int retries = QLA8044_FLASH_READ_RETRY_COUNT;
3151         int ret_val = QLA_SUCCESS;
3152
3153         while (retries--) {
3154                 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
3155                     &flash_status);
3156                 if (ret_val) {
3157                         ql_log(ql_log_warn, vha, 0xb13c,
3158                             "%s: Failed to read FLASH_STATUS reg.\n",
3159                             __func__);
3160                         break;
3161                 }
3162                 if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
3163                     QLA8044_FLASH_STATUS_READY)
3164                         break;
3165                 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
3166         }
3167
3168         if (!retries)
3169                 ret_val = QLA_FUNCTION_FAILED;
3170
3171         return ret_val;
3172 }
3173
3174 static int
3175 qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
3176                                uint32_t data)
3177 {
3178         int ret_val = QLA_SUCCESS;
3179         uint32_t cmd;
3180
3181         cmd = vha->hw->fdt_wrt_sts_reg_cmd;
3182
3183         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3184             QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
3185         if (ret_val) {
3186                 ql_log(ql_log_warn, vha, 0xb125,
3187                     "%s: Failed to write to FLASH_ADDR.\n", __func__);
3188                 goto exit_func;
3189         }
3190
3191         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
3192         if (ret_val) {
3193                 ql_log(ql_log_warn, vha, 0xb126,
3194                     "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3195                 goto exit_func;
3196         }
3197
3198         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3199             QLA8044_FLASH_SECOND_ERASE_MS_VAL);
3200         if (ret_val) {
3201                 ql_log(ql_log_warn, vha, 0xb127,
3202                     "%s: Failed to write to FLASH_CONTROL.\n", __func__);
3203                 goto exit_func;
3204         }
3205
3206         ret_val = qla8044_poll_flash_status_reg(vha);
3207         if (ret_val)
3208                 ql_log(ql_log_warn, vha, 0xb128,
3209                     "%s: Error polling flash status reg.\n", __func__);
3210
3211 exit_func:
3212         return ret_val;
3213 }
3214
3215 /*
3216  * This function assumes that the flash lock is held.
3217  */
3218 static int
3219 qla8044_unprotect_flash(scsi_qla_host_t *vha)
3220 {
3221         int ret_val;
3222         struct qla_hw_data *ha = vha->hw;
3223
3224         ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
3225         if (ret_val)
3226                 ql_log(ql_log_warn, vha, 0xb139,
3227                     "%s: Write flash status failed.\n", __func__);
3228
3229         return ret_val;
3230 }
3231
3232 /*
3233  * This function assumes that the flash lock is held.
3234  */
3235 static int
3236 qla8044_protect_flash(scsi_qla_host_t *vha)
3237 {
3238         int ret_val;
3239         struct qla_hw_data *ha = vha->hw;
3240
3241         ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
3242         if (ret_val)
3243                 ql_log(ql_log_warn, vha, 0xb13b,
3244                     "%s: Write flash status failed.\n", __func__);
3245
3246         return ret_val;
3247 }
3248
3249
3250 static int
3251 qla8044_erase_flash_sector(struct scsi_qla_host *vha,
3252                            uint32_t sector_start_addr)
3253 {
3254         uint32_t reversed_addr;
3255         int ret_val = QLA_SUCCESS;
3256
3257         ret_val = qla8044_poll_flash_status_reg(vha);
3258         if (ret_val) {
3259                 ql_log(ql_log_warn, vha, 0xb12e,
3260                     "%s: Poll flash status after erase failed..\n", __func__);
3261         }
3262
3263         reversed_addr = (((sector_start_addr & 0xFF) << 16) |
3264             (sector_start_addr & 0xFF00) |
3265             ((sector_start_addr & 0xFF0000) >> 16));
3266
3267         ret_val = qla8044_wr_reg_indirect(vha,
3268             QLA8044_FLASH_WRDATA, reversed_addr);
3269         if (ret_val) {
3270                 ql_log(ql_log_warn, vha, 0xb12f,
3271                     "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3272         }
3273         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3274            QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
3275         if (ret_val) {
3276                 ql_log(ql_log_warn, vha, 0xb130,
3277                     "%s: Failed to write to FLASH_ADDR.\n", __func__);
3278         }
3279         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3280             QLA8044_FLASH_LAST_ERASE_MS_VAL);
3281         if (ret_val) {
3282                 ql_log(ql_log_warn, vha, 0xb131,
3283                     "%s: Failed write to FLASH_CONTROL.\n", __func__);
3284         }
3285         ret_val = qla8044_poll_flash_status_reg(vha);
3286         if (ret_val) {
3287                 ql_log(ql_log_warn, vha, 0xb132,
3288                     "%s: Poll flash status failed.\n", __func__);
3289         }
3290
3291
3292         return ret_val;
3293 }
3294
3295 /*
3296  * qla8044_flash_write_u32 - Write data to flash
3297  *
3298  * @ha : Pointer to adapter structure
3299  * addr : Flash address to write to
3300  * p_data : Data to be written
3301  *
3302  * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3303  *
3304  * NOTE: Lock should be held on entry
3305  */
3306 static int
3307 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3308                         uint32_t *p_data)
3309 {
3310         int ret_val = QLA_SUCCESS;
3311
3312         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3313             0x00800000 | (addr >> 2));
3314         if (ret_val) {
3315                 ql_log(ql_log_warn, vha, 0xb134,
3316                     "%s: Failed write to FLASH_ADDR.\n", __func__);
3317                 goto exit_func;
3318         }
3319         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
3320         if (ret_val) {
3321                 ql_log(ql_log_warn, vha, 0xb135,
3322                     "%s: Failed write to FLASH_WRDATA.\n", __func__);
3323                 goto exit_func;
3324         }
3325         ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
3326         if (ret_val) {
3327                 ql_log(ql_log_warn, vha, 0xb136,
3328                     "%s: Failed write to FLASH_CONTROL.\n", __func__);
3329                 goto exit_func;
3330         }
3331         ret_val = qla8044_poll_flash_status_reg(vha);
3332         if (ret_val) {
3333                 ql_log(ql_log_warn, vha, 0xb137,
3334                     "%s: Poll flash status failed.\n", __func__);
3335         }
3336
3337 exit_func:
3338         return ret_val;
3339 }
3340
3341 static int
3342 qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3343                                 uint32_t faddr, uint32_t dwords)
3344 {
3345         int ret = QLA_FUNCTION_FAILED;
3346         uint32_t spi_val;
3347
3348         if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
3349             dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
3350                 ql_dbg(ql_dbg_user, vha, 0xb123,
3351                     "Got unsupported dwords = 0x%x.\n",
3352                     dwords);
3353                 return QLA_FUNCTION_FAILED;
3354         }
3355
3356         qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
3357         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3358             spi_val | QLA8044_FLASH_SPI_CTL);
3359         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3360             QLA8044_FLASH_FIRST_TEMP_VAL);
3361
3362         /* First DWORD write to FLASH_WRDATA */
3363         ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
3364             *dwptr++);
3365         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3366             QLA8044_FLASH_FIRST_MS_PATTERN);
3367
3368         ret = qla8044_poll_flash_status_reg(vha);
3369         if (ret) {
3370                 ql_log(ql_log_warn, vha, 0xb124,
3371                     "%s: Failed.\n", __func__);
3372                 goto exit_func;
3373         }
3374
3375         dwords--;
3376
3377         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3378             QLA8044_FLASH_SECOND_TEMP_VAL);
3379
3380
3381         /* Second to N-1 DWORDS writes */
3382         while (dwords != 1) {
3383                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3384                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3385                     QLA8044_FLASH_SECOND_MS_PATTERN);
3386                 ret = qla8044_poll_flash_status_reg(vha);
3387                 if (ret) {
3388                         ql_log(ql_log_warn, vha, 0xb129,
3389                             "%s: Failed.\n", __func__);
3390                         goto exit_func;
3391                 }
3392                 dwords--;
3393         }
3394
3395         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3396             QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
3397
3398         /* Last DWORD write */
3399         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3400         qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3401             QLA8044_FLASH_LAST_MS_PATTERN);
3402         ret = qla8044_poll_flash_status_reg(vha);
3403         if (ret) {
3404                 ql_log(ql_log_warn, vha, 0xb12a,
3405                     "%s: Failed.\n", __func__);
3406                 goto exit_func;
3407         }
3408         qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
3409
3410         if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
3411                 ql_log(ql_log_warn, vha, 0xb12b,
3412                     "%s: Failed.\n", __func__);
3413                 spi_val = 0;
3414                 /* Operation failed, clear error bit. */
3415                 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3416                     &spi_val);
3417                 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3418                     spi_val | QLA8044_FLASH_SPI_CTL);
3419         }
3420 exit_func:
3421         return ret;
3422 }
3423
3424 static int
3425 qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3426                                uint32_t faddr, uint32_t dwords)
3427 {
3428         int ret = QLA_FUNCTION_FAILED;
3429         uint32_t liter;
3430
3431         for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3432                 ret = qla8044_flash_write_u32(vha, faddr, dwptr);
3433                 if (ret) {
3434                         ql_dbg(ql_dbg_p3p, vha, 0xb141,
3435                             "%s: flash address=%x data=%x.\n", __func__,
3436                              faddr, *dwptr);
3437                         break;
3438                 }
3439         }
3440
3441         return ret;
3442 }
3443
3444 int
3445 qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3446                           uint32_t offset, uint32_t length)
3447 {
3448         int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
3449         int dword_count, erase_sec_count;
3450         uint32_t erase_offset;
3451         uint8_t *p_cache, *p_src;
3452
3453         erase_offset = offset;
3454
3455         p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
3456         if (!p_cache)
3457                 return QLA_FUNCTION_FAILED;
3458
3459         memcpy(p_cache, buf, length);
3460         p_src = p_cache;
3461         dword_count = length / sizeof(uint32_t);
3462         /* Since the offset and legth are sector aligned, it will be always
3463          * multiple of burst_iter_count (64)
3464          */
3465         burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
3466         erase_sec_count = length / QLA8044_SECTOR_SIZE;
3467
3468         /* Suspend HBA. */
3469         scsi_block_requests(vha->host);
3470         /* Lock and enable write for whole operation. */
3471         qla8044_flash_lock(vha);
3472         qla8044_unprotect_flash(vha);
3473
3474         /* Erasing the sectors */
3475         for (i = 0; i < erase_sec_count; i++) {
3476                 rval = qla8044_erase_flash_sector(vha, erase_offset);
3477                 ql_dbg(ql_dbg_user, vha, 0xb138,
3478                     "Done erase of sector=0x%x.\n",
3479                     erase_offset);
3480                 if (rval) {
3481                         ql_log(ql_log_warn, vha, 0xb121,
3482                             "Failed to erase the sector having address: "
3483                             "0x%x.\n", erase_offset);
3484                         goto out;
3485                 }
3486                 erase_offset += QLA8044_SECTOR_SIZE;
3487         }
3488         ql_dbg(ql_dbg_user, vha, 0xb13f,
3489             "Got write for addr = 0x%x length=0x%x.\n",
3490             offset, length);
3491
3492         for (i = 0; i < burst_iter_count; i++) {
3493
3494                 /* Go with write. */
3495                 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
3496                     offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
3497                 if (rval) {
3498                         /* Buffer Mode failed skip to dword mode */
3499                         ql_log(ql_log_warn, vha, 0xb122,
3500                             "Failed to write flash in buffer mode, "
3501                             "Reverting to slow-write.\n");
3502                         rval = qla8044_write_flash_dword_mode(vha,
3503                             (uint32_t *)p_src, offset,
3504                             QLA8044_MAX_OPTROM_BURST_DWORDS);
3505                 }
3506                 p_src +=  sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3507                 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3508         }
3509         ql_dbg(ql_dbg_user, vha, 0xb133,
3510             "Done writing.\n");
3511
3512 out:
3513         qla8044_protect_flash(vha);
3514         qla8044_flash_unlock(vha);
3515         scsi_unblock_requests(vha->host);
3516         kfree(p_cache);
3517
3518         return rval;
3519 }
3520
3521 #define LEG_INT_PTR_B31         (1 << 31)
3522 #define LEG_INT_PTR_B30         (1 << 30)
3523 #define PF_BITS_MASK            (0xF << 16)
3524 /**
3525  * qla8044_intr_handler() - Process interrupts for the ISP8044
3526  * @irq:
3527  * @dev_id: SCSI driver HA context
3528  *
3529  * Called by system whenever the host adapter generates an interrupt.
3530  *
3531  * Returns handled flag.
3532  */
3533 irqreturn_t
3534 qla8044_intr_handler(int irq, void *dev_id)
3535 {
3536         scsi_qla_host_t *vha;
3537         struct qla_hw_data *ha;
3538         struct rsp_que *rsp;
3539         struct device_reg_82xx __iomem *reg;
3540         int             status = 0;
3541         unsigned long   flags;
3542         unsigned long   iter;
3543         uint32_t        stat;
3544         uint16_t        mb[4];
3545         uint32_t leg_int_ptr = 0, pf_bit;
3546
3547         rsp = (struct rsp_que *) dev_id;
3548         if (!rsp) {
3549                 ql_log(ql_log_info, NULL, 0xb143,
3550                     "%s(): NULL response queue pointer\n", __func__);
3551                 return IRQ_NONE;
3552         }
3553         ha = rsp->hw;
3554         vha = pci_get_drvdata(ha->pdev);
3555
3556         if (unlikely(pci_channel_offline(ha->pdev)))
3557                 return IRQ_HANDLED;
3558
3559         leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3560
3561         /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
3562         if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
3563                 ql_dbg(ql_dbg_p3p, vha, 0xb144,
3564                     "%s: Legacy Interrupt Bit 31 not set, "
3565                     "spurious interrupt!\n", __func__);
3566                 return IRQ_NONE;
3567         }
3568
3569         pf_bit = ha->portnum << 16;
3570         /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
3571         if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
3572                 ql_dbg(ql_dbg_p3p, vha, 0xb145,
3573                     "%s: Incorrect function ID 0x%x in "
3574                     "legacy interrupt register, "
3575                     "ha->pf_bit = 0x%x\n", __func__,
3576                     (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
3577                 return IRQ_NONE;
3578         }
3579
3580         /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
3581          * Control register and poll till Legacy Interrupt Pointer register
3582          * bit32 is 0.
3583          */
3584         qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
3585         do {
3586                 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3587                 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
3588                         break;
3589         } while (leg_int_ptr & (LEG_INT_PTR_B30));
3590
3591         reg = &ha->iobase->isp82;
3592         spin_lock_irqsave(&ha->hardware_lock, flags);
3593         for (iter = 1; iter--; ) {
3594
3595                 if (RD_REG_DWORD(&reg->host_int)) {
3596                         stat = RD_REG_DWORD(&reg->host_status);
3597                         if ((stat & HSRX_RISC_INT) == 0)
3598                                 break;
3599
3600                         switch (stat & 0xff) {
3601                         case 0x1:
3602                         case 0x2:
3603                         case 0x10:
3604                         case 0x11:
3605                                 qla82xx_mbx_completion(vha, MSW(stat));
3606                                 status |= MBX_INTERRUPT;
3607                                 break;
3608                         case 0x12:
3609                                 mb[0] = MSW(stat);
3610                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
3611                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
3612                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
3613                                 qla2x00_async_event(vha, rsp, mb);
3614                                 break;
3615                         case 0x13:
3616                                 qla24xx_process_response_queue(vha, rsp);
3617                                 break;
3618                         default:
3619                                 ql_dbg(ql_dbg_p3p, vha, 0xb146,
3620                                     "Unrecognized interrupt type "
3621                                     "(%d).\n", stat & 0xff);
3622                                 break;
3623                         }
3624                 }
3625                 WRT_REG_DWORD(&reg->host_int, 0);
3626         }
3627
3628         qla2x00_handle_mbx_completion(ha, status);
3629         spin_unlock_irqrestore(&ha->hardware_lock, flags);
3630
3631         return IRQ_HANDLED;
3632 }
3633
3634 static int
3635 qla8044_idc_dontreset(struct qla_hw_data *ha)
3636 {
3637         uint32_t idc_ctrl;
3638
3639         idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3640         return idc_ctrl & DONTRESET_BIT0;
3641 }
3642
3643 static void
3644 qla8044_clear_rst_ready(scsi_qla_host_t *vha)
3645 {
3646         uint32_t drv_state;
3647
3648         drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
3649
3650         /*
3651          * For ISP8044, drv_active register has 1 bit per function,
3652          * shift 1 by func_num to set a bit for the function.
3653          * For ISP82xx, drv_active has 4 bits per function
3654          */
3655         drv_state &= ~(1 << vha->hw->portnum);
3656
3657         ql_dbg(ql_dbg_p3p, vha, 0xb13d,
3658             "drv_state: 0x%08x\n", drv_state);
3659         qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
3660 }
3661
3662 int
3663 qla8044_abort_isp(scsi_qla_host_t *vha)
3664 {
3665         int rval;
3666         uint32_t dev_state;
3667         struct qla_hw_data *ha = vha->hw;
3668
3669         qla8044_idc_lock(ha);
3670         dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3671
3672         if (ql2xdontresethba)
3673                 qla8044_set_idc_dontreset(vha);
3674
3675         /* If device_state is NEED_RESET, go ahead with
3676          * Reset,irrespective of ql2xdontresethba. This is to allow a
3677          * non-reset-owner to force a reset. Non-reset-owner sets
3678          * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
3679          * and then forces a Reset by setting device_state to
3680          * NEED_RESET. */
3681         if (dev_state == QLA8XXX_DEV_READY) {
3682                 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
3683                  * recovery */
3684                 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
3685                         ql_dbg(ql_dbg_p3p, vha, 0xb13e,
3686                             "Reset recovery disabled\n");
3687                         rval = QLA_FUNCTION_FAILED;
3688                         goto exit_isp_reset;
3689                 }
3690
3691                 ql_dbg(ql_dbg_p3p, vha, 0xb140,
3692                     "HW State: NEED RESET\n");
3693                 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3694                     QLA8XXX_DEV_NEED_RESET);
3695         }
3696
3697         /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
3698          * and which drivers are present. Unlike ISP82XX, the function setting
3699          * NEED_RESET, may not be the Reset owner. */
3700         qla83xx_reset_ownership(vha);
3701
3702         qla8044_idc_unlock(ha);
3703         rval = qla8044_device_state_handler(vha);
3704         qla8044_idc_lock(ha);
3705         qla8044_clear_rst_ready(vha);
3706
3707 exit_isp_reset:
3708         qla8044_idc_unlock(ha);
3709         if (rval == QLA_SUCCESS) {
3710                 ha->flags.isp82xx_fw_hung = 0;
3711                 ha->flags.nic_core_reset_hdlr_active = 0;
3712                 rval = qla82xx_restart_isp(vha);
3713         }
3714
3715         return rval;
3716 }
3717