Pileus Git - ~andy/linux/blob - drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.signature       = pm8001_mr32(address, 0x00);
  54         pm8001_ha->main_cfg_tbl.interface_rev   = pm8001_mr32(address, 0x04);
  55         pm8001_ha->main_cfg_tbl.firmware_rev    = pm8001_mr32(address, 0x08);
  56         pm8001_ha->main_cfg_tbl.max_out_io      = pm8001_mr32(address, 0x0C);
  57         pm8001_ha->main_cfg_tbl.max_sgl         = pm8001_mr32(address, 0x10);
  58         pm8001_ha->main_cfg_tbl.ctrl_cap_flag   = pm8001_mr32(address, 0x14);
  59         pm8001_ha->main_cfg_tbl.gst_offset      = pm8001_mr32(address, 0x18);
  60         pm8001_ha->main_cfg_tbl.inbound_queue_offset =
  61                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  62         pm8001_ha->main_cfg_tbl.outbound_queue_offset =
  63                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  64         pm8001_ha->main_cfg_tbl.hda_mode_flag   =
  65                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  66
  67         /* read analog Setting offset from the configuration table */
  68         pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
  69                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  70
  71         /* read Error Dump Offset and Length */
  72         pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
  73                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  74         pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
  75                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  76         pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
  77                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  78         pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
  79                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  80 }
  81
  82 /**
  83  * read_general_status_table - read the general status table and save it.
  84  * @pm8001_ha: our hba card information
  85  */
  86 static void __devinit
  87 read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  88 {
  89         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  90         pm8001_ha->gs_tbl.gst_len_mpistate      = pm8001_mr32(address, 0x00);
  91         pm8001_ha->gs_tbl.iq_freeze_state0      = pm8001_mr32(address, 0x04);
  92         pm8001_ha->gs_tbl.iq_freeze_state1      = pm8001_mr32(address, 0x08);
  93         pm8001_ha->gs_tbl.msgu_tcnt             = pm8001_mr32(address, 0x0C);
  94         pm8001_ha->gs_tbl.iop_tcnt              = pm8001_mr32(address, 0x10);
  95         pm8001_ha->gs_tbl.reserved              = pm8001_mr32(address, 0x14);
  96         pm8001_ha->gs_tbl.phy_state[0]  = pm8001_mr32(address, 0x18);
  97         pm8001_ha->gs_tbl.phy_state[1]  = pm8001_mr32(address, 0x1C);
  98         pm8001_ha->gs_tbl.phy_state[2]  = pm8001_mr32(address, 0x20);
  99         pm8001_ha->gs_tbl.phy_state[3]  = pm8001_mr32(address, 0x24);
 100         pm8001_ha->gs_tbl.phy_state[4]  = pm8001_mr32(address, 0x28);
 101         pm8001_ha->gs_tbl.phy_state[5]  = pm8001_mr32(address, 0x2C);
 102         pm8001_ha->gs_tbl.phy_state[6]  = pm8001_mr32(address, 0x30);
 103         pm8001_ha->gs_tbl.phy_state[7]  = pm8001_mr32(address, 0x34);
 104         pm8001_ha->gs_tbl.reserved1             = pm8001_mr32(address, 0x38);
 105         pm8001_ha->gs_tbl.reserved2             = pm8001_mr32(address, 0x3C);
 106         pm8001_ha->gs_tbl.reserved3             = pm8001_mr32(address, 0x40);
 107         pm8001_ha->gs_tbl.recover_err_info[0]   = pm8001_mr32(address, 0x44);
 108         pm8001_ha->gs_tbl.recover_err_info[1]   = pm8001_mr32(address, 0x48);
 109         pm8001_ha->gs_tbl.recover_err_info[2]   = pm8001_mr32(address, 0x4C);
 110         pm8001_ha->gs_tbl.recover_err_info[3]   = pm8001_mr32(address, 0x50);
 111         pm8001_ha->gs_tbl.recover_err_info[4]   = pm8001_mr32(address, 0x54);
 112         pm8001_ha->gs_tbl.recover_err_info[5]   = pm8001_mr32(address, 0x58);
 113         pm8001_ha->gs_tbl.recover_err_info[6]   = pm8001_mr32(address, 0x5C);
 114         pm8001_ha->gs_tbl.recover_err_info[7]   = pm8001_mr32(address, 0x60);
 115 }
 116
 117 /**
 118  * read_inbnd_queue_table - read the inbound queue table and save it.
 119  * @pm8001_ha: our hba card information
 120  */
 121 static void __devinit
 122 read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 123 {
 124         int inbQ_num = 1;
 125         int i;
 126         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 127         for (i = 0; i < inbQ_num; i++) {
 128                 u32 offset = i * 0x20;
 129                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 130                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 131                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 132                         pm8001_mr32(address, (offset + 0x18));
 133         }
 134 }
 135
 136 /**
 137  * read_outbnd_queue_table - read the outbound queue table and save it.
 138  * @pm8001_ha: our hba card information
 139  */
 140 static void __devinit
 141 read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 142 {
 143         int outbQ_num = 1;
 144         int i;
 145         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 146         for (i = 0; i < outbQ_num; i++) {
 147                 u32 offset = i * 0x24;
 148                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 149                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 150                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 151                         pm8001_mr32(address, (offset + 0x18));
 152         }
 153 }
 154
 155 /**
 156  * init_default_table_values - init the default table.
 157  * @pm8001_ha: our hba card information
 158  */
 159 static void __devinit
 160 init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 161 {
 162         int qn = 1;
 163         int i;
 164         u32 offsetib, offsetob;
 165         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 166         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 167
 168         pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd                     = 0;
 169         pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3                = 0;
 170         pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7                = 0;
 171         pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3               = 0;
 172         pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7               = 0;
 173         pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3       = 0;
 174         pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7       = 0;
 175         pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3   = 0;
 176         pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7   = 0;
 177         pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3   = 0;
 178         pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7   = 0;
 179
 180         pm8001_ha->main_cfg_tbl.upper_event_log_addr            =
 181                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 182         pm8001_ha->main_cfg_tbl.lower_event_log_addr            =
 183                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 184         pm8001_ha->main_cfg_tbl.event_log_size  = PM8001_EVENT_LOG_SIZE;
 185         pm8001_ha->main_cfg_tbl.event_log_option                = 0x01;
 186         pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr        =
 187                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 188         pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr        =
 189                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 190         pm8001_ha->main_cfg_tbl.iop_event_log_size      = PM8001_EVENT_LOG_SIZE;
 191         pm8001_ha->main_cfg_tbl.iop_event_log_option            = 0x01;
 192         pm8001_ha->main_cfg_tbl.fatal_err_interrupt             = 0x01;
 193         for (i = 0; i < qn; i++) {
 194                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 195                         PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
 196                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 197                         pm8001_ha->memoryMap.region[IB].phys_addr_hi;
 198                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 199                 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
 200                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 201                         (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
 202                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 203                         pm8001_ha->memoryMap.region[IB].total_len;
 204                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 205                         pm8001_ha->memoryMap.region[CI].phys_addr_hi;
 206                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 207                         pm8001_ha->memoryMap.region[CI].phys_addr_lo;
 208                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 209                         pm8001_ha->memoryMap.region[CI].virt_ptr;
 210                 offsetib = i * 0x20;
 211                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 212                         get_pci_bar_index(pm8001_mr32(addressib,
 213                                 (offsetib + 0x14)));
 214                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 215                         pm8001_mr32(addressib, (offsetib + 0x18));
 216                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 217                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 218         }
 219         for (i = 0; i < qn; i++) {
 220                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 221                         PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
 222                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 223                         pm8001_ha->memoryMap.region[OB].phys_addr_hi;
 224                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 225                         pm8001_ha->memoryMap.region[OB].phys_addr_lo;
 226                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 227                         (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
 228                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 229                         pm8001_ha->memoryMap.region[OB].total_len;
 230                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 231                         pm8001_ha->memoryMap.region[PI].phys_addr_hi;
 232                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 233                         pm8001_ha->memoryMap.region[PI].phys_addr_lo;
 234                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 235                         0 | (10 << 16) | (0 << 24);
 236                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 237                         pm8001_ha->memoryMap.region[PI].virt_ptr;
 238                 offsetob = i * 0x24;
 239                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 240                         get_pci_bar_index(pm8001_mr32(addressob,
 241                         offsetob + 0x14));
 242                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 243                         pm8001_mr32(addressob, (offsetob + 0x18));
 244                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 245                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 246         }
 247 }
 248
 249 /**
 250  * update_main_config_table - update the main default table to the HBA.
 251  * @pm8001_ha: our hba card information
 252  */
 253 static void __devinit
 254 update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 255 {
 256         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 257         pm8001_mw32(address, 0x24,
 258                 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
 259         pm8001_mw32(address, 0x28,
 260                 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
 261         pm8001_mw32(address, 0x2C,
 262                 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
 263         pm8001_mw32(address, 0x30,
 264                 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
 265         pm8001_mw32(address, 0x34,
 266                 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
 267         pm8001_mw32(address, 0x38,
 268                 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
 269         pm8001_mw32(address, 0x3C,
 270                 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
 271         pm8001_mw32(address, 0x40,
 272                 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
 273         pm8001_mw32(address, 0x44,
 274                 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
 275         pm8001_mw32(address, 0x48,
 276                 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
 277         pm8001_mw32(address, 0x4C,
 278                 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
 279         pm8001_mw32(address, 0x50,
 280                 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
 281         pm8001_mw32(address, 0x54,
 282                 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
 283         pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
 284         pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
 285         pm8001_mw32(address, 0x60,
 286                 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
 287         pm8001_mw32(address, 0x64,
 288                 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
 289         pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
 290         pm8001_mw32(address, 0x6C,
 291                 pm8001_ha->main_cfg_tbl.iop_event_log_option);
 292         pm8001_mw32(address, 0x70,
 293                 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
 294 }
 295
 296 /**
 297  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 298  * @pm8001_ha: our hba card information
 299  */
 300 static void __devinit
 301 update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
 302 {
 303         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 304         u16 offset = number * 0x20;
 305         pm8001_mw32(address, offset + 0x00,
 306                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 307         pm8001_mw32(address, offset + 0x04,
 308                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 309         pm8001_mw32(address, offset + 0x08,
 310                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 311         pm8001_mw32(address, offset + 0x0C,
 312                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 313         pm8001_mw32(address, offset + 0x10,
 314                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 315 }
 316
 317 /**
 318  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 319  * @pm8001_ha: our hba card information
 320  */
 321 static void __devinit
 322 update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
 323 {
 324         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 325         u16 offset = number * 0x24;
 326         pm8001_mw32(address, offset + 0x00,
 327                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 328         pm8001_mw32(address, offset + 0x04,
 329                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 330         pm8001_mw32(address, offset + 0x08,
 331                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 332         pm8001_mw32(address, offset + 0x0C,
 333                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 334         pm8001_mw32(address, offset + 0x10,
 335                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 336         pm8001_mw32(address, offset + 0x1C,
 337                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 338 }
 339
 340 /**
 341  * pm8001_bar4_shift - function is called to shift BAR base address
 342  * @pm8001_ha : our hba card infomation
 343  * @shiftValue : shifting value in memory bar.
 344  */
 345 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 346 {
 347         u32 regVal;
 348         unsigned long start;
 349
 350         /* program the inbound AXI translation Lower Address */
 351         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 352
 353         /* confirm the setting is written */
 354         start = jiffies + HZ; /* 1 sec */
 355         do {
 356                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 357         } while ((regVal != shiftValue) && time_before(jiffies, start));
 358
 359         if (regVal != shiftValue) {
 360                 PM8001_INIT_DBG(pm8001_ha,
 361                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 362                         " = 0x%x\n", regVal));
 363                 return -1;
 364         }
 365         return 0;
 366 }
 367
 368 /**
 369  * mpi_set_phys_g3_with_ssc
 370  * @pm8001_ha: our hba card information
 371  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 372  */
 373 static void __devinit
 374 mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
 375 {
 376         u32 value, offset, i;
 377         unsigned long flags;
 378
 379 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 380 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 381 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 382 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 383 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 384 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 385 #define SNW3_PHY_CAPABILITIES_PARITY 31
 386
 387    /*
 388     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 389     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 390     */
 391         spin_lock_irqsave(&pm8001_ha->lock, flags);
 392         if (-1 == pm8001_bar4_shift(pm8001_ha,
 393                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 394                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 395                 return;
 396         }
 397
 398         for (i = 0; i < 4; i++) {
 399                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 400                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 401         }
 402         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 403         if (-1 == pm8001_bar4_shift(pm8001_ha,
 404                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 405                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 406                 return;
 407         }
 408         for (i = 4; i < 8; i++) {
 409                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 410                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 411         }
 412         /*************************************************************
 413         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 414         Device MABC SMOD0 Controls
 415         Address: (via MEMBASE-III):
 416         Using shifted destination address 0x0_0000: with Offset 0xD8
 417
 418         31:28 R/W Reserved Do not change
 419         27:24 R/W SAS_SMOD_SPRDUP 0000
 420         23:20 R/W SAS_SMOD_SPRDDN 0000
 421         19:0  R/W  Reserved Do not change
 422         Upon power-up this register will read as 0x8990c016,
 423         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 424         so that the written value will be 0x8090c016.
 425         This will ensure only down-spreading SSC is enabled on the SPC.
 426         *************************************************************/
 427         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 428         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 429
 430         /*set the shifted destination address to 0x0 to avoid error operation */
 431         pm8001_bar4_shift(pm8001_ha, 0x0);
 432         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 433         return;
 434 }
 435
 436 /**
 437  * mpi_set_open_retry_interval_reg
 438  * @pm8001_ha: our hba card information
 439  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 440  */
 441 static void __devinit
 442 mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 443                                 u32 interval)
 444 {
 445         u32 offset;
 446         u32 value;
 447         u32 i;
 448         unsigned long flags;
 449
 450 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 451 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 452 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 453 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 454 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 455
 456         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 457         spin_lock_irqsave(&pm8001_ha->lock, flags);
 458         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 459         if (-1 == pm8001_bar4_shift(pm8001_ha,
 460                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 461                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 462                 return;
 463         }
 464         for (i = 0; i < 4; i++) {
 465                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 466                 pm8001_cw32(pm8001_ha, 2, offset, value);
 467         }
 468
 469         if (-1 == pm8001_bar4_shift(pm8001_ha,
 470                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 471                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 472                 return;
 473         }
 474         for (i = 4; i < 8; i++) {
 475                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 476                 pm8001_cw32(pm8001_ha, 2, offset, value);
 477         }
 478         /*set the shifted destination address to 0x0 to avoid error operation */
 479         pm8001_bar4_shift(pm8001_ha, 0x0);
 480         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 481         return;
 482 }
 483
 484 /**
 485  * mpi_init_check - check firmware initialization status.
 486  * @pm8001_ha: our hba card information
 487  */
 488 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 489 {
 490         u32 max_wait_count;
 491         u32 value;
 492         u32 gst_len_mpistate;
 493         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 494         table is updated */
 495         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 496         /* wait until Inbound DoorBell Clear Register toggled */
 497         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 498         do {
 499                 udelay(1);
 500                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 501                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 502         } while ((value != 0) && (--max_wait_count));
 503
 504         if (!max_wait_count)
 505                 return -1;
 506         /* check the MPI-State for initialization */
 507         gst_len_mpistate =
 508                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 509                 GST_GSTLEN_MPIS_OFFSET);
 510         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 511                 return -1;
 512         /* check MPI Initialization error */
 513         gst_len_mpistate = gst_len_mpistate >> 16;
 514         if (0x0000 != gst_len_mpistate)
 515                 return -1;
 516         return 0;
 517 }
 518
 519 /**
 520  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 521  * @pm8001_ha: our hba card information
 522  */
 523 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 524 {
 525         u32 value, value1;
 526         u32 max_wait_count;
 527         /* check error state */
 528         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 529         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 530         /* check AAP error */
 531         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 532                 /* error state */
 533                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 534                 return -1;
 535         }
 536
 537         /* check IOP error */
 538         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 539                 /* error state */
 540                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 541                 return -1;
 542         }
 543
 544         /* bit 4-31 of scratch pad1 should be zeros if it is not
 545         in error state*/
 546         if (value & SCRATCH_PAD1_STATE_MASK) {
 547                 /* error case */
 548                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 549                 return -1;
 550         }
 551
 552         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 553         in error state */
 554         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 555                 /* error case */
 556                 return -1;
 557         }
 558
 559         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 560
 561         /* wait until scratch pad 1 and 2 registers in ready state  */
 562         do {
 563                 udelay(1);
 564                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 565                         & SCRATCH_PAD1_RDY;
 566                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 567                         & SCRATCH_PAD2_RDY;
 568                 if ((--max_wait_count) == 0)
 569                         return -1;
 570         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 571         return 0;
 572 }
 573
 574 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 575 {
 576         void __iomem *base_addr;
 577         u32     value;
 578         u32     offset;
 579         u32     pcibar;
 580         u32     pcilogic;
 581
 582         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 583         offset = value & 0x03FFFFFF;
 584         PM8001_INIT_DBG(pm8001_ha,
 585                 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
 586         pcilogic = (value & 0xFC000000) >> 26;
 587         pcibar = get_pci_bar_index(pcilogic);
 588         PM8001_INIT_DBG(pm8001_ha,
 589                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 590         pm8001_ha->main_cfg_tbl_addr = base_addr =
 591                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 592         pm8001_ha->general_stat_tbl_addr =
 593                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 594         pm8001_ha->inbnd_q_tbl_addr =
 595                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 596         pm8001_ha->outbnd_q_tbl_addr =
 597                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 598 }
 599
 600 /**
 601  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 602  * @pm8001_ha: our hba card information
 603  */
 604 static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 605 {
 606         /* check the firmware status */
 607         if (-1 == check_fw_ready(pm8001_ha)) {
 608                 PM8001_FAIL_DBG(pm8001_ha,
 609                         pm8001_printk("Firmware is not ready!\n"));
 610                 return -EBUSY;
 611         }
 612
 613         /* Initialize pci space address eg: mpi offset */
 614         init_pci_device_addresses(pm8001_ha);
 615         init_default_table_values(pm8001_ha);
 616         read_main_config_table(pm8001_ha);
 617         read_general_status_table(pm8001_ha);
 618         read_inbnd_queue_table(pm8001_ha);
 619         read_outbnd_queue_table(pm8001_ha);
 620         /* update main config table ,inbound table and outbound table */
 621         update_main_config_table(pm8001_ha);
 622         update_inbnd_queue_table(pm8001_ha, 0);
 623         update_outbnd_queue_table(pm8001_ha, 0);
 624         mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 625         /* 7->130ms, 34->500ms, 119->1.5s */
 626         mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 627         /* notify firmware update finished and check initialization status */
 628         if (0 == mpi_init_check(pm8001_ha)) {
 629                 PM8001_INIT_DBG(pm8001_ha,
 630                         pm8001_printk("MPI initialize successful!\n"));
 631         } else
 632                 return -EBUSY;
 633         /*This register is a 16-bit timer with a resolution of 1us. This is the
 634         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 635         Zero is not a valid value. A value of 1 in the register will cause the
 636         interrupts to be normal. A value greater than 1 will cause coalescing
 637         delays.*/
 638         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 639         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 640         return 0;
 641 }
 642
 643 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 644 {
 645         u32 max_wait_count;
 646         u32 value;
 647         u32 gst_len_mpistate;
 648         init_pci_device_addresses(pm8001_ha);
 649         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 650         table is stop */
 651         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 652
 653         /* wait until Inbound DoorBell Clear Register toggled */
 654         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 655         do {
 656                 udelay(1);
 657                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 658                 value &= SPC_MSGU_CFG_TABLE_RESET;
 659         } while ((value != 0) && (--max_wait_count));
 660
 661         if (!max_wait_count) {
 662                 PM8001_FAIL_DBG(pm8001_ha,
 663                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 664                 return -1;
 665         }
 666
 667         /* check the MPI-State for termination in progress */
 668         /* wait until Inbound DoorBell Clear Register toggled */
 669         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 670         do {
 671                 udelay(1);
 672                 gst_len_mpistate =
 673                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 674                         GST_GSTLEN_MPIS_OFFSET);
 675                 if (GST_MPI_STATE_UNINIT ==
 676                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 677                         break;
 678         } while (--max_wait_count);
 679         if (!max_wait_count) {
 680                 PM8001_FAIL_DBG(pm8001_ha,
 681                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 682                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 683                 return -1;
 684         }
 685         return 0;
 686 }
 687
 688 /**
 689  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 690  * @pm8001_ha: our hba card information
 691  */
 692 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 693 {
 694         u32 regVal, regVal1, regVal2;
 695         if (mpi_uninit_check(pm8001_ha) != 0) {
 696                 PM8001_FAIL_DBG(pm8001_ha,
 697                         pm8001_printk("MPI state is not ready\n"));
 698                 return -1;
 699         }
 700         /* read the scratch pad 2 register bit 2 */
 701         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 702                 & SCRATCH_PAD2_FWRDY_RST;
 703         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 704                 PM8001_INIT_DBG(pm8001_ha,
 705                         pm8001_printk("Firmware is ready for reset .\n"));
 706         } else {
 707                 unsigned long flags;
 708                 /* Trigger NMI twice via RB6 */
 709                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 710                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 711                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 712                         PM8001_FAIL_DBG(pm8001_ha,
 713                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 714                                         RB6_ACCESS_REG));
 715                         return -1;
 716                 }
 717                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 718                         RB6_MAGIC_NUMBER_RST);
 719                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 720                 /* wait for 100 ms */
 721                 mdelay(100);
 722                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 723                         SCRATCH_PAD2_FWRDY_RST;
 724                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 725                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 726                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 727                         PM8001_FAIL_DBG(pm8001_ha,
 728                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 729                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 730                                 regVal1, regVal2));
 731                         PM8001_FAIL_DBG(pm8001_ha,
 732                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 733                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 734                         PM8001_FAIL_DBG(pm8001_ha,
 735                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 736                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 737                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 738                         return -1;
 739                 }
 740                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 741         }
 742         return 0;
 743 }
 744
 745 /**
 746  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 747  * the FW register status to the originated status.
 748  * @pm8001_ha: our hba card information
 749  * @signature: signature in host scratch pad0 register.
 750  */
 751 static int
 752 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
 753 {
 754         u32     regVal, toggleVal;
 755         u32     max_wait_count;
 756         u32     regVal1, regVal2, regVal3;
 757         unsigned long flags;
 758
 759         /* step1: Check FW is ready for soft reset */
 760         if (soft_reset_ready_check(pm8001_ha) != 0) {
 761                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 762                 return -1;
 763         }
 764
 765         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 766         value to clear */
 767         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 768         spin_lock_irqsave(&pm8001_ha->lock, flags);
 769         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 770                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 771                 PM8001_FAIL_DBG(pm8001_ha,
 772                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 773                         MBIC_AAP1_ADDR_BASE));
 774                 return -1;
 775         }
 776         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 777         PM8001_INIT_DBG(pm8001_ha,
 778                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 779         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 780         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 781         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 782                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 783                 PM8001_FAIL_DBG(pm8001_ha,
 784                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 785                         MBIC_IOP_ADDR_BASE));
 786                 return -1;
 787         }
 788         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 789         PM8001_INIT_DBG(pm8001_ha,
 790                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 791         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 792
 793         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 794         PM8001_INIT_DBG(pm8001_ha,
 795                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 796         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 797
 798         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 799         PM8001_INIT_DBG(pm8001_ha,
 800                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 801         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 802
 803         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 804         PM8001_INIT_DBG(pm8001_ha,
 805                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 806         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 807
 808         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 809         PM8001_INIT_DBG(pm8001_ha,
 810                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 811         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 812
 813         /* read the scratch pad 1 register bit 2 */
 814         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 815                 & SCRATCH_PAD1_RST;
 816         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 817
 818         /* set signature in host scratch pad0 register to tell SPC that the
 819         host performs the soft reset */
 820         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 821
 822         /* read required registers for confirmming */
 823         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 824         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 825                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 826                 PM8001_FAIL_DBG(pm8001_ha,
 827                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 828                         GSM_ADDR_BASE));
 829                 return -1;
 830         }
 831         PM8001_INIT_DBG(pm8001_ha,
 832                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 833                 " Reset = 0x%x\n",
 834                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 835
 836         /* step 3: host read GSM Configuration and Reset register */
 837         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 838         /* Put those bits to low */
 839         /* GSM XCBI offset = 0x70 0000
 840         0x00 Bit 13 COM_SLV_SW_RSTB 1
 841         0x00 Bit 12 QSSP_SW_RSTB 1
 842         0x00 Bit 11 RAAE_SW_RSTB 1
 843         0x00 Bit 9 RB_1_SW_RSTB 1
 844         0x00 Bit 8 SM_SW_RSTB 1
 845         */
 846         regVal &= ~(0x00003b00);
 847         /* host write GSM Configuration and Reset register */
 848         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 849         PM8001_INIT_DBG(pm8001_ha,
 850                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 851                 "Configuration and Reset is set to = 0x%x\n",
 852                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 853
 854         /* step 4: */
 855         /* disable GSM - Read Address Parity Check */
 856         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 857         PM8001_INIT_DBG(pm8001_ha,
 858                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 859                 "Enable = 0x%x\n", regVal1));
 860         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 861         PM8001_INIT_DBG(pm8001_ha,
 862                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 863                 "is set to = 0x%x\n",
 864                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 865
 866         /* disable GSM - Write Address Parity Check */
 867         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 868         PM8001_INIT_DBG(pm8001_ha,
 869                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 870                 " Enable = 0x%x\n", regVal2));
 871         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 872         PM8001_INIT_DBG(pm8001_ha,
 873                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 874                 "Enable is set to = 0x%x\n",
 875                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 876
 877         /* disable GSM - Write Data Parity Check */
 878         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 879         PM8001_INIT_DBG(pm8001_ha,
 880                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 881                 " Enable = 0x%x\n", regVal3));
 882         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 883         PM8001_INIT_DBG(pm8001_ha,
 884                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 885                 "is set to = 0x%x\n",
 886         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 887
 888         /* step 5: delay 10 usec */
 889         udelay(10);
 890         /* step 5-b: set GPIO-0 output control to tristate anyway */
 891         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 892                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 893                 PM8001_INIT_DBG(pm8001_ha,
 894                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 895                                 GPIO_ADDR_BASE));
 896                 return -1;
 897         }
 898         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 899                 PM8001_INIT_DBG(pm8001_ha,
 900                                 pm8001_printk("GPIO Output Control Register:"
 901                                 " = 0x%x\n", regVal));
 902         /* set GPIO-0 output control to tri-state */
 903         regVal &= 0xFFFFFFFC;
 904         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 905
 906         /* Step 6: Reset the IOP and AAP1 */
 907         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 908         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 909                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 910                 PM8001_FAIL_DBG(pm8001_ha,
 911                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 912                         SPC_TOP_LEVEL_ADDR_BASE));
 913                 return -1;
 914         }
 915         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 916         PM8001_INIT_DBG(pm8001_ha,
 917                 pm8001_printk("Top Register before resetting IOP/AAP1"
 918                 ":= 0x%x\n", regVal));
 919         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 920         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 921
 922         /* step 7: Reset the BDMA/OSSP */
 923         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 924         PM8001_INIT_DBG(pm8001_ha,
 925                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 926                 ": = 0x%x\n", regVal));
 927         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 928         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 929
 930         /* step 8: delay 10 usec */
 931         udelay(10);
 932
 933         /* step 9: bring the BDMA and OSSP out of reset */
 934         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 935         PM8001_INIT_DBG(pm8001_ha,
 936                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
 937                 ":= 0x%x\n", regVal));
 938         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 939         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 940
 941         /* step 10: delay 10 usec */
 942         udelay(10);
 943
 944         /* step 11: reads and sets the GSM Configuration and Reset Register */
 945         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 946         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 947                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 948                 PM8001_FAIL_DBG(pm8001_ha,
 949                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 950                         GSM_ADDR_BASE));
 951                 return -1;
 952         }
 953         PM8001_INIT_DBG(pm8001_ha,
 954                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
 955                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 956         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 957         /* Put those bits to high */
 958         /* GSM XCBI offset = 0x70 0000
 959         0x00 Bit 13 COM_SLV_SW_RSTB 1
 960         0x00 Bit 12 QSSP_SW_RSTB 1
 961         0x00 Bit 11 RAAE_SW_RSTB 1
 962         0x00 Bit 9   RB_1_SW_RSTB 1
 963         0x00 Bit 8   SM_SW_RSTB 1
 964         */
 965         regVal |= (GSM_CONFIG_RESET_VALUE);
 966         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 967         PM8001_INIT_DBG(pm8001_ha,
 968                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
 969                 " Configuration and Reset is set to = 0x%x\n",
 970                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 971
 972         /* step 12: Restore GSM - Read Address Parity Check */
 973         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 974         /* just for debugging */
 975         PM8001_INIT_DBG(pm8001_ha,
 976                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 977                 " = 0x%x\n", regVal));
 978         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
 979         PM8001_INIT_DBG(pm8001_ha,
 980                 pm8001_printk("GSM 0x700038 - Read Address Parity"
 981                 " Check Enable is set to = 0x%x\n",
 982                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 983         /* Restore GSM - Write Address Parity Check */
 984         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 985         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
 986         PM8001_INIT_DBG(pm8001_ha,
 987                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 988                 " Enable is set to = 0x%x\n",
 989                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 990         /* Restore GSM - Write Data Parity Check */
 991         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 992         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
 993         PM8001_INIT_DBG(pm8001_ha,
 994                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
 995                 "is set to = 0x%x\n",
 996                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 997
 998         /* step 13: bring the IOP and AAP1 out of reset */
 999         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1000         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1001                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1002                 PM8001_FAIL_DBG(pm8001_ha,
1003                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
1004                         SPC_TOP_LEVEL_ADDR_BASE));
1005                 return -1;
1006         }
1007         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1008         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1009         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1010
1011         /* step 14: delay 10 usec - Normal Mode */
1012         udelay(10);
1013         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1014         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1015                 /* step 15 (Normal Mode): wait until scratch pad1 register
1016                 bit 2 toggled */
1017                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1018                 do {
1019                         udelay(1);
1020                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1021                                 SCRATCH_PAD1_RST;
1022                 } while ((regVal != toggleVal) && (--max_wait_count));
1023
1024                 if (!max_wait_count) {
1025                         regVal = pm8001_cr32(pm8001_ha, 0,
1026                                 MSGU_SCRATCH_PAD_1);
1027                         PM8001_FAIL_DBG(pm8001_ha,
1028                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1029                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1030                                 toggleVal, regVal));
1031                         PM8001_FAIL_DBG(pm8001_ha,
1032                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1033                                 pm8001_cr32(pm8001_ha, 0,
1034                                 MSGU_SCRATCH_PAD_0)));
1035                         PM8001_FAIL_DBG(pm8001_ha,
1036                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1037                                 pm8001_cr32(pm8001_ha, 0,
1038                                 MSGU_SCRATCH_PAD_2)));
1039                         PM8001_FAIL_DBG(pm8001_ha,
1040                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1041                                 pm8001_cr32(pm8001_ha, 0,
1042                                 MSGU_SCRATCH_PAD_3)));
1043                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1044                         return -1;
1045                 }
1046
1047                 /* step 16 (Normal) - Clear ODMR and ODCR */
1048                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1049                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1050
1051                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1052                 ready - 1 sec timeout */
1053                 /* Wait for the SPC Configuration Table to be ready */
1054                 if (check_fw_ready(pm8001_ha) == -1) {
1055                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1056                         /* return error if MPI Configuration Table not ready */
1057                         PM8001_INIT_DBG(pm8001_ha,
1058                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1059                                 " = 0x%x\n", regVal));
1060                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1061                         /* return error if MPI Configuration Table not ready */
1062                         PM8001_INIT_DBG(pm8001_ha,
1063                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1064                                 " = 0x%x\n", regVal));
1065                         PM8001_INIT_DBG(pm8001_ha,
1066                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1067                                 pm8001_cr32(pm8001_ha, 0,
1068                                 MSGU_SCRATCH_PAD_0)));
1069                         PM8001_INIT_DBG(pm8001_ha,
1070                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1071                                 pm8001_cr32(pm8001_ha, 0,
1072                                 MSGU_SCRATCH_PAD_3)));
1073                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1074                         return -1;
1075                 }
1076         }
1077         pm8001_bar4_shift(pm8001_ha, 0);
1078         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1079
1080         PM8001_INIT_DBG(pm8001_ha,
1081                 pm8001_printk("SPC soft reset Complete\n"));
1082         return 0;
1083 }
1084
1085 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1086 {
1087         u32 i;
1088         u32 regVal;
1089         PM8001_INIT_DBG(pm8001_ha,
1090                 pm8001_printk("chip reset start\n"));
1091
1092         /* do SPC chip reset. */
1093         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1094         regVal &= ~(SPC_REG_RESET_DEVICE);
1095         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1096
1097         /* delay 10 usec */
1098         udelay(10);
1099
1100         /* bring chip reset out of reset */
1101         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1102         regVal |= SPC_REG_RESET_DEVICE;
1103         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1104
1105         /* delay 10 usec */
1106         udelay(10);
1107
1108         /* wait for 20 msec until the firmware gets reloaded */
1109         i = 20;
1110         do {
1111                 mdelay(1);
1112         } while ((--i) != 0);
1113
1114         PM8001_INIT_DBG(pm8001_ha,
1115                 pm8001_printk("chip reset finished\n"));
1116 }
1117
1118 /**
1119  * pm8001_chip_iounmap - which maped when initialized.
1120  * @pm8001_ha: our hba card information
1121  */
1122 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1123 {
1124         s8 bar, logical = 0;
1125         for (bar = 0; bar < 6; bar++) {
1126                 /*
1127                 ** logical BARs for SPC:
1128                 ** bar 0 and 1 - logical BAR0
1129                 ** bar 2 and 3 - logical BAR1
1130                 ** bar4 - logical BAR2
1131                 ** bar5 - logical BAR3
1132                 ** Skip the appropriate assignments:
1133                 */
1134                 if ((bar == 1) || (bar == 3))
1135                         continue;
1136                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1137                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1138                         logical++;
1139                 }
1140         }
1141 }
1142
1143 /**
1144  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1145  * @pm8001_ha: our hba card information
1146  */
1147 static void
1148 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1149 {
1150         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1151         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1152 }
1153
1154  /**
1155   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1156   * @pm8001_ha: our hba card information
1157   */
1158 static void
1159 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1160 {
1161         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1162 }
1163
1164 /**
1165  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1166  * @pm8001_ha: our hba card information
1167  */
1168 static void
1169 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1170         u32 int_vec_idx)
1171 {
1172         u32 msi_index;
1173         u32 value;
1174         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1175         msi_index += MSIX_TABLE_BASE;
1176         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1177         value = (1 << int_vec_idx);
1178         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1179
1180 }
1181
1182 /**
1183  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1184  * @pm8001_ha: our hba card information
1185  */
1186 static void
1187 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1188         u32 int_vec_idx)
1189 {
1190         u32 msi_index;
1191         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1192         msi_index += MSIX_TABLE_BASE;
1193         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1194 }
1195
1196 /**
1197  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1198  * @pm8001_ha: our hba card information
1199  */
1200 static void
1201 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1202 {
1203 #ifdef PM8001_USE_MSIX
1204         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1205         return;
1206 #endif
1207         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1208
1209 }
1210
1211 /**
1212  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1213  * @pm8001_ha: our hba card information
1214  */
1215 static void
1216 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1217 {
1218 #ifdef PM8001_USE_MSIX
1219         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1220         return;
1221 #endif
1222         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1223
1224 }
1225
1226 /**
1227  * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1228  * @circularQ: the inbound queue  we want to transfer to HBA.
1229  * @messageSize: the message size of this transfer, normally it is 64 bytes
1230  * @messagePtr: the pointer to message.
1231  */
1232 static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1233                             u16 messageSize, void **messagePtr)
1234 {
1235         u32 offset, consumer_index;
1236         struct mpi_msg_hdr *msgHeader;
1237         u8 bcCount = 1; /* only support single buffer */
1238
1239         /* Checks is the requested message size can be allocated in this queue*/
1240         if (messageSize > 64) {
1241                 *messagePtr = NULL;
1242                 return -1;
1243         }
1244
1245         /* Stores the new consumer index */
1246         consumer_index = pm8001_read_32(circularQ->ci_virt);
1247         circularQ->consumer_index = cpu_to_le32(consumer_index);
1248         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1249                 le32_to_cpu(circularQ->consumer_index)) {
1250                 *messagePtr = NULL;
1251                 return -1;
1252         }
1253         /* get memory IOMB buffer address */
1254         offset = circularQ->producer_idx * 64;
1255         /* increment to next bcCount element */
1256         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1257                                 % PM8001_MPI_QUEUE;
1258         /* Adds that distance to the base of the region virtual address plus
1259         the message header size*/
1260         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1261         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1262         return 0;
1263 }
1264
1265 /**
1266  * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1267  * to tell the fw to get this message from IOMB.
1268  * @pm8001_ha: our hba card information
1269  * @circularQ: the inbound queue we want to transfer to HBA.
1270  * @opCode: the operation code represents commands which LLDD and fw recognized.
1271  * @payload: the command payload of each operation command.
1272  */
1273 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1274                          struct inbound_queue_table *circularQ,
1275                          u32 opCode, void *payload)
1276 {
1277         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1278         u32 responseQueue = 0;
1279         void *pMessage;
1280
1281         if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1282                 PM8001_IO_DBG(pm8001_ha,
1283                         pm8001_printk("No free mpi buffer\n"));
1284                 return -1;
1285         }
1286         BUG_ON(!payload);
1287         /*Copy to the payload*/
1288         memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1289
1290         /*Build the header*/
1291         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1292                 | ((responseQueue & 0x3F) << 16)
1293                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1294
1295         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1296         /*Update the PI to the firmware*/
1297         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1298                 circularQ->pi_offset, circularQ->producer_idx);
1299         PM8001_IO_DBG(pm8001_ha,
1300                 pm8001_printk("after PI= %d CI= %d\n", circularQ->producer_idx,
1301                 circularQ->consumer_index));
1302         return 0;
1303 }
1304
1305 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1306                             struct outbound_queue_table *circularQ, u8 bc)
1307 {
1308         u32 producer_index;
1309         struct mpi_msg_hdr *msgHeader;
1310         struct mpi_msg_hdr *pOutBoundMsgHeader;
1311
1312         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1313         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1314                                 circularQ->consumer_idx * 64);
1315         if (pOutBoundMsgHeader != msgHeader) {
1316                 PM8001_FAIL_DBG(pm8001_ha,
1317                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1318                         circularQ->consumer_idx, msgHeader));
1319
1320                 /* Update the producer index from SPC */
1321                 producer_index = pm8001_read_32(circularQ->pi_virt);
1322                 circularQ->producer_index = cpu_to_le32(producer_index);
1323                 PM8001_FAIL_DBG(pm8001_ha,
1324                         pm8001_printk("consumer_idx = %d producer_index = %d"
1325                         "msgHeader = %p\n", circularQ->consumer_idx,
1326                         circularQ->producer_index, msgHeader));
1327                 return 0;
1328         }
1329         /* free the circular queue buffer elements associated with the message*/
1330         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1331                                 % PM8001_MPI_QUEUE;
1332         /* update the CI of outbound queue */
1333         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1334                 circularQ->consumer_idx);
1335         /* Update the producer index from SPC*/
1336         producer_index = pm8001_read_32(circularQ->pi_virt);
1337         circularQ->producer_index = cpu_to_le32(producer_index);
1338         PM8001_IO_DBG(pm8001_ha,
1339                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1340                 circularQ->producer_index));
1341         return 0;
1342 }
1343
1344 /**
1345  * mpi_msg_consume- get the MPI message from  outbound queue message table.
1346  * @pm8001_ha: our hba card information
1347  * @circularQ: the outbound queue  table.
1348  * @messagePtr1: the message contents of this outbound message.
1349  * @pBC: the message size.
1350  */
1351 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1352                            struct outbound_queue_table *circularQ,
1353                            void **messagePtr1, u8 *pBC)
1354 {
1355         struct mpi_msg_hdr      *msgHeader;
1356         __le32  msgHeader_tmp;
1357         u32 header_tmp;
1358         do {
1359                 /* If there are not-yet-delivered messages ... */
1360                 if (le32_to_cpu(circularQ->producer_index)
1361                         != circularQ->consumer_idx) {
1362                         /*Get the pointer to the circular queue buffer element*/
1363                         msgHeader = (struct mpi_msg_hdr *)
1364                                 (circularQ->base_virt +
1365                                 circularQ->consumer_idx * 64);
1366                         /* read header */
1367                         header_tmp = pm8001_read_32(msgHeader);
1368                         msgHeader_tmp = cpu_to_le32(header_tmp);
1369                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1370                                 if (OPC_OUB_SKIP_ENTRY !=
1371                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1372                                         *messagePtr1 =
1373                                                 ((u8 *)msgHeader) +
1374                                                 sizeof(struct mpi_msg_hdr);
1375                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1376                                                 >> 24) & 0x1f);
1377                                         PM8001_IO_DBG(pm8001_ha,
1378                                                 pm8001_printk(": CI=%d PI=%d "
1379                                                 "msgHeader=%x\n",
1380                                                 circularQ->consumer_idx,
1381                                                 circularQ->producer_index,
1382                                                 msgHeader_tmp));
1383                                         return MPI_IO_STATUS_SUCCESS;
1384                                 } else {
1385                                         circularQ->consumer_idx =
1386                                                 (circularQ->consumer_idx +
1387                                                 ((le32_to_cpu(msgHeader_tmp)
1388                                                  >> 24) & 0x1f))
1389                                                         % PM8001_MPI_QUEUE;
1390                                         msgHeader_tmp = 0;
1391                                         pm8001_write_32(msgHeader, 0, 0);
1392                                         /* update the CI of outbound queue */
1393                                         pm8001_cw32(pm8001_ha,
1394                                                 circularQ->ci_pci_bar,
1395                                                 circularQ->ci_offset,
1396                                                 circularQ->consumer_idx);
1397                                 }
1398                         } else {
1399                                 circularQ->consumer_idx =
1400                                         (circularQ->consumer_idx +
1401                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1402                                         0x1f)) % PM8001_MPI_QUEUE;
1403                                 msgHeader_tmp = 0;
1404                                 pm8001_write_32(msgHeader, 0, 0);
1405                                 /* update the CI of outbound queue */
1406                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1407                                         circularQ->ci_offset,
1408                                         circularQ->consumer_idx);
1409                                 return MPI_IO_STATUS_FAIL;
1410                         }
1411                 } else {
1412                         u32 producer_index;
1413                         void *pi_virt = circularQ->pi_virt;
1414                         /* Update the producer index from SPC */
1415                         producer_index = pm8001_read_32(pi_virt);
1416                         circularQ->producer_index = cpu_to_le32(producer_index);
1417                 }
1418         } while (le32_to_cpu(circularQ->producer_index) !=
1419                 circularQ->consumer_idx);
1420         /* while we don't have any more not-yet-delivered message */
1421         /* report empty */
1422         return MPI_IO_STATUS_BUSY;
1423 }
1424
1425 static void pm8001_work_fn(struct work_struct *work)
1426 {
1427         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1428         struct pm8001_device *pm8001_dev;
1429         struct domain_device *dev;
1430
1431         /*
1432          * So far, all users of this stash an associated structure here.
1433          * If we get here, and this pointer is null, then the action
1434          * was cancelled. This nullification happens when the device
1435          * goes away.
1436          */
1437         pm8001_dev = pw->data; /* Most stash device structure */
1438         if ((pm8001_dev == NULL)
1439          || ((pw->handler != IO_XFER_ERROR_BREAK)
1440           && (pm8001_dev->dev_type == NO_DEVICE))) {
1441                 kfree(pw);
1442                 return;
1443         }
1444
1445         switch (pw->handler) {
1446         case IO_XFER_ERROR_BREAK:
1447         {       /* This one stashes the sas_task instead */
1448                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1449                 u32 tag;
1450                 struct pm8001_ccb_info *ccb;
1451                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1452                 unsigned long flags, flags1;
1453                 struct task_status_struct *ts;
1454                 int i;
1455
1456                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1457                         break; /* Task still on lu */
1458                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1459
1460                 spin_lock_irqsave(&t->task_state_lock, flags1);
1461                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1462                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1463                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1464                         break; /* Task got completed by another */
1465                 }
1466                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1467
1468                 /* Search for a possible ccb that matches the task */
1469                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1470                         ccb = &pm8001_ha->ccb_info[i];
1471                         tag = ccb->ccb_tag;
1472                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1473                                 break;
1474                 }
1475                 if (!ccb) {
1476                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1477                         break; /* Task got freed by another */
1478                 }
1479                 ts = &t->task_status;
1480                 ts->resp = SAS_TASK_COMPLETE;
1481                 /* Force the midlayer to retry */
1482                 ts->stat = SAS_QUEUE_FULL;
1483                 pm8001_dev = ccb->device;
1484                 if (pm8001_dev)
1485                         pm8001_dev->running_req--;
1486                 spin_lock_irqsave(&t->task_state_lock, flags1);
1487                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1488                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1489                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1490                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1491                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1492                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1493                                 " done with event 0x%x resp 0x%x stat 0x%x but"
1494                                 " aborted by upper layer!\n",
1495                                 t, pw->handler, ts->resp, ts->stat));
1496                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1497                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1498                 } else {
1499                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1500                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1501                         mb();/* in order to force CPU ordering */
1502                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1503                         t->task_done(t);
1504                 }
1505         }       break;
1506         case IO_XFER_OPEN_RETRY_TIMEOUT:
1507         {       /* This one stashes the sas_task instead */
1508                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1509                 u32 tag;
1510                 struct pm8001_ccb_info *ccb;
1511                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1512                 unsigned long flags, flags1;
1513                 int i, ret = 0;
1514
1515                 PM8001_IO_DBG(pm8001_ha,
1516                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1517
1518                 ret = pm8001_query_task(t);
1519
1520                 PM8001_IO_DBG(pm8001_ha,
1521                         switch (ret) {
1522                         case TMF_RESP_FUNC_SUCC:
1523                                 pm8001_printk("...Task on lu\n");
1524                                 break;
1525
1526                         case TMF_RESP_FUNC_COMPLETE:
1527                                 pm8001_printk("...Task NOT on lu\n");
1528                                 break;
1529
1530                         default:
1531                                 pm8001_printk("...query task failed!!!\n");
1532                                 break;
1533                         });
1534
1535                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1536
1537                 spin_lock_irqsave(&t->task_state_lock, flags1);
1538
1539                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1540                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1541                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1542                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1543                                 (void)pm8001_abort_task(t);
1544                         break; /* Task got completed by another */
1545                 }
1546
1547                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1548
1549                 /* Search for a possible ccb that matches the task */
1550                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1551                         ccb = &pm8001_ha->ccb_info[i];
1552                         tag = ccb->ccb_tag;
1553                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1554                                 break;
1555                 }
1556                 if (!ccb) {
1557                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1558                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1559                                 (void)pm8001_abort_task(t);
1560                         break; /* Task got freed by another */
1561                 }
1562
1563                 pm8001_dev = ccb->device;
1564                 dev = pm8001_dev->sas_device;
1565
1566                 switch (ret) {
1567                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1568                         ccb->open_retry = 1; /* Snub completion */
1569                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1570                         ret = pm8001_abort_task(t);
1571                         ccb->open_retry = 0;
1572                         switch (ret) {
1573                         case TMF_RESP_FUNC_SUCC:
1574                         case TMF_RESP_FUNC_COMPLETE:
1575                                 break;
1576                         default: /* device misbehavior */
1577                                 ret = TMF_RESP_FUNC_FAILED;
1578                                 PM8001_IO_DBG(pm8001_ha,
1579                                         pm8001_printk("...Reset phy\n"));
1580                                 pm8001_I_T_nexus_reset(dev);
1581                                 break;
1582                         }
1583                         break;
1584
1585                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1586                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1587                         /* Do we need to abort the task locally? */
1588                         break;
1589
1590                 default: /* device misbehavior */
1591                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1592                         ret = TMF_RESP_FUNC_FAILED;
1593                         PM8001_IO_DBG(pm8001_ha,
1594                                 pm8001_printk("...Reset phy\n"));
1595                         pm8001_I_T_nexus_reset(dev);
1596                 }
1597
1598                 if (ret == TMF_RESP_FUNC_FAILED)
1599                         t = NULL;
1600                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1601                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1602         }       break;
1603         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1604                 dev = pm8001_dev->sas_device;
1605                 pm8001_I_T_nexus_reset(dev);
1606                 break;
1607         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1608                 dev = pm8001_dev->sas_device;
1609                 pm8001_I_T_nexus_reset(dev);
1610                 break;
1611         case IO_DS_IN_ERROR:
1612                 dev = pm8001_dev->sas_device;
1613                 pm8001_I_T_nexus_reset(dev);
1614                 break;
1615         case IO_DS_NON_OPERATIONAL:
1616                 dev = pm8001_dev->sas_device;
1617                 pm8001_I_T_nexus_reset(dev);
1618                 break;
1619         }
1620         kfree(pw);
1621 }
1622
1623 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1624                                int handler)
1625 {
1626         struct pm8001_work *pw;
1627         int ret = 0;
1628
1629         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1630         if (pw) {
1631                 pw->pm8001_ha = pm8001_ha;
1632                 pw->data = data;
1633                 pw->handler = handler;
1634                 INIT_WORK(&pw->work, pm8001_work_fn);
1635                 queue_work(pm8001_wq, &pw->work);
1636         } else
1637                 ret = -ENOMEM;
1638
1639         return ret;
1640 }
1641
1642 /**
1643  * mpi_ssp_completion- process the event that FW response to the SSP request.
1644  * @pm8001_ha: our hba card information
1645  * @piomb: the message contents of this outbound message.
1646  *
1647  * When FW has completed a ssp request for example a IO request, after it has
1648  * filled the SG data with the data, it will trigger this event represent
1649  * that he has finished the job,please check the coresponding buffer.
1650  * So we will tell the caller who maybe waiting the result to tell upper layer
1651  * that the task has been finished.
1652  */
1653 static void
1654 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1655 {
1656         struct sas_task *t;
1657         struct pm8001_ccb_info *ccb;
1658         unsigned long flags;
1659         u32 status;
1660         u32 param;
1661         u32 tag;
1662         struct ssp_completion_resp *psspPayload;
1663         struct task_status_struct *ts;
1664         struct ssp_response_iu *iu;
1665         struct pm8001_device *pm8001_dev;
1666         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1667         status = le32_to_cpu(psspPayload->status);
1668         tag = le32_to_cpu(psspPayload->tag);
1669         ccb = &pm8001_ha->ccb_info[tag];
1670         if ((status == IO_ABORTED) && ccb->open_retry) {
1671                 /* Being completed by another */
1672                 ccb->open_retry = 0;
1673                 return;
1674         }
1675         pm8001_dev = ccb->device;
1676         param = le32_to_cpu(psspPayload->param);
1677
1678         t = ccb->task;
1679
1680         if (status && status != IO_UNDERFLOW)
1681                 PM8001_FAIL_DBG(pm8001_ha,
1682                         pm8001_printk("sas IO status 0x%x\n", status));
1683         if (unlikely(!t || !t->lldd_task || !t->dev))
1684                 return;
1685         ts = &t->task_status;
1686         switch (status) {
1687         case IO_SUCCESS:
1688                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1689                         ",param = %d\n", param));
1690                 if (param == 0) {
1691                         ts->resp = SAS_TASK_COMPLETE;
1692                         ts->stat = SAM_STAT_GOOD;
1693                 } else {
1694                         ts->resp = SAS_TASK_COMPLETE;
1695                         ts->stat = SAS_PROTO_RESPONSE;
1696                         ts->residual = param;
1697                         iu = &psspPayload->ssp_resp_iu;
1698                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1699                 }
1700                 if (pm8001_dev)
1701                         pm8001_dev->running_req--;
1702                 break;
1703         case IO_ABORTED:
1704                 PM8001_IO_DBG(pm8001_ha,
1705                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1706                 ts->resp = SAS_TASK_COMPLETE;
1707                 ts->stat = SAS_ABORTED_TASK;
1708                 break;
1709         case IO_UNDERFLOW:
1710                 /* SSP Completion with error */
1711                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1712                         ",param = %d\n", param));
1713                 ts->resp = SAS_TASK_COMPLETE;
1714                 ts->stat = SAS_DATA_UNDERRUN;
1715                 ts->residual = param;
1716                 if (pm8001_dev)
1717                         pm8001_dev->running_req--;
1718                 break;
1719         case IO_NO_DEVICE:
1720                 PM8001_IO_DBG(pm8001_ha,
1721                         pm8001_printk("IO_NO_DEVICE\n"));
1722                 ts->resp = SAS_TASK_UNDELIVERED;
1723                 ts->stat = SAS_PHY_DOWN;
1724                 break;
1725         case IO_XFER_ERROR_BREAK:
1726                 PM8001_IO_DBG(pm8001_ha,
1727                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1728                 ts->resp = SAS_TASK_COMPLETE;
1729                 ts->stat = SAS_OPEN_REJECT;
1730                 /* Force the midlayer to retry */
1731                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1732                 break;
1733         case IO_XFER_ERROR_PHY_NOT_READY:
1734                 PM8001_IO_DBG(pm8001_ha,
1735                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1736                 ts->resp = SAS_TASK_COMPLETE;
1737                 ts->stat = SAS_OPEN_REJECT;
1738                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1739                 break;
1740         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1741                 PM8001_IO_DBG(pm8001_ha,
1742                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1743                 ts->resp = SAS_TASK_COMPLETE;
1744                 ts->stat = SAS_OPEN_REJECT;
1745                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1746                 break;
1747         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1748                 PM8001_IO_DBG(pm8001_ha,
1749                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1750                 ts->resp = SAS_TASK_COMPLETE;
1751                 ts->stat = SAS_OPEN_REJECT;
1752                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1753                 break;
1754         case IO_OPEN_CNX_ERROR_BREAK:
1755                 PM8001_IO_DBG(pm8001_ha,
1756                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1757                 ts->resp = SAS_TASK_COMPLETE;
1758                 ts->stat = SAS_OPEN_REJECT;
1759                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1760                 break;
1761         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1762                 PM8001_IO_DBG(pm8001_ha,
1763                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1764                 ts->resp = SAS_TASK_COMPLETE;
1765                 ts->stat = SAS_OPEN_REJECT;
1766                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1767                 if (!t->uldd_task)
1768                         pm8001_handle_event(pm8001_ha,
1769                                 pm8001_dev,
1770                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1771                 break;
1772         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1773                 PM8001_IO_DBG(pm8001_ha,
1774                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1775                 ts->resp = SAS_TASK_COMPLETE;
1776                 ts->stat = SAS_OPEN_REJECT;
1777                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1778                 break;
1779         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1780                 PM8001_IO_DBG(pm8001_ha,
1781                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1782                         "NOT_SUPPORTED\n"));
1783                 ts->resp = SAS_TASK_COMPLETE;
1784                 ts->stat = SAS_OPEN_REJECT;
1785                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1786                 break;
1787         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1788                 PM8001_IO_DBG(pm8001_ha,
1789                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1790                 ts->resp = SAS_TASK_UNDELIVERED;
1791                 ts->stat = SAS_OPEN_REJECT;
1792                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1793                 break;
1794         case IO_XFER_ERROR_NAK_RECEIVED:
1795                 PM8001_IO_DBG(pm8001_ha,
1796                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1797                 ts->resp = SAS_TASK_COMPLETE;
1798                 ts->stat = SAS_OPEN_REJECT;
1799                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1800                 break;
1801         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1802                 PM8001_IO_DBG(pm8001_ha,
1803                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1804                 ts->resp = SAS_TASK_COMPLETE;
1805                 ts->stat = SAS_NAK_R_ERR;
1806                 break;
1807         case IO_XFER_ERROR_DMA:
1808                 PM8001_IO_DBG(pm8001_ha,
1809                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1810                 ts->resp = SAS_TASK_COMPLETE;
1811                 ts->stat = SAS_OPEN_REJECT;
1812                 break;
1813         case IO_XFER_OPEN_RETRY_TIMEOUT:
1814                 PM8001_IO_DBG(pm8001_ha,
1815                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1816                 ts->resp = SAS_TASK_COMPLETE;
1817                 ts->stat = SAS_OPEN_REJECT;
1818                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1819                 break;
1820         case IO_XFER_ERROR_OFFSET_MISMATCH:
1821                 PM8001_IO_DBG(pm8001_ha,
1822                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1823                 ts->resp = SAS_TASK_COMPLETE;
1824                 ts->stat = SAS_OPEN_REJECT;
1825                 break;
1826         case IO_PORT_IN_RESET:
1827                 PM8001_IO_DBG(pm8001_ha,
1828                         pm8001_printk("IO_PORT_IN_RESET\n"));
1829                 ts->resp = SAS_TASK_COMPLETE;
1830                 ts->stat = SAS_OPEN_REJECT;
1831                 break;
1832         case IO_DS_NON_OPERATIONAL:
1833                 PM8001_IO_DBG(pm8001_ha,
1834                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1835                 ts->resp = SAS_TASK_COMPLETE;
1836                 ts->stat = SAS_OPEN_REJECT;
1837                 if (!t->uldd_task)
1838                         pm8001_handle_event(pm8001_ha,
1839                                 pm8001_dev,
1840                                 IO_DS_NON_OPERATIONAL);
1841                 break;
1842         case IO_DS_IN_RECOVERY:
1843                 PM8001_IO_DBG(pm8001_ha,
1844                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1845                 ts->resp = SAS_TASK_COMPLETE;
1846                 ts->stat = SAS_OPEN_REJECT;
1847                 break;
1848         case IO_TM_TAG_NOT_FOUND:
1849                 PM8001_IO_DBG(pm8001_ha,
1850                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1851                 ts->resp = SAS_TASK_COMPLETE;
1852                 ts->stat = SAS_OPEN_REJECT;
1853                 break;
1854         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1855                 PM8001_IO_DBG(pm8001_ha,
1856                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1857                 ts->resp = SAS_TASK_COMPLETE;
1858                 ts->stat = SAS_OPEN_REJECT;
1859                 break;
1860         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1861                 PM8001_IO_DBG(pm8001_ha,
1862                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1863                 ts->resp = SAS_TASK_COMPLETE;
1864                 ts->stat = SAS_OPEN_REJECT;
1865                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1866                 break;
1867         default:
1868                 PM8001_IO_DBG(pm8001_ha,
1869                         pm8001_printk("Unknown status 0x%x\n", status));
1870                 /* not allowed case. Therefore, return failed status */
1871                 ts->resp = SAS_TASK_COMPLETE;
1872                 ts->stat = SAS_OPEN_REJECT;
1873                 break;
1874         }
1875         PM8001_IO_DBG(pm8001_ha,
1876                 pm8001_printk("scsi_status = %x \n ",
1877                 psspPayload->ssp_resp_iu.status));
1878         spin_lock_irqsave(&t->task_state_lock, flags);
1879         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1880         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1881         t->task_state_flags |= SAS_TASK_STATE_DONE;
1882         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1883                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1884                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1885                         " io_status 0x%x resp 0x%x "
1886                         "stat 0x%x but aborted by upper layer!\n",
1887                         t, status, ts->resp, ts->stat));
1888                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1889         } else {
1890                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1891                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1892                 mb();/* in order to force CPU ordering */
1893                 t->task_done(t);
1894         }
1895 }
1896
1897 /*See the comments for mpi_ssp_completion */
1898 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1899 {
1900         struct sas_task *t;
1901         unsigned long flags;
1902         struct task_status_struct *ts;
1903         struct pm8001_ccb_info *ccb;
1904         struct pm8001_device *pm8001_dev;
1905         struct ssp_event_resp *psspPayload =
1906                 (struct ssp_event_resp *)(piomb + 4);
1907         u32 event = le32_to_cpu(psspPayload->event);
1908         u32 tag = le32_to_cpu(psspPayload->tag);
1909         u32 port_id = le32_to_cpu(psspPayload->port_id);
1910         u32 dev_id = le32_to_cpu(psspPayload->device_id);
1911
1912         ccb = &pm8001_ha->ccb_info[tag];
1913         t = ccb->task;
1914         pm8001_dev = ccb->device;
1915         if (event)
1916                 PM8001_FAIL_DBG(pm8001_ha,
1917                         pm8001_printk("sas IO status 0x%x\n", event));
1918         if (unlikely(!t || !t->lldd_task || !t->dev))
1919                 return;
1920         ts = &t->task_status;
1921         PM8001_IO_DBG(pm8001_ha,
1922                 pm8001_printk("port_id = %x,device_id = %x\n",
1923                 port_id, dev_id));
1924         switch (event) {
1925         case IO_OVERFLOW:
1926                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1927                 ts->resp = SAS_TASK_COMPLETE;
1928                 ts->stat = SAS_DATA_OVERRUN;
1929                 ts->residual = 0;
1930                 if (pm8001_dev)
1931                         pm8001_dev->running_req--;
1932                 break;
1933         case IO_XFER_ERROR_BREAK:
1934                 PM8001_IO_DBG(pm8001_ha,
1935                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1936                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1937                 return;
1938         case IO_XFER_ERROR_PHY_NOT_READY:
1939                 PM8001_IO_DBG(pm8001_ha,
1940                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1941                 ts->resp = SAS_TASK_COMPLETE;
1942                 ts->stat = SAS_OPEN_REJECT;
1943                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1944                 break;
1945         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1946                 PM8001_IO_DBG(pm8001_ha,
1947                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1948                         "_SUPPORTED\n"));
1949                 ts->resp = SAS_TASK_COMPLETE;
1950                 ts->stat = SAS_OPEN_REJECT;
1951                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1952                 break;
1953         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1954                 PM8001_IO_DBG(pm8001_ha,
1955                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1956                 ts->resp = SAS_TASK_COMPLETE;
1957                 ts->stat = SAS_OPEN_REJECT;
1958                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1959                 break;
1960         case IO_OPEN_CNX_ERROR_BREAK:
1961                 PM8001_IO_DBG(pm8001_ha,
1962                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1963                 ts->resp = SAS_TASK_COMPLETE;
1964                 ts->stat = SAS_OPEN_REJECT;
1965                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1966                 break;
1967         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1968                 PM8001_IO_DBG(pm8001_ha,
1969                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1970                 ts->resp = SAS_TASK_COMPLETE;
1971                 ts->stat = SAS_OPEN_REJECT;
1972                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1973                 if (!t->uldd_task)
1974                         pm8001_handle_event(pm8001_ha,
1975                                 pm8001_dev,
1976                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1977                 break;
1978         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1979                 PM8001_IO_DBG(pm8001_ha,
1980                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1981                 ts->resp = SAS_TASK_COMPLETE;
1982                 ts->stat = SAS_OPEN_REJECT;
1983                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1984                 break;
1985         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1986                 PM8001_IO_DBG(pm8001_ha,
1987                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1988                         "NOT_SUPPORTED\n"));
1989                 ts->resp = SAS_TASK_COMPLETE;
1990                 ts->stat = SAS_OPEN_REJECT;
1991                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1992                 break;
1993         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1994                 PM8001_IO_DBG(pm8001_ha,
1995                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1996                 ts->resp = SAS_TASK_COMPLETE;
1997                 ts->stat = SAS_OPEN_REJECT;
1998                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1999                 break;
2000         case IO_XFER_ERROR_NAK_RECEIVED:
2001                 PM8001_IO_DBG(pm8001_ha,
2002                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2003                 ts->resp = SAS_TASK_COMPLETE;
2004                 ts->stat = SAS_OPEN_REJECT;
2005                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2006                 break;
2007         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2008                 PM8001_IO_DBG(pm8001_ha,
2009                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2010                 ts->resp = SAS_TASK_COMPLETE;
2011                 ts->stat = SAS_NAK_R_ERR;
2012                 break;
2013         case IO_XFER_OPEN_RETRY_TIMEOUT:
2014                 PM8001_IO_DBG(pm8001_ha,
2015                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2016                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2017                 return;
2018         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2019                 PM8001_IO_DBG(pm8001_ha,
2020                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2021                 ts->resp = SAS_TASK_COMPLETE;
2022                 ts->stat = SAS_DATA_OVERRUN;
2023                 break;
2024         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2025                 PM8001_IO_DBG(pm8001_ha,
2026                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2027                 ts->resp = SAS_TASK_COMPLETE;
2028                 ts->stat = SAS_DATA_OVERRUN;
2029                 break;
2030         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2031                 PM8001_IO_DBG(pm8001_ha,
2032                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2033                 ts->resp = SAS_TASK_COMPLETE;
2034                 ts->stat = SAS_DATA_OVERRUN;
2035                 break;
2036         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2037                 PM8001_IO_DBG(pm8001_ha,
2038                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2039                 ts->resp = SAS_TASK_COMPLETE;
2040                 ts->stat = SAS_DATA_OVERRUN;
2041                 break;
2042         case IO_XFER_ERROR_OFFSET_MISMATCH:
2043                 PM8001_IO_DBG(pm8001_ha,
2044                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2045                 ts->resp = SAS_TASK_COMPLETE;
2046                 ts->stat = SAS_DATA_OVERRUN;
2047                 break;
2048         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2049                 PM8001_IO_DBG(pm8001_ha,
2050                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2051                 ts->resp = SAS_TASK_COMPLETE;
2052                 ts->stat = SAS_DATA_OVERRUN;
2053                 break;
2054         case IO_XFER_CMD_FRAME_ISSUED:
2055                 PM8001_IO_DBG(pm8001_ha,
2056                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
2057                 return;
2058         default:
2059                 PM8001_IO_DBG(pm8001_ha,
2060                         pm8001_printk("Unknown status 0x%x\n", event));
2061                 /* not allowed case. Therefore, return failed status */
2062                 ts->resp = SAS_TASK_COMPLETE;
2063                 ts->stat = SAS_DATA_OVERRUN;
2064                 break;
2065         }
2066         spin_lock_irqsave(&t->task_state_lock, flags);
2067         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2068         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2069         t->task_state_flags |= SAS_TASK_STATE_DONE;
2070         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2071                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2072                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2073                         " event 0x%x resp 0x%x "
2074                         "stat 0x%x but aborted by upper layer!\n",
2075                         t, event, ts->resp, ts->stat));
2076                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2077         } else {
2078                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2079                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2080                 mb();/* in order to force CPU ordering */
2081                 t->task_done(t);
2082         }
2083 }
2084
2085 /*See the comments for mpi_ssp_completion */
2086 static void
2087 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2088 {
2089         struct sas_task *t;
2090         struct pm8001_ccb_info *ccb;
2091         u32 param;
2092         u32 status;
2093         u32 tag;
2094         struct sata_completion_resp *psataPayload;
2095         struct task_status_struct *ts;
2096         struct ata_task_resp *resp ;
2097         u32 *sata_resp;
2098         struct pm8001_device *pm8001_dev;
2099         unsigned long flags;
2100
2101         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2102         status = le32_to_cpu(psataPayload->status);
2103         tag = le32_to_cpu(psataPayload->tag);
2104
2105         ccb = &pm8001_ha->ccb_info[tag];
2106         param = le32_to_cpu(psataPayload->param);
2107         t = ccb->task;
2108         ts = &t->task_status;
2109         pm8001_dev = ccb->device;
2110         if (status)
2111                 PM8001_FAIL_DBG(pm8001_ha,
2112                         pm8001_printk("sata IO status 0x%x\n", status));
2113         if (unlikely(!t || !t->lldd_task || !t->dev))
2114                 return;
2115
2116         switch (status) {
2117         case IO_SUCCESS:
2118                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2119                 if (param == 0) {
2120                         ts->resp = SAS_TASK_COMPLETE;
2121                         ts->stat = SAM_STAT_GOOD;
2122                 } else {
2123                         u8 len;
2124                         ts->resp = SAS_TASK_COMPLETE;
2125                         ts->stat = SAS_PROTO_RESPONSE;
2126                         ts->residual = param;
2127                         PM8001_IO_DBG(pm8001_ha,
2128                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2129                                 param));
2130                         sata_resp = &psataPayload->sata_resp[0];
2131                         resp = (struct ata_task_resp *)ts->buf;
2132                         if (t->ata_task.dma_xfer == 0 &&
2133                         t->data_dir == PCI_DMA_FROMDEVICE) {
2134                                 len = sizeof(struct pio_setup_fis);
2135                                 PM8001_IO_DBG(pm8001_ha,
2136                                 pm8001_printk("PIO read len = %d\n", len));
2137                         } else if (t->ata_task.use_ncq) {
2138                                 len = sizeof(struct set_dev_bits_fis);
2139                                 PM8001_IO_DBG(pm8001_ha,
2140                                         pm8001_printk("FPDMA len = %d\n", len));
2141                         } else {
2142                                 len = sizeof(struct dev_to_host_fis);
2143                                 PM8001_IO_DBG(pm8001_ha,
2144                                 pm8001_printk("other len = %d\n", len));
2145                         }
2146                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2147                                 resp->frame_len = len;
2148                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2149                                 ts->buf_valid_size = sizeof(*resp);
2150                         } else
2151                                 PM8001_IO_DBG(pm8001_ha,
2152                                         pm8001_printk("response to large\n"));
2153                 }
2154                 if (pm8001_dev)
2155                         pm8001_dev->running_req--;
2156                 break;
2157         case IO_ABORTED:
2158                 PM8001_IO_DBG(pm8001_ha,
2159                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2160                 ts->resp = SAS_TASK_COMPLETE;
2161                 ts->stat = SAS_ABORTED_TASK;
2162                 if (pm8001_dev)
2163                         pm8001_dev->running_req--;
2164                 break;
2165                 /* following cases are to do cases */
2166         case IO_UNDERFLOW:
2167                 /* SATA Completion with error */
2168                 PM8001_IO_DBG(pm8001_ha,
2169                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2170                 ts->resp = SAS_TASK_COMPLETE;
2171                 ts->stat = SAS_DATA_UNDERRUN;
2172                 ts->residual =  param;
2173                 if (pm8001_dev)
2174                         pm8001_dev->running_req--;
2175                 break;
2176         case IO_NO_DEVICE:
2177                 PM8001_IO_DBG(pm8001_ha,
2178                         pm8001_printk("IO_NO_DEVICE\n"));
2179                 ts->resp = SAS_TASK_UNDELIVERED;
2180                 ts->stat = SAS_PHY_DOWN;
2181                 break;
2182         case IO_XFER_ERROR_BREAK:
2183                 PM8001_IO_DBG(pm8001_ha,
2184                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2185                 ts->resp = SAS_TASK_COMPLETE;
2186                 ts->stat = SAS_INTERRUPTED;
2187                 break;
2188         case IO_XFER_ERROR_PHY_NOT_READY:
2189                 PM8001_IO_DBG(pm8001_ha,
2190                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2191                 ts->resp = SAS_TASK_COMPLETE;
2192                 ts->stat = SAS_OPEN_REJECT;
2193                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2194                 break;
2195         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2196                 PM8001_IO_DBG(pm8001_ha,
2197                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2198                         "_SUPPORTED\n"));
2199                 ts->resp = SAS_TASK_COMPLETE;
2200                 ts->stat = SAS_OPEN_REJECT;
2201                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2202                 break;
2203         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2204                 PM8001_IO_DBG(pm8001_ha,
2205                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2206                 ts->resp = SAS_TASK_COMPLETE;
2207                 ts->stat = SAS_OPEN_REJECT;
2208                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2209                 break;
2210         case IO_OPEN_CNX_ERROR_BREAK:
2211                 PM8001_IO_DBG(pm8001_ha,
2212                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2213                 ts->resp = SAS_TASK_COMPLETE;
2214                 ts->stat = SAS_OPEN_REJECT;
2215                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2216                 break;
2217         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2218                 PM8001_IO_DBG(pm8001_ha,
2219                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2220                 ts->resp = SAS_TASK_COMPLETE;
2221                 ts->stat = SAS_DEV_NO_RESPONSE;
2222                 if (!t->uldd_task) {
2223                         pm8001_handle_event(pm8001_ha,
2224                                 pm8001_dev,
2225                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2226                         ts->resp = SAS_TASK_UNDELIVERED;
2227                         ts->stat = SAS_QUEUE_FULL;
2228                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2229                         mb();/*in order to force CPU ordering*/
2230                         spin_unlock_irq(&pm8001_ha->lock);
2231                         t->task_done(t);
2232                         spin_lock_irq(&pm8001_ha->lock);
2233                         return;
2234                 }
2235                 break;
2236         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2237                 PM8001_IO_DBG(pm8001_ha,
2238                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2239                 ts->resp = SAS_TASK_UNDELIVERED;
2240                 ts->stat = SAS_OPEN_REJECT;
2241                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2242                 if (!t->uldd_task) {
2243                         pm8001_handle_event(pm8001_ha,
2244                                 pm8001_dev,
2245                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2246                         ts->resp = SAS_TASK_UNDELIVERED;
2247                         ts->stat = SAS_QUEUE_FULL;
2248                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2249                         mb();/*ditto*/
2250                         spin_unlock_irq(&pm8001_ha->lock);
2251                         t->task_done(t);
2252                         spin_lock_irq(&pm8001_ha->lock);
2253                         return;
2254                 }
2255                 break;
2256         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2257                 PM8001_IO_DBG(pm8001_ha,
2258                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2259                         "NOT_SUPPORTED\n"));
2260                 ts->resp = SAS_TASK_COMPLETE;
2261                 ts->stat = SAS_OPEN_REJECT;
2262                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2263                 break;
2264         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2265                 PM8001_IO_DBG(pm8001_ha,
2266                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2267                         "_BUSY\n"));
2268                 ts->resp = SAS_TASK_COMPLETE;
2269                 ts->stat = SAS_DEV_NO_RESPONSE;
2270                 if (!t->uldd_task) {
2271                         pm8001_handle_event(pm8001_ha,
2272                                 pm8001_dev,
2273                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2274                         ts->resp = SAS_TASK_UNDELIVERED;
2275                         ts->stat = SAS_QUEUE_FULL;
2276                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2277                         mb();/* ditto*/
2278                         spin_unlock_irq(&pm8001_ha->lock);
2279                         t->task_done(t);
2280                         spin_lock_irq(&pm8001_ha->lock);
2281                         return;
2282                 }
2283                 break;
2284         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2285                 PM8001_IO_DBG(pm8001_ha,
2286                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2287                 ts->resp = SAS_TASK_COMPLETE;
2288                 ts->stat = SAS_OPEN_REJECT;
2289                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2290                 break;
2291         case IO_XFER_ERROR_NAK_RECEIVED:
2292                 PM8001_IO_DBG(pm8001_ha,
2293                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2294                 ts->resp = SAS_TASK_COMPLETE;
2295                 ts->stat = SAS_NAK_R_ERR;
2296                 break;
2297         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2298                 PM8001_IO_DBG(pm8001_ha,
2299                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2300                 ts->resp = SAS_TASK_COMPLETE;
2301                 ts->stat = SAS_NAK_R_ERR;
2302                 break;
2303         case IO_XFER_ERROR_DMA:
2304                 PM8001_IO_DBG(pm8001_ha,
2305                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2306                 ts->resp = SAS_TASK_COMPLETE;
2307                 ts->stat = SAS_ABORTED_TASK;
2308                 break;
2309         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2310                 PM8001_IO_DBG(pm8001_ha,
2311                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2312                 ts->resp = SAS_TASK_UNDELIVERED;
2313                 ts->stat = SAS_DEV_NO_RESPONSE;
2314                 break;
2315         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2316                 PM8001_IO_DBG(pm8001_ha,
2317                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2318                 ts->resp = SAS_TASK_COMPLETE;
2319                 ts->stat = SAS_DATA_UNDERRUN;
2320                 break;
2321         case IO_XFER_OPEN_RETRY_TIMEOUT:
2322                 PM8001_IO_DBG(pm8001_ha,
2323                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2324                 ts->resp = SAS_TASK_COMPLETE;
2325                 ts->stat = SAS_OPEN_TO;
2326                 break;
2327         case IO_PORT_IN_RESET:
2328                 PM8001_IO_DBG(pm8001_ha,
2329                         pm8001_printk("IO_PORT_IN_RESET\n"));
2330                 ts->resp = SAS_TASK_COMPLETE;
2331                 ts->stat = SAS_DEV_NO_RESPONSE;
2332                 break;
2333         case IO_DS_NON_OPERATIONAL:
2334                 PM8001_IO_DBG(pm8001_ha,
2335                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2336                 ts->resp = SAS_TASK_COMPLETE;
2337                 ts->stat = SAS_DEV_NO_RESPONSE;
2338                 if (!t->uldd_task) {
2339                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2340                                     IO_DS_NON_OPERATIONAL);
2341                         ts->resp = SAS_TASK_UNDELIVERED;
2342                         ts->stat = SAS_QUEUE_FULL;
2343                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2344                         mb();/*ditto*/
2345                         spin_unlock_irq(&pm8001_ha->lock);
2346                         t->task_done(t);
2347                         spin_lock_irq(&pm8001_ha->lock);
2348                         return;
2349                 }
2350                 break;
2351         case IO_DS_IN_RECOVERY:
2352                 PM8001_IO_DBG(pm8001_ha,
2353                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2354                 ts->resp = SAS_TASK_COMPLETE;
2355                 ts->stat = SAS_DEV_NO_RESPONSE;
2356                 break;
2357         case IO_DS_IN_ERROR:
2358                 PM8001_IO_DBG(pm8001_ha,
2359                         pm8001_printk("IO_DS_IN_ERROR\n"));
2360                 ts->resp = SAS_TASK_COMPLETE;
2361                 ts->stat = SAS_DEV_NO_RESPONSE;
2362                 if (!t->uldd_task) {
2363                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2364                                     IO_DS_IN_ERROR);
2365                         ts->resp = SAS_TASK_UNDELIVERED;
2366                         ts->stat = SAS_QUEUE_FULL;
2367                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2368                         mb();/*ditto*/
2369                         spin_unlock_irq(&pm8001_ha->lock);
2370                         t->task_done(t);
2371                         spin_lock_irq(&pm8001_ha->lock);
2372                         return;
2373                 }
2374                 break;
2375         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2376                 PM8001_IO_DBG(pm8001_ha,
2377                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2378                 ts->resp = SAS_TASK_COMPLETE;
2379                 ts->stat = SAS_OPEN_REJECT;
2380                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2381         default:
2382                 PM8001_IO_DBG(pm8001_ha,
2383                         pm8001_printk("Unknown status 0x%x\n", status));
2384                 /* not allowed case. Therefore, return failed status */
2385                 ts->resp = SAS_TASK_COMPLETE;
2386                 ts->stat = SAS_DEV_NO_RESPONSE;
2387                 break;
2388         }
2389         spin_lock_irqsave(&t->task_state_lock, flags);
2390         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2391         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2392         t->task_state_flags |= SAS_TASK_STATE_DONE;
2393         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2394                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2395                 PM8001_FAIL_DBG(pm8001_ha,
2396                         pm8001_printk("task 0x%p done with io_status 0x%x"
2397                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2398                         t, status, ts->resp, ts->stat));
2399                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2400         } else if (t->uldd_task) {
2401                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2402                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2403                 mb();/* ditto */
2404                 spin_unlock_irq(&pm8001_ha->lock);
2405                 t->task_done(t);
2406                 spin_lock_irq(&pm8001_ha->lock);
2407         } else if (!t->uldd_task) {
2408                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2409                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2410                 mb();/*ditto*/
2411                 spin_unlock_irq(&pm8001_ha->lock);
2412                 t->task_done(t);
2413                 spin_lock_irq(&pm8001_ha->lock);
2414         }
2415 }
2416
2417 /*See the comments for mpi_ssp_completion */
2418 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2419 {
2420         struct sas_task *t;
2421         struct task_status_struct *ts;
2422         struct pm8001_ccb_info *ccb;
2423         struct pm8001_device *pm8001_dev;
2424         struct sata_event_resp *psataPayload =
2425                 (struct sata_event_resp *)(piomb + 4);
2426         u32 event = le32_to_cpu(psataPayload->event);
2427         u32 tag = le32_to_cpu(psataPayload->tag);
2428         u32 port_id = le32_to_cpu(psataPayload->port_id);
2429         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2430         unsigned long flags;
2431
2432         ccb = &pm8001_ha->ccb_info[tag];
2433         t = ccb->task;
2434         pm8001_dev = ccb->device;
2435         if (event)
2436                 PM8001_FAIL_DBG(pm8001_ha,
2437                         pm8001_printk("sata IO status 0x%x\n", event));
2438         if (unlikely(!t || !t->lldd_task || !t->dev))
2439                 return;
2440         ts = &t->task_status;
2441         PM8001_IO_DBG(pm8001_ha,
2442                 pm8001_printk("port_id = %x,device_id = %x\n",
2443                 port_id, dev_id));
2444         switch (event) {
2445         case IO_OVERFLOW:
2446                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2447                 ts->resp = SAS_TASK_COMPLETE;
2448                 ts->stat = SAS_DATA_OVERRUN;
2449                 ts->residual = 0;
2450                 if (pm8001_dev)
2451                         pm8001_dev->running_req--;
2452                 break;
2453         case IO_XFER_ERROR_BREAK:
2454                 PM8001_IO_DBG(pm8001_ha,
2455                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2456                 ts->resp = SAS_TASK_COMPLETE;
2457                 ts->stat = SAS_INTERRUPTED;
2458                 break;
2459         case IO_XFER_ERROR_PHY_NOT_READY:
2460                 PM8001_IO_DBG(pm8001_ha,
2461                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2462                 ts->resp = SAS_TASK_COMPLETE;
2463                 ts->stat = SAS_OPEN_REJECT;
2464                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2465                 break;
2466         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2467                 PM8001_IO_DBG(pm8001_ha,
2468                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2469                         "_SUPPORTED\n"));
2470                 ts->resp = SAS_TASK_COMPLETE;
2471                 ts->stat = SAS_OPEN_REJECT;
2472                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2473                 break;
2474         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2475                 PM8001_IO_DBG(pm8001_ha,
2476                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2477                 ts->resp = SAS_TASK_COMPLETE;
2478                 ts->stat = SAS_OPEN_REJECT;
2479                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2480                 break;
2481         case IO_OPEN_CNX_ERROR_BREAK:
2482                 PM8001_IO_DBG(pm8001_ha,
2483                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2484                 ts->resp = SAS_TASK_COMPLETE;
2485                 ts->stat = SAS_OPEN_REJECT;
2486                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2487                 break;
2488         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2489                 PM8001_IO_DBG(pm8001_ha,
2490                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2491                 ts->resp = SAS_TASK_UNDELIVERED;
2492                 ts->stat = SAS_DEV_NO_RESPONSE;
2493                 if (!t->uldd_task) {
2494                         pm8001_handle_event(pm8001_ha,
2495                                 pm8001_dev,
2496                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2497                         ts->resp = SAS_TASK_COMPLETE;
2498                         ts->stat = SAS_QUEUE_FULL;
2499                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2500                         mb();/*ditto*/
2501                         spin_unlock_irq(&pm8001_ha->lock);
2502                         t->task_done(t);
2503                         spin_lock_irq(&pm8001_ha->lock);
2504                         return;
2505                 }
2506                 break;
2507         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2508                 PM8001_IO_DBG(pm8001_ha,
2509                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2510                 ts->resp = SAS_TASK_UNDELIVERED;
2511                 ts->stat = SAS_OPEN_REJECT;
2512                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2513                 break;
2514         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2515                 PM8001_IO_DBG(pm8001_ha,
2516                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2517                         "NOT_SUPPORTED\n"));
2518                 ts->resp = SAS_TASK_COMPLETE;
2519                 ts->stat = SAS_OPEN_REJECT;
2520                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2521                 break;
2522         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2523                 PM8001_IO_DBG(pm8001_ha,
2524                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2525                 ts->resp = SAS_TASK_COMPLETE;
2526                 ts->stat = SAS_OPEN_REJECT;
2527                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2528                 break;
2529         case IO_XFER_ERROR_NAK_RECEIVED:
2530                 PM8001_IO_DBG(pm8001_ha,
2531                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2532                 ts->resp = SAS_TASK_COMPLETE;
2533                 ts->stat = SAS_NAK_R_ERR;
2534                 break;
2535         case IO_XFER_ERROR_PEER_ABORTED:
2536                 PM8001_IO_DBG(pm8001_ha,
2537                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2538                 ts->resp = SAS_TASK_COMPLETE;
2539                 ts->stat = SAS_NAK_R_ERR;
2540                 break;
2541         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2542                 PM8001_IO_DBG(pm8001_ha,
2543                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2544                 ts->resp = SAS_TASK_COMPLETE;
2545                 ts->stat = SAS_DATA_UNDERRUN;
2546                 break;
2547         case IO_XFER_OPEN_RETRY_TIMEOUT:
2548                 PM8001_IO_DBG(pm8001_ha,
2549                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2550                 ts->resp = SAS_TASK_COMPLETE;
2551                 ts->stat = SAS_OPEN_TO;
2552                 break;
2553         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2554                 PM8001_IO_DBG(pm8001_ha,
2555                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2556                 ts->resp = SAS_TASK_COMPLETE;
2557                 ts->stat = SAS_OPEN_TO;
2558                 break;
2559         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2560                 PM8001_IO_DBG(pm8001_ha,
2561                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2562                 ts->resp = SAS_TASK_COMPLETE;
2563                 ts->stat = SAS_OPEN_TO;
2564                 break;
2565         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2566                 PM8001_IO_DBG(pm8001_ha,
2567                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2568                 ts->resp = SAS_TASK_COMPLETE;
2569                 ts->stat = SAS_OPEN_TO;
2570                 break;
2571         case IO_XFER_ERROR_OFFSET_MISMATCH:
2572                 PM8001_IO_DBG(pm8001_ha,
2573                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2574                 ts->resp = SAS_TASK_COMPLETE;
2575                 ts->stat = SAS_OPEN_TO;
2576                 break;
2577         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2578                 PM8001_IO_DBG(pm8001_ha,
2579                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2580                 ts->resp = SAS_TASK_COMPLETE;
2581                 ts->stat = SAS_OPEN_TO;
2582                 break;
2583         case IO_XFER_CMD_FRAME_ISSUED:
2584                 PM8001_IO_DBG(pm8001_ha,
2585                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2586                 break;
2587         case IO_XFER_PIO_SETUP_ERROR:
2588                 PM8001_IO_DBG(pm8001_ha,
2589                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2590                 ts->resp = SAS_TASK_COMPLETE;
2591                 ts->stat = SAS_OPEN_TO;
2592                 break;
2593         default:
2594                 PM8001_IO_DBG(pm8001_ha,
2595                         pm8001_printk("Unknown status 0x%x\n", event));
2596                 /* not allowed case. Therefore, return failed status */
2597                 ts->resp = SAS_TASK_COMPLETE;
2598                 ts->stat = SAS_OPEN_TO;
2599                 break;
2600         }
2601         spin_lock_irqsave(&t->task_state_lock, flags);
2602         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2603         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2604         t->task_state_flags |= SAS_TASK_STATE_DONE;
2605         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2606                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2607                 PM8001_FAIL_DBG(pm8001_ha,
2608                         pm8001_printk("task 0x%p done with io_status 0x%x"
2609                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2610                         t, event, ts->resp, ts->stat));
2611                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2612         } else if (t->uldd_task) {
2613                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2614                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2615                 mb();/* ditto */
2616                 spin_unlock_irq(&pm8001_ha->lock);
2617                 t->task_done(t);
2618                 spin_lock_irq(&pm8001_ha->lock);
2619         } else if (!t->uldd_task) {
2620                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2621                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2622                 mb();/*ditto*/
2623                 spin_unlock_irq(&pm8001_ha->lock);
2624                 t->task_done(t);
2625                 spin_lock_irq(&pm8001_ha->lock);
2626         }
2627 }
2628
2629 /*See the comments for mpi_ssp_completion */
2630 static void
2631 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2632 {
2633         u32 param;
2634         struct sas_task *t;
2635         struct pm8001_ccb_info *ccb;
2636         unsigned long flags;
2637         u32 status;
2638         u32 tag;
2639         struct smp_completion_resp *psmpPayload;
2640         struct task_status_struct *ts;
2641         struct pm8001_device *pm8001_dev;
2642
2643         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2644         status = le32_to_cpu(psmpPayload->status);
2645         tag = le32_to_cpu(psmpPayload->tag);
2646
2647         ccb = &pm8001_ha->ccb_info[tag];
2648         param = le32_to_cpu(psmpPayload->param);
2649         t = ccb->task;
2650         ts = &t->task_status;
2651         pm8001_dev = ccb->device;
2652         if (status)
2653                 PM8001_FAIL_DBG(pm8001_ha,
2654                         pm8001_printk("smp IO status 0x%x\n", status));
2655         if (unlikely(!t || !t->lldd_task || !t->dev))
2656                 return;
2657
2658         switch (status) {
2659         case IO_SUCCESS:
2660                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2661                 ts->resp = SAS_TASK_COMPLETE;
2662                 ts->stat = SAM_STAT_GOOD;
2663         if (pm8001_dev)
2664                         pm8001_dev->running_req--;
2665                 break;
2666         case IO_ABORTED:
2667                 PM8001_IO_DBG(pm8001_ha,
2668                         pm8001_printk("IO_ABORTED IOMB\n"));
2669                 ts->resp = SAS_TASK_COMPLETE;
2670                 ts->stat = SAS_ABORTED_TASK;
2671                 if (pm8001_dev)
2672                         pm8001_dev->running_req--;
2673                 break;
2674         case IO_OVERFLOW:
2675                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2676                 ts->resp = SAS_TASK_COMPLETE;
2677                 ts->stat = SAS_DATA_OVERRUN;
2678                 ts->residual = 0;
2679                 if (pm8001_dev)
2680                         pm8001_dev->running_req--;
2681                 break;
2682         case IO_NO_DEVICE:
2683                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2684                 ts->resp = SAS_TASK_COMPLETE;
2685                 ts->stat = SAS_PHY_DOWN;
2686                 break;
2687         case IO_ERROR_HW_TIMEOUT:
2688                 PM8001_IO_DBG(pm8001_ha,
2689                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2690                 ts->resp = SAS_TASK_COMPLETE;
2691                 ts->stat = SAM_STAT_BUSY;
2692                 break;
2693         case IO_XFER_ERROR_BREAK:
2694                 PM8001_IO_DBG(pm8001_ha,
2695                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2696                 ts->resp = SAS_TASK_COMPLETE;
2697                 ts->stat = SAM_STAT_BUSY;
2698                 break;
2699         case IO_XFER_ERROR_PHY_NOT_READY:
2700                 PM8001_IO_DBG(pm8001_ha,
2701                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2702                 ts->resp = SAS_TASK_COMPLETE;
2703                 ts->stat = SAM_STAT_BUSY;
2704                 break;
2705         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2706                 PM8001_IO_DBG(pm8001_ha,
2707                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2708                 ts->resp = SAS_TASK_COMPLETE;
2709                 ts->stat = SAS_OPEN_REJECT;
2710                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2711                 break;
2712         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2713                 PM8001_IO_DBG(pm8001_ha,
2714                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2715                 ts->resp = SAS_TASK_COMPLETE;
2716                 ts->stat = SAS_OPEN_REJECT;
2717                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2718                 break;
2719         case IO_OPEN_CNX_ERROR_BREAK:
2720                 PM8001_IO_DBG(pm8001_ha,
2721                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2722                 ts->resp = SAS_TASK_COMPLETE;
2723                 ts->stat = SAS_OPEN_REJECT;
2724                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2725                 break;
2726         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2727                 PM8001_IO_DBG(pm8001_ha,
2728                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2729                 ts->resp = SAS_TASK_COMPLETE;
2730                 ts->stat = SAS_OPEN_REJECT;
2731                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2732                 pm8001_handle_event(pm8001_ha,
2733                                 pm8001_dev,
2734                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2735                 break;
2736         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2737                 PM8001_IO_DBG(pm8001_ha,
2738                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2739                 ts->resp = SAS_TASK_COMPLETE;
2740                 ts->stat = SAS_OPEN_REJECT;
2741                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2742                 break;
2743         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2744                 PM8001_IO_DBG(pm8001_ha,
2745                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2746                         "NOT_SUPPORTED\n"));
2747                 ts->resp = SAS_TASK_COMPLETE;
2748                 ts->stat = SAS_OPEN_REJECT;
2749                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2750                 break;
2751         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2752                 PM8001_IO_DBG(pm8001_ha,
2753                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2754                 ts->resp = SAS_TASK_COMPLETE;
2755                 ts->stat = SAS_OPEN_REJECT;
2756                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2757                 break;
2758         case IO_XFER_ERROR_RX_FRAME:
2759                 PM8001_IO_DBG(pm8001_ha,
2760                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2761                 ts->resp = SAS_TASK_COMPLETE;
2762                 ts->stat = SAS_DEV_NO_RESPONSE;
2763                 break;
2764         case IO_XFER_OPEN_RETRY_TIMEOUT:
2765                 PM8001_IO_DBG(pm8001_ha,
2766                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2767                 ts->resp = SAS_TASK_COMPLETE;
2768                 ts->stat = SAS_OPEN_REJECT;
2769                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2770                 break;
2771         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2772                 PM8001_IO_DBG(pm8001_ha,
2773                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2774                 ts->resp = SAS_TASK_COMPLETE;
2775                 ts->stat = SAS_QUEUE_FULL;
2776                 break;
2777         case IO_PORT_IN_RESET:
2778                 PM8001_IO_DBG(pm8001_ha,
2779                         pm8001_printk("IO_PORT_IN_RESET\n"));
2780                 ts->resp = SAS_TASK_COMPLETE;
2781                 ts->stat = SAS_OPEN_REJECT;
2782                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2783                 break;
2784         case IO_DS_NON_OPERATIONAL:
2785                 PM8001_IO_DBG(pm8001_ha,
2786                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2787                 ts->resp = SAS_TASK_COMPLETE;
2788                 ts->stat = SAS_DEV_NO_RESPONSE;
2789                 break;
2790         case IO_DS_IN_RECOVERY:
2791                 PM8001_IO_DBG(pm8001_ha,
2792                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2793                 ts->resp = SAS_TASK_COMPLETE;
2794                 ts->stat = SAS_OPEN_REJECT;
2795                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2796                 break;
2797         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2798                 PM8001_IO_DBG(pm8001_ha,
2799                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2800                 ts->resp = SAS_TASK_COMPLETE;
2801                 ts->stat = SAS_OPEN_REJECT;
2802                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2803                 break;
2804         default:
2805                 PM8001_IO_DBG(pm8001_ha,
2806                         pm8001_printk("Unknown status 0x%x\n", status));
2807                 ts->resp = SAS_TASK_COMPLETE;
2808                 ts->stat = SAS_DEV_NO_RESPONSE;
2809                 /* not allowed case. Therefore, return failed status */
2810                 break;
2811         }
2812         spin_lock_irqsave(&t->task_state_lock, flags);
2813         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2814         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2815         t->task_state_flags |= SAS_TASK_STATE_DONE;
2816         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2817                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2818                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2819                         " io_status 0x%x resp 0x%x "
2820                         "stat 0x%x but aborted by upper layer!\n",
2821                         t, status, ts->resp, ts->stat));
2822                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2823         } else {
2824                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2825                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2826                 mb();/* in order to force CPU ordering */
2827                 t->task_done(t);
2828         }
2829 }
2830
2831 static void
2832 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2833 {
2834         struct set_dev_state_resp *pPayload =
2835                 (struct set_dev_state_resp *)(piomb + 4);
2836         u32 tag = le32_to_cpu(pPayload->tag);
2837         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2838         struct pm8001_device *pm8001_dev = ccb->device;
2839         u32 status = le32_to_cpu(pPayload->status);
2840         u32 device_id = le32_to_cpu(pPayload->device_id);
2841         u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2842         u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2843         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2844                 "from 0x%x to 0x%x status = 0x%x!\n",
2845                 device_id, pds, nds, status));
2846         complete(pm8001_dev->setds_completion);
2847         ccb->task = NULL;
2848         ccb->ccb_tag = 0xFFFFFFFF;
2849         pm8001_ccb_free(pm8001_ha, tag);
2850 }
2851
2852 static void
2853 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2854 {
2855         struct get_nvm_data_resp *pPayload =
2856                 (struct get_nvm_data_resp *)(piomb + 4);
2857         u32 tag = le32_to_cpu(pPayload->tag);
2858         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2859         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2860         complete(pm8001_ha->nvmd_completion);
2861         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2862         if ((dlen_status & NVMD_STAT) != 0) {
2863                 PM8001_FAIL_DBG(pm8001_ha,
2864                         pm8001_printk("Set nvm data error!\n"));
2865                 return;
2866         }
2867         ccb->task = NULL;
2868         ccb->ccb_tag = 0xFFFFFFFF;
2869         pm8001_ccb_free(pm8001_ha, tag);
2870 }
2871
2872 static void
2873 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2874 {
2875         struct fw_control_ex    *fw_control_context;
2876         struct get_nvm_data_resp *pPayload =
2877                 (struct get_nvm_data_resp *)(piomb + 4);
2878         u32 tag = le32_to_cpu(pPayload->tag);
2879         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2880         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2881         u32 ir_tds_bn_dps_das_nvm =
2882                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2883         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2884         fw_control_context = ccb->fw_control_context;
2885
2886         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2887         if ((dlen_status & NVMD_STAT) != 0) {
2888                 PM8001_FAIL_DBG(pm8001_ha,
2889                         pm8001_printk("Get nvm data error!\n"));
2890                 complete(pm8001_ha->nvmd_completion);
2891                 return;
2892         }
2893
2894         if (ir_tds_bn_dps_das_nvm & IPMode) {
2895                 /* indirect mode - IR bit set */
2896                 PM8001_MSG_DBG(pm8001_ha,
2897                         pm8001_printk("Get NVMD success, IR=1\n"));
2898                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2899                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2900                                 memcpy(pm8001_ha->sas_addr,
2901                                       ((u8 *)virt_addr + 4),
2902                                        SAS_ADDR_SIZE);
2903                                 PM8001_MSG_DBG(pm8001_ha,
2904                                         pm8001_printk("Get SAS address"
2905                                         " from VPD successfully!\n"));
2906                         }
2907                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2908                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2909                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2910                                 ;
2911                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2912                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2913                         ;
2914                 } else {
2915                         /* Should not be happened*/
2916                         PM8001_MSG_DBG(pm8001_ha,
2917                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2918                                 ir_tds_bn_dps_das_nvm));
2919                 }
2920         } else /* direct mode */{
2921                 PM8001_MSG_DBG(pm8001_ha,
2922                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2923                         (dlen_status & NVMD_LEN) >> 24));
2924         }
2925         memcpy(fw_control_context->usrAddr,
2926                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2927                 fw_control_context->len);
2928         complete(pm8001_ha->nvmd_completion);
2929         ccb->task = NULL;
2930         ccb->ccb_tag = 0xFFFFFFFF;
2931         pm8001_ccb_free(pm8001_ha, tag);
2932 }
2933
2934 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2935 {
2936         struct local_phy_ctl_resp *pPayload =
2937                 (struct local_phy_ctl_resp *)(piomb + 4);
2938         u32 status = le32_to_cpu(pPayload->status);
2939         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2940         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2941         if (status != 0) {
2942                 PM8001_MSG_DBG(pm8001_ha,
2943                         pm8001_printk("%x phy execute %x phy op failed!\n",
2944                         phy_id, phy_op));
2945         } else
2946                 PM8001_MSG_DBG(pm8001_ha,
2947                         pm8001_printk("%x phy execute %x phy op success!\n",
2948                         phy_id, phy_op));
2949         return 0;
2950 }
2951
2952 /**
2953  * pm8001_bytes_dmaed - one of the interface function communication with libsas
2954  * @pm8001_ha: our hba card information
2955  * @i: which phy that received the event.
2956  *
2957  * when HBA driver received the identify done event or initiate FIS received
2958  * event(for SATA), it will invoke this function to notify the sas layer that
2959  * the sas toplogy has formed, please discover the the whole sas domain,
2960  * while receive a broadcast(change) primitive just tell the sas
2961  * layer to discover the changed domain rather than the whole domain.
2962  */
2963 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2964 {
2965         struct pm8001_phy *phy = &pm8001_ha->phy[i];
2966         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2967         struct sas_ha_struct *sas_ha;
2968         if (!phy->phy_attached)
2969                 return;
2970
2971         sas_ha = pm8001_ha->sas;
2972         if (sas_phy->phy) {
2973                 struct sas_phy *sphy = sas_phy->phy;
2974                 sphy->negotiated_linkrate = sas_phy->linkrate;
2975                 sphy->minimum_linkrate = phy->minimum_linkrate;
2976                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2977                 sphy->maximum_linkrate = phy->maximum_linkrate;
2978                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2979         }
2980
2981         if (phy->phy_type & PORT_TYPE_SAS) {
2982                 struct sas_identify_frame *id;
2983                 id = (struct sas_identify_frame *)phy->frame_rcvd;
2984                 id->dev_type = phy->identify.device_type;
2985                 id->initiator_bits = SAS_PROTOCOL_ALL;
2986                 id->target_bits = phy->identify.target_port_protocols;
2987         } else if (phy->phy_type & PORT_TYPE_SATA) {
2988                 /*Nothing*/
2989         }
2990         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2991
2992         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2993         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2994 }
2995
2996 /* Get the link rate speed  */
2997 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2998 {
2999         struct sas_phy *sas_phy = phy->sas_phy.phy;
3000
3001         switch (link_rate) {
3002         case PHY_SPEED_60:
3003                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3004                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3005                 break;
3006         case PHY_SPEED_30:
3007                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3008                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3009                 break;
3010         case PHY_SPEED_15:
3011                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3012                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3013                 break;
3014         }
3015         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3016         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3017         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3018         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3019         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3020 }
3021
3022 /**
3023  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3024  * @phy: pointer to asd_phy
3025  * @sas_addr: pointer to buffer where the SAS address is to be written
3026  *
3027  * This function extracts the SAS address from an IDENTIFY frame
3028  * received.  If OOB is SATA, then a SAS address is generated from the
3029  * HA tables.
3030  *
3031  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3032  * buffer.
3033  */
3034 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3035         u8 *sas_addr)
3036 {
3037         if (phy->sas_phy.frame_rcvd[0] == 0x34
3038                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3039                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3040                 /* FIS device-to-host */
3041                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3042                 addr += phy->sas_phy.id;
3043                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3044         } else {
3045                 struct sas_identify_frame *idframe =
3046                         (void *) phy->sas_phy.frame_rcvd;
3047                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3048         }
3049 }
3050
3051 /**
3052  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3053  * @pm8001_ha: our hba card information
3054  * @Qnum: the outbound queue message number.
3055  * @SEA: source of event to ack
3056  * @port_id: port id.
3057  * @phyId: phy id.
3058  * @param0: parameter 0.
3059  * @param1: parameter 1.
3060  */
3061 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3062         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3063 {
3064         struct hw_event_ack_req  payload;
3065         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3066
3067         struct inbound_queue_table *circularQ;
3068
3069         memset((u8 *)&payload, 0, sizeof(payload));
3070         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3071         payload.tag = cpu_to_le32(1);
3072         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3073                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3074         payload.param0 = cpu_to_le32(param0);
3075         payload.param1 = cpu_to_le32(param1);
3076         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3077 }
3078
3079 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3080         u32 phyId, u32 phy_op);
3081
3082 /**
3083  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3084  * @pm8001_ha: our hba card information
3085  * @piomb: IO message buffer
3086  */
3087 static void
3088 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3089 {
3090         struct hw_event_resp *pPayload =
3091                 (struct hw_event_resp *)(piomb + 4);
3092         u32 lr_evt_status_phyid_portid =
3093                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3094         u8 link_rate =
3095                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3096         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3097         u8 phy_id =
3098                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3099         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3100         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3101         struct pm8001_port *port = &pm8001_ha->port[port_id];
3102         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3103         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3104         unsigned long flags;
3105         u8 deviceType = pPayload->sas_identify.dev_type;
3106         port->port_state =  portstate;
3107         PM8001_MSG_DBG(pm8001_ha,
3108                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3109                 port_id, phy_id));
3110
3111         switch (deviceType) {
3112         case SAS_PHY_UNUSED:
3113                 PM8001_MSG_DBG(pm8001_ha,
3114                         pm8001_printk("device type no device.\n"));
3115                 break;
3116         case SAS_END_DEVICE:
3117                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3118                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3119                         PHY_NOTIFY_ENABLE_SPINUP);
3120                 port->port_attached = 1;
3121                 get_lrate_mode(phy, link_rate);
3122                 break;
3123         case SAS_EDGE_EXPANDER_DEVICE:
3124                 PM8001_MSG_DBG(pm8001_ha,
3125                         pm8001_printk("expander device.\n"));
3126                 port->port_attached = 1;
3127                 get_lrate_mode(phy, link_rate);
3128                 break;
3129         case SAS_FANOUT_EXPANDER_DEVICE:
3130                 PM8001_MSG_DBG(pm8001_ha,
3131                         pm8001_printk("fanout expander device.\n"));
3132                 port->port_attached = 1;
3133                 get_lrate_mode(phy, link_rate);
3134                 break;
3135         default:
3136                 PM8001_MSG_DBG(pm8001_ha,
3137                         pm8001_printk("unknown device type(%x)\n", deviceType));
3138                 break;
3139         }
3140         phy->phy_type |= PORT_TYPE_SAS;
3141         phy->identify.device_type = deviceType;
3142         phy->phy_attached = 1;
3143         if (phy->identify.device_type == SAS_END_DEVICE)
3144                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3145         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3146                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3147         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3148         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3149         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3150         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3151                 sizeof(struct sas_identify_frame)-4);
3152         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3153         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3154         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3155         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3156                 mdelay(200);/*delay a moment to wait disk to spinup*/
3157         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3158 }
3159
3160 /**
3161  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3162  * @pm8001_ha: our hba card information
3163  * @piomb: IO message buffer
3164  */
3165 static void
3166 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3167 {
3168         struct hw_event_resp *pPayload =
3169                 (struct hw_event_resp *)(piomb + 4);
3170         u32 lr_evt_status_phyid_portid =
3171                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3172         u8 link_rate =
3173                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3174         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3175         u8 phy_id =
3176                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3177         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3178         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3179         struct pm8001_port *port = &pm8001_ha->port[port_id];
3180         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3181         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3182         unsigned long flags;
3183         PM8001_MSG_DBG(pm8001_ha,
3184                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3185                 " phy id = %d\n", port_id, phy_id));
3186         port->port_state =  portstate;
3187         port->port_attached = 1;
3188         get_lrate_mode(phy, link_rate);
3189         phy->phy_type |= PORT_TYPE_SATA;
3190         phy->phy_attached = 1;
3191         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3192         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3193         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3194         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3195                 sizeof(struct dev_to_host_fis));
3196         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3197         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3198         phy->identify.device_type = SATA_DEV;
3199         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3200         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3201         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3202 }
3203
3204 /**
3205  * hw_event_phy_down -we should notify the libsas the phy is down.
3206  * @pm8001_ha: our hba card information
3207  * @piomb: IO message buffer
3208  */
3209 static void
3210 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3211 {
3212         struct hw_event_resp *pPayload =
3213                 (struct hw_event_resp *)(piomb + 4);
3214         u32 lr_evt_status_phyid_portid =
3215                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3216         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3217         u8 phy_id =
3218                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3219         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3220         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3221         struct pm8001_port *port = &pm8001_ha->port[port_id];
3222         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3223         port->port_state =  portstate;
3224         phy->phy_type = 0;
3225         phy->identify.device_type = 0;
3226         phy->phy_attached = 0;
3227         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3228         switch (portstate) {
3229         case PORT_VALID:
3230                 break;
3231         case PORT_INVALID:
3232                 PM8001_MSG_DBG(pm8001_ha,
3233                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3234                 PM8001_MSG_DBG(pm8001_ha,
3235                         pm8001_printk(" Last phy Down and port invalid\n"));
3236                 port->port_attached = 0;
3237                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3238                         port_id, phy_id, 0, 0);
3239                 break;
3240         case PORT_IN_RESET:
3241                 PM8001_MSG_DBG(pm8001_ha,
3242                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3243                 break;
3244         case PORT_NOT_ESTABLISHED:
3245                 PM8001_MSG_DBG(pm8001_ha,
3246                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3247                 port->port_attached = 0;
3248                 break;
3249         case PORT_LOSTCOMM:
3250                 PM8001_MSG_DBG(pm8001_ha,
3251                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3252                 PM8001_MSG_DBG(pm8001_ha,
3253                         pm8001_printk(" Last phy Down and port invalid\n"));
3254                 port->port_attached = 0;
3255                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3256                         port_id, phy_id, 0, 0);
3257                 break;
3258         default:
3259                 port->port_attached = 0;
3260                 PM8001_MSG_DBG(pm8001_ha,
3261                         pm8001_printk(" phy Down and(default) = %x\n",
3262                         portstate));
3263                 break;
3264
3265         }
3266 }
3267
3268 /**
3269  * mpi_reg_resp -process register device ID response.
3270  * @pm8001_ha: our hba card information
3271  * @piomb: IO message buffer
3272  *
3273  * when sas layer find a device it will notify LLDD, then the driver register
3274  * the domain device to FW, this event is the return device ID which the FW
3275  * has assigned, from now,inter-communication with FW is no longer using the
3276  * SAS address, use device ID which FW assigned.
3277  */
3278 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3279 {
3280         u32 status;
3281         u32 device_id;
3282         u32 htag;
3283         struct pm8001_ccb_info *ccb;
3284         struct pm8001_device *pm8001_dev;
3285         struct dev_reg_resp *registerRespPayload =
3286                 (struct dev_reg_resp *)(piomb + 4);
3287
3288         htag = le32_to_cpu(registerRespPayload->tag);
3289         ccb = &pm8001_ha->ccb_info[htag];
3290         pm8001_dev = ccb->device;
3291         status = le32_to_cpu(registerRespPayload->status);
3292         device_id = le32_to_cpu(registerRespPayload->device_id);
3293         PM8001_MSG_DBG(pm8001_ha,
3294                 pm8001_printk(" register device is status = %d\n", status));
3295         switch (status) {
3296         case DEVREG_SUCCESS:
3297                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3298                 pm8001_dev->device_id = device_id;
3299                 break;
3300         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3301                 PM8001_MSG_DBG(pm8001_ha,
3302                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3303                 break;
3304         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3305                 PM8001_MSG_DBG(pm8001_ha,
3306                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3307                 break;
3308         case DEVREG_FAILURE_INVALID_PHY_ID:
3309                 PM8001_MSG_DBG(pm8001_ha,
3310                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3311                 break;
3312         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3313                 PM8001_MSG_DBG(pm8001_ha,
3314                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3315                 break;
3316         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3317                 PM8001_MSG_DBG(pm8001_ha,
3318                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3319                 break;
3320         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3321                 PM8001_MSG_DBG(pm8001_ha,
3322                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3323                 break;
3324         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3325                 PM8001_MSG_DBG(pm8001_ha,
3326                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3327                 break;
3328         default:
3329                 PM8001_MSG_DBG(pm8001_ha,
3330                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3331                 break;
3332         }
3333         complete(pm8001_dev->dcompletion);
3334         ccb->task = NULL;
3335         ccb->ccb_tag = 0xFFFFFFFF;
3336         pm8001_ccb_free(pm8001_ha, htag);
3337         return 0;
3338 }
3339
3340 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3341 {
3342         u32 status;
3343         u32 device_id;
3344         struct dev_reg_resp *registerRespPayload =
3345                 (struct dev_reg_resp *)(piomb + 4);
3346
3347         status = le32_to_cpu(registerRespPayload->status);
3348         device_id = le32_to_cpu(registerRespPayload->device_id);
3349         if (status != 0)
3350                 PM8001_MSG_DBG(pm8001_ha,
3351                         pm8001_printk(" deregister device failed ,status = %x"
3352                         ", device_id = %x\n", status, device_id));
3353         return 0;
3354 }
3355
3356 static int
3357 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3358 {
3359         u32 status;
3360         struct fw_control_ex    fw_control_context;
3361         struct fw_flash_Update_resp *ppayload =
3362                 (struct fw_flash_Update_resp *)(piomb + 4);
3363         u32 tag = le32_to_cpu(ppayload->tag);
3364         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3365         status = le32_to_cpu(ppayload->status);
3366         memcpy(&fw_control_context,
3367                 ccb->fw_control_context,
3368                 sizeof(fw_control_context));
3369         switch (status) {
3370         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3371                 PM8001_MSG_DBG(pm8001_ha,
3372                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3373                 break;
3374         case FLASH_UPDATE_IN_PROGRESS:
3375                 PM8001_MSG_DBG(pm8001_ha,
3376                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3377                 break;
3378         case FLASH_UPDATE_HDR_ERR:
3379                 PM8001_MSG_DBG(pm8001_ha,
3380                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3381                 break;
3382         case FLASH_UPDATE_OFFSET_ERR:
3383                 PM8001_MSG_DBG(pm8001_ha,
3384                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3385                 break;
3386         case FLASH_UPDATE_CRC_ERR:
3387                 PM8001_MSG_DBG(pm8001_ha,
3388                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3389                 break;
3390         case FLASH_UPDATE_LENGTH_ERR:
3391                 PM8001_MSG_DBG(pm8001_ha,
3392                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3393                 break;
3394         case FLASH_UPDATE_HW_ERR:
3395                 PM8001_MSG_DBG(pm8001_ha,
3396                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3397                 break;
3398         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3399                 PM8001_MSG_DBG(pm8001_ha,
3400                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3401                 break;
3402         case FLASH_UPDATE_DISABLED:
3403                 PM8001_MSG_DBG(pm8001_ha,
3404                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3405                 break;
3406         default:
3407                 PM8001_MSG_DBG(pm8001_ha,
3408                         pm8001_printk("No matched status = %d\n", status));
3409                 break;
3410         }
3411         ccb->fw_control_context->fw_control->retcode = status;
3412         pci_free_consistent(pm8001_ha->pdev,
3413                         fw_control_context.len,
3414                         fw_control_context.virtAddr,
3415                         fw_control_context.phys_addr);
3416         complete(pm8001_ha->nvmd_completion);
3417         ccb->task = NULL;
3418         ccb->ccb_tag = 0xFFFFFFFF;
3419         pm8001_ccb_free(pm8001_ha, tag);
3420         return 0;
3421 }
3422
3423 static int
3424 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3425 {
3426         u32 status;
3427         int i;
3428         struct general_event_resp *pPayload =
3429                 (struct general_event_resp *)(piomb + 4);
3430         status = le32_to_cpu(pPayload->status);
3431         PM8001_MSG_DBG(pm8001_ha,
3432                 pm8001_printk(" status = 0x%x\n", status));
3433         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3434                 PM8001_MSG_DBG(pm8001_ha,
3435                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3436                         pPayload->inb_IOMB_payload[i]));
3437         return 0;
3438 }
3439
3440 static int
3441 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3442 {
3443         struct sas_task *t;
3444         struct pm8001_ccb_info *ccb;
3445         unsigned long flags;
3446         u32 status ;
3447         u32 tag, scp;
3448         struct task_status_struct *ts;
3449
3450         struct task_abort_resp *pPayload =
3451                 (struct task_abort_resp *)(piomb + 4);
3452
3453         status = le32_to_cpu(pPayload->status);
3454         tag = le32_to_cpu(pPayload->tag);
3455         scp = le32_to_cpu(pPayload->scp);
3456         ccb = &pm8001_ha->ccb_info[tag];
3457         t = ccb->task;
3458         PM8001_IO_DBG(pm8001_ha,
3459                 pm8001_printk(" status = 0x%x\n", status));
3460         if (t == NULL)
3461                 return -1;
3462         ts = &t->task_status;
3463         if (status != 0)
3464                 PM8001_FAIL_DBG(pm8001_ha,
3465                         pm8001_printk("task abort failed status 0x%x ,"
3466                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3467         switch (status) {
3468         case IO_SUCCESS:
3469                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3470                 ts->resp = SAS_TASK_COMPLETE;
3471                 ts->stat = SAM_STAT_GOOD;
3472                 break;
3473         case IO_NOT_VALID:
3474                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3475                 ts->resp = TMF_RESP_FUNC_FAILED;
3476                 break;
3477         }
3478         spin_lock_irqsave(&t->task_state_lock, flags);
3479         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3480         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3481         t->task_state_flags |= SAS_TASK_STATE_DONE;
3482         spin_unlock_irqrestore(&t->task_state_lock, flags);
3483         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3484         mb();
3485         t->task_done(t);
3486         return 0;
3487 }
3488
3489 /**
3490  * mpi_hw_event -The hw event has come.
3491  * @pm8001_ha: our hba card information
3492  * @piomb: IO message buffer
3493  */
3494 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3495 {
3496         unsigned long flags;
3497         struct hw_event_resp *pPayload =
3498                 (struct hw_event_resp *)(piomb + 4);
3499         u32 lr_evt_status_phyid_portid =
3500                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3501         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3502         u8 phy_id =
3503                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3504         u16 eventType =
3505                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3506         u8 status =
3507                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3508         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3509         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3510         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3511         PM8001_MSG_DBG(pm8001_ha,
3512                 pm8001_printk("outbound queue HW event & event type : "));
3513         switch (eventType) {
3514         case HW_EVENT_PHY_START_STATUS:
3515                 PM8001_MSG_DBG(pm8001_ha,
3516                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3517                         " status = %x\n", status));
3518                 if (status == 0) {
3519                         phy->phy_state = 1;
3520                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3521                                 complete(phy->enable_completion);
3522                 }
3523                 break;
3524         case HW_EVENT_SAS_PHY_UP:
3525                 PM8001_MSG_DBG(pm8001_ha,
3526                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3527                 hw_event_sas_phy_up(pm8001_ha, piomb);
3528                 break;
3529         case HW_EVENT_SATA_PHY_UP:
3530                 PM8001_MSG_DBG(pm8001_ha,
3531                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3532                 hw_event_sata_phy_up(pm8001_ha, piomb);
3533                 break;
3534         case HW_EVENT_PHY_STOP_STATUS:
3535                 PM8001_MSG_DBG(pm8001_ha,
3536                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3537                         "status = %x\n", status));
3538                 if (status == 0)
3539                         phy->phy_state = 0;
3540                 break;
3541         case HW_EVENT_SATA_SPINUP_HOLD:
3542                 PM8001_MSG_DBG(pm8001_ha,
3543                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3544                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3545                 break;
3546         case HW_EVENT_PHY_DOWN:
3547                 PM8001_MSG_DBG(pm8001_ha,
3548                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3549                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3550                 phy->phy_attached = 0;
3551                 phy->phy_state = 0;
3552                 hw_event_phy_down(pm8001_ha, piomb);
3553                 break;
3554         case HW_EVENT_PORT_INVALID:
3555                 PM8001_MSG_DBG(pm8001_ha,
3556                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3557                 sas_phy_disconnected(sas_phy);
3558                 phy->phy_attached = 0;
3559                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3560                 break;
3561         /* the broadcast change primitive received, tell the LIBSAS this event
3562         to revalidate the sas domain*/
3563         case HW_EVENT_BROADCAST_CHANGE:
3564                 PM8001_MSG_DBG(pm8001_ha,
3565                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3566                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3567                         port_id, phy_id, 1, 0);
3568                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3569                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3570                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3571                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3572                 break;
3573         case HW_EVENT_PHY_ERROR:
3574                 PM8001_MSG_DBG(pm8001_ha,
3575                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3576                 sas_phy_disconnected(&phy->sas_phy);
3577                 phy->phy_attached = 0;
3578                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3579                 break;
3580         case HW_EVENT_BROADCAST_EXP:
3581                 PM8001_MSG_DBG(pm8001_ha,
3582                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3583                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3584                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3585                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3586                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3587                 break;
3588         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3589                 PM8001_MSG_DBG(pm8001_ha,
3590                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3591                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3592                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3593                 sas_phy_disconnected(sas_phy);
3594                 phy->phy_attached = 0;
3595                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3596                 break;
3597         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3598                 PM8001_MSG_DBG(pm8001_ha,
3599                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3600                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3601                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3602                         port_id, phy_id, 0, 0);
3603                 sas_phy_disconnected(sas_phy);
3604                 phy->phy_attached = 0;
3605                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3606                 break;
3607         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3608                 PM8001_MSG_DBG(pm8001_ha,
3609                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3610                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3611                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3612                         port_id, phy_id, 0, 0);
3613                 sas_phy_disconnected(sas_phy);
3614                 phy->phy_attached = 0;
3615                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3616                 break;
3617         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3618                 PM8001_MSG_DBG(pm8001_ha,
3619                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3620                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3621                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3622                         port_id, phy_id, 0, 0);
3623                 sas_phy_disconnected(sas_phy);
3624                 phy->phy_attached = 0;
3625                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3626                 break;
3627         case HW_EVENT_MALFUNCTION:
3628                 PM8001_MSG_DBG(pm8001_ha,
3629                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3630                 break;
3631         case HW_EVENT_BROADCAST_SES:
3632                 PM8001_MSG_DBG(pm8001_ha,
3633                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3634                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3635                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3636                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3637                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3638                 break;
3639         case HW_EVENT_INBOUND_CRC_ERROR:
3640                 PM8001_MSG_DBG(pm8001_ha,
3641                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3642                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3643                         HW_EVENT_INBOUND_CRC_ERROR,
3644                         port_id, phy_id, 0, 0);
3645                 break;
3646         case HW_EVENT_HARD_RESET_RECEIVED:
3647                 PM8001_MSG_DBG(pm8001_ha,
3648                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3649                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3650                 break;
3651         case HW_EVENT_ID_FRAME_TIMEOUT:
3652                 PM8001_MSG_DBG(pm8001_ha,
3653                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3654                 sas_phy_disconnected(sas_phy);
3655                 phy->phy_attached = 0;
3656                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3657                 break;
3658         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3659                 PM8001_MSG_DBG(pm8001_ha,
3660                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3661                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3662                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3663                         port_id, phy_id, 0, 0);
3664                 sas_phy_disconnected(sas_phy);
3665                 phy->phy_attached = 0;
3666                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3667                 break;
3668         case HW_EVENT_PORT_RESET_TIMER_TMO:
3669                 PM8001_MSG_DBG(pm8001_ha,
3670                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3671                 sas_phy_disconnected(sas_phy);
3672                 phy->phy_attached = 0;
3673                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3674                 break;
3675         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3676                 PM8001_MSG_DBG(pm8001_ha,
3677                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3678                 sas_phy_disconnected(sas_phy);
3679                 phy->phy_attached = 0;
3680                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3681                 break;
3682         case HW_EVENT_PORT_RECOVER:
3683                 PM8001_MSG_DBG(pm8001_ha,
3684                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3685                 break;
3686         case HW_EVENT_PORT_RESET_COMPLETE:
3687                 PM8001_MSG_DBG(pm8001_ha,
3688                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3689                 break;
3690         case EVENT_BROADCAST_ASYNCH_EVENT:
3691                 PM8001_MSG_DBG(pm8001_ha,
3692                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3693                 break;
3694         default:
3695                 PM8001_MSG_DBG(pm8001_ha,
3696                         pm8001_printk("Unknown event type = %x\n", eventType));
3697                 break;
3698         }
3699         return 0;
3700 }
3701
3702 /**
3703  * process_one_iomb - process one outbound Queue memory block
3704  * @pm8001_ha: our hba card information
3705  * @piomb: IO message buffer
3706  */
3707 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3708 {
3709         __le32 pHeader = *(__le32 *)piomb;
3710         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3711
3712         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3713
3714         switch (opc) {
3715         case OPC_OUB_ECHO:
3716                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3717                 break;
3718         case OPC_OUB_HW_EVENT:
3719                 PM8001_MSG_DBG(pm8001_ha,
3720                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3721                 mpi_hw_event(pm8001_ha, piomb);
3722                 break;
3723         case OPC_OUB_SSP_COMP:
3724                 PM8001_MSG_DBG(pm8001_ha,
3725                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3726                 mpi_ssp_completion(pm8001_ha, piomb);
3727                 break;
3728         case OPC_OUB_SMP_COMP:
3729                 PM8001_MSG_DBG(pm8001_ha,
3730                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3731                 mpi_smp_completion(pm8001_ha, piomb);
3732                 break;
3733         case OPC_OUB_LOCAL_PHY_CNTRL:
3734                 PM8001_MSG_DBG(pm8001_ha,
3735                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3736                 mpi_local_phy_ctl(pm8001_ha, piomb);
3737                 break;
3738         case OPC_OUB_DEV_REGIST:
3739                 PM8001_MSG_DBG(pm8001_ha,
3740                         pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3741                 mpi_reg_resp(pm8001_ha, piomb);
3742                 break;
3743         case OPC_OUB_DEREG_DEV:
3744                 PM8001_MSG_DBG(pm8001_ha,
3745                         pm8001_printk("unregister the device\n"));
3746                 mpi_dereg_resp(pm8001_ha, piomb);
3747                 break;
3748         case OPC_OUB_GET_DEV_HANDLE:
3749                 PM8001_MSG_DBG(pm8001_ha,
3750                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3751                 break;
3752         case OPC_OUB_SATA_COMP:
3753                 PM8001_MSG_DBG(pm8001_ha,
3754                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3755                 mpi_sata_completion(pm8001_ha, piomb);
3756                 break;
3757         case OPC_OUB_SATA_EVENT:
3758                 PM8001_MSG_DBG(pm8001_ha,
3759                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3760                 mpi_sata_event(pm8001_ha, piomb);
3761                 break;
3762         case OPC_OUB_SSP_EVENT:
3763                 PM8001_MSG_DBG(pm8001_ha,
3764                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3765                 mpi_ssp_event(pm8001_ha, piomb);
3766                 break;
3767         case OPC_OUB_DEV_HANDLE_ARRIV:
3768                 PM8001_MSG_DBG(pm8001_ha,
3769                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3770                 /*This is for target*/
3771                 break;
3772         case OPC_OUB_SSP_RECV_EVENT:
3773                 PM8001_MSG_DBG(pm8001_ha,
3774                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3775                 /*This is for target*/
3776                 break;
3777         case OPC_OUB_DEV_INFO:
3778                 PM8001_MSG_DBG(pm8001_ha,
3779                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
3780                 break;
3781         case OPC_OUB_FW_FLASH_UPDATE:
3782                 PM8001_MSG_DBG(pm8001_ha,
3783                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3784                 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3785                 break;
3786         case OPC_OUB_GPIO_RESPONSE:
3787                 PM8001_MSG_DBG(pm8001_ha,
3788                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3789                 break;
3790         case OPC_OUB_GPIO_EVENT:
3791                 PM8001_MSG_DBG(pm8001_ha,
3792                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3793                 break;
3794         case OPC_OUB_GENERAL_EVENT:
3795                 PM8001_MSG_DBG(pm8001_ha,
3796                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3797                 mpi_general_event(pm8001_ha, piomb);
3798                 break;
3799         case OPC_OUB_SSP_ABORT_RSP:
3800                 PM8001_MSG_DBG(pm8001_ha,
3801                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3802                 mpi_task_abort_resp(pm8001_ha, piomb);
3803                 break;
3804         case OPC_OUB_SATA_ABORT_RSP:
3805                 PM8001_MSG_DBG(pm8001_ha,
3806                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3807                 mpi_task_abort_resp(pm8001_ha, piomb);
3808                 break;
3809         case OPC_OUB_SAS_DIAG_MODE_START_END:
3810                 PM8001_MSG_DBG(pm8001_ha,
3811                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3812                 break;
3813         case OPC_OUB_SAS_DIAG_EXECUTE:
3814                 PM8001_MSG_DBG(pm8001_ha,
3815                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3816                 break;
3817         case OPC_OUB_GET_TIME_STAMP:
3818                 PM8001_MSG_DBG(pm8001_ha,
3819                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3820                 break;
3821         case OPC_OUB_SAS_HW_EVENT_ACK:
3822                 PM8001_MSG_DBG(pm8001_ha,
3823                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3824                 break;
3825         case OPC_OUB_PORT_CONTROL:
3826                 PM8001_MSG_DBG(pm8001_ha,
3827                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3828                 break;
3829         case OPC_OUB_SMP_ABORT_RSP:
3830                 PM8001_MSG_DBG(pm8001_ha,
3831                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3832                 mpi_task_abort_resp(pm8001_ha, piomb);
3833                 break;
3834         case OPC_OUB_GET_NVMD_DATA:
3835                 PM8001_MSG_DBG(pm8001_ha,
3836                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3837                 mpi_get_nvmd_resp(pm8001_ha, piomb);
3838                 break;
3839         case OPC_OUB_SET_NVMD_DATA:
3840                 PM8001_MSG_DBG(pm8001_ha,
3841                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3842                 mpi_set_nvmd_resp(pm8001_ha, piomb);
3843                 break;
3844         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3845                 PM8001_MSG_DBG(pm8001_ha,
3846                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3847                 break;
3848         case OPC_OUB_SET_DEVICE_STATE:
3849                 PM8001_MSG_DBG(pm8001_ha,
3850                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3851                 mpi_set_dev_state_resp(pm8001_ha, piomb);
3852                 break;
3853         case OPC_OUB_GET_DEVICE_STATE:
3854                 PM8001_MSG_DBG(pm8001_ha,
3855                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3856                 break;
3857         case OPC_OUB_SET_DEV_INFO:
3858                 PM8001_MSG_DBG(pm8001_ha,
3859                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3860                 break;
3861         case OPC_OUB_SAS_RE_INITIALIZE:
3862                 PM8001_MSG_DBG(pm8001_ha,
3863                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3864                 break;
3865         default:
3866                 PM8001_MSG_DBG(pm8001_ha,
3867                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3868                         opc));
3869                 break;
3870         }
3871 }
3872
3873 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3874 {
3875         struct outbound_queue_table *circularQ;
3876         void *pMsg1 = NULL;
3877         u8 uninitialized_var(bc);
3878         u32 ret = MPI_IO_STATUS_FAIL;
3879         unsigned long flags;
3880
3881         spin_lock_irqsave(&pm8001_ha->lock, flags);
3882         circularQ = &pm8001_ha->outbnd_q_tbl[0];
3883         do {
3884                 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3885                 if (MPI_IO_STATUS_SUCCESS == ret) {
3886                         /* process the outbound message */
3887                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3888                         /* free the message from the outbound circular buffer */
3889                         mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3890                 }
3891                 if (MPI_IO_STATUS_BUSY == ret) {
3892                         /* Update the producer index from SPC */
3893                         circularQ->producer_index =
3894                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3895                         if (le32_to_cpu(circularQ->producer_index) ==
3896                                 circularQ->consumer_idx)
3897                                 /* OQ is empty */
3898                                 break;
3899                 }
3900         } while (1);
3901         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3902         return ret;
3903 }
3904
3905 /* PCI_DMA_... to our direction translation. */
3906 static const u8 data_dir_flags[] = {
3907         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3908         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3909         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3910         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3911 };
3912 static void
3913 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3914 {
3915         int i;
3916         struct scatterlist *sg;
3917         struct pm8001_prd *buf_prd = prd;
3918
3919         for_each_sg(scatter, sg, nr, i) {
3920                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3921                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3922                 buf_prd->im_len.e = 0;
3923                 buf_prd++;
3924         }
3925 }
3926
3927 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
3928 {
3929         psmp_cmd->tag = hTag;
3930         psmp_cmd->device_id = cpu_to_le32(deviceID);
3931         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3932 }
3933
3934 /**
3935  * pm8001_chip_smp_req - send a SMP task to FW
3936  * @pm8001_ha: our hba card information.
3937  * @ccb: the ccb information this request used.
3938  */
3939 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3940         struct pm8001_ccb_info *ccb)
3941 {
3942         int elem, rc;
3943         struct sas_task *task = ccb->task;
3944         struct domain_device *dev = task->dev;
3945         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3946         struct scatterlist *sg_req, *sg_resp;
3947         u32 req_len, resp_len;
3948         struct smp_req smp_cmd;
3949         u32 opc;
3950         struct inbound_queue_table *circularQ;
3951
3952         memset(&smp_cmd, 0, sizeof(smp_cmd));
3953         /*
3954          * DMA-map SMP request, response buffers
3955          */
3956         sg_req = &task->smp_task.smp_req;
3957         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3958         if (!elem)
3959                 return -ENOMEM;
3960         req_len = sg_dma_len(sg_req);
3961
3962         sg_resp = &task->smp_task.smp_resp;
3963         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3964         if (!elem) {
3965                 rc = -ENOMEM;
3966                 goto err_out;
3967         }
3968         resp_len = sg_dma_len(sg_resp);
3969         /* must be in dwords */
3970         if ((req_len & 0x3) || (resp_len & 0x3)) {
3971                 rc = -EINVAL;
3972                 goto err_out_2;
3973         }
3974
3975         opc = OPC_INB_SMP_REQUEST;
3976         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3977         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3978         smp_cmd.long_smp_req.long_req_addr =
3979                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3980         smp_cmd.long_smp_req.long_req_size =
3981                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3982         smp_cmd.long_smp_req.long_resp_addr =
3983                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3984         smp_cmd.long_smp_req.long_resp_size =
3985                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3986         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3987         mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3988         return 0;
3989
3990 err_out_2:
3991         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3992                         PCI_DMA_FROMDEVICE);
3993 err_out:
3994         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3995                         PCI_DMA_TODEVICE);
3996         return rc;
3997 }
3998
3999 /**
4000  * pm8001_chip_ssp_io_req - send a SSP task to FW
4001  * @pm8001_ha: our hba card information.
4002  * @ccb: the ccb information this request used.
4003  */
4004 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4005         struct pm8001_ccb_info *ccb)
4006 {
4007         struct sas_task *task = ccb->task;
4008         struct domain_device *dev = task->dev;
4009         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4010         struct ssp_ini_io_start_req ssp_cmd;
4011         u32 tag = ccb->ccb_tag;
4012         int ret;
4013         u64 phys_addr;
4014         struct inbound_queue_table *circularQ;
4015         u32 opc = OPC_INB_SSPINIIOSTART;
4016         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4017         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4018         ssp_cmd.dir_m_tlr =
4019                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4020         SAS 1.1 compatible TLR*/
4021         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4022         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4023         ssp_cmd.tag = cpu_to_le32(tag);
4024         if (task->ssp_task.enable_first_burst)
4025                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4026         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4027         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4028         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
4029         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4030
4031         /* fill in PRD (scatter/gather) table, if any */
4032         if (task->num_scatter > 1) {
4033                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4034                 phys_addr = ccb->ccb_dma_handle +
4035                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4036                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4037                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4038                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4039         } else if (task->num_scatter == 1) {
4040                 u64 dma_addr = sg_dma_address(task->scatter);
4041                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4042                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4043                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4044                 ssp_cmd.esgl = 0;
4045         } else if (task->num_scatter == 0) {
4046                 ssp_cmd.addr_low = 0;
4047                 ssp_cmd.addr_high = 0;
4048                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4049                 ssp_cmd.esgl = 0;
4050         }
4051         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
4052         return ret;
4053 }
4054
4055 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4056         struct pm8001_ccb_info *ccb)
4057 {
4058         struct sas_task *task = ccb->task;
4059         struct domain_device *dev = task->dev;
4060         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4061         u32 tag = ccb->ccb_tag;
4062         int ret;
4063         struct sata_start_req sata_cmd;
4064         u32 hdr_tag, ncg_tag = 0;
4065         u64 phys_addr;
4066         u32 ATAP = 0x0;
4067         u32 dir;
4068         struct inbound_queue_table *circularQ;
4069         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4070         memset(&sata_cmd, 0, sizeof(sata_cmd));
4071         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4072         if (task->data_dir == PCI_DMA_NONE) {
4073                 ATAP = 0x04;  /* no data*/
4074                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4075         } else if (likely(!task->ata_task.device_control_reg_update)) {
4076                 if (task->ata_task.dma_xfer) {
4077                         ATAP = 0x06; /* DMA */
4078                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4079                 } else {
4080                         ATAP = 0x05; /* PIO*/
4081                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4082                 }
4083                 if (task->ata_task.use_ncq &&
4084                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4085                         ATAP = 0x07; /* FPDMA */
4086                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4087                 }
4088         }
4089         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
4090                 ncg_tag = hdr_tag;
4091         dir = data_dir_flags[task->data_dir] << 8;
4092         sata_cmd.tag = cpu_to_le32(tag);
4093         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4094         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4095         sata_cmd.ncqtag_atap_dir_m =
4096                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4097         sata_cmd.sata_fis = task->ata_task.fis;
4098         if (likely(!task->ata_task.device_control_reg_update))
4099                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4100         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4101         /* fill in PRD (scatter/gather) table, if any */
4102         if (task->num_scatter > 1) {
4103                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4104                 phys_addr = ccb->ccb_dma_handle +
4105                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4106                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4107                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4108                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4109         } else if (task->num_scatter == 1) {
4110                 u64 dma_addr = sg_dma_address(task->scatter);
4111                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4112                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4113                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4114                 sata_cmd.esgl = 0;
4115         } else if (task->num_scatter == 0) {
4116                 sata_cmd.addr_low = 0;
4117                 sata_cmd.addr_high = 0;
4118                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4119                 sata_cmd.esgl = 0;
4120         }
4121         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
4122         return ret;
4123 }
4124
4125 /**
4126  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4127  * @pm8001_ha: our hba card information.
4128  * @num: the inbound queue number
4129  * @phy_id: the phy id which we wanted to start up.
4130  */
4131 static int
4132 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4133 {
4134         struct phy_start_req payload;
4135         struct inbound_queue_table *circularQ;
4136         int ret;
4137         u32 tag = 0x01;
4138         u32 opcode = OPC_INB_PHYSTART;
4139         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4140         memset(&payload, 0, sizeof(payload));
4141         payload.tag = cpu_to_le32(tag);
4142         /*
4143          ** [0:7]   PHY Identifier
4144          ** [8:11]  link rate 1.5G, 3G, 6G
4145          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4146          ** [14]    0b disable spin up hold; 1b enable spin up hold
4147          */
4148         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4149                 LINKMODE_AUTO | LINKRATE_15 |
4150                 LINKRATE_30 | LINKRATE_60 | phy_id);
4151         payload.sas_identify.dev_type = SAS_END_DEV;
4152         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4153         memcpy(payload.sas_identify.sas_addr,
4154                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4155         payload.sas_identify.phy_id = phy_id;
4156         ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4157         return ret;
4158 }
4159
4160 /**
4161  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4162  * @pm8001_ha: our hba card information.
4163  * @num: the inbound queue number
4164  * @phy_id: the phy id which we wanted to start up.
4165  */
4166 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4167         u8 phy_id)
4168 {
4169         struct phy_stop_req payload;
4170         struct inbound_queue_table *circularQ;
4171         int ret;
4172         u32 tag = 0x01;
4173         u32 opcode = OPC_INB_PHYSTOP;
4174         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4175         memset(&payload, 0, sizeof(payload));
4176         payload.tag = cpu_to_le32(tag);
4177         payload.phy_id = cpu_to_le32(phy_id);
4178         ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4179         return ret;
4180 }
4181
4182 /**
4183  * see comments on mpi_reg_resp.
4184  */
4185 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4186         struct pm8001_device *pm8001_dev, u32 flag)
4187 {
4188         struct reg_dev_req payload;
4189         u32     opc;
4190         u32 stp_sspsmp_sata = 0x4;
4191         struct inbound_queue_table *circularQ;
4192         u32 linkrate, phy_id;
4193         int rc, tag = 0xdeadbeef;
4194         struct pm8001_ccb_info *ccb;
4195         u8 retryFlag = 0x1;
4196         u16 firstBurstSize = 0;
4197         u16 ITNT = 2000;
4198         struct domain_device *dev = pm8001_dev->sas_device;
4199         struct domain_device *parent_dev = dev->parent;
4200         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4201
4202         memset(&payload, 0, sizeof(payload));
4203         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4204         if (rc)
4205                 return rc;
4206         ccb = &pm8001_ha->ccb_info[tag];
4207         ccb->device = pm8001_dev;
4208         ccb->ccb_tag = tag;
4209         payload.tag = cpu_to_le32(tag);
4210         if (flag == 1)
4211                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4212         else {
4213                 if (pm8001_dev->dev_type == SATA_DEV)
4214                         stp_sspsmp_sata = 0x00; /* stp*/
4215                 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4216                         pm8001_dev->dev_type == EDGE_DEV ||
4217                         pm8001_dev->dev_type == FANOUT_DEV)
4218                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4219         }
4220         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4221                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4222         else
4223                 phy_id = pm8001_dev->attached_phy;
4224         opc = OPC_INB_REG_DEV;
4225         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4226                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4227         payload.phyid_portid =
4228                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4229                 ((phy_id & 0x0F) << 4));
4230         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4231                 ((linkrate & 0x0F) * 0x1000000) |
4232                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4233         payload.firstburstsize_ITNexustimeout =
4234                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4235         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4236                 SAS_ADDR_SIZE);
4237         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4238         return rc;
4239 }
4240
4241 /**
4242  * see comments on mpi_reg_resp.
4243  */
4244 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4245         u32 device_id)
4246 {
4247         struct dereg_dev_req payload;
4248         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4249         int ret;
4250         struct inbound_queue_table *circularQ;
4251
4252         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4253         memset(&payload, 0, sizeof(payload));
4254         payload.tag = cpu_to_le32(1);
4255         payload.device_id = cpu_to_le32(device_id);
4256         PM8001_MSG_DBG(pm8001_ha,
4257                 pm8001_printk("unregister device device_id = %d\n", device_id));
4258         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4259         return ret;
4260 }
4261
4262 /**
4263  * pm8001_chip_phy_ctl_req - support the local phy operation
4264  * @pm8001_ha: our hba card information.
4265  * @num: the inbound queue number
4266  * @phy_id: the phy id which we wanted to operate
4267  * @phy_op:
4268  */
4269 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4270         u32 phyId, u32 phy_op)
4271 {
4272         struct local_phy_ctl_req payload;
4273         struct inbound_queue_table *circularQ;
4274         int ret;
4275         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4276         memset(&payload, 0, sizeof(payload));
4277         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4278         payload.tag = cpu_to_le32(1);
4279         payload.phyop_phyid =
4280                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4281         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4282         return ret;
4283 }
4284
4285 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4286 {
4287         u32 value;
4288 #ifdef PM8001_USE_MSIX
4289         return 1;
4290 #endif
4291         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4292         if (value)
4293                 return 1;
4294         return 0;
4295
4296 }
4297
4298 /**
4299  * pm8001_chip_isr - PM8001 isr handler.
4300  * @pm8001_ha: our hba card information.
4301  * @irq: irq number.
4302  * @stat: stat.
4303  */
4304 static irqreturn_t
4305 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4306 {
4307         pm8001_chip_interrupt_disable(pm8001_ha);
4308         process_oq(pm8001_ha);
4309         pm8001_chip_interrupt_enable(pm8001_ha);
4310         return IRQ_HANDLED;
4311 }
4312
4313 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4314         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4315 {
4316         struct task_abort_req task_abort;
4317         struct inbound_queue_table *circularQ;
4318         int ret;
4319         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4320         memset(&task_abort, 0, sizeof(task_abort));
4321         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4322                 task_abort.abort_all = 0;
4323                 task_abort.device_id = cpu_to_le32(dev_id);
4324                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4325                 task_abort.tag = cpu_to_le32(cmd_tag);
4326         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4327                 task_abort.abort_all = cpu_to_le32(1);
4328                 task_abort.device_id = cpu_to_le32(dev_id);
4329                 task_abort.tag = cpu_to_le32(cmd_tag);
4330         }
4331         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4332         return ret;
4333 }
4334
4335 /**
4336  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4337  * @task: the task we wanted to aborted.
4338  * @flag: the abort flag.
4339  */
4340 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4341         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4342 {
4343         u32 opc, device_id;
4344         int rc = TMF_RESP_FUNC_FAILED;
4345         PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4346                 " = %x", cmd_tag, task_tag));
4347         if (pm8001_dev->dev_type == SAS_END_DEV)
4348                 opc = OPC_INB_SSP_ABORT;
4349         else if (pm8001_dev->dev_type == SATA_DEV)
4350                 opc = OPC_INB_SATA_ABORT;
4351         else
4352                 opc = OPC_INB_SMP_ABORT;/* SMP */
4353         device_id = pm8001_dev->device_id;
4354         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4355                 task_tag, cmd_tag);
4356         if (rc != TMF_RESP_FUNC_COMPLETE)
4357                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4358         return rc;
4359 }
4360
4361 /**
4362  * pm8001_chip_ssp_tm_req - built the task management command.
4363  * @pm8001_ha: our hba card information.
4364  * @ccb: the ccb information.
4365  * @tmf: task management function.
4366  */
4367 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4368         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4369 {
4370         struct sas_task *task = ccb->task;
4371         struct domain_device *dev = task->dev;
4372         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4373         u32 opc = OPC_INB_SSPINITMSTART;
4374         struct inbound_queue_table *circularQ;
4375         struct ssp_ini_tm_start_req sspTMCmd;
4376         int ret;
4377
4378         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4379         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4380         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4381         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4382         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4383         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4384         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4385         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4386         return ret;
4387 }
4388
4389 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4390         void *payload)
4391 {
4392         u32 opc = OPC_INB_GET_NVMD_DATA;
4393         u32 nvmd_type;
4394         int rc;
4395         u32 tag;
4396         struct pm8001_ccb_info *ccb;
4397         struct inbound_queue_table *circularQ;
4398         struct get_nvm_data_req nvmd_req;
4399         struct fw_control_ex *fw_control_context;
4400         struct pm8001_ioctl_payload *ioctl_payload = payload;
4401
4402         nvmd_type = ioctl_payload->minor_function;
4403         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4404         if (!fw_control_context)
4405                 return -ENOMEM;
4406         fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4407         fw_control_context->len = ioctl_payload->length;
4408         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4409         memset(&nvmd_req, 0, sizeof(nvmd_req));
4410         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4411         if (rc) {
4412                 kfree(fw_control_context);
4413                 return rc;
4414         }
4415         ccb = &pm8001_ha->ccb_info[tag];
4416         ccb->ccb_tag = tag;
4417         ccb->fw_control_context = fw_control_context;
4418         nvmd_req.tag = cpu_to_le32(tag);
4419
4420         switch (nvmd_type) {
4421         case TWI_DEVICE: {
4422                 u32 twi_addr, twi_page_size;
4423                 twi_addr = 0xa8;
4424                 twi_page_size = 2;
4425
4426                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4427                         twi_page_size << 8 | TWI_DEVICE);
4428                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4429                 nvmd_req.resp_addr_hi =
4430                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4431                 nvmd_req.resp_addr_lo =
4432                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4433                 break;
4434         }
4435         case C_SEEPROM: {
4436                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4437                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4438                 nvmd_req.resp_addr_hi =
4439                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4440                 nvmd_req.resp_addr_lo =
4441                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4442                 break;
4443         }
4444         case VPD_FLASH: {
4445                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4446                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4447                 nvmd_req.resp_addr_hi =
4448                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4449                 nvmd_req.resp_addr_lo =
4450                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4451                 break;
4452         }
4453         case EXPAN_ROM: {
4454                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4455                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4456                 nvmd_req.resp_addr_hi =
4457                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4458                 nvmd_req.resp_addr_lo =
4459                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4460                 break;
4461         }
4462         default:
4463                 break;
4464         }
4465         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4466         return rc;
4467 }
4468
4469 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4470         void *payload)
4471 {
4472         u32 opc = OPC_INB_SET_NVMD_DATA;
4473         u32 nvmd_type;
4474         int rc;
4475         u32 tag;
4476         struct pm8001_ccb_info *ccb;
4477         struct inbound_queue_table *circularQ;
4478         struct set_nvm_data_req nvmd_req;
4479         struct fw_control_ex *fw_control_context;
4480         struct pm8001_ioctl_payload *ioctl_payload = payload;
4481
4482         nvmd_type = ioctl_payload->minor_function;
4483         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4484         if (!fw_control_context)
4485                 return -ENOMEM;
4486         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4487         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4488                 ioctl_payload->func_specific,
4489                 ioctl_payload->length);
4490         memset(&nvmd_req, 0, sizeof(nvmd_req));
4491         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4492         if (rc) {
4493                 kfree(fw_control_context);
4494                 return rc;
4495         }
4496         ccb = &pm8001_ha->ccb_info[tag];
4497         ccb->fw_control_context = fw_control_context;
4498         ccb->ccb_tag = tag;
4499         nvmd_req.tag = cpu_to_le32(tag);
4500         switch (nvmd_type) {
4501         case TWI_DEVICE: {
4502                 u32 twi_addr, twi_page_size;
4503                 twi_addr = 0xa8;
4504                 twi_page_size = 2;
4505                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4506                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4507                         twi_page_size << 8 | TWI_DEVICE);
4508                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4509                 nvmd_req.resp_addr_hi =
4510                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4511                 nvmd_req.resp_addr_lo =
4512                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4513                 break;
4514         }
4515         case C_SEEPROM:
4516                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4517                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4518                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4519                 nvmd_req.resp_addr_hi =
4520                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4521                 nvmd_req.resp_addr_lo =
4522                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4523                 break;
4524         case VPD_FLASH:
4525                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4526                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4527                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4528                 nvmd_req.resp_addr_hi =
4529                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4530                 nvmd_req.resp_addr_lo =
4531                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4532                 break;
4533         case EXPAN_ROM:
4534                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4535                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4536                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4537                 nvmd_req.resp_addr_hi =
4538                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4539                 nvmd_req.resp_addr_lo =
4540                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4541                 break;
4542         default:
4543                 break;
4544         }
4545         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4546         return rc;
4547 }
4548
4549 /**
4550  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4551  * @pm8001_ha: our hba card information.
4552  * @fw_flash_updata_info: firmware flash update param
4553  */
4554 static int
4555 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4556         void *fw_flash_updata_info, u32 tag)
4557 {
4558         struct fw_flash_Update_req payload;
4559         struct fw_flash_updata_info *info;
4560         struct inbound_queue_table *circularQ;
4561         int ret;
4562         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4563
4564         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4565         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4566         info = fw_flash_updata_info;
4567         payload.tag = cpu_to_le32(tag);
4568         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4569         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4570         payload.total_image_len = cpu_to_le32(info->total_image_len);
4571         payload.len = info->sgl.im_len.len ;
4572         payload.sgl_addr_lo =
4573                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4574         payload.sgl_addr_hi =
4575                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4576         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4577         return ret;
4578 }
4579
4580 static int
4581 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4582         void *payload)
4583 {
4584         struct fw_flash_updata_info flash_update_info;
4585         struct fw_control_info *fw_control;
4586         struct fw_control_ex *fw_control_context;
4587         int rc;
4588         u32 tag;
4589         struct pm8001_ccb_info *ccb;
4590         void *buffer = NULL;
4591         dma_addr_t phys_addr;
4592         u32 phys_addr_hi;
4593         u32 phys_addr_lo;
4594         struct pm8001_ioctl_payload *ioctl_payload = payload;
4595
4596         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4597         if (!fw_control_context)
4598                 return -ENOMEM;
4599         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4600         if (fw_control->len != 0) {
4601                 if (pm8001_mem_alloc(pm8001_ha->pdev,
4602                         (void **)&buffer,
4603                         &phys_addr,
4604                         &phys_addr_hi,
4605                         &phys_addr_lo,
4606                         fw_control->len, 0) != 0) {
4607                                 PM8001_FAIL_DBG(pm8001_ha,
4608                                         pm8001_printk("Mem alloc failure\n"));
4609                                 kfree(fw_control_context);
4610                                 return -ENOMEM;
4611                 }
4612         }
4613         memcpy(buffer, fw_control->buffer, fw_control->len);
4614         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4615         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4616         flash_update_info.sgl.im_len.e = 0;
4617         flash_update_info.cur_image_offset = fw_control->offset;
4618         flash_update_info.cur_image_len = fw_control->len;
4619         flash_update_info.total_image_len = fw_control->size;
4620         fw_control_context->fw_control = fw_control;
4621         fw_control_context->virtAddr = buffer;
4622         fw_control_context->len = fw_control->len;
4623         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4624         if (rc) {
4625                 kfree(fw_control_context);
4626                 return rc;
4627         }
4628         ccb = &pm8001_ha->ccb_info[tag];
4629         ccb->fw_control_context = fw_control_context;
4630         ccb->ccb_tag = tag;
4631         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4632                 tag);
4633         return rc;
4634 }
4635
4636 static int
4637 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4638         struct pm8001_device *pm8001_dev, u32 state)
4639 {
4640         struct set_dev_state_req payload;
4641         struct inbound_queue_table *circularQ;
4642         struct pm8001_ccb_info *ccb;
4643         int rc;
4644         u32 tag;
4645         u32 opc = OPC_INB_SET_DEVICE_STATE;
4646         memset(&payload, 0, sizeof(payload));
4647         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4648         if (rc)
4649                 return -1;
4650         ccb = &pm8001_ha->ccb_info[tag];
4651         ccb->ccb_tag = tag;
4652         ccb->device = pm8001_dev;
4653         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4654         payload.tag = cpu_to_le32(tag);
4655         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4656         payload.nds = cpu_to_le32(state);
4657         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4658         return rc;
4659
4660 }
4661
4662 static int
4663 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4664 {
4665         struct sas_re_initialization_req payload;
4666         struct inbound_queue_table *circularQ;
4667         struct pm8001_ccb_info *ccb;
4668         int rc;
4669         u32 tag;
4670         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4671         memset(&payload, 0, sizeof(payload));
4672         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4673         if (rc)
4674                 return -1;
4675         ccb = &pm8001_ha->ccb_info[tag];
4676         ccb->ccb_tag = tag;
4677         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4678         payload.tag = cpu_to_le32(tag);
4679         payload.SSAHOLT = cpu_to_le32(0xd << 25);
4680         payload.sata_hol_tmo = cpu_to_le32(80);
4681         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4682         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4683         return rc;
4684
4685 }
4686
4687 const struct pm8001_dispatch pm8001_8001_dispatch = {
4688         .name                   = "pmc8001",
4689         .chip_init              = pm8001_chip_init,
4690         .chip_soft_rst          = pm8001_chip_soft_rst,
4691         .chip_rst               = pm8001_hw_chip_rst,
4692         .chip_iounmap           = pm8001_chip_iounmap,
4693         .isr                    = pm8001_chip_isr,
4694         .is_our_interupt        = pm8001_chip_is_our_interupt,
4695         .isr_process_oq         = process_oq,
4696         .interrupt_enable       = pm8001_chip_interrupt_enable,
4697         .interrupt_disable      = pm8001_chip_interrupt_disable,
4698         .make_prd               = pm8001_chip_make_sg,
4699         .smp_req                = pm8001_chip_smp_req,
4700         .ssp_io_req             = pm8001_chip_ssp_io_req,
4701         .sata_req               = pm8001_chip_sata_req,
4702         .phy_start_req          = pm8001_chip_phy_start_req,
4703         .phy_stop_req           = pm8001_chip_phy_stop_req,
4704         .reg_dev_req            = pm8001_chip_reg_dev_req,
4705         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4706         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
4707         .task_abort             = pm8001_chip_abort_task,
4708         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4709         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4710         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4711         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4712         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4713         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
4714 };
4715