Pileus Git - ~andy/linux/blob - drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                 pm8001_mr32(address, 0x00);
  55         pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                 pm8001_mr32(address, 0x04);
  57         pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                 pm8001_mr32(address, 0x08);
  59         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                 pm8001_mr32(address, 0x0C);
  61         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                 pm8001_mr32(address, 0x10);
  63         pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                 pm8001_mr32(address, 0x14);
  65         pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                 pm8001_mr32(address, 0x18);
  67         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71         pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74         /* read analog Setting offset from the configuration table */
  75         pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78         /* read Error Dump Offset and Length */
  79         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87 }
  88
  89 /**
  90  * read_general_status_table - read the general status table and save it.
  91  * @pm8001_ha: our hba card information
  92  */
  93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94 {
  95         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96         pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                 pm8001_mr32(address, 0x00);
  98         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                 pm8001_mr32(address, 0x04);
 100         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                 pm8001_mr32(address, 0x08);
 102         pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                 pm8001_mr32(address, 0x0C);
 104         pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                 pm8001_mr32(address, 0x10);
 106         pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                 pm8001_mr32(address, 0x14);
 108         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                 pm8001_mr32(address, 0x18);
 110         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                 pm8001_mr32(address, 0x1C);
 112         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                 pm8001_mr32(address, 0x20);
 114         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                 pm8001_mr32(address, 0x24);
 116         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                 pm8001_mr32(address, 0x28);
 118         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                 pm8001_mr32(address, 0x2C);
 120         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                 pm8001_mr32(address, 0x30);
 122         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                 pm8001_mr32(address, 0x34);
 124         pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                 pm8001_mr32(address, 0x38);
 126         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                 pm8001_mr32(address, 0x3C);
 128         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                 pm8001_mr32(address, 0x40);
 130         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                 pm8001_mr32(address, 0x44);
 132         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                 pm8001_mr32(address, 0x48);
 134         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                 pm8001_mr32(address, 0x4C);
 136         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                 pm8001_mr32(address, 0x50);
 138         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                 pm8001_mr32(address, 0x54);
 140         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                 pm8001_mr32(address, 0x58);
 142         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                 pm8001_mr32(address, 0x5C);
 144         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                 pm8001_mr32(address, 0x60);
 146 }
 147
 148 /**
 149  * read_inbnd_queue_table - read the inbound queue table and save it.
 150  * @pm8001_ha: our hba card information
 151  */
 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153 {
 154         int inbQ_num = 1;
 155         int i;
 156         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 157         for (i = 0; i < inbQ_num; i++) {
 158                 u32 offset = i * 0x20;
 159                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 160                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 161                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 162                         pm8001_mr32(address, (offset + 0x18));
 163         }
 164 }
 165
 166 /**
 167  * read_outbnd_queue_table - read the outbound queue table and save it.
 168  * @pm8001_ha: our hba card information
 169  */
 170 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 171 {
 172         int outbQ_num = 1;
 173         int i;
 174         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 175         for (i = 0; i < outbQ_num; i++) {
 176                 u32 offset = i * 0x24;
 177                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 178                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 179                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 180                         pm8001_mr32(address, (offset + 0x18));
 181         }
 182 }
 183
 184 /**
 185  * init_default_table_values - init the default table.
 186  * @pm8001_ha: our hba card information
 187  */
 188 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 189 {
 190         int i;
 191         u32 offsetib, offsetob;
 192         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 193         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 194
 195         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 196         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 197         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 198         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 199         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 200         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 201                                                                          0;
 202         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 203                                                                          0;
 204         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 205         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 206         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 207         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 208
 209         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 210                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 211         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 212                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 213         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 214                 PM8001_EVENT_LOG_SIZE;
 215         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 216         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 217                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 218         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 219                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 220         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 221                 PM8001_EVENT_LOG_SIZE;
 222         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 223         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 224         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 225                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 226                         PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
 227                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 228                         pm8001_ha->memoryMap.region[IB].phys_addr_hi;
 229                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 230                 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
 231                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 232                         (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
 233                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 234                         pm8001_ha->memoryMap.region[IB].total_len;
 235                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 236                         pm8001_ha->memoryMap.region[CI].phys_addr_hi;
 237                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 238                         pm8001_ha->memoryMap.region[CI].phys_addr_lo;
 239                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 240                         pm8001_ha->memoryMap.region[CI].virt_ptr;
 241                 offsetib = i * 0x20;
 242                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 243                         get_pci_bar_index(pm8001_mr32(addressib,
 244                                 (offsetib + 0x14)));
 245                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 246                         pm8001_mr32(addressib, (offsetib + 0x18));
 247                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 248                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 249         }
 250         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 251                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 252                         PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
 253                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 254                         pm8001_ha->memoryMap.region[OB].phys_addr_hi;
 255                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 256                         pm8001_ha->memoryMap.region[OB].phys_addr_lo;
 257                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 258                         (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
 259                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 260                         pm8001_ha->memoryMap.region[OB].total_len;
 261                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 262                         pm8001_ha->memoryMap.region[PI].phys_addr_hi;
 263                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 264                         pm8001_ha->memoryMap.region[PI].phys_addr_lo;
 265                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 266                         0 | (10 << 16) | (0 << 24);
 267                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 268                         pm8001_ha->memoryMap.region[PI].virt_ptr;
 269                 offsetob = i * 0x24;
 270                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 271                         get_pci_bar_index(pm8001_mr32(addressob,
 272                         offsetob + 0x14));
 273                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 274                         pm8001_mr32(addressob, (offsetob + 0x18));
 275                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 276                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 277         }
 278 }
 279
 280 /**
 281  * update_main_config_table - update the main default table to the HBA.
 282  * @pm8001_ha: our hba card information
 283  */
 284 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 285 {
 286         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 287         pm8001_mw32(address, 0x24,
 288                 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 289         pm8001_mw32(address, 0x28,
 290                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 291         pm8001_mw32(address, 0x2C,
 292                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 293         pm8001_mw32(address, 0x30,
 294                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 295         pm8001_mw32(address, 0x34,
 296                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 297         pm8001_mw32(address, 0x38,
 298                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 299                                         outbound_tgt_ITNexus_event_pid0_3);
 300         pm8001_mw32(address, 0x3C,
 301                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 302                                         outbound_tgt_ITNexus_event_pid4_7);
 303         pm8001_mw32(address, 0x40,
 304                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 305                                         outbound_tgt_ssp_event_pid0_3);
 306         pm8001_mw32(address, 0x44,
 307                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 308                                         outbound_tgt_ssp_event_pid4_7);
 309         pm8001_mw32(address, 0x48,
 310                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 311                                         outbound_tgt_smp_event_pid0_3);
 312         pm8001_mw32(address, 0x4C,
 313                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 314                                         outbound_tgt_smp_event_pid4_7);
 315         pm8001_mw32(address, 0x50,
 316                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 317         pm8001_mw32(address, 0x54,
 318                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 319         pm8001_mw32(address, 0x58,
 320                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 321         pm8001_mw32(address, 0x5C,
 322                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 323         pm8001_mw32(address, 0x60,
 324                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 325         pm8001_mw32(address, 0x64,
 326                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 327         pm8001_mw32(address, 0x68,
 328                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 329         pm8001_mw32(address, 0x6C,
 330                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 331         pm8001_mw32(address, 0x70,
 332                 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 333 }
 334
 335 /**
 336  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 337  * @pm8001_ha: our hba card information
 338  */
 339 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 340                                      int number)
 341 {
 342         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 343         u16 offset = number * 0x20;
 344         pm8001_mw32(address, offset + 0x00,
 345                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 346         pm8001_mw32(address, offset + 0x04,
 347                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 348         pm8001_mw32(address, offset + 0x08,
 349                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 350         pm8001_mw32(address, offset + 0x0C,
 351                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 352         pm8001_mw32(address, offset + 0x10,
 353                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 354 }
 355
 356 /**
 357  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 358  * @pm8001_ha: our hba card information
 359  */
 360 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 361                                       int number)
 362 {
 363         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 364         u16 offset = number * 0x24;
 365         pm8001_mw32(address, offset + 0x00,
 366                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 367         pm8001_mw32(address, offset + 0x04,
 368                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 369         pm8001_mw32(address, offset + 0x08,
 370                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 371         pm8001_mw32(address, offset + 0x0C,
 372                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 373         pm8001_mw32(address, offset + 0x10,
 374                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 375         pm8001_mw32(address, offset + 0x1C,
 376                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 377 }
 378
 379 /**
 380  * pm8001_bar4_shift - function is called to shift BAR base address
 381  * @pm8001_ha : our hba card infomation
 382  * @shiftValue : shifting value in memory bar.
 383  */
 384 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 385 {
 386         u32 regVal;
 387         unsigned long start;
 388
 389         /* program the inbound AXI translation Lower Address */
 390         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 391
 392         /* confirm the setting is written */
 393         start = jiffies + HZ; /* 1 sec */
 394         do {
 395                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 396         } while ((regVal != shiftValue) && time_before(jiffies, start));
 397
 398         if (regVal != shiftValue) {
 399                 PM8001_INIT_DBG(pm8001_ha,
 400                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 401                         " = 0x%x\n", regVal));
 402                 return -1;
 403         }
 404         return 0;
 405 }
 406
 407 /**
 408  * mpi_set_phys_g3_with_ssc
 409  * @pm8001_ha: our hba card information
 410  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 411  */
 412 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 413                                      u32 SSCbit)
 414 {
 415         u32 value, offset, i;
 416         unsigned long flags;
 417
 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 420 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 421 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 422 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 423 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 424 #define SNW3_PHY_CAPABILITIES_PARITY 31
 425
 426    /*
 427     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 428     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 429     */
 430         spin_lock_irqsave(&pm8001_ha->lock, flags);
 431         if (-1 == pm8001_bar4_shift(pm8001_ha,
 432                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 433                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 434                 return;
 435         }
 436
 437         for (i = 0; i < 4; i++) {
 438                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 439                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 440         }
 441         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 442         if (-1 == pm8001_bar4_shift(pm8001_ha,
 443                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 444                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 445                 return;
 446         }
 447         for (i = 4; i < 8; i++) {
 448                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 449                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 450         }
 451         /*************************************************************
 452         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 453         Device MABC SMOD0 Controls
 454         Address: (via MEMBASE-III):
 455         Using shifted destination address 0x0_0000: with Offset 0xD8
 456
 457         31:28 R/W Reserved Do not change
 458         27:24 R/W SAS_SMOD_SPRDUP 0000
 459         23:20 R/W SAS_SMOD_SPRDDN 0000
 460         19:0  R/W  Reserved Do not change
 461         Upon power-up this register will read as 0x8990c016,
 462         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 463         so that the written value will be 0x8090c016.
 464         This will ensure only down-spreading SSC is enabled on the SPC.
 465         *************************************************************/
 466         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 467         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 468
 469         /*set the shifted destination address to 0x0 to avoid error operation */
 470         pm8001_bar4_shift(pm8001_ha, 0x0);
 471         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 472         return;
 473 }
 474
 475 /**
 476  * mpi_set_open_retry_interval_reg
 477  * @pm8001_ha: our hba card information
 478  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 479  */
 480 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 481                                             u32 interval)
 482 {
 483         u32 offset;
 484         u32 value;
 485         u32 i;
 486         unsigned long flags;
 487
 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 490 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 491 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 492 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 493
 494         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 495         spin_lock_irqsave(&pm8001_ha->lock, flags);
 496         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 497         if (-1 == pm8001_bar4_shift(pm8001_ha,
 498                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 499                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 500                 return;
 501         }
 502         for (i = 0; i < 4; i++) {
 503                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 504                 pm8001_cw32(pm8001_ha, 2, offset, value);
 505         }
 506
 507         if (-1 == pm8001_bar4_shift(pm8001_ha,
 508                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 509                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 510                 return;
 511         }
 512         for (i = 4; i < 8; i++) {
 513                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 514                 pm8001_cw32(pm8001_ha, 2, offset, value);
 515         }
 516         /*set the shifted destination address to 0x0 to avoid error operation */
 517         pm8001_bar4_shift(pm8001_ha, 0x0);
 518         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 519         return;
 520 }
 521
 522 /**
 523  * mpi_init_check - check firmware initialization status.
 524  * @pm8001_ha: our hba card information
 525  */
 526 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 527 {
 528         u32 max_wait_count;
 529         u32 value;
 530         u32 gst_len_mpistate;
 531         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 532         table is updated */
 533         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 534         /* wait until Inbound DoorBell Clear Register toggled */
 535         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 536         do {
 537                 udelay(1);
 538                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 539                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 540         } while ((value != 0) && (--max_wait_count));
 541
 542         if (!max_wait_count)
 543                 return -1;
 544         /* check the MPI-State for initialization */
 545         gst_len_mpistate =
 546                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 547                 GST_GSTLEN_MPIS_OFFSET);
 548         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 549                 return -1;
 550         /* check MPI Initialization error */
 551         gst_len_mpistate = gst_len_mpistate >> 16;
 552         if (0x0000 != gst_len_mpistate)
 553                 return -1;
 554         return 0;
 555 }
 556
 557 /**
 558  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 559  * @pm8001_ha: our hba card information
 560  */
 561 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 562 {
 563         u32 value, value1;
 564         u32 max_wait_count;
 565         /* check error state */
 566         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 567         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 568         /* check AAP error */
 569         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 570                 /* error state */
 571                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 572                 return -1;
 573         }
 574
 575         /* check IOP error */
 576         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 577                 /* error state */
 578                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 579                 return -1;
 580         }
 581
 582         /* bit 4-31 of scratch pad1 should be zeros if it is not
 583         in error state*/
 584         if (value & SCRATCH_PAD1_STATE_MASK) {
 585                 /* error case */
 586                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 587                 return -1;
 588         }
 589
 590         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 591         in error state */
 592         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 593                 /* error case */
 594                 return -1;
 595         }
 596
 597         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 598
 599         /* wait until scratch pad 1 and 2 registers in ready state  */
 600         do {
 601                 udelay(1);
 602                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 603                         & SCRATCH_PAD1_RDY;
 604                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 605                         & SCRATCH_PAD2_RDY;
 606                 if ((--max_wait_count) == 0)
 607                         return -1;
 608         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 609         return 0;
 610 }
 611
 612 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 613 {
 614         void __iomem *base_addr;
 615         u32     value;
 616         u32     offset;
 617         u32     pcibar;
 618         u32     pcilogic;
 619
 620         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 621         offset = value & 0x03FFFFFF;
 622         PM8001_INIT_DBG(pm8001_ha,
 623                 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
 624         pcilogic = (value & 0xFC000000) >> 26;
 625         pcibar = get_pci_bar_index(pcilogic);
 626         PM8001_INIT_DBG(pm8001_ha,
 627                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 628         pm8001_ha->main_cfg_tbl_addr = base_addr =
 629                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 630         pm8001_ha->general_stat_tbl_addr =
 631                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 632         pm8001_ha->inbnd_q_tbl_addr =
 633                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 634         pm8001_ha->outbnd_q_tbl_addr =
 635                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 636 }
 637
 638 /**
 639  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 640  * @pm8001_ha: our hba card information
 641  */
 642 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 643 {
 644         /* check the firmware status */
 645         if (-1 == check_fw_ready(pm8001_ha)) {
 646                 PM8001_FAIL_DBG(pm8001_ha,
 647                         pm8001_printk("Firmware is not ready!\n"));
 648                 return -EBUSY;
 649         }
 650
 651         /* Initialize pci space address eg: mpi offset */
 652         init_pci_device_addresses(pm8001_ha);
 653         init_default_table_values(pm8001_ha);
 654         read_main_config_table(pm8001_ha);
 655         read_general_status_table(pm8001_ha);
 656         read_inbnd_queue_table(pm8001_ha);
 657         read_outbnd_queue_table(pm8001_ha);
 658         /* update main config table ,inbound table and outbound table */
 659         update_main_config_table(pm8001_ha);
 660         update_inbnd_queue_table(pm8001_ha, 0);
 661         update_outbnd_queue_table(pm8001_ha, 0);
 662         mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 663         /* 7->130ms, 34->500ms, 119->1.5s */
 664         mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 665         /* notify firmware update finished and check initialization status */
 666         if (0 == mpi_init_check(pm8001_ha)) {
 667                 PM8001_INIT_DBG(pm8001_ha,
 668                         pm8001_printk("MPI initialize successful!\n"));
 669         } else
 670                 return -EBUSY;
 671         /*This register is a 16-bit timer with a resolution of 1us. This is the
 672         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 673         Zero is not a valid value. A value of 1 in the register will cause the
 674         interrupts to be normal. A value greater than 1 will cause coalescing
 675         delays.*/
 676         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 677         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 678         return 0;
 679 }
 680
 681 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 682 {
 683         u32 max_wait_count;
 684         u32 value;
 685         u32 gst_len_mpistate;
 686         init_pci_device_addresses(pm8001_ha);
 687         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 688         table is stop */
 689         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 690
 691         /* wait until Inbound DoorBell Clear Register toggled */
 692         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 693         do {
 694                 udelay(1);
 695                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 696                 value &= SPC_MSGU_CFG_TABLE_RESET;
 697         } while ((value != 0) && (--max_wait_count));
 698
 699         if (!max_wait_count) {
 700                 PM8001_FAIL_DBG(pm8001_ha,
 701                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 702                 return -1;
 703         }
 704
 705         /* check the MPI-State for termination in progress */
 706         /* wait until Inbound DoorBell Clear Register toggled */
 707         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 708         do {
 709                 udelay(1);
 710                 gst_len_mpistate =
 711                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 712                         GST_GSTLEN_MPIS_OFFSET);
 713                 if (GST_MPI_STATE_UNINIT ==
 714                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 715                         break;
 716         } while (--max_wait_count);
 717         if (!max_wait_count) {
 718                 PM8001_FAIL_DBG(pm8001_ha,
 719                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 720                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 721                 return -1;
 722         }
 723         return 0;
 724 }
 725
 726 /**
 727  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 728  * @pm8001_ha: our hba card information
 729  */
 730 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 731 {
 732         u32 regVal, regVal1, regVal2;
 733         if (mpi_uninit_check(pm8001_ha) != 0) {
 734                 PM8001_FAIL_DBG(pm8001_ha,
 735                         pm8001_printk("MPI state is not ready\n"));
 736                 return -1;
 737         }
 738         /* read the scratch pad 2 register bit 2 */
 739         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 740                 & SCRATCH_PAD2_FWRDY_RST;
 741         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 742                 PM8001_INIT_DBG(pm8001_ha,
 743                         pm8001_printk("Firmware is ready for reset .\n"));
 744         } else {
 745                 unsigned long flags;
 746                 /* Trigger NMI twice via RB6 */
 747                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 748                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 749                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 750                         PM8001_FAIL_DBG(pm8001_ha,
 751                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 752                                         RB6_ACCESS_REG));
 753                         return -1;
 754                 }
 755                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 756                         RB6_MAGIC_NUMBER_RST);
 757                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 758                 /* wait for 100 ms */
 759                 mdelay(100);
 760                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 761                         SCRATCH_PAD2_FWRDY_RST;
 762                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 763                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 764                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 765                         PM8001_FAIL_DBG(pm8001_ha,
 766                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 767                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 768                                 regVal1, regVal2));
 769                         PM8001_FAIL_DBG(pm8001_ha,
 770                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 771                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 772                         PM8001_FAIL_DBG(pm8001_ha,
 773                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 774                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 775                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 776                         return -1;
 777                 }
 778                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 779         }
 780         return 0;
 781 }
 782
 783 /**
 784  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 785  * the FW register status to the originated status.
 786  * @pm8001_ha: our hba card information
 787  * @signature: signature in host scratch pad0 register.
 788  */
 789 static int
 790 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
 791 {
 792         u32     regVal, toggleVal;
 793         u32     max_wait_count;
 794         u32     regVal1, regVal2, regVal3;
 795         unsigned long flags;
 796
 797         /* step1: Check FW is ready for soft reset */
 798         if (soft_reset_ready_check(pm8001_ha) != 0) {
 799                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 800                 return -1;
 801         }
 802
 803         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 804         value to clear */
 805         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 806         spin_lock_irqsave(&pm8001_ha->lock, flags);
 807         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 808                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 809                 PM8001_FAIL_DBG(pm8001_ha,
 810                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 811                         MBIC_AAP1_ADDR_BASE));
 812                 return -1;
 813         }
 814         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 815         PM8001_INIT_DBG(pm8001_ha,
 816                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 817         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 818         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 819         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 820                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 821                 PM8001_FAIL_DBG(pm8001_ha,
 822                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 823                         MBIC_IOP_ADDR_BASE));
 824                 return -1;
 825         }
 826         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 827         PM8001_INIT_DBG(pm8001_ha,
 828                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 829         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 830
 831         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 832         PM8001_INIT_DBG(pm8001_ha,
 833                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 834         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 835
 836         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 837         PM8001_INIT_DBG(pm8001_ha,
 838                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 839         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 840
 841         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 842         PM8001_INIT_DBG(pm8001_ha,
 843                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 844         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 845
 846         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 847         PM8001_INIT_DBG(pm8001_ha,
 848                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 849         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 850
 851         /* read the scratch pad 1 register bit 2 */
 852         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 853                 & SCRATCH_PAD1_RST;
 854         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 855
 856         /* set signature in host scratch pad0 register to tell SPC that the
 857         host performs the soft reset */
 858         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 859
 860         /* read required registers for confirmming */
 861         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 862         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 863                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 864                 PM8001_FAIL_DBG(pm8001_ha,
 865                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 866                         GSM_ADDR_BASE));
 867                 return -1;
 868         }
 869         PM8001_INIT_DBG(pm8001_ha,
 870                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 871                 " Reset = 0x%x\n",
 872                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 873
 874         /* step 3: host read GSM Configuration and Reset register */
 875         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 876         /* Put those bits to low */
 877         /* GSM XCBI offset = 0x70 0000
 878         0x00 Bit 13 COM_SLV_SW_RSTB 1
 879         0x00 Bit 12 QSSP_SW_RSTB 1
 880         0x00 Bit 11 RAAE_SW_RSTB 1
 881         0x00 Bit 9 RB_1_SW_RSTB 1
 882         0x00 Bit 8 SM_SW_RSTB 1
 883         */
 884         regVal &= ~(0x00003b00);
 885         /* host write GSM Configuration and Reset register */
 886         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 887         PM8001_INIT_DBG(pm8001_ha,
 888                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 889                 "Configuration and Reset is set to = 0x%x\n",
 890                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 891
 892         /* step 4: */
 893         /* disable GSM - Read Address Parity Check */
 894         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 895         PM8001_INIT_DBG(pm8001_ha,
 896                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 897                 "Enable = 0x%x\n", regVal1));
 898         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 899         PM8001_INIT_DBG(pm8001_ha,
 900                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 901                 "is set to = 0x%x\n",
 902                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 903
 904         /* disable GSM - Write Address Parity Check */
 905         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 906         PM8001_INIT_DBG(pm8001_ha,
 907                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 908                 " Enable = 0x%x\n", regVal2));
 909         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 910         PM8001_INIT_DBG(pm8001_ha,
 911                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 912                 "Enable is set to = 0x%x\n",
 913                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 914
 915         /* disable GSM - Write Data Parity Check */
 916         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 917         PM8001_INIT_DBG(pm8001_ha,
 918                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 919                 " Enable = 0x%x\n", regVal3));
 920         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 921         PM8001_INIT_DBG(pm8001_ha,
 922                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 923                 "is set to = 0x%x\n",
 924         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 925
 926         /* step 5: delay 10 usec */
 927         udelay(10);
 928         /* step 5-b: set GPIO-0 output control to tristate anyway */
 929         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 930                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 931                 PM8001_INIT_DBG(pm8001_ha,
 932                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 933                                 GPIO_ADDR_BASE));
 934                 return -1;
 935         }
 936         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 937                 PM8001_INIT_DBG(pm8001_ha,
 938                                 pm8001_printk("GPIO Output Control Register:"
 939                                 " = 0x%x\n", regVal));
 940         /* set GPIO-0 output control to tri-state */
 941         regVal &= 0xFFFFFFFC;
 942         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 943
 944         /* Step 6: Reset the IOP and AAP1 */
 945         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 946         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 947                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 948                 PM8001_FAIL_DBG(pm8001_ha,
 949                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 950                         SPC_TOP_LEVEL_ADDR_BASE));
 951                 return -1;
 952         }
 953         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 954         PM8001_INIT_DBG(pm8001_ha,
 955                 pm8001_printk("Top Register before resetting IOP/AAP1"
 956                 ":= 0x%x\n", regVal));
 957         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 958         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 959
 960         /* step 7: Reset the BDMA/OSSP */
 961         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 962         PM8001_INIT_DBG(pm8001_ha,
 963                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 964                 ": = 0x%x\n", regVal));
 965         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 966         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 967
 968         /* step 8: delay 10 usec */
 969         udelay(10);
 970
 971         /* step 9: bring the BDMA and OSSP out of reset */
 972         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 973         PM8001_INIT_DBG(pm8001_ha,
 974                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
 975                 ":= 0x%x\n", regVal));
 976         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 977         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 978
 979         /* step 10: delay 10 usec */
 980         udelay(10);
 981
 982         /* step 11: reads and sets the GSM Configuration and Reset Register */
 983         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 984         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 985                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 986                 PM8001_FAIL_DBG(pm8001_ha,
 987                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 988                         GSM_ADDR_BASE));
 989                 return -1;
 990         }
 991         PM8001_INIT_DBG(pm8001_ha,
 992                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
 993                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 994         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 995         /* Put those bits to high */
 996         /* GSM XCBI offset = 0x70 0000
 997         0x00 Bit 13 COM_SLV_SW_RSTB 1
 998         0x00 Bit 12 QSSP_SW_RSTB 1
 999         0x00 Bit 11 RAAE_SW_RSTB 1
1000         0x00 Bit 9   RB_1_SW_RSTB 1
1001         0x00 Bit 8   SM_SW_RSTB 1
1002         */
1003         regVal |= (GSM_CONFIG_RESET_VALUE);
1004         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1005         PM8001_INIT_DBG(pm8001_ha,
1006                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1007                 " Configuration and Reset is set to = 0x%x\n",
1008                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1009
1010         /* step 12: Restore GSM - Read Address Parity Check */
1011         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1012         /* just for debugging */
1013         PM8001_INIT_DBG(pm8001_ha,
1014                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1015                 " = 0x%x\n", regVal));
1016         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1017         PM8001_INIT_DBG(pm8001_ha,
1018                 pm8001_printk("GSM 0x700038 - Read Address Parity"
1019                 " Check Enable is set to = 0x%x\n",
1020                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1021         /* Restore GSM - Write Address Parity Check */
1022         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1023         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1024         PM8001_INIT_DBG(pm8001_ha,
1025                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1026                 " Enable is set to = 0x%x\n",
1027                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1028         /* Restore GSM - Write Data Parity Check */
1029         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1030         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1031         PM8001_INIT_DBG(pm8001_ha,
1032                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1033                 "is set to = 0x%x\n",
1034                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1035
1036         /* step 13: bring the IOP and AAP1 out of reset */
1037         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1038         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1039                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1040                 PM8001_FAIL_DBG(pm8001_ha,
1041                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
1042                         SPC_TOP_LEVEL_ADDR_BASE));
1043                 return -1;
1044         }
1045         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1046         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1047         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1048
1049         /* step 14: delay 10 usec - Normal Mode */
1050         udelay(10);
1051         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1052         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1053                 /* step 15 (Normal Mode): wait until scratch pad1 register
1054                 bit 2 toggled */
1055                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1056                 do {
1057                         udelay(1);
1058                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1059                                 SCRATCH_PAD1_RST;
1060                 } while ((regVal != toggleVal) && (--max_wait_count));
1061
1062                 if (!max_wait_count) {
1063                         regVal = pm8001_cr32(pm8001_ha, 0,
1064                                 MSGU_SCRATCH_PAD_1);
1065                         PM8001_FAIL_DBG(pm8001_ha,
1066                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1067                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1068                                 toggleVal, regVal));
1069                         PM8001_FAIL_DBG(pm8001_ha,
1070                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1071                                 pm8001_cr32(pm8001_ha, 0,
1072                                 MSGU_SCRATCH_PAD_0)));
1073                         PM8001_FAIL_DBG(pm8001_ha,
1074                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1075                                 pm8001_cr32(pm8001_ha, 0,
1076                                 MSGU_SCRATCH_PAD_2)));
1077                         PM8001_FAIL_DBG(pm8001_ha,
1078                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1079                                 pm8001_cr32(pm8001_ha, 0,
1080                                 MSGU_SCRATCH_PAD_3)));
1081                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1082                         return -1;
1083                 }
1084
1085                 /* step 16 (Normal) - Clear ODMR and ODCR */
1086                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1087                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1088
1089                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1090                 ready - 1 sec timeout */
1091                 /* Wait for the SPC Configuration Table to be ready */
1092                 if (check_fw_ready(pm8001_ha) == -1) {
1093                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1094                         /* return error if MPI Configuration Table not ready */
1095                         PM8001_INIT_DBG(pm8001_ha,
1096                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1097                                 " = 0x%x\n", regVal));
1098                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1099                         /* return error if MPI Configuration Table not ready */
1100                         PM8001_INIT_DBG(pm8001_ha,
1101                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1102                                 " = 0x%x\n", regVal));
1103                         PM8001_INIT_DBG(pm8001_ha,
1104                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1105                                 pm8001_cr32(pm8001_ha, 0,
1106                                 MSGU_SCRATCH_PAD_0)));
1107                         PM8001_INIT_DBG(pm8001_ha,
1108                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1109                                 pm8001_cr32(pm8001_ha, 0,
1110                                 MSGU_SCRATCH_PAD_3)));
1111                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1112                         return -1;
1113                 }
1114         }
1115         pm8001_bar4_shift(pm8001_ha, 0);
1116         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1117
1118         PM8001_INIT_DBG(pm8001_ha,
1119                 pm8001_printk("SPC soft reset Complete\n"));
1120         return 0;
1121 }
1122
1123 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1124 {
1125         u32 i;
1126         u32 regVal;
1127         PM8001_INIT_DBG(pm8001_ha,
1128                 pm8001_printk("chip reset start\n"));
1129
1130         /* do SPC chip reset. */
1131         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1132         regVal &= ~(SPC_REG_RESET_DEVICE);
1133         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1134
1135         /* delay 10 usec */
1136         udelay(10);
1137
1138         /* bring chip reset out of reset */
1139         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1140         regVal |= SPC_REG_RESET_DEVICE;
1141         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1142
1143         /* delay 10 usec */
1144         udelay(10);
1145
1146         /* wait for 20 msec until the firmware gets reloaded */
1147         i = 20;
1148         do {
1149                 mdelay(1);
1150         } while ((--i) != 0);
1151
1152         PM8001_INIT_DBG(pm8001_ha,
1153                 pm8001_printk("chip reset finished\n"));
1154 }
1155
1156 /**
1157  * pm8001_chip_iounmap - which maped when initialized.
1158  * @pm8001_ha: our hba card information
1159  */
1160 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1161 {
1162         s8 bar, logical = 0;
1163         for (bar = 0; bar < 6; bar++) {
1164                 /*
1165                 ** logical BARs for SPC:
1166                 ** bar 0 and 1 - logical BAR0
1167                 ** bar 2 and 3 - logical BAR1
1168                 ** bar4 - logical BAR2
1169                 ** bar5 - logical BAR3
1170                 ** Skip the appropriate assignments:
1171                 */
1172                 if ((bar == 1) || (bar == 3))
1173                         continue;
1174                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1175                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1176                         logical++;
1177                 }
1178         }
1179 }
1180
1181 /**
1182  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1183  * @pm8001_ha: our hba card information
1184  */
1185 static void
1186 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1187 {
1188         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1189         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1190 }
1191
1192  /**
1193   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1194   * @pm8001_ha: our hba card information
1195   */
1196 static void
1197 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1198 {
1199         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1200 }
1201
1202 /**
1203  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1204  * @pm8001_ha: our hba card information
1205  */
1206 static void
1207 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1208         u32 int_vec_idx)
1209 {
1210         u32 msi_index;
1211         u32 value;
1212         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1213         msi_index += MSIX_TABLE_BASE;
1214         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1215         value = (1 << int_vec_idx);
1216         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1217
1218 }
1219
1220 /**
1221  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1222  * @pm8001_ha: our hba card information
1223  */
1224 static void
1225 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1226         u32 int_vec_idx)
1227 {
1228         u32 msi_index;
1229         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1230         msi_index += MSIX_TABLE_BASE;
1231         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1232 }
1233
1234 /**
1235  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1236  * @pm8001_ha: our hba card information
1237  */
1238 static void
1239 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1240 {
1241 #ifdef PM8001_USE_MSIX
1242         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1243         return;
1244 #endif
1245         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1246
1247 }
1248
1249 /**
1250  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1251  * @pm8001_ha: our hba card information
1252  */
1253 static void
1254 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1255 {
1256 #ifdef PM8001_USE_MSIX
1257         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1258         return;
1259 #endif
1260         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1261
1262 }
1263
1264 /**
1265  * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1266  * @circularQ: the inbound queue  we want to transfer to HBA.
1267  * @messageSize: the message size of this transfer, normally it is 64 bytes
1268  * @messagePtr: the pointer to message.
1269  */
1270 static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1271                             u16 messageSize, void **messagePtr)
1272 {
1273         u32 offset, consumer_index;
1274         struct mpi_msg_hdr *msgHeader;
1275         u8 bcCount = 1; /* only support single buffer */
1276
1277         /* Checks is the requested message size can be allocated in this queue*/
1278         if (messageSize > 64) {
1279                 *messagePtr = NULL;
1280                 return -1;
1281         }
1282
1283         /* Stores the new consumer index */
1284         consumer_index = pm8001_read_32(circularQ->ci_virt);
1285         circularQ->consumer_index = cpu_to_le32(consumer_index);
1286         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1287                 le32_to_cpu(circularQ->consumer_index)) {
1288                 *messagePtr = NULL;
1289                 return -1;
1290         }
1291         /* get memory IOMB buffer address */
1292         offset = circularQ->producer_idx * 64;
1293         /* increment to next bcCount element */
1294         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1295                                 % PM8001_MPI_QUEUE;
1296         /* Adds that distance to the base of the region virtual address plus
1297         the message header size*/
1298         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1299         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1300         return 0;
1301 }
1302
1303 /**
1304  * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1305  * to tell the fw to get this message from IOMB.
1306  * @pm8001_ha: our hba card information
1307  * @circularQ: the inbound queue we want to transfer to HBA.
1308  * @opCode: the operation code represents commands which LLDD and fw recognized.
1309  * @payload: the command payload of each operation command.
1310  */
1311 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1312                          struct inbound_queue_table *circularQ,
1313                          u32 opCode, void *payload)
1314 {
1315         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1316         u32 responseQueue = 0;
1317         void *pMessage;
1318
1319         if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1320                 PM8001_IO_DBG(pm8001_ha,
1321                         pm8001_printk("No free mpi buffer\n"));
1322                 return -1;
1323         }
1324         BUG_ON(!payload);
1325         /*Copy to the payload*/
1326         memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1327
1328         /*Build the header*/
1329         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1330                 | ((responseQueue & 0x3F) << 16)
1331                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1332
1333         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1334         /*Update the PI to the firmware*/
1335         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1336                 circularQ->pi_offset, circularQ->producer_idx);
1337         PM8001_IO_DBG(pm8001_ha,
1338                 pm8001_printk("after PI= %d CI= %d\n", circularQ->producer_idx,
1339                 circularQ->consumer_index));
1340         return 0;
1341 }
1342
1343 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1344                             struct outbound_queue_table *circularQ, u8 bc)
1345 {
1346         u32 producer_index;
1347         struct mpi_msg_hdr *msgHeader;
1348         struct mpi_msg_hdr *pOutBoundMsgHeader;
1349
1350         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1351         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1352                                 circularQ->consumer_idx * 64);
1353         if (pOutBoundMsgHeader != msgHeader) {
1354                 PM8001_FAIL_DBG(pm8001_ha,
1355                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1356                         circularQ->consumer_idx, msgHeader));
1357
1358                 /* Update the producer index from SPC */
1359                 producer_index = pm8001_read_32(circularQ->pi_virt);
1360                 circularQ->producer_index = cpu_to_le32(producer_index);
1361                 PM8001_FAIL_DBG(pm8001_ha,
1362                         pm8001_printk("consumer_idx = %d producer_index = %d"
1363                         "msgHeader = %p\n", circularQ->consumer_idx,
1364                         circularQ->producer_index, msgHeader));
1365                 return 0;
1366         }
1367         /* free the circular queue buffer elements associated with the message*/
1368         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1369                                 % PM8001_MPI_QUEUE;
1370         /* update the CI of outbound queue */
1371         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1372                 circularQ->consumer_idx);
1373         /* Update the producer index from SPC*/
1374         producer_index = pm8001_read_32(circularQ->pi_virt);
1375         circularQ->producer_index = cpu_to_le32(producer_index);
1376         PM8001_IO_DBG(pm8001_ha,
1377                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1378                 circularQ->producer_index));
1379         return 0;
1380 }
1381
1382 /**
1383  * mpi_msg_consume- get the MPI message from  outbound queue message table.
1384  * @pm8001_ha: our hba card information
1385  * @circularQ: the outbound queue  table.
1386  * @messagePtr1: the message contents of this outbound message.
1387  * @pBC: the message size.
1388  */
1389 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1390                            struct outbound_queue_table *circularQ,
1391                            void **messagePtr1, u8 *pBC)
1392 {
1393         struct mpi_msg_hdr      *msgHeader;
1394         __le32  msgHeader_tmp;
1395         u32 header_tmp;
1396         do {
1397                 /* If there are not-yet-delivered messages ... */
1398                 if (le32_to_cpu(circularQ->producer_index)
1399                         != circularQ->consumer_idx) {
1400                         /*Get the pointer to the circular queue buffer element*/
1401                         msgHeader = (struct mpi_msg_hdr *)
1402                                 (circularQ->base_virt +
1403                                 circularQ->consumer_idx * 64);
1404                         /* read header */
1405                         header_tmp = pm8001_read_32(msgHeader);
1406                         msgHeader_tmp = cpu_to_le32(header_tmp);
1407                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1408                                 if (OPC_OUB_SKIP_ENTRY !=
1409                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1410                                         *messagePtr1 =
1411                                                 ((u8 *)msgHeader) +
1412                                                 sizeof(struct mpi_msg_hdr);
1413                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1414                                                 >> 24) & 0x1f);
1415                                         PM8001_IO_DBG(pm8001_ha,
1416                                                 pm8001_printk(": CI=%d PI=%d "
1417                                                 "msgHeader=%x\n",
1418                                                 circularQ->consumer_idx,
1419                                                 circularQ->producer_index,
1420                                                 msgHeader_tmp));
1421                                         return MPI_IO_STATUS_SUCCESS;
1422                                 } else {
1423                                         circularQ->consumer_idx =
1424                                                 (circularQ->consumer_idx +
1425                                                 ((le32_to_cpu(msgHeader_tmp)
1426                                                  >> 24) & 0x1f))
1427                                                         % PM8001_MPI_QUEUE;
1428                                         msgHeader_tmp = 0;
1429                                         pm8001_write_32(msgHeader, 0, 0);
1430                                         /* update the CI of outbound queue */
1431                                         pm8001_cw32(pm8001_ha,
1432                                                 circularQ->ci_pci_bar,
1433                                                 circularQ->ci_offset,
1434                                                 circularQ->consumer_idx);
1435                                 }
1436                         } else {
1437                                 circularQ->consumer_idx =
1438                                         (circularQ->consumer_idx +
1439                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1440                                         0x1f)) % PM8001_MPI_QUEUE;
1441                                 msgHeader_tmp = 0;
1442                                 pm8001_write_32(msgHeader, 0, 0);
1443                                 /* update the CI of outbound queue */
1444                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1445                                         circularQ->ci_offset,
1446                                         circularQ->consumer_idx);
1447                                 return MPI_IO_STATUS_FAIL;
1448                         }
1449                 } else {
1450                         u32 producer_index;
1451                         void *pi_virt = circularQ->pi_virt;
1452                         /* Update the producer index from SPC */
1453                         producer_index = pm8001_read_32(pi_virt);
1454                         circularQ->producer_index = cpu_to_le32(producer_index);
1455                 }
1456         } while (le32_to_cpu(circularQ->producer_index) !=
1457                 circularQ->consumer_idx);
1458         /* while we don't have any more not-yet-delivered message */
1459         /* report empty */
1460         return MPI_IO_STATUS_BUSY;
1461 }
1462
1463 static void pm8001_work_fn(struct work_struct *work)
1464 {
1465         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1466         struct pm8001_device *pm8001_dev;
1467         struct domain_device *dev;
1468
1469         /*
1470          * So far, all users of this stash an associated structure here.
1471          * If we get here, and this pointer is null, then the action
1472          * was cancelled. This nullification happens when the device
1473          * goes away.
1474          */
1475         pm8001_dev = pw->data; /* Most stash device structure */
1476         if ((pm8001_dev == NULL)
1477          || ((pw->handler != IO_XFER_ERROR_BREAK)
1478           && (pm8001_dev->dev_type == NO_DEVICE))) {
1479                 kfree(pw);
1480                 return;
1481         }
1482
1483         switch (pw->handler) {
1484         case IO_XFER_ERROR_BREAK:
1485         {       /* This one stashes the sas_task instead */
1486                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1487                 u32 tag;
1488                 struct pm8001_ccb_info *ccb;
1489                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1490                 unsigned long flags, flags1;
1491                 struct task_status_struct *ts;
1492                 int i;
1493
1494                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1495                         break; /* Task still on lu */
1496                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1497
1498                 spin_lock_irqsave(&t->task_state_lock, flags1);
1499                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1500                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1501                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1502                         break; /* Task got completed by another */
1503                 }
1504                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1505
1506                 /* Search for a possible ccb that matches the task */
1507                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1508                         ccb = &pm8001_ha->ccb_info[i];
1509                         tag = ccb->ccb_tag;
1510                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1511                                 break;
1512                 }
1513                 if (!ccb) {
1514                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1515                         break; /* Task got freed by another */
1516                 }
1517                 ts = &t->task_status;
1518                 ts->resp = SAS_TASK_COMPLETE;
1519                 /* Force the midlayer to retry */
1520                 ts->stat = SAS_QUEUE_FULL;
1521                 pm8001_dev = ccb->device;
1522                 if (pm8001_dev)
1523                         pm8001_dev->running_req--;
1524                 spin_lock_irqsave(&t->task_state_lock, flags1);
1525                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1526                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1527                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1528                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1529                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1530                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1531                                 " done with event 0x%x resp 0x%x stat 0x%x but"
1532                                 " aborted by upper layer!\n",
1533                                 t, pw->handler, ts->resp, ts->stat));
1534                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1535                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1536                 } else {
1537                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1538                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1539                         mb();/* in order to force CPU ordering */
1540                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1541                         t->task_done(t);
1542                 }
1543         }       break;
1544         case IO_XFER_OPEN_RETRY_TIMEOUT:
1545         {       /* This one stashes the sas_task instead */
1546                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1547                 u32 tag;
1548                 struct pm8001_ccb_info *ccb;
1549                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1550                 unsigned long flags, flags1;
1551                 int i, ret = 0;
1552
1553                 PM8001_IO_DBG(pm8001_ha,
1554                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1555
1556                 ret = pm8001_query_task(t);
1557
1558                 PM8001_IO_DBG(pm8001_ha,
1559                         switch (ret) {
1560                         case TMF_RESP_FUNC_SUCC:
1561                                 pm8001_printk("...Task on lu\n");
1562                                 break;
1563
1564                         case TMF_RESP_FUNC_COMPLETE:
1565                                 pm8001_printk("...Task NOT on lu\n");
1566                                 break;
1567
1568                         default:
1569                                 pm8001_printk("...query task failed!!!\n");
1570                                 break;
1571                         });
1572
1573                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1574
1575                 spin_lock_irqsave(&t->task_state_lock, flags1);
1576
1577                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1578                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1579                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1580                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1581                                 (void)pm8001_abort_task(t);
1582                         break; /* Task got completed by another */
1583                 }
1584
1585                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1586
1587                 /* Search for a possible ccb that matches the task */
1588                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1589                         ccb = &pm8001_ha->ccb_info[i];
1590                         tag = ccb->ccb_tag;
1591                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1592                                 break;
1593                 }
1594                 if (!ccb) {
1595                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1596                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1597                                 (void)pm8001_abort_task(t);
1598                         break; /* Task got freed by another */
1599                 }
1600
1601                 pm8001_dev = ccb->device;
1602                 dev = pm8001_dev->sas_device;
1603
1604                 switch (ret) {
1605                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1606                         ccb->open_retry = 1; /* Snub completion */
1607                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1608                         ret = pm8001_abort_task(t);
1609                         ccb->open_retry = 0;
1610                         switch (ret) {
1611                         case TMF_RESP_FUNC_SUCC:
1612                         case TMF_RESP_FUNC_COMPLETE:
1613                                 break;
1614                         default: /* device misbehavior */
1615                                 ret = TMF_RESP_FUNC_FAILED;
1616                                 PM8001_IO_DBG(pm8001_ha,
1617                                         pm8001_printk("...Reset phy\n"));
1618                                 pm8001_I_T_nexus_reset(dev);
1619                                 break;
1620                         }
1621                         break;
1622
1623                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1624                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1625                         /* Do we need to abort the task locally? */
1626                         break;
1627
1628                 default: /* device misbehavior */
1629                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1630                         ret = TMF_RESP_FUNC_FAILED;
1631                         PM8001_IO_DBG(pm8001_ha,
1632                                 pm8001_printk("...Reset phy\n"));
1633                         pm8001_I_T_nexus_reset(dev);
1634                 }
1635
1636                 if (ret == TMF_RESP_FUNC_FAILED)
1637                         t = NULL;
1638                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1639                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1640         }       break;
1641         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1642                 dev = pm8001_dev->sas_device;
1643                 pm8001_I_T_nexus_reset(dev);
1644                 break;
1645         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1646                 dev = pm8001_dev->sas_device;
1647                 pm8001_I_T_nexus_reset(dev);
1648                 break;
1649         case IO_DS_IN_ERROR:
1650                 dev = pm8001_dev->sas_device;
1651                 pm8001_I_T_nexus_reset(dev);
1652                 break;
1653         case IO_DS_NON_OPERATIONAL:
1654                 dev = pm8001_dev->sas_device;
1655                 pm8001_I_T_nexus_reset(dev);
1656                 break;
1657         }
1658         kfree(pw);
1659 }
1660
1661 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1662                                int handler)
1663 {
1664         struct pm8001_work *pw;
1665         int ret = 0;
1666
1667         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1668         if (pw) {
1669                 pw->pm8001_ha = pm8001_ha;
1670                 pw->data = data;
1671                 pw->handler = handler;
1672                 INIT_WORK(&pw->work, pm8001_work_fn);
1673                 queue_work(pm8001_wq, &pw->work);
1674         } else
1675                 ret = -ENOMEM;
1676
1677         return ret;
1678 }
1679
1680 /**
1681  * mpi_ssp_completion- process the event that FW response to the SSP request.
1682  * @pm8001_ha: our hba card information
1683  * @piomb: the message contents of this outbound message.
1684  *
1685  * When FW has completed a ssp request for example a IO request, after it has
1686  * filled the SG data with the data, it will trigger this event represent
1687  * that he has finished the job,please check the coresponding buffer.
1688  * So we will tell the caller who maybe waiting the result to tell upper layer
1689  * that the task has been finished.
1690  */
1691 static void
1692 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1693 {
1694         struct sas_task *t;
1695         struct pm8001_ccb_info *ccb;
1696         unsigned long flags;
1697         u32 status;
1698         u32 param;
1699         u32 tag;
1700         struct ssp_completion_resp *psspPayload;
1701         struct task_status_struct *ts;
1702         struct ssp_response_iu *iu;
1703         struct pm8001_device *pm8001_dev;
1704         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1705         status = le32_to_cpu(psspPayload->status);
1706         tag = le32_to_cpu(psspPayload->tag);
1707         ccb = &pm8001_ha->ccb_info[tag];
1708         if ((status == IO_ABORTED) && ccb->open_retry) {
1709                 /* Being completed by another */
1710                 ccb->open_retry = 0;
1711                 return;
1712         }
1713         pm8001_dev = ccb->device;
1714         param = le32_to_cpu(psspPayload->param);
1715
1716         t = ccb->task;
1717
1718         if (status && status != IO_UNDERFLOW)
1719                 PM8001_FAIL_DBG(pm8001_ha,
1720                         pm8001_printk("sas IO status 0x%x\n", status));
1721         if (unlikely(!t || !t->lldd_task || !t->dev))
1722                 return;
1723         ts = &t->task_status;
1724         switch (status) {
1725         case IO_SUCCESS:
1726                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1727                         ",param = %d\n", param));
1728                 if (param == 0) {
1729                         ts->resp = SAS_TASK_COMPLETE;
1730                         ts->stat = SAM_STAT_GOOD;
1731                 } else {
1732                         ts->resp = SAS_TASK_COMPLETE;
1733                         ts->stat = SAS_PROTO_RESPONSE;
1734                         ts->residual = param;
1735                         iu = &psspPayload->ssp_resp_iu;
1736                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1737                 }
1738                 if (pm8001_dev)
1739                         pm8001_dev->running_req--;
1740                 break;
1741         case IO_ABORTED:
1742                 PM8001_IO_DBG(pm8001_ha,
1743                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1744                 ts->resp = SAS_TASK_COMPLETE;
1745                 ts->stat = SAS_ABORTED_TASK;
1746                 break;
1747         case IO_UNDERFLOW:
1748                 /* SSP Completion with error */
1749                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1750                         ",param = %d\n", param));
1751                 ts->resp = SAS_TASK_COMPLETE;
1752                 ts->stat = SAS_DATA_UNDERRUN;
1753                 ts->residual = param;
1754                 if (pm8001_dev)
1755                         pm8001_dev->running_req--;
1756                 break;
1757         case IO_NO_DEVICE:
1758                 PM8001_IO_DBG(pm8001_ha,
1759                         pm8001_printk("IO_NO_DEVICE\n"));
1760                 ts->resp = SAS_TASK_UNDELIVERED;
1761                 ts->stat = SAS_PHY_DOWN;
1762                 break;
1763         case IO_XFER_ERROR_BREAK:
1764                 PM8001_IO_DBG(pm8001_ha,
1765                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1766                 ts->resp = SAS_TASK_COMPLETE;
1767                 ts->stat = SAS_OPEN_REJECT;
1768                 /* Force the midlayer to retry */
1769                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1770                 break;
1771         case IO_XFER_ERROR_PHY_NOT_READY:
1772                 PM8001_IO_DBG(pm8001_ha,
1773                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1774                 ts->resp = SAS_TASK_COMPLETE;
1775                 ts->stat = SAS_OPEN_REJECT;
1776                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1777                 break;
1778         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1779                 PM8001_IO_DBG(pm8001_ha,
1780                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1781                 ts->resp = SAS_TASK_COMPLETE;
1782                 ts->stat = SAS_OPEN_REJECT;
1783                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1784                 break;
1785         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1786                 PM8001_IO_DBG(pm8001_ha,
1787                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1788                 ts->resp = SAS_TASK_COMPLETE;
1789                 ts->stat = SAS_OPEN_REJECT;
1790                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1791                 break;
1792         case IO_OPEN_CNX_ERROR_BREAK:
1793                 PM8001_IO_DBG(pm8001_ha,
1794                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1795                 ts->resp = SAS_TASK_COMPLETE;
1796                 ts->stat = SAS_OPEN_REJECT;
1797                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1798                 break;
1799         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1800                 PM8001_IO_DBG(pm8001_ha,
1801                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1802                 ts->resp = SAS_TASK_COMPLETE;
1803                 ts->stat = SAS_OPEN_REJECT;
1804                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1805                 if (!t->uldd_task)
1806                         pm8001_handle_event(pm8001_ha,
1807                                 pm8001_dev,
1808                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1809                 break;
1810         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1811                 PM8001_IO_DBG(pm8001_ha,
1812                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1813                 ts->resp = SAS_TASK_COMPLETE;
1814                 ts->stat = SAS_OPEN_REJECT;
1815                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1816                 break;
1817         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1818                 PM8001_IO_DBG(pm8001_ha,
1819                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1820                         "NOT_SUPPORTED\n"));
1821                 ts->resp = SAS_TASK_COMPLETE;
1822                 ts->stat = SAS_OPEN_REJECT;
1823                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1824                 break;
1825         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1826                 PM8001_IO_DBG(pm8001_ha,
1827                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1828                 ts->resp = SAS_TASK_UNDELIVERED;
1829                 ts->stat = SAS_OPEN_REJECT;
1830                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1831                 break;
1832         case IO_XFER_ERROR_NAK_RECEIVED:
1833                 PM8001_IO_DBG(pm8001_ha,
1834                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1835                 ts->resp = SAS_TASK_COMPLETE;
1836                 ts->stat = SAS_OPEN_REJECT;
1837                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1838                 break;
1839         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1840                 PM8001_IO_DBG(pm8001_ha,
1841                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1842                 ts->resp = SAS_TASK_COMPLETE;
1843                 ts->stat = SAS_NAK_R_ERR;
1844                 break;
1845         case IO_XFER_ERROR_DMA:
1846                 PM8001_IO_DBG(pm8001_ha,
1847                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1848                 ts->resp = SAS_TASK_COMPLETE;
1849                 ts->stat = SAS_OPEN_REJECT;
1850                 break;
1851         case IO_XFER_OPEN_RETRY_TIMEOUT:
1852                 PM8001_IO_DBG(pm8001_ha,
1853                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1854                 ts->resp = SAS_TASK_COMPLETE;
1855                 ts->stat = SAS_OPEN_REJECT;
1856                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1857                 break;
1858         case IO_XFER_ERROR_OFFSET_MISMATCH:
1859                 PM8001_IO_DBG(pm8001_ha,
1860                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1861                 ts->resp = SAS_TASK_COMPLETE;
1862                 ts->stat = SAS_OPEN_REJECT;
1863                 break;
1864         case IO_PORT_IN_RESET:
1865                 PM8001_IO_DBG(pm8001_ha,
1866                         pm8001_printk("IO_PORT_IN_RESET\n"));
1867                 ts->resp = SAS_TASK_COMPLETE;
1868                 ts->stat = SAS_OPEN_REJECT;
1869                 break;
1870         case IO_DS_NON_OPERATIONAL:
1871                 PM8001_IO_DBG(pm8001_ha,
1872                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1873                 ts->resp = SAS_TASK_COMPLETE;
1874                 ts->stat = SAS_OPEN_REJECT;
1875                 if (!t->uldd_task)
1876                         pm8001_handle_event(pm8001_ha,
1877                                 pm8001_dev,
1878                                 IO_DS_NON_OPERATIONAL);
1879                 break;
1880         case IO_DS_IN_RECOVERY:
1881                 PM8001_IO_DBG(pm8001_ha,
1882                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1883                 ts->resp = SAS_TASK_COMPLETE;
1884                 ts->stat = SAS_OPEN_REJECT;
1885                 break;
1886         case IO_TM_TAG_NOT_FOUND:
1887                 PM8001_IO_DBG(pm8001_ha,
1888                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1889                 ts->resp = SAS_TASK_COMPLETE;
1890                 ts->stat = SAS_OPEN_REJECT;
1891                 break;
1892         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1893                 PM8001_IO_DBG(pm8001_ha,
1894                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1895                 ts->resp = SAS_TASK_COMPLETE;
1896                 ts->stat = SAS_OPEN_REJECT;
1897                 break;
1898         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1899                 PM8001_IO_DBG(pm8001_ha,
1900                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1901                 ts->resp = SAS_TASK_COMPLETE;
1902                 ts->stat = SAS_OPEN_REJECT;
1903                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1904                 break;
1905         default:
1906                 PM8001_IO_DBG(pm8001_ha,
1907                         pm8001_printk("Unknown status 0x%x\n", status));
1908                 /* not allowed case. Therefore, return failed status */
1909                 ts->resp = SAS_TASK_COMPLETE;
1910                 ts->stat = SAS_OPEN_REJECT;
1911                 break;
1912         }
1913         PM8001_IO_DBG(pm8001_ha,
1914                 pm8001_printk("scsi_status = %x \n ",
1915                 psspPayload->ssp_resp_iu.status));
1916         spin_lock_irqsave(&t->task_state_lock, flags);
1917         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1918         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1919         t->task_state_flags |= SAS_TASK_STATE_DONE;
1920         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1921                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1922                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1923                         " io_status 0x%x resp 0x%x "
1924                         "stat 0x%x but aborted by upper layer!\n",
1925                         t, status, ts->resp, ts->stat));
1926                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1927         } else {
1928                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1929                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1930                 mb();/* in order to force CPU ordering */
1931                 t->task_done(t);
1932         }
1933 }
1934
1935 /*See the comments for mpi_ssp_completion */
1936 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1937 {
1938         struct sas_task *t;
1939         unsigned long flags;
1940         struct task_status_struct *ts;
1941         struct pm8001_ccb_info *ccb;
1942         struct pm8001_device *pm8001_dev;
1943         struct ssp_event_resp *psspPayload =
1944                 (struct ssp_event_resp *)(piomb + 4);
1945         u32 event = le32_to_cpu(psspPayload->event);
1946         u32 tag = le32_to_cpu(psspPayload->tag);
1947         u32 port_id = le32_to_cpu(psspPayload->port_id);
1948         u32 dev_id = le32_to_cpu(psspPayload->device_id);
1949
1950         ccb = &pm8001_ha->ccb_info[tag];
1951         t = ccb->task;
1952         pm8001_dev = ccb->device;
1953         if (event)
1954                 PM8001_FAIL_DBG(pm8001_ha,
1955                         pm8001_printk("sas IO status 0x%x\n", event));
1956         if (unlikely(!t || !t->lldd_task || !t->dev))
1957                 return;
1958         ts = &t->task_status;
1959         PM8001_IO_DBG(pm8001_ha,
1960                 pm8001_printk("port_id = %x,device_id = %x\n",
1961                 port_id, dev_id));
1962         switch (event) {
1963         case IO_OVERFLOW:
1964                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1965                 ts->resp = SAS_TASK_COMPLETE;
1966                 ts->stat = SAS_DATA_OVERRUN;
1967                 ts->residual = 0;
1968                 if (pm8001_dev)
1969                         pm8001_dev->running_req--;
1970                 break;
1971         case IO_XFER_ERROR_BREAK:
1972                 PM8001_IO_DBG(pm8001_ha,
1973                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1974                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1975                 return;
1976         case IO_XFER_ERROR_PHY_NOT_READY:
1977                 PM8001_IO_DBG(pm8001_ha,
1978                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1979                 ts->resp = SAS_TASK_COMPLETE;
1980                 ts->stat = SAS_OPEN_REJECT;
1981                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1982                 break;
1983         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1984                 PM8001_IO_DBG(pm8001_ha,
1985                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1986                         "_SUPPORTED\n"));
1987                 ts->resp = SAS_TASK_COMPLETE;
1988                 ts->stat = SAS_OPEN_REJECT;
1989                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1990                 break;
1991         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1992                 PM8001_IO_DBG(pm8001_ha,
1993                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1994                 ts->resp = SAS_TASK_COMPLETE;
1995                 ts->stat = SAS_OPEN_REJECT;
1996                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1997                 break;
1998         case IO_OPEN_CNX_ERROR_BREAK:
1999                 PM8001_IO_DBG(pm8001_ha,
2000                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2001                 ts->resp = SAS_TASK_COMPLETE;
2002                 ts->stat = SAS_OPEN_REJECT;
2003                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2004                 break;
2005         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2006                 PM8001_IO_DBG(pm8001_ha,
2007                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2008                 ts->resp = SAS_TASK_COMPLETE;
2009                 ts->stat = SAS_OPEN_REJECT;
2010                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2011                 if (!t->uldd_task)
2012                         pm8001_handle_event(pm8001_ha,
2013                                 pm8001_dev,
2014                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2015                 break;
2016         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2017                 PM8001_IO_DBG(pm8001_ha,
2018                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2019                 ts->resp = SAS_TASK_COMPLETE;
2020                 ts->stat = SAS_OPEN_REJECT;
2021                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2022                 break;
2023         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2024                 PM8001_IO_DBG(pm8001_ha,
2025                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2026                         "NOT_SUPPORTED\n"));
2027                 ts->resp = SAS_TASK_COMPLETE;
2028                 ts->stat = SAS_OPEN_REJECT;
2029                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2030                 break;
2031         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2032                 PM8001_IO_DBG(pm8001_ha,
2033                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2034                 ts->resp = SAS_TASK_COMPLETE;
2035                 ts->stat = SAS_OPEN_REJECT;
2036                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2037                 break;
2038         case IO_XFER_ERROR_NAK_RECEIVED:
2039                 PM8001_IO_DBG(pm8001_ha,
2040                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2041                 ts->resp = SAS_TASK_COMPLETE;
2042                 ts->stat = SAS_OPEN_REJECT;
2043                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2044                 break;
2045         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2046                 PM8001_IO_DBG(pm8001_ha,
2047                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2048                 ts->resp = SAS_TASK_COMPLETE;
2049                 ts->stat = SAS_NAK_R_ERR;
2050                 break;
2051         case IO_XFER_OPEN_RETRY_TIMEOUT:
2052                 PM8001_IO_DBG(pm8001_ha,
2053                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2054                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2055                 return;
2056         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2057                 PM8001_IO_DBG(pm8001_ha,
2058                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2059                 ts->resp = SAS_TASK_COMPLETE;
2060                 ts->stat = SAS_DATA_OVERRUN;
2061                 break;
2062         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2063                 PM8001_IO_DBG(pm8001_ha,
2064                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2065                 ts->resp = SAS_TASK_COMPLETE;
2066                 ts->stat = SAS_DATA_OVERRUN;
2067                 break;
2068         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2069                 PM8001_IO_DBG(pm8001_ha,
2070                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2071                 ts->resp = SAS_TASK_COMPLETE;
2072                 ts->stat = SAS_DATA_OVERRUN;
2073                 break;
2074         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2075                 PM8001_IO_DBG(pm8001_ha,
2076                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2077                 ts->resp = SAS_TASK_COMPLETE;
2078                 ts->stat = SAS_DATA_OVERRUN;
2079                 break;
2080         case IO_XFER_ERROR_OFFSET_MISMATCH:
2081                 PM8001_IO_DBG(pm8001_ha,
2082                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2083                 ts->resp = SAS_TASK_COMPLETE;
2084                 ts->stat = SAS_DATA_OVERRUN;
2085                 break;
2086         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2087                 PM8001_IO_DBG(pm8001_ha,
2088                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2089                 ts->resp = SAS_TASK_COMPLETE;
2090                 ts->stat = SAS_DATA_OVERRUN;
2091                 break;
2092         case IO_XFER_CMD_FRAME_ISSUED:
2093                 PM8001_IO_DBG(pm8001_ha,
2094                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
2095                 return;
2096         default:
2097                 PM8001_IO_DBG(pm8001_ha,
2098                         pm8001_printk("Unknown status 0x%x\n", event));
2099                 /* not allowed case. Therefore, return failed status */
2100                 ts->resp = SAS_TASK_COMPLETE;
2101                 ts->stat = SAS_DATA_OVERRUN;
2102                 break;
2103         }
2104         spin_lock_irqsave(&t->task_state_lock, flags);
2105         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2106         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2107         t->task_state_flags |= SAS_TASK_STATE_DONE;
2108         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2109                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2110                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2111                         " event 0x%x resp 0x%x "
2112                         "stat 0x%x but aborted by upper layer!\n",
2113                         t, event, ts->resp, ts->stat));
2114                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2115         } else {
2116                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2117                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2118                 mb();/* in order to force CPU ordering */
2119                 t->task_done(t);
2120         }
2121 }
2122
2123 /*See the comments for mpi_ssp_completion */
2124 static void
2125 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2126 {
2127         struct sas_task *t;
2128         struct pm8001_ccb_info *ccb;
2129         u32 param;
2130         u32 status;
2131         u32 tag;
2132         struct sata_completion_resp *psataPayload;
2133         struct task_status_struct *ts;
2134         struct ata_task_resp *resp ;
2135         u32 *sata_resp;
2136         struct pm8001_device *pm8001_dev;
2137         unsigned long flags;
2138
2139         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2140         status = le32_to_cpu(psataPayload->status);
2141         tag = le32_to_cpu(psataPayload->tag);
2142
2143         ccb = &pm8001_ha->ccb_info[tag];
2144         param = le32_to_cpu(psataPayload->param);
2145         t = ccb->task;
2146         ts = &t->task_status;
2147         pm8001_dev = ccb->device;
2148         if (status)
2149                 PM8001_FAIL_DBG(pm8001_ha,
2150                         pm8001_printk("sata IO status 0x%x\n", status));
2151         if (unlikely(!t || !t->lldd_task || !t->dev))
2152                 return;
2153
2154         switch (status) {
2155         case IO_SUCCESS:
2156                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2157                 if (param == 0) {
2158                         ts->resp = SAS_TASK_COMPLETE;
2159                         ts->stat = SAM_STAT_GOOD;
2160                 } else {
2161                         u8 len;
2162                         ts->resp = SAS_TASK_COMPLETE;
2163                         ts->stat = SAS_PROTO_RESPONSE;
2164                         ts->residual = param;
2165                         PM8001_IO_DBG(pm8001_ha,
2166                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2167                                 param));
2168                         sata_resp = &psataPayload->sata_resp[0];
2169                         resp = (struct ata_task_resp *)ts->buf;
2170                         if (t->ata_task.dma_xfer == 0 &&
2171                         t->data_dir == PCI_DMA_FROMDEVICE) {
2172                                 len = sizeof(struct pio_setup_fis);
2173                                 PM8001_IO_DBG(pm8001_ha,
2174                                 pm8001_printk("PIO read len = %d\n", len));
2175                         } else if (t->ata_task.use_ncq) {
2176                                 len = sizeof(struct set_dev_bits_fis);
2177                                 PM8001_IO_DBG(pm8001_ha,
2178                                         pm8001_printk("FPDMA len = %d\n", len));
2179                         } else {
2180                                 len = sizeof(struct dev_to_host_fis);
2181                                 PM8001_IO_DBG(pm8001_ha,
2182                                 pm8001_printk("other len = %d\n", len));
2183                         }
2184                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2185                                 resp->frame_len = len;
2186                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2187                                 ts->buf_valid_size = sizeof(*resp);
2188                         } else
2189                                 PM8001_IO_DBG(pm8001_ha,
2190                                         pm8001_printk("response to large\n"));
2191                 }
2192                 if (pm8001_dev)
2193                         pm8001_dev->running_req--;
2194                 break;
2195         case IO_ABORTED:
2196                 PM8001_IO_DBG(pm8001_ha,
2197                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2198                 ts->resp = SAS_TASK_COMPLETE;
2199                 ts->stat = SAS_ABORTED_TASK;
2200                 if (pm8001_dev)
2201                         pm8001_dev->running_req--;
2202                 break;
2203                 /* following cases are to do cases */
2204         case IO_UNDERFLOW:
2205                 /* SATA Completion with error */
2206                 PM8001_IO_DBG(pm8001_ha,
2207                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2208                 ts->resp = SAS_TASK_COMPLETE;
2209                 ts->stat = SAS_DATA_UNDERRUN;
2210                 ts->residual =  param;
2211                 if (pm8001_dev)
2212                         pm8001_dev->running_req--;
2213                 break;
2214         case IO_NO_DEVICE:
2215                 PM8001_IO_DBG(pm8001_ha,
2216                         pm8001_printk("IO_NO_DEVICE\n"));
2217                 ts->resp = SAS_TASK_UNDELIVERED;
2218                 ts->stat = SAS_PHY_DOWN;
2219                 break;
2220         case IO_XFER_ERROR_BREAK:
2221                 PM8001_IO_DBG(pm8001_ha,
2222                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2223                 ts->resp = SAS_TASK_COMPLETE;
2224                 ts->stat = SAS_INTERRUPTED;
2225                 break;
2226         case IO_XFER_ERROR_PHY_NOT_READY:
2227                 PM8001_IO_DBG(pm8001_ha,
2228                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2229                 ts->resp = SAS_TASK_COMPLETE;
2230                 ts->stat = SAS_OPEN_REJECT;
2231                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2232                 break;
2233         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2234                 PM8001_IO_DBG(pm8001_ha,
2235                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2236                         "_SUPPORTED\n"));
2237                 ts->resp = SAS_TASK_COMPLETE;
2238                 ts->stat = SAS_OPEN_REJECT;
2239                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2240                 break;
2241         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2242                 PM8001_IO_DBG(pm8001_ha,
2243                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2244                 ts->resp = SAS_TASK_COMPLETE;
2245                 ts->stat = SAS_OPEN_REJECT;
2246                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2247                 break;
2248         case IO_OPEN_CNX_ERROR_BREAK:
2249                 PM8001_IO_DBG(pm8001_ha,
2250                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2251                 ts->resp = SAS_TASK_COMPLETE;
2252                 ts->stat = SAS_OPEN_REJECT;
2253                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2254                 break;
2255         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2256                 PM8001_IO_DBG(pm8001_ha,
2257                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2258                 ts->resp = SAS_TASK_COMPLETE;
2259                 ts->stat = SAS_DEV_NO_RESPONSE;
2260                 if (!t->uldd_task) {
2261                         pm8001_handle_event(pm8001_ha,
2262                                 pm8001_dev,
2263                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2264                         ts->resp = SAS_TASK_UNDELIVERED;
2265                         ts->stat = SAS_QUEUE_FULL;
2266                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2267                         mb();/*in order to force CPU ordering*/
2268                         spin_unlock_irq(&pm8001_ha->lock);
2269                         t->task_done(t);
2270                         spin_lock_irq(&pm8001_ha->lock);
2271                         return;
2272                 }
2273                 break;
2274         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2275                 PM8001_IO_DBG(pm8001_ha,
2276                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2277                 ts->resp = SAS_TASK_UNDELIVERED;
2278                 ts->stat = SAS_OPEN_REJECT;
2279                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2280                 if (!t->uldd_task) {
2281                         pm8001_handle_event(pm8001_ha,
2282                                 pm8001_dev,
2283                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2284                         ts->resp = SAS_TASK_UNDELIVERED;
2285                         ts->stat = SAS_QUEUE_FULL;
2286                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2287                         mb();/*ditto*/
2288                         spin_unlock_irq(&pm8001_ha->lock);
2289                         t->task_done(t);
2290                         spin_lock_irq(&pm8001_ha->lock);
2291                         return;
2292                 }
2293                 break;
2294         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2295                 PM8001_IO_DBG(pm8001_ha,
2296                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2297                         "NOT_SUPPORTED\n"));
2298                 ts->resp = SAS_TASK_COMPLETE;
2299                 ts->stat = SAS_OPEN_REJECT;
2300                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2301                 break;
2302         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2303                 PM8001_IO_DBG(pm8001_ha,
2304                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2305                         "_BUSY\n"));
2306                 ts->resp = SAS_TASK_COMPLETE;
2307                 ts->stat = SAS_DEV_NO_RESPONSE;
2308                 if (!t->uldd_task) {
2309                         pm8001_handle_event(pm8001_ha,
2310                                 pm8001_dev,
2311                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2312                         ts->resp = SAS_TASK_UNDELIVERED;
2313                         ts->stat = SAS_QUEUE_FULL;
2314                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2315                         mb();/* ditto*/
2316                         spin_unlock_irq(&pm8001_ha->lock);
2317                         t->task_done(t);
2318                         spin_lock_irq(&pm8001_ha->lock);
2319                         return;
2320                 }
2321                 break;
2322         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2323                 PM8001_IO_DBG(pm8001_ha,
2324                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2325                 ts->resp = SAS_TASK_COMPLETE;
2326                 ts->stat = SAS_OPEN_REJECT;
2327                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2328                 break;
2329         case IO_XFER_ERROR_NAK_RECEIVED:
2330                 PM8001_IO_DBG(pm8001_ha,
2331                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2332                 ts->resp = SAS_TASK_COMPLETE;
2333                 ts->stat = SAS_NAK_R_ERR;
2334                 break;
2335         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2336                 PM8001_IO_DBG(pm8001_ha,
2337                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2338                 ts->resp = SAS_TASK_COMPLETE;
2339                 ts->stat = SAS_NAK_R_ERR;
2340                 break;
2341         case IO_XFER_ERROR_DMA:
2342                 PM8001_IO_DBG(pm8001_ha,
2343                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2344                 ts->resp = SAS_TASK_COMPLETE;
2345                 ts->stat = SAS_ABORTED_TASK;
2346                 break;
2347         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2348                 PM8001_IO_DBG(pm8001_ha,
2349                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2350                 ts->resp = SAS_TASK_UNDELIVERED;
2351                 ts->stat = SAS_DEV_NO_RESPONSE;
2352                 break;
2353         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2354                 PM8001_IO_DBG(pm8001_ha,
2355                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2356                 ts->resp = SAS_TASK_COMPLETE;
2357                 ts->stat = SAS_DATA_UNDERRUN;
2358                 break;
2359         case IO_XFER_OPEN_RETRY_TIMEOUT:
2360                 PM8001_IO_DBG(pm8001_ha,
2361                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2362                 ts->resp = SAS_TASK_COMPLETE;
2363                 ts->stat = SAS_OPEN_TO;
2364                 break;
2365         case IO_PORT_IN_RESET:
2366                 PM8001_IO_DBG(pm8001_ha,
2367                         pm8001_printk("IO_PORT_IN_RESET\n"));
2368                 ts->resp = SAS_TASK_COMPLETE;
2369                 ts->stat = SAS_DEV_NO_RESPONSE;
2370                 break;
2371         case IO_DS_NON_OPERATIONAL:
2372                 PM8001_IO_DBG(pm8001_ha,
2373                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2374                 ts->resp = SAS_TASK_COMPLETE;
2375                 ts->stat = SAS_DEV_NO_RESPONSE;
2376                 if (!t->uldd_task) {
2377                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2378                                     IO_DS_NON_OPERATIONAL);
2379                         ts->resp = SAS_TASK_UNDELIVERED;
2380                         ts->stat = SAS_QUEUE_FULL;
2381                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2382                         mb();/*ditto*/
2383                         spin_unlock_irq(&pm8001_ha->lock);
2384                         t->task_done(t);
2385                         spin_lock_irq(&pm8001_ha->lock);
2386                         return;
2387                 }
2388                 break;
2389         case IO_DS_IN_RECOVERY:
2390                 PM8001_IO_DBG(pm8001_ha,
2391                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2392                 ts->resp = SAS_TASK_COMPLETE;
2393                 ts->stat = SAS_DEV_NO_RESPONSE;
2394                 break;
2395         case IO_DS_IN_ERROR:
2396                 PM8001_IO_DBG(pm8001_ha,
2397                         pm8001_printk("IO_DS_IN_ERROR\n"));
2398                 ts->resp = SAS_TASK_COMPLETE;
2399                 ts->stat = SAS_DEV_NO_RESPONSE;
2400                 if (!t->uldd_task) {
2401                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2402                                     IO_DS_IN_ERROR);
2403                         ts->resp = SAS_TASK_UNDELIVERED;
2404                         ts->stat = SAS_QUEUE_FULL;
2405                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2406                         mb();/*ditto*/
2407                         spin_unlock_irq(&pm8001_ha->lock);
2408                         t->task_done(t);
2409                         spin_lock_irq(&pm8001_ha->lock);
2410                         return;
2411                 }
2412                 break;
2413         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2414                 PM8001_IO_DBG(pm8001_ha,
2415                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2416                 ts->resp = SAS_TASK_COMPLETE;
2417                 ts->stat = SAS_OPEN_REJECT;
2418                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2419         default:
2420                 PM8001_IO_DBG(pm8001_ha,
2421                         pm8001_printk("Unknown status 0x%x\n", status));
2422                 /* not allowed case. Therefore, return failed status */
2423                 ts->resp = SAS_TASK_COMPLETE;
2424                 ts->stat = SAS_DEV_NO_RESPONSE;
2425                 break;
2426         }
2427         spin_lock_irqsave(&t->task_state_lock, flags);
2428         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2429         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2430         t->task_state_flags |= SAS_TASK_STATE_DONE;
2431         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2432                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2433                 PM8001_FAIL_DBG(pm8001_ha,
2434                         pm8001_printk("task 0x%p done with io_status 0x%x"
2435                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2436                         t, status, ts->resp, ts->stat));
2437                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2438         } else if (t->uldd_task) {
2439                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2440                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2441                 mb();/* ditto */
2442                 spin_unlock_irq(&pm8001_ha->lock);
2443                 t->task_done(t);
2444                 spin_lock_irq(&pm8001_ha->lock);
2445         } else if (!t->uldd_task) {
2446                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2447                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2448                 mb();/*ditto*/
2449                 spin_unlock_irq(&pm8001_ha->lock);
2450                 t->task_done(t);
2451                 spin_lock_irq(&pm8001_ha->lock);
2452         }
2453 }
2454
2455 /*See the comments for mpi_ssp_completion */
2456 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2457 {
2458         struct sas_task *t;
2459         struct task_status_struct *ts;
2460         struct pm8001_ccb_info *ccb;
2461         struct pm8001_device *pm8001_dev;
2462         struct sata_event_resp *psataPayload =
2463                 (struct sata_event_resp *)(piomb + 4);
2464         u32 event = le32_to_cpu(psataPayload->event);
2465         u32 tag = le32_to_cpu(psataPayload->tag);
2466         u32 port_id = le32_to_cpu(psataPayload->port_id);
2467         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2468         unsigned long flags;
2469
2470         ccb = &pm8001_ha->ccb_info[tag];
2471         t = ccb->task;
2472         pm8001_dev = ccb->device;
2473         if (event)
2474                 PM8001_FAIL_DBG(pm8001_ha,
2475                         pm8001_printk("sata IO status 0x%x\n", event));
2476         if (unlikely(!t || !t->lldd_task || !t->dev))
2477                 return;
2478         ts = &t->task_status;
2479         PM8001_IO_DBG(pm8001_ha,
2480                 pm8001_printk("port_id = %x,device_id = %x\n",
2481                 port_id, dev_id));
2482         switch (event) {
2483         case IO_OVERFLOW:
2484                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2485                 ts->resp = SAS_TASK_COMPLETE;
2486                 ts->stat = SAS_DATA_OVERRUN;
2487                 ts->residual = 0;
2488                 if (pm8001_dev)
2489                         pm8001_dev->running_req--;
2490                 break;
2491         case IO_XFER_ERROR_BREAK:
2492                 PM8001_IO_DBG(pm8001_ha,
2493                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2494                 ts->resp = SAS_TASK_COMPLETE;
2495                 ts->stat = SAS_INTERRUPTED;
2496                 break;
2497         case IO_XFER_ERROR_PHY_NOT_READY:
2498                 PM8001_IO_DBG(pm8001_ha,
2499                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2500                 ts->resp = SAS_TASK_COMPLETE;
2501                 ts->stat = SAS_OPEN_REJECT;
2502                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2503                 break;
2504         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2505                 PM8001_IO_DBG(pm8001_ha,
2506                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2507                         "_SUPPORTED\n"));
2508                 ts->resp = SAS_TASK_COMPLETE;
2509                 ts->stat = SAS_OPEN_REJECT;
2510                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2511                 break;
2512         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2513                 PM8001_IO_DBG(pm8001_ha,
2514                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2515                 ts->resp = SAS_TASK_COMPLETE;
2516                 ts->stat = SAS_OPEN_REJECT;
2517                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2518                 break;
2519         case IO_OPEN_CNX_ERROR_BREAK:
2520                 PM8001_IO_DBG(pm8001_ha,
2521                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2522                 ts->resp = SAS_TASK_COMPLETE;
2523                 ts->stat = SAS_OPEN_REJECT;
2524                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2525                 break;
2526         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2527                 PM8001_IO_DBG(pm8001_ha,
2528                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2529                 ts->resp = SAS_TASK_UNDELIVERED;
2530                 ts->stat = SAS_DEV_NO_RESPONSE;
2531                 if (!t->uldd_task) {
2532                         pm8001_handle_event(pm8001_ha,
2533                                 pm8001_dev,
2534                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2535                         ts->resp = SAS_TASK_COMPLETE;
2536                         ts->stat = SAS_QUEUE_FULL;
2537                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2538                         mb();/*ditto*/
2539                         spin_unlock_irq(&pm8001_ha->lock);
2540                         t->task_done(t);
2541                         spin_lock_irq(&pm8001_ha->lock);
2542                         return;
2543                 }
2544                 break;
2545         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2546                 PM8001_IO_DBG(pm8001_ha,
2547                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2548                 ts->resp = SAS_TASK_UNDELIVERED;
2549                 ts->stat = SAS_OPEN_REJECT;
2550                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2551                 break;
2552         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2553                 PM8001_IO_DBG(pm8001_ha,
2554                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2555                         "NOT_SUPPORTED\n"));
2556                 ts->resp = SAS_TASK_COMPLETE;
2557                 ts->stat = SAS_OPEN_REJECT;
2558                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2559                 break;
2560         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2561                 PM8001_IO_DBG(pm8001_ha,
2562                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2563                 ts->resp = SAS_TASK_COMPLETE;
2564                 ts->stat = SAS_OPEN_REJECT;
2565                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2566                 break;
2567         case IO_XFER_ERROR_NAK_RECEIVED:
2568                 PM8001_IO_DBG(pm8001_ha,
2569                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2570                 ts->resp = SAS_TASK_COMPLETE;
2571                 ts->stat = SAS_NAK_R_ERR;
2572                 break;
2573         case IO_XFER_ERROR_PEER_ABORTED:
2574                 PM8001_IO_DBG(pm8001_ha,
2575                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2576                 ts->resp = SAS_TASK_COMPLETE;
2577                 ts->stat = SAS_NAK_R_ERR;
2578                 break;
2579         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2580                 PM8001_IO_DBG(pm8001_ha,
2581                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2582                 ts->resp = SAS_TASK_COMPLETE;
2583                 ts->stat = SAS_DATA_UNDERRUN;
2584                 break;
2585         case IO_XFER_OPEN_RETRY_TIMEOUT:
2586                 PM8001_IO_DBG(pm8001_ha,
2587                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2588                 ts->resp = SAS_TASK_COMPLETE;
2589                 ts->stat = SAS_OPEN_TO;
2590                 break;
2591         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2592                 PM8001_IO_DBG(pm8001_ha,
2593                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2594                 ts->resp = SAS_TASK_COMPLETE;
2595                 ts->stat = SAS_OPEN_TO;
2596                 break;
2597         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2598                 PM8001_IO_DBG(pm8001_ha,
2599                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2600                 ts->resp = SAS_TASK_COMPLETE;
2601                 ts->stat = SAS_OPEN_TO;
2602                 break;
2603         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2604                 PM8001_IO_DBG(pm8001_ha,
2605                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2606                 ts->resp = SAS_TASK_COMPLETE;
2607                 ts->stat = SAS_OPEN_TO;
2608                 break;
2609         case IO_XFER_ERROR_OFFSET_MISMATCH:
2610                 PM8001_IO_DBG(pm8001_ha,
2611                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2612                 ts->resp = SAS_TASK_COMPLETE;
2613                 ts->stat = SAS_OPEN_TO;
2614                 break;
2615         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2616                 PM8001_IO_DBG(pm8001_ha,
2617                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2618                 ts->resp = SAS_TASK_COMPLETE;
2619                 ts->stat = SAS_OPEN_TO;
2620                 break;
2621         case IO_XFER_CMD_FRAME_ISSUED:
2622                 PM8001_IO_DBG(pm8001_ha,
2623                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2624                 break;
2625         case IO_XFER_PIO_SETUP_ERROR:
2626                 PM8001_IO_DBG(pm8001_ha,
2627                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2628                 ts->resp = SAS_TASK_COMPLETE;
2629                 ts->stat = SAS_OPEN_TO;
2630                 break;
2631         default:
2632                 PM8001_IO_DBG(pm8001_ha,
2633                         pm8001_printk("Unknown status 0x%x\n", event));
2634                 /* not allowed case. Therefore, return failed status */
2635                 ts->resp = SAS_TASK_COMPLETE;
2636                 ts->stat = SAS_OPEN_TO;
2637                 break;
2638         }
2639         spin_lock_irqsave(&t->task_state_lock, flags);
2640         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2641         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2642         t->task_state_flags |= SAS_TASK_STATE_DONE;
2643         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2644                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2645                 PM8001_FAIL_DBG(pm8001_ha,
2646                         pm8001_printk("task 0x%p done with io_status 0x%x"
2647                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2648                         t, event, ts->resp, ts->stat));
2649                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2650         } else if (t->uldd_task) {
2651                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2652                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2653                 mb();/* ditto */
2654                 spin_unlock_irq(&pm8001_ha->lock);
2655                 t->task_done(t);
2656                 spin_lock_irq(&pm8001_ha->lock);
2657         } else if (!t->uldd_task) {
2658                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2659                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2660                 mb();/*ditto*/
2661                 spin_unlock_irq(&pm8001_ha->lock);
2662                 t->task_done(t);
2663                 spin_lock_irq(&pm8001_ha->lock);
2664         }
2665 }
2666
2667 /*See the comments for mpi_ssp_completion */
2668 static void
2669 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2670 {
2671         u32 param;
2672         struct sas_task *t;
2673         struct pm8001_ccb_info *ccb;
2674         unsigned long flags;
2675         u32 status;
2676         u32 tag;
2677         struct smp_completion_resp *psmpPayload;
2678         struct task_status_struct *ts;
2679         struct pm8001_device *pm8001_dev;
2680
2681         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2682         status = le32_to_cpu(psmpPayload->status);
2683         tag = le32_to_cpu(psmpPayload->tag);
2684
2685         ccb = &pm8001_ha->ccb_info[tag];
2686         param = le32_to_cpu(psmpPayload->param);
2687         t = ccb->task;
2688         ts = &t->task_status;
2689         pm8001_dev = ccb->device;
2690         if (status)
2691                 PM8001_FAIL_DBG(pm8001_ha,
2692                         pm8001_printk("smp IO status 0x%x\n", status));
2693         if (unlikely(!t || !t->lldd_task || !t->dev))
2694                 return;
2695
2696         switch (status) {
2697         case IO_SUCCESS:
2698                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2699                 ts->resp = SAS_TASK_COMPLETE;
2700                 ts->stat = SAM_STAT_GOOD;
2701         if (pm8001_dev)
2702                         pm8001_dev->running_req--;
2703                 break;
2704         case IO_ABORTED:
2705                 PM8001_IO_DBG(pm8001_ha,
2706                         pm8001_printk("IO_ABORTED IOMB\n"));
2707                 ts->resp = SAS_TASK_COMPLETE;
2708                 ts->stat = SAS_ABORTED_TASK;
2709                 if (pm8001_dev)
2710                         pm8001_dev->running_req--;
2711                 break;
2712         case IO_OVERFLOW:
2713                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2714                 ts->resp = SAS_TASK_COMPLETE;
2715                 ts->stat = SAS_DATA_OVERRUN;
2716                 ts->residual = 0;
2717                 if (pm8001_dev)
2718                         pm8001_dev->running_req--;
2719                 break;
2720         case IO_NO_DEVICE:
2721                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2722                 ts->resp = SAS_TASK_COMPLETE;
2723                 ts->stat = SAS_PHY_DOWN;
2724                 break;
2725         case IO_ERROR_HW_TIMEOUT:
2726                 PM8001_IO_DBG(pm8001_ha,
2727                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2728                 ts->resp = SAS_TASK_COMPLETE;
2729                 ts->stat = SAM_STAT_BUSY;
2730                 break;
2731         case IO_XFER_ERROR_BREAK:
2732                 PM8001_IO_DBG(pm8001_ha,
2733                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2734                 ts->resp = SAS_TASK_COMPLETE;
2735                 ts->stat = SAM_STAT_BUSY;
2736                 break;
2737         case IO_XFER_ERROR_PHY_NOT_READY:
2738                 PM8001_IO_DBG(pm8001_ha,
2739                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2740                 ts->resp = SAS_TASK_COMPLETE;
2741                 ts->stat = SAM_STAT_BUSY;
2742                 break;
2743         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2744                 PM8001_IO_DBG(pm8001_ha,
2745                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2746                 ts->resp = SAS_TASK_COMPLETE;
2747                 ts->stat = SAS_OPEN_REJECT;
2748                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2749                 break;
2750         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2751                 PM8001_IO_DBG(pm8001_ha,
2752                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2753                 ts->resp = SAS_TASK_COMPLETE;
2754                 ts->stat = SAS_OPEN_REJECT;
2755                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2756                 break;
2757         case IO_OPEN_CNX_ERROR_BREAK:
2758                 PM8001_IO_DBG(pm8001_ha,
2759                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2760                 ts->resp = SAS_TASK_COMPLETE;
2761                 ts->stat = SAS_OPEN_REJECT;
2762                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2763                 break;
2764         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2765                 PM8001_IO_DBG(pm8001_ha,
2766                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2767                 ts->resp = SAS_TASK_COMPLETE;
2768                 ts->stat = SAS_OPEN_REJECT;
2769                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2770                 pm8001_handle_event(pm8001_ha,
2771                                 pm8001_dev,
2772                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2773                 break;
2774         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2775                 PM8001_IO_DBG(pm8001_ha,
2776                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2777                 ts->resp = SAS_TASK_COMPLETE;
2778                 ts->stat = SAS_OPEN_REJECT;
2779                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2780                 break;
2781         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2782                 PM8001_IO_DBG(pm8001_ha,
2783                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2784                         "NOT_SUPPORTED\n"));
2785                 ts->resp = SAS_TASK_COMPLETE;
2786                 ts->stat = SAS_OPEN_REJECT;
2787                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2788                 break;
2789         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2790                 PM8001_IO_DBG(pm8001_ha,
2791                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2792                 ts->resp = SAS_TASK_COMPLETE;
2793                 ts->stat = SAS_OPEN_REJECT;
2794                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2795                 break;
2796         case IO_XFER_ERROR_RX_FRAME:
2797                 PM8001_IO_DBG(pm8001_ha,
2798                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2799                 ts->resp = SAS_TASK_COMPLETE;
2800                 ts->stat = SAS_DEV_NO_RESPONSE;
2801                 break;
2802         case IO_XFER_OPEN_RETRY_TIMEOUT:
2803                 PM8001_IO_DBG(pm8001_ha,
2804                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2805                 ts->resp = SAS_TASK_COMPLETE;
2806                 ts->stat = SAS_OPEN_REJECT;
2807                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2808                 break;
2809         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2810                 PM8001_IO_DBG(pm8001_ha,
2811                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2812                 ts->resp = SAS_TASK_COMPLETE;
2813                 ts->stat = SAS_QUEUE_FULL;
2814                 break;
2815         case IO_PORT_IN_RESET:
2816                 PM8001_IO_DBG(pm8001_ha,
2817                         pm8001_printk("IO_PORT_IN_RESET\n"));
2818                 ts->resp = SAS_TASK_COMPLETE;
2819                 ts->stat = SAS_OPEN_REJECT;
2820                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2821                 break;
2822         case IO_DS_NON_OPERATIONAL:
2823                 PM8001_IO_DBG(pm8001_ha,
2824                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2825                 ts->resp = SAS_TASK_COMPLETE;
2826                 ts->stat = SAS_DEV_NO_RESPONSE;
2827                 break;
2828         case IO_DS_IN_RECOVERY:
2829                 PM8001_IO_DBG(pm8001_ha,
2830                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2831                 ts->resp = SAS_TASK_COMPLETE;
2832                 ts->stat = SAS_OPEN_REJECT;
2833                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2834                 break;
2835         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2836                 PM8001_IO_DBG(pm8001_ha,
2837                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2838                 ts->resp = SAS_TASK_COMPLETE;
2839                 ts->stat = SAS_OPEN_REJECT;
2840                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2841                 break;
2842         default:
2843                 PM8001_IO_DBG(pm8001_ha,
2844                         pm8001_printk("Unknown status 0x%x\n", status));
2845                 ts->resp = SAS_TASK_COMPLETE;
2846                 ts->stat = SAS_DEV_NO_RESPONSE;
2847                 /* not allowed case. Therefore, return failed status */
2848                 break;
2849         }
2850         spin_lock_irqsave(&t->task_state_lock, flags);
2851         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2852         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2853         t->task_state_flags |= SAS_TASK_STATE_DONE;
2854         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2855                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2856                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2857                         " io_status 0x%x resp 0x%x "
2858                         "stat 0x%x but aborted by upper layer!\n",
2859                         t, status, ts->resp, ts->stat));
2860                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2861         } else {
2862                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2863                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2864                 mb();/* in order to force CPU ordering */
2865                 t->task_done(t);
2866         }
2867 }
2868
2869 static void
2870 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2871 {
2872         struct set_dev_state_resp *pPayload =
2873                 (struct set_dev_state_resp *)(piomb + 4);
2874         u32 tag = le32_to_cpu(pPayload->tag);
2875         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2876         struct pm8001_device *pm8001_dev = ccb->device;
2877         u32 status = le32_to_cpu(pPayload->status);
2878         u32 device_id = le32_to_cpu(pPayload->device_id);
2879         u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2880         u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2881         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2882                 "from 0x%x to 0x%x status = 0x%x!\n",
2883                 device_id, pds, nds, status));
2884         complete(pm8001_dev->setds_completion);
2885         ccb->task = NULL;
2886         ccb->ccb_tag = 0xFFFFFFFF;
2887         pm8001_ccb_free(pm8001_ha, tag);
2888 }
2889
2890 static void
2891 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2892 {
2893         struct get_nvm_data_resp *pPayload =
2894                 (struct get_nvm_data_resp *)(piomb + 4);
2895         u32 tag = le32_to_cpu(pPayload->tag);
2896         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2897         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2898         complete(pm8001_ha->nvmd_completion);
2899         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2900         if ((dlen_status & NVMD_STAT) != 0) {
2901                 PM8001_FAIL_DBG(pm8001_ha,
2902                         pm8001_printk("Set nvm data error!\n"));
2903                 return;
2904         }
2905         ccb->task = NULL;
2906         ccb->ccb_tag = 0xFFFFFFFF;
2907         pm8001_ccb_free(pm8001_ha, tag);
2908 }
2909
2910 static void
2911 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2912 {
2913         struct fw_control_ex    *fw_control_context;
2914         struct get_nvm_data_resp *pPayload =
2915                 (struct get_nvm_data_resp *)(piomb + 4);
2916         u32 tag = le32_to_cpu(pPayload->tag);
2917         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2918         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2919         u32 ir_tds_bn_dps_das_nvm =
2920                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2921         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2922         fw_control_context = ccb->fw_control_context;
2923
2924         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2925         if ((dlen_status & NVMD_STAT) != 0) {
2926                 PM8001_FAIL_DBG(pm8001_ha,
2927                         pm8001_printk("Get nvm data error!\n"));
2928                 complete(pm8001_ha->nvmd_completion);
2929                 return;
2930         }
2931
2932         if (ir_tds_bn_dps_das_nvm & IPMode) {
2933                 /* indirect mode - IR bit set */
2934                 PM8001_MSG_DBG(pm8001_ha,
2935                         pm8001_printk("Get NVMD success, IR=1\n"));
2936                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2937                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2938                                 memcpy(pm8001_ha->sas_addr,
2939                                       ((u8 *)virt_addr + 4),
2940                                        SAS_ADDR_SIZE);
2941                                 PM8001_MSG_DBG(pm8001_ha,
2942                                         pm8001_printk("Get SAS address"
2943                                         " from VPD successfully!\n"));
2944                         }
2945                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2946                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2947                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2948                                 ;
2949                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2950                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2951                         ;
2952                 } else {
2953                         /* Should not be happened*/
2954                         PM8001_MSG_DBG(pm8001_ha,
2955                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2956                                 ir_tds_bn_dps_das_nvm));
2957                 }
2958         } else /* direct mode */{
2959                 PM8001_MSG_DBG(pm8001_ha,
2960                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2961                         (dlen_status & NVMD_LEN) >> 24));
2962         }
2963         memcpy(fw_control_context->usrAddr,
2964                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2965                 fw_control_context->len);
2966         complete(pm8001_ha->nvmd_completion);
2967         ccb->task = NULL;
2968         ccb->ccb_tag = 0xFFFFFFFF;
2969         pm8001_ccb_free(pm8001_ha, tag);
2970 }
2971
2972 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2973 {
2974         struct local_phy_ctl_resp *pPayload =
2975                 (struct local_phy_ctl_resp *)(piomb + 4);
2976         u32 status = le32_to_cpu(pPayload->status);
2977         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2978         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2979         if (status != 0) {
2980                 PM8001_MSG_DBG(pm8001_ha,
2981                         pm8001_printk("%x phy execute %x phy op failed!\n",
2982                         phy_id, phy_op));
2983         } else
2984                 PM8001_MSG_DBG(pm8001_ha,
2985                         pm8001_printk("%x phy execute %x phy op success!\n",
2986                         phy_id, phy_op));
2987         return 0;
2988 }
2989
2990 /**
2991  * pm8001_bytes_dmaed - one of the interface function communication with libsas
2992  * @pm8001_ha: our hba card information
2993  * @i: which phy that received the event.
2994  *
2995  * when HBA driver received the identify done event or initiate FIS received
2996  * event(for SATA), it will invoke this function to notify the sas layer that
2997  * the sas toplogy has formed, please discover the the whole sas domain,
2998  * while receive a broadcast(change) primitive just tell the sas
2999  * layer to discover the changed domain rather than the whole domain.
3000  */
3001 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3002 {
3003         struct pm8001_phy *phy = &pm8001_ha->phy[i];
3004         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3005         struct sas_ha_struct *sas_ha;
3006         if (!phy->phy_attached)
3007                 return;
3008
3009         sas_ha = pm8001_ha->sas;
3010         if (sas_phy->phy) {
3011                 struct sas_phy *sphy = sas_phy->phy;
3012                 sphy->negotiated_linkrate = sas_phy->linkrate;
3013                 sphy->minimum_linkrate = phy->minimum_linkrate;
3014                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3015                 sphy->maximum_linkrate = phy->maximum_linkrate;
3016                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3017         }
3018
3019         if (phy->phy_type & PORT_TYPE_SAS) {
3020                 struct sas_identify_frame *id;
3021                 id = (struct sas_identify_frame *)phy->frame_rcvd;
3022                 id->dev_type = phy->identify.device_type;
3023                 id->initiator_bits = SAS_PROTOCOL_ALL;
3024                 id->target_bits = phy->identify.target_port_protocols;
3025         } else if (phy->phy_type & PORT_TYPE_SATA) {
3026                 /*Nothing*/
3027         }
3028         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3029
3030         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3031         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3032 }
3033
3034 /* Get the link rate speed  */
3035 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3036 {
3037         struct sas_phy *sas_phy = phy->sas_phy.phy;
3038
3039         switch (link_rate) {
3040         case PHY_SPEED_60:
3041                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3042                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3043                 break;
3044         case PHY_SPEED_30:
3045                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3046                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3047                 break;
3048         case PHY_SPEED_15:
3049                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3050                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3051                 break;
3052         }
3053         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3054         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3055         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3056         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3057         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3058 }
3059
3060 /**
3061  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3062  * @phy: pointer to asd_phy
3063  * @sas_addr: pointer to buffer where the SAS address is to be written
3064  *
3065  * This function extracts the SAS address from an IDENTIFY frame
3066  * received.  If OOB is SATA, then a SAS address is generated from the
3067  * HA tables.
3068  *
3069  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3070  * buffer.
3071  */
3072 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3073         u8 *sas_addr)
3074 {
3075         if (phy->sas_phy.frame_rcvd[0] == 0x34
3076                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3077                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3078                 /* FIS device-to-host */
3079                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3080                 addr += phy->sas_phy.id;
3081                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3082         } else {
3083                 struct sas_identify_frame *idframe =
3084                         (void *) phy->sas_phy.frame_rcvd;
3085                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3086         }
3087 }
3088
3089 /**
3090  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3091  * @pm8001_ha: our hba card information
3092  * @Qnum: the outbound queue message number.
3093  * @SEA: source of event to ack
3094  * @port_id: port id.
3095  * @phyId: phy id.
3096  * @param0: parameter 0.
3097  * @param1: parameter 1.
3098  */
3099 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3100         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3101 {
3102         struct hw_event_ack_req  payload;
3103         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3104
3105         struct inbound_queue_table *circularQ;
3106
3107         memset((u8 *)&payload, 0, sizeof(payload));
3108         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3109         payload.tag = cpu_to_le32(1);
3110         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3111                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3112         payload.param0 = cpu_to_le32(param0);
3113         payload.param1 = cpu_to_le32(param1);
3114         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3115 }
3116
3117 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3118         u32 phyId, u32 phy_op);
3119
3120 /**
3121  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3122  * @pm8001_ha: our hba card information
3123  * @piomb: IO message buffer
3124  */
3125 static void
3126 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3127 {
3128         struct hw_event_resp *pPayload =
3129                 (struct hw_event_resp *)(piomb + 4);
3130         u32 lr_evt_status_phyid_portid =
3131                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3132         u8 link_rate =
3133                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3134         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3135         u8 phy_id =
3136                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3137         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3138         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3139         struct pm8001_port *port = &pm8001_ha->port[port_id];
3140         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3141         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3142         unsigned long flags;
3143         u8 deviceType = pPayload->sas_identify.dev_type;
3144         port->port_state =  portstate;
3145         PM8001_MSG_DBG(pm8001_ha,
3146                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3147                 port_id, phy_id));
3148
3149         switch (deviceType) {
3150         case SAS_PHY_UNUSED:
3151                 PM8001_MSG_DBG(pm8001_ha,
3152                         pm8001_printk("device type no device.\n"));
3153                 break;
3154         case SAS_END_DEVICE:
3155                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3156                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3157                         PHY_NOTIFY_ENABLE_SPINUP);
3158                 port->port_attached = 1;
3159                 get_lrate_mode(phy, link_rate);
3160                 break;
3161         case SAS_EDGE_EXPANDER_DEVICE:
3162                 PM8001_MSG_DBG(pm8001_ha,
3163                         pm8001_printk("expander device.\n"));
3164                 port->port_attached = 1;
3165                 get_lrate_mode(phy, link_rate);
3166                 break;
3167         case SAS_FANOUT_EXPANDER_DEVICE:
3168                 PM8001_MSG_DBG(pm8001_ha,
3169                         pm8001_printk("fanout expander device.\n"));
3170                 port->port_attached = 1;
3171                 get_lrate_mode(phy, link_rate);
3172                 break;
3173         default:
3174                 PM8001_MSG_DBG(pm8001_ha,
3175                         pm8001_printk("unknown device type(%x)\n", deviceType));
3176                 break;
3177         }
3178         phy->phy_type |= PORT_TYPE_SAS;
3179         phy->identify.device_type = deviceType;
3180         phy->phy_attached = 1;
3181         if (phy->identify.device_type == SAS_END_DEVICE)
3182                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3183         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3184                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3185         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3186         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3187         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3188         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3189                 sizeof(struct sas_identify_frame)-4);
3190         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3191         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3192         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3193         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3194                 mdelay(200);/*delay a moment to wait disk to spinup*/
3195         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3196 }
3197
3198 /**
3199  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3200  * @pm8001_ha: our hba card information
3201  * @piomb: IO message buffer
3202  */
3203 static void
3204 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3205 {
3206         struct hw_event_resp *pPayload =
3207                 (struct hw_event_resp *)(piomb + 4);
3208         u32 lr_evt_status_phyid_portid =
3209                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3210         u8 link_rate =
3211                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3212         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3213         u8 phy_id =
3214                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3215         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3216         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3217         struct pm8001_port *port = &pm8001_ha->port[port_id];
3218         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3219         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3220         unsigned long flags;
3221         PM8001_MSG_DBG(pm8001_ha,
3222                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3223                 " phy id = %d\n", port_id, phy_id));
3224         port->port_state =  portstate;
3225         port->port_attached = 1;
3226         get_lrate_mode(phy, link_rate);
3227         phy->phy_type |= PORT_TYPE_SATA;
3228         phy->phy_attached = 1;
3229         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3230         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3231         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3232         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3233                 sizeof(struct dev_to_host_fis));
3234         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3235         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3236         phy->identify.device_type = SATA_DEV;
3237         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3238         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3239         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3240 }
3241
3242 /**
3243  * hw_event_phy_down -we should notify the libsas the phy is down.
3244  * @pm8001_ha: our hba card information
3245  * @piomb: IO message buffer
3246  */
3247 static void
3248 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3249 {
3250         struct hw_event_resp *pPayload =
3251                 (struct hw_event_resp *)(piomb + 4);
3252         u32 lr_evt_status_phyid_portid =
3253                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3254         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3255         u8 phy_id =
3256                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3257         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3258         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3259         struct pm8001_port *port = &pm8001_ha->port[port_id];
3260         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3261         port->port_state =  portstate;
3262         phy->phy_type = 0;
3263         phy->identify.device_type = 0;
3264         phy->phy_attached = 0;
3265         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3266         switch (portstate) {
3267         case PORT_VALID:
3268                 break;
3269         case PORT_INVALID:
3270                 PM8001_MSG_DBG(pm8001_ha,
3271                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3272                 PM8001_MSG_DBG(pm8001_ha,
3273                         pm8001_printk(" Last phy Down and port invalid\n"));
3274                 port->port_attached = 0;
3275                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3276                         port_id, phy_id, 0, 0);
3277                 break;
3278         case PORT_IN_RESET:
3279                 PM8001_MSG_DBG(pm8001_ha,
3280                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3281                 break;
3282         case PORT_NOT_ESTABLISHED:
3283                 PM8001_MSG_DBG(pm8001_ha,
3284                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3285                 port->port_attached = 0;
3286                 break;
3287         case PORT_LOSTCOMM:
3288                 PM8001_MSG_DBG(pm8001_ha,
3289                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3290                 PM8001_MSG_DBG(pm8001_ha,
3291                         pm8001_printk(" Last phy Down and port invalid\n"));
3292                 port->port_attached = 0;
3293                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3294                         port_id, phy_id, 0, 0);
3295                 break;
3296         default:
3297                 port->port_attached = 0;
3298                 PM8001_MSG_DBG(pm8001_ha,
3299                         pm8001_printk(" phy Down and(default) = %x\n",
3300                         portstate));
3301                 break;
3302
3303         }
3304 }
3305
3306 /**
3307  * mpi_reg_resp -process register device ID response.
3308  * @pm8001_ha: our hba card information
3309  * @piomb: IO message buffer
3310  *
3311  * when sas layer find a device it will notify LLDD, then the driver register
3312  * the domain device to FW, this event is the return device ID which the FW
3313  * has assigned, from now,inter-communication with FW is no longer using the
3314  * SAS address, use device ID which FW assigned.
3315  */
3316 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3317 {
3318         u32 status;
3319         u32 device_id;
3320         u32 htag;
3321         struct pm8001_ccb_info *ccb;
3322         struct pm8001_device *pm8001_dev;
3323         struct dev_reg_resp *registerRespPayload =
3324                 (struct dev_reg_resp *)(piomb + 4);
3325
3326         htag = le32_to_cpu(registerRespPayload->tag);
3327         ccb = &pm8001_ha->ccb_info[htag];
3328         pm8001_dev = ccb->device;
3329         status = le32_to_cpu(registerRespPayload->status);
3330         device_id = le32_to_cpu(registerRespPayload->device_id);
3331         PM8001_MSG_DBG(pm8001_ha,
3332                 pm8001_printk(" register device is status = %d\n", status));
3333         switch (status) {
3334         case DEVREG_SUCCESS:
3335                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3336                 pm8001_dev->device_id = device_id;
3337                 break;
3338         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3339                 PM8001_MSG_DBG(pm8001_ha,
3340                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3341                 break;
3342         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3343                 PM8001_MSG_DBG(pm8001_ha,
3344                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3345                 break;
3346         case DEVREG_FAILURE_INVALID_PHY_ID:
3347                 PM8001_MSG_DBG(pm8001_ha,
3348                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3349                 break;
3350         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3351                 PM8001_MSG_DBG(pm8001_ha,
3352                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3353                 break;
3354         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3355                 PM8001_MSG_DBG(pm8001_ha,
3356                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3357                 break;
3358         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3359                 PM8001_MSG_DBG(pm8001_ha,
3360                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3361                 break;
3362         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3363                 PM8001_MSG_DBG(pm8001_ha,
3364                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3365                 break;
3366         default:
3367                 PM8001_MSG_DBG(pm8001_ha,
3368                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3369                 break;
3370         }
3371         complete(pm8001_dev->dcompletion);
3372         ccb->task = NULL;
3373         ccb->ccb_tag = 0xFFFFFFFF;
3374         pm8001_ccb_free(pm8001_ha, htag);
3375         return 0;
3376 }
3377
3378 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3379 {
3380         u32 status;
3381         u32 device_id;
3382         struct dev_reg_resp *registerRespPayload =
3383                 (struct dev_reg_resp *)(piomb + 4);
3384
3385         status = le32_to_cpu(registerRespPayload->status);
3386         device_id = le32_to_cpu(registerRespPayload->device_id);
3387         if (status != 0)
3388                 PM8001_MSG_DBG(pm8001_ha,
3389                         pm8001_printk(" deregister device failed ,status = %x"
3390                         ", device_id = %x\n", status, device_id));
3391         return 0;
3392 }
3393
3394 static int
3395 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3396 {
3397         u32 status;
3398         struct fw_control_ex    fw_control_context;
3399         struct fw_flash_Update_resp *ppayload =
3400                 (struct fw_flash_Update_resp *)(piomb + 4);
3401         u32 tag = le32_to_cpu(ppayload->tag);
3402         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3403         status = le32_to_cpu(ppayload->status);
3404         memcpy(&fw_control_context,
3405                 ccb->fw_control_context,
3406                 sizeof(fw_control_context));
3407         switch (status) {
3408         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3409                 PM8001_MSG_DBG(pm8001_ha,
3410                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3411                 break;
3412         case FLASH_UPDATE_IN_PROGRESS:
3413                 PM8001_MSG_DBG(pm8001_ha,
3414                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3415                 break;
3416         case FLASH_UPDATE_HDR_ERR:
3417                 PM8001_MSG_DBG(pm8001_ha,
3418                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3419                 break;
3420         case FLASH_UPDATE_OFFSET_ERR:
3421                 PM8001_MSG_DBG(pm8001_ha,
3422                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3423                 break;
3424         case FLASH_UPDATE_CRC_ERR:
3425                 PM8001_MSG_DBG(pm8001_ha,
3426                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3427                 break;
3428         case FLASH_UPDATE_LENGTH_ERR:
3429                 PM8001_MSG_DBG(pm8001_ha,
3430                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3431                 break;
3432         case FLASH_UPDATE_HW_ERR:
3433                 PM8001_MSG_DBG(pm8001_ha,
3434                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3435                 break;
3436         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3437                 PM8001_MSG_DBG(pm8001_ha,
3438                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3439                 break;
3440         case FLASH_UPDATE_DISABLED:
3441                 PM8001_MSG_DBG(pm8001_ha,
3442                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3443                 break;
3444         default:
3445                 PM8001_MSG_DBG(pm8001_ha,
3446                         pm8001_printk("No matched status = %d\n", status));
3447                 break;
3448         }
3449         ccb->fw_control_context->fw_control->retcode = status;
3450         pci_free_consistent(pm8001_ha->pdev,
3451                         fw_control_context.len,
3452                         fw_control_context.virtAddr,
3453                         fw_control_context.phys_addr);
3454         complete(pm8001_ha->nvmd_completion);
3455         ccb->task = NULL;
3456         ccb->ccb_tag = 0xFFFFFFFF;
3457         pm8001_ccb_free(pm8001_ha, tag);
3458         return 0;
3459 }
3460
3461 static int
3462 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3463 {
3464         u32 status;
3465         int i;
3466         struct general_event_resp *pPayload =
3467                 (struct general_event_resp *)(piomb + 4);
3468         status = le32_to_cpu(pPayload->status);
3469         PM8001_MSG_DBG(pm8001_ha,
3470                 pm8001_printk(" status = 0x%x\n", status));
3471         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3472                 PM8001_MSG_DBG(pm8001_ha,
3473                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3474                         pPayload->inb_IOMB_payload[i]));
3475         return 0;
3476 }
3477
3478 static int
3479 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3480 {
3481         struct sas_task *t;
3482         struct pm8001_ccb_info *ccb;
3483         unsigned long flags;
3484         u32 status ;
3485         u32 tag, scp;
3486         struct task_status_struct *ts;
3487
3488         struct task_abort_resp *pPayload =
3489                 (struct task_abort_resp *)(piomb + 4);
3490
3491         status = le32_to_cpu(pPayload->status);
3492         tag = le32_to_cpu(pPayload->tag);
3493         scp = le32_to_cpu(pPayload->scp);
3494         ccb = &pm8001_ha->ccb_info[tag];
3495         t = ccb->task;
3496         PM8001_IO_DBG(pm8001_ha,
3497                 pm8001_printk(" status = 0x%x\n", status));
3498         if (t == NULL)
3499                 return -1;
3500         ts = &t->task_status;
3501         if (status != 0)
3502                 PM8001_FAIL_DBG(pm8001_ha,
3503                         pm8001_printk("task abort failed status 0x%x ,"
3504                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3505         switch (status) {
3506         case IO_SUCCESS:
3507                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3508                 ts->resp = SAS_TASK_COMPLETE;
3509                 ts->stat = SAM_STAT_GOOD;
3510                 break;
3511         case IO_NOT_VALID:
3512                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3513                 ts->resp = TMF_RESP_FUNC_FAILED;
3514                 break;
3515         }
3516         spin_lock_irqsave(&t->task_state_lock, flags);
3517         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3518         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3519         t->task_state_flags |= SAS_TASK_STATE_DONE;
3520         spin_unlock_irqrestore(&t->task_state_lock, flags);
3521         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3522         mb();
3523         t->task_done(t);
3524         return 0;
3525 }
3526
3527 /**
3528  * mpi_hw_event -The hw event has come.
3529  * @pm8001_ha: our hba card information
3530  * @piomb: IO message buffer
3531  */
3532 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3533 {
3534         unsigned long flags;
3535         struct hw_event_resp *pPayload =
3536                 (struct hw_event_resp *)(piomb + 4);
3537         u32 lr_evt_status_phyid_portid =
3538                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3539         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3540         u8 phy_id =
3541                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3542         u16 eventType =
3543                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3544         u8 status =
3545                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3546         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3547         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3548         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3549         PM8001_MSG_DBG(pm8001_ha,
3550                 pm8001_printk("outbound queue HW event & event type : "));
3551         switch (eventType) {
3552         case HW_EVENT_PHY_START_STATUS:
3553                 PM8001_MSG_DBG(pm8001_ha,
3554                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3555                         " status = %x\n", status));
3556                 if (status == 0) {
3557                         phy->phy_state = 1;
3558                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3559                                 complete(phy->enable_completion);
3560                 }
3561                 break;
3562         case HW_EVENT_SAS_PHY_UP:
3563                 PM8001_MSG_DBG(pm8001_ha,
3564                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3565                 hw_event_sas_phy_up(pm8001_ha, piomb);
3566                 break;
3567         case HW_EVENT_SATA_PHY_UP:
3568                 PM8001_MSG_DBG(pm8001_ha,
3569                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3570                 hw_event_sata_phy_up(pm8001_ha, piomb);
3571                 break;
3572         case HW_EVENT_PHY_STOP_STATUS:
3573                 PM8001_MSG_DBG(pm8001_ha,
3574                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3575                         "status = %x\n", status));
3576                 if (status == 0)
3577                         phy->phy_state = 0;
3578                 break;
3579         case HW_EVENT_SATA_SPINUP_HOLD:
3580                 PM8001_MSG_DBG(pm8001_ha,
3581                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3582                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3583                 break;
3584         case HW_EVENT_PHY_DOWN:
3585                 PM8001_MSG_DBG(pm8001_ha,
3586                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3587                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3588                 phy->phy_attached = 0;
3589                 phy->phy_state = 0;
3590                 hw_event_phy_down(pm8001_ha, piomb);
3591                 break;
3592         case HW_EVENT_PORT_INVALID:
3593                 PM8001_MSG_DBG(pm8001_ha,
3594                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3595                 sas_phy_disconnected(sas_phy);
3596                 phy->phy_attached = 0;
3597                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3598                 break;
3599         /* the broadcast change primitive received, tell the LIBSAS this event
3600         to revalidate the sas domain*/
3601         case HW_EVENT_BROADCAST_CHANGE:
3602                 PM8001_MSG_DBG(pm8001_ha,
3603                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3604                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3605                         port_id, phy_id, 1, 0);
3606                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3607                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3608                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3609                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3610                 break;
3611         case HW_EVENT_PHY_ERROR:
3612                 PM8001_MSG_DBG(pm8001_ha,
3613                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3614                 sas_phy_disconnected(&phy->sas_phy);
3615                 phy->phy_attached = 0;
3616                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3617                 break;
3618         case HW_EVENT_BROADCAST_EXP:
3619                 PM8001_MSG_DBG(pm8001_ha,
3620                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3621                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3622                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3623                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3624                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3625                 break;
3626         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3627                 PM8001_MSG_DBG(pm8001_ha,
3628                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3629                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3630                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3631                 sas_phy_disconnected(sas_phy);
3632                 phy->phy_attached = 0;
3633                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3634                 break;
3635         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3636                 PM8001_MSG_DBG(pm8001_ha,
3637                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3638                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3639                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3640                         port_id, phy_id, 0, 0);
3641                 sas_phy_disconnected(sas_phy);
3642                 phy->phy_attached = 0;
3643                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3644                 break;
3645         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3646                 PM8001_MSG_DBG(pm8001_ha,
3647                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3648                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3649                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3650                         port_id, phy_id, 0, 0);
3651                 sas_phy_disconnected(sas_phy);
3652                 phy->phy_attached = 0;
3653                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3654                 break;
3655         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3656                 PM8001_MSG_DBG(pm8001_ha,
3657                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3658                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3659                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3660                         port_id, phy_id, 0, 0);
3661                 sas_phy_disconnected(sas_phy);
3662                 phy->phy_attached = 0;
3663                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3664                 break;
3665         case HW_EVENT_MALFUNCTION:
3666                 PM8001_MSG_DBG(pm8001_ha,
3667                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3668                 break;
3669         case HW_EVENT_BROADCAST_SES:
3670                 PM8001_MSG_DBG(pm8001_ha,
3671                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3672                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3673                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3674                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3675                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3676                 break;
3677         case HW_EVENT_INBOUND_CRC_ERROR:
3678                 PM8001_MSG_DBG(pm8001_ha,
3679                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3680                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3681                         HW_EVENT_INBOUND_CRC_ERROR,
3682                         port_id, phy_id, 0, 0);
3683                 break;
3684         case HW_EVENT_HARD_RESET_RECEIVED:
3685                 PM8001_MSG_DBG(pm8001_ha,
3686                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3687                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3688                 break;
3689         case HW_EVENT_ID_FRAME_TIMEOUT:
3690                 PM8001_MSG_DBG(pm8001_ha,
3691                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3692                 sas_phy_disconnected(sas_phy);
3693                 phy->phy_attached = 0;
3694                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3695                 break;
3696         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3697                 PM8001_MSG_DBG(pm8001_ha,
3698                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3699                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3700                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3701                         port_id, phy_id, 0, 0);
3702                 sas_phy_disconnected(sas_phy);
3703                 phy->phy_attached = 0;
3704                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3705                 break;
3706         case HW_EVENT_PORT_RESET_TIMER_TMO:
3707                 PM8001_MSG_DBG(pm8001_ha,
3708                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3709                 sas_phy_disconnected(sas_phy);
3710                 phy->phy_attached = 0;
3711                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3712                 break;
3713         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3714                 PM8001_MSG_DBG(pm8001_ha,
3715                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3716                 sas_phy_disconnected(sas_phy);
3717                 phy->phy_attached = 0;
3718                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3719                 break;
3720         case HW_EVENT_PORT_RECOVER:
3721                 PM8001_MSG_DBG(pm8001_ha,
3722                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3723                 break;
3724         case HW_EVENT_PORT_RESET_COMPLETE:
3725                 PM8001_MSG_DBG(pm8001_ha,
3726                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3727                 break;
3728         case EVENT_BROADCAST_ASYNCH_EVENT:
3729                 PM8001_MSG_DBG(pm8001_ha,
3730                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3731                 break;
3732         default:
3733                 PM8001_MSG_DBG(pm8001_ha,
3734                         pm8001_printk("Unknown event type = %x\n", eventType));
3735                 break;
3736         }
3737         return 0;
3738 }
3739
3740 /**
3741  * process_one_iomb - process one outbound Queue memory block
3742  * @pm8001_ha: our hba card information
3743  * @piomb: IO message buffer
3744  */
3745 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3746 {
3747         __le32 pHeader = *(__le32 *)piomb;
3748         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3749
3750         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3751
3752         switch (opc) {
3753         case OPC_OUB_ECHO:
3754                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3755                 break;
3756         case OPC_OUB_HW_EVENT:
3757                 PM8001_MSG_DBG(pm8001_ha,
3758                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3759                 mpi_hw_event(pm8001_ha, piomb);
3760                 break;
3761         case OPC_OUB_SSP_COMP:
3762                 PM8001_MSG_DBG(pm8001_ha,
3763                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3764                 mpi_ssp_completion(pm8001_ha, piomb);
3765                 break;
3766         case OPC_OUB_SMP_COMP:
3767                 PM8001_MSG_DBG(pm8001_ha,
3768                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3769                 mpi_smp_completion(pm8001_ha, piomb);
3770                 break;
3771         case OPC_OUB_LOCAL_PHY_CNTRL:
3772                 PM8001_MSG_DBG(pm8001_ha,
3773                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3774                 mpi_local_phy_ctl(pm8001_ha, piomb);
3775                 break;
3776         case OPC_OUB_DEV_REGIST:
3777                 PM8001_MSG_DBG(pm8001_ha,
3778                         pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3779                 mpi_reg_resp(pm8001_ha, piomb);
3780                 break;
3781         case OPC_OUB_DEREG_DEV:
3782                 PM8001_MSG_DBG(pm8001_ha,
3783                         pm8001_printk("unregister the device\n"));
3784                 mpi_dereg_resp(pm8001_ha, piomb);
3785                 break;
3786         case OPC_OUB_GET_DEV_HANDLE:
3787                 PM8001_MSG_DBG(pm8001_ha,
3788                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3789                 break;
3790         case OPC_OUB_SATA_COMP:
3791                 PM8001_MSG_DBG(pm8001_ha,
3792                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3793                 mpi_sata_completion(pm8001_ha, piomb);
3794                 break;
3795         case OPC_OUB_SATA_EVENT:
3796                 PM8001_MSG_DBG(pm8001_ha,
3797                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3798                 mpi_sata_event(pm8001_ha, piomb);
3799                 break;
3800         case OPC_OUB_SSP_EVENT:
3801                 PM8001_MSG_DBG(pm8001_ha,
3802                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3803                 mpi_ssp_event(pm8001_ha, piomb);
3804                 break;
3805         case OPC_OUB_DEV_HANDLE_ARRIV:
3806                 PM8001_MSG_DBG(pm8001_ha,
3807                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3808                 /*This is for target*/
3809                 break;
3810         case OPC_OUB_SSP_RECV_EVENT:
3811                 PM8001_MSG_DBG(pm8001_ha,
3812                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3813                 /*This is for target*/
3814                 break;
3815         case OPC_OUB_DEV_INFO:
3816                 PM8001_MSG_DBG(pm8001_ha,
3817                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
3818                 break;
3819         case OPC_OUB_FW_FLASH_UPDATE:
3820                 PM8001_MSG_DBG(pm8001_ha,
3821                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3822                 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3823                 break;
3824         case OPC_OUB_GPIO_RESPONSE:
3825                 PM8001_MSG_DBG(pm8001_ha,
3826                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3827                 break;
3828         case OPC_OUB_GPIO_EVENT:
3829                 PM8001_MSG_DBG(pm8001_ha,
3830                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3831                 break;
3832         case OPC_OUB_GENERAL_EVENT:
3833                 PM8001_MSG_DBG(pm8001_ha,
3834                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3835                 mpi_general_event(pm8001_ha, piomb);
3836                 break;
3837         case OPC_OUB_SSP_ABORT_RSP:
3838                 PM8001_MSG_DBG(pm8001_ha,
3839                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3840                 mpi_task_abort_resp(pm8001_ha, piomb);
3841                 break;
3842         case OPC_OUB_SATA_ABORT_RSP:
3843                 PM8001_MSG_DBG(pm8001_ha,
3844                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3845                 mpi_task_abort_resp(pm8001_ha, piomb);
3846                 break;
3847         case OPC_OUB_SAS_DIAG_MODE_START_END:
3848                 PM8001_MSG_DBG(pm8001_ha,
3849                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3850                 break;
3851         case OPC_OUB_SAS_DIAG_EXECUTE:
3852                 PM8001_MSG_DBG(pm8001_ha,
3853                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3854                 break;
3855         case OPC_OUB_GET_TIME_STAMP:
3856                 PM8001_MSG_DBG(pm8001_ha,
3857                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3858                 break;
3859         case OPC_OUB_SAS_HW_EVENT_ACK:
3860                 PM8001_MSG_DBG(pm8001_ha,
3861                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3862                 break;
3863         case OPC_OUB_PORT_CONTROL:
3864                 PM8001_MSG_DBG(pm8001_ha,
3865                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3866                 break;
3867         case OPC_OUB_SMP_ABORT_RSP:
3868                 PM8001_MSG_DBG(pm8001_ha,
3869                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3870                 mpi_task_abort_resp(pm8001_ha, piomb);
3871                 break;
3872         case OPC_OUB_GET_NVMD_DATA:
3873                 PM8001_MSG_DBG(pm8001_ha,
3874                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3875                 mpi_get_nvmd_resp(pm8001_ha, piomb);
3876                 break;
3877         case OPC_OUB_SET_NVMD_DATA:
3878                 PM8001_MSG_DBG(pm8001_ha,
3879                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3880                 mpi_set_nvmd_resp(pm8001_ha, piomb);
3881                 break;
3882         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3883                 PM8001_MSG_DBG(pm8001_ha,
3884                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3885                 break;
3886         case OPC_OUB_SET_DEVICE_STATE:
3887                 PM8001_MSG_DBG(pm8001_ha,
3888                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3889                 mpi_set_dev_state_resp(pm8001_ha, piomb);
3890                 break;
3891         case OPC_OUB_GET_DEVICE_STATE:
3892                 PM8001_MSG_DBG(pm8001_ha,
3893                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3894                 break;
3895         case OPC_OUB_SET_DEV_INFO:
3896                 PM8001_MSG_DBG(pm8001_ha,
3897                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3898                 break;
3899         case OPC_OUB_SAS_RE_INITIALIZE:
3900                 PM8001_MSG_DBG(pm8001_ha,
3901                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3902                 break;
3903         default:
3904                 PM8001_MSG_DBG(pm8001_ha,
3905                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3906                         opc));
3907                 break;
3908         }
3909 }
3910
3911 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3912 {
3913         struct outbound_queue_table *circularQ;
3914         void *pMsg1 = NULL;
3915         u8 uninitialized_var(bc);
3916         u32 ret = MPI_IO_STATUS_FAIL;
3917         unsigned long flags;
3918
3919         spin_lock_irqsave(&pm8001_ha->lock, flags);
3920         circularQ = &pm8001_ha->outbnd_q_tbl[0];
3921         do {
3922                 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3923                 if (MPI_IO_STATUS_SUCCESS == ret) {
3924                         /* process the outbound message */
3925                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3926                         /* free the message from the outbound circular buffer */
3927                         mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3928                 }
3929                 if (MPI_IO_STATUS_BUSY == ret) {
3930                         /* Update the producer index from SPC */
3931                         circularQ->producer_index =
3932                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3933                         if (le32_to_cpu(circularQ->producer_index) ==
3934                                 circularQ->consumer_idx)
3935                                 /* OQ is empty */
3936                                 break;
3937                 }
3938         } while (1);
3939         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3940         return ret;
3941 }
3942
3943 /* PCI_DMA_... to our direction translation. */
3944 static const u8 data_dir_flags[] = {
3945         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3946         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3947         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3948         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3949 };
3950 static void
3951 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3952 {
3953         int i;
3954         struct scatterlist *sg;
3955         struct pm8001_prd *buf_prd = prd;
3956
3957         for_each_sg(scatter, sg, nr, i) {
3958                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3959                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3960                 buf_prd->im_len.e = 0;
3961                 buf_prd++;
3962         }
3963 }
3964
3965 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
3966 {
3967         psmp_cmd->tag = hTag;
3968         psmp_cmd->device_id = cpu_to_le32(deviceID);
3969         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3970 }
3971
3972 /**
3973  * pm8001_chip_smp_req - send a SMP task to FW
3974  * @pm8001_ha: our hba card information.
3975  * @ccb: the ccb information this request used.
3976  */
3977 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3978         struct pm8001_ccb_info *ccb)
3979 {
3980         int elem, rc;
3981         struct sas_task *task = ccb->task;
3982         struct domain_device *dev = task->dev;
3983         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3984         struct scatterlist *sg_req, *sg_resp;
3985         u32 req_len, resp_len;
3986         struct smp_req smp_cmd;
3987         u32 opc;
3988         struct inbound_queue_table *circularQ;
3989
3990         memset(&smp_cmd, 0, sizeof(smp_cmd));
3991         /*
3992          * DMA-map SMP request, response buffers
3993          */
3994         sg_req = &task->smp_task.smp_req;
3995         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3996         if (!elem)
3997                 return -ENOMEM;
3998         req_len = sg_dma_len(sg_req);
3999
4000         sg_resp = &task->smp_task.smp_resp;
4001         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
4002         if (!elem) {
4003                 rc = -ENOMEM;
4004                 goto err_out;
4005         }
4006         resp_len = sg_dma_len(sg_resp);
4007         /* must be in dwords */
4008         if ((req_len & 0x3) || (resp_len & 0x3)) {
4009                 rc = -EINVAL;
4010                 goto err_out_2;
4011         }
4012
4013         opc = OPC_INB_SMP_REQUEST;
4014         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4015         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4016         smp_cmd.long_smp_req.long_req_addr =
4017                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4018         smp_cmd.long_smp_req.long_req_size =
4019                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4020         smp_cmd.long_smp_req.long_resp_addr =
4021                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4022         smp_cmd.long_smp_req.long_resp_size =
4023                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4024         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4025         mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
4026         return 0;
4027
4028 err_out_2:
4029         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4030                         PCI_DMA_FROMDEVICE);
4031 err_out:
4032         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4033                         PCI_DMA_TODEVICE);
4034         return rc;
4035 }
4036
4037 /**
4038  * pm8001_chip_ssp_io_req - send a SSP task to FW
4039  * @pm8001_ha: our hba card information.
4040  * @ccb: the ccb information this request used.
4041  */
4042 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4043         struct pm8001_ccb_info *ccb)
4044 {
4045         struct sas_task *task = ccb->task;
4046         struct domain_device *dev = task->dev;
4047         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4048         struct ssp_ini_io_start_req ssp_cmd;
4049         u32 tag = ccb->ccb_tag;
4050         int ret;
4051         u64 phys_addr;
4052         struct inbound_queue_table *circularQ;
4053         u32 opc = OPC_INB_SSPINIIOSTART;
4054         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4055         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4056         ssp_cmd.dir_m_tlr =
4057                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4058         SAS 1.1 compatible TLR*/
4059         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4060         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4061         ssp_cmd.tag = cpu_to_le32(tag);
4062         if (task->ssp_task.enable_first_burst)
4063                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4064         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4065         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4066         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
4067         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4068
4069         /* fill in PRD (scatter/gather) table, if any */
4070         if (task->num_scatter > 1) {
4071                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4072                 phys_addr = ccb->ccb_dma_handle +
4073                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4074                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4075                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4076                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4077         } else if (task->num_scatter == 1) {
4078                 u64 dma_addr = sg_dma_address(task->scatter);
4079                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4080                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4081                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4082                 ssp_cmd.esgl = 0;
4083         } else if (task->num_scatter == 0) {
4084                 ssp_cmd.addr_low = 0;
4085                 ssp_cmd.addr_high = 0;
4086                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4087                 ssp_cmd.esgl = 0;
4088         }
4089         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
4090         return ret;
4091 }
4092
4093 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4094         struct pm8001_ccb_info *ccb)
4095 {
4096         struct sas_task *task = ccb->task;
4097         struct domain_device *dev = task->dev;
4098         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4099         u32 tag = ccb->ccb_tag;
4100         int ret;
4101         struct sata_start_req sata_cmd;
4102         u32 hdr_tag, ncg_tag = 0;
4103         u64 phys_addr;
4104         u32 ATAP = 0x0;
4105         u32 dir;
4106         struct inbound_queue_table *circularQ;
4107         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4108         memset(&sata_cmd, 0, sizeof(sata_cmd));
4109         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4110         if (task->data_dir == PCI_DMA_NONE) {
4111                 ATAP = 0x04;  /* no data*/
4112                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4113         } else if (likely(!task->ata_task.device_control_reg_update)) {
4114                 if (task->ata_task.dma_xfer) {
4115                         ATAP = 0x06; /* DMA */
4116                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4117                 } else {
4118                         ATAP = 0x05; /* PIO*/
4119                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4120                 }
4121                 if (task->ata_task.use_ncq &&
4122                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4123                         ATAP = 0x07; /* FPDMA */
4124                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4125                 }
4126         }
4127         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
4128                 ncg_tag = hdr_tag;
4129         dir = data_dir_flags[task->data_dir] << 8;
4130         sata_cmd.tag = cpu_to_le32(tag);
4131         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4132         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4133         sata_cmd.ncqtag_atap_dir_m =
4134                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4135         sata_cmd.sata_fis = task->ata_task.fis;
4136         if (likely(!task->ata_task.device_control_reg_update))
4137                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4138         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4139         /* fill in PRD (scatter/gather) table, if any */
4140         if (task->num_scatter > 1) {
4141                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4142                 phys_addr = ccb->ccb_dma_handle +
4143                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4144                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4145                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4146                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4147         } else if (task->num_scatter == 1) {
4148                 u64 dma_addr = sg_dma_address(task->scatter);
4149                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4150                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4151                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4152                 sata_cmd.esgl = 0;
4153         } else if (task->num_scatter == 0) {
4154                 sata_cmd.addr_low = 0;
4155                 sata_cmd.addr_high = 0;
4156                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4157                 sata_cmd.esgl = 0;
4158         }
4159         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
4160         return ret;
4161 }
4162
4163 /**
4164  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4165  * @pm8001_ha: our hba card information.
4166  * @num: the inbound queue number
4167  * @phy_id: the phy id which we wanted to start up.
4168  */
4169 static int
4170 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4171 {
4172         struct phy_start_req payload;
4173         struct inbound_queue_table *circularQ;
4174         int ret;
4175         u32 tag = 0x01;
4176         u32 opcode = OPC_INB_PHYSTART;
4177         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4178         memset(&payload, 0, sizeof(payload));
4179         payload.tag = cpu_to_le32(tag);
4180         /*
4181          ** [0:7]   PHY Identifier
4182          ** [8:11]  link rate 1.5G, 3G, 6G
4183          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4184          ** [14]    0b disable spin up hold; 1b enable spin up hold
4185          */
4186         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4187                 LINKMODE_AUTO | LINKRATE_15 |
4188                 LINKRATE_30 | LINKRATE_60 | phy_id);
4189         payload.sas_identify.dev_type = SAS_END_DEV;
4190         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4191         memcpy(payload.sas_identify.sas_addr,
4192                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4193         payload.sas_identify.phy_id = phy_id;
4194         ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4195         return ret;
4196 }
4197
4198 /**
4199  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4200  * @pm8001_ha: our hba card information.
4201  * @num: the inbound queue number
4202  * @phy_id: the phy id which we wanted to start up.
4203  */
4204 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4205         u8 phy_id)
4206 {
4207         struct phy_stop_req payload;
4208         struct inbound_queue_table *circularQ;
4209         int ret;
4210         u32 tag = 0x01;
4211         u32 opcode = OPC_INB_PHYSTOP;
4212         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4213         memset(&payload, 0, sizeof(payload));
4214         payload.tag = cpu_to_le32(tag);
4215         payload.phy_id = cpu_to_le32(phy_id);
4216         ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4217         return ret;
4218 }
4219
4220 /**
4221  * see comments on mpi_reg_resp.
4222  */
4223 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4224         struct pm8001_device *pm8001_dev, u32 flag)
4225 {
4226         struct reg_dev_req payload;
4227         u32     opc;
4228         u32 stp_sspsmp_sata = 0x4;
4229         struct inbound_queue_table *circularQ;
4230         u32 linkrate, phy_id;
4231         int rc, tag = 0xdeadbeef;
4232         struct pm8001_ccb_info *ccb;
4233         u8 retryFlag = 0x1;
4234         u16 firstBurstSize = 0;
4235         u16 ITNT = 2000;
4236         struct domain_device *dev = pm8001_dev->sas_device;
4237         struct domain_device *parent_dev = dev->parent;
4238         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4239
4240         memset(&payload, 0, sizeof(payload));
4241         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4242         if (rc)
4243                 return rc;
4244         ccb = &pm8001_ha->ccb_info[tag];
4245         ccb->device = pm8001_dev;
4246         ccb->ccb_tag = tag;
4247         payload.tag = cpu_to_le32(tag);
4248         if (flag == 1)
4249                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4250         else {
4251                 if (pm8001_dev->dev_type == SATA_DEV)
4252                         stp_sspsmp_sata = 0x00; /* stp*/
4253                 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4254                         pm8001_dev->dev_type == EDGE_DEV ||
4255                         pm8001_dev->dev_type == FANOUT_DEV)
4256                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4257         }
4258         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4259                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4260         else
4261                 phy_id = pm8001_dev->attached_phy;
4262         opc = OPC_INB_REG_DEV;
4263         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4264                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4265         payload.phyid_portid =
4266                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4267                 ((phy_id & 0x0F) << 4));
4268         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4269                 ((linkrate & 0x0F) * 0x1000000) |
4270                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4271         payload.firstburstsize_ITNexustimeout =
4272                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4273         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4274                 SAS_ADDR_SIZE);
4275         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4276         return rc;
4277 }
4278
4279 /**
4280  * see comments on mpi_reg_resp.
4281  */
4282 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4283         u32 device_id)
4284 {
4285         struct dereg_dev_req payload;
4286         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4287         int ret;
4288         struct inbound_queue_table *circularQ;
4289
4290         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4291         memset(&payload, 0, sizeof(payload));
4292         payload.tag = cpu_to_le32(1);
4293         payload.device_id = cpu_to_le32(device_id);
4294         PM8001_MSG_DBG(pm8001_ha,
4295                 pm8001_printk("unregister device device_id = %d\n", device_id));
4296         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4297         return ret;
4298 }
4299
4300 /**
4301  * pm8001_chip_phy_ctl_req - support the local phy operation
4302  * @pm8001_ha: our hba card information.
4303  * @num: the inbound queue number
4304  * @phy_id: the phy id which we wanted to operate
4305  * @phy_op:
4306  */
4307 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4308         u32 phyId, u32 phy_op)
4309 {
4310         struct local_phy_ctl_req payload;
4311         struct inbound_queue_table *circularQ;
4312         int ret;
4313         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4314         memset(&payload, 0, sizeof(payload));
4315         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4316         payload.tag = cpu_to_le32(1);
4317         payload.phyop_phyid =
4318                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4319         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4320         return ret;
4321 }
4322
4323 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4324 {
4325         u32 value;
4326 #ifdef PM8001_USE_MSIX
4327         return 1;
4328 #endif
4329         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4330         if (value)
4331                 return 1;
4332         return 0;
4333
4334 }
4335
4336 /**
4337  * pm8001_chip_isr - PM8001 isr handler.
4338  * @pm8001_ha: our hba card information.
4339  * @irq: irq number.
4340  * @stat: stat.
4341  */
4342 static irqreturn_t
4343 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4344 {
4345         pm8001_chip_interrupt_disable(pm8001_ha);
4346         process_oq(pm8001_ha);
4347         pm8001_chip_interrupt_enable(pm8001_ha);
4348         return IRQ_HANDLED;
4349 }
4350
4351 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4352         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4353 {
4354         struct task_abort_req task_abort;
4355         struct inbound_queue_table *circularQ;
4356         int ret;
4357         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4358         memset(&task_abort, 0, sizeof(task_abort));
4359         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4360                 task_abort.abort_all = 0;
4361                 task_abort.device_id = cpu_to_le32(dev_id);
4362                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4363                 task_abort.tag = cpu_to_le32(cmd_tag);
4364         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4365                 task_abort.abort_all = cpu_to_le32(1);
4366                 task_abort.device_id = cpu_to_le32(dev_id);
4367                 task_abort.tag = cpu_to_le32(cmd_tag);
4368         }
4369         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4370         return ret;
4371 }
4372
4373 /**
4374  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4375  * @task: the task we wanted to aborted.
4376  * @flag: the abort flag.
4377  */
4378 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4379         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4380 {
4381         u32 opc, device_id;
4382         int rc = TMF_RESP_FUNC_FAILED;
4383         PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4384                 " = %x", cmd_tag, task_tag));
4385         if (pm8001_dev->dev_type == SAS_END_DEV)
4386                 opc = OPC_INB_SSP_ABORT;
4387         else if (pm8001_dev->dev_type == SATA_DEV)
4388                 opc = OPC_INB_SATA_ABORT;
4389         else
4390                 opc = OPC_INB_SMP_ABORT;/* SMP */
4391         device_id = pm8001_dev->device_id;
4392         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4393                 task_tag, cmd_tag);
4394         if (rc != TMF_RESP_FUNC_COMPLETE)
4395                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4396         return rc;
4397 }
4398
4399 /**
4400  * pm8001_chip_ssp_tm_req - built the task management command.
4401  * @pm8001_ha: our hba card information.
4402  * @ccb: the ccb information.
4403  * @tmf: task management function.
4404  */
4405 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4406         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4407 {
4408         struct sas_task *task = ccb->task;
4409         struct domain_device *dev = task->dev;
4410         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4411         u32 opc = OPC_INB_SSPINITMSTART;
4412         struct inbound_queue_table *circularQ;
4413         struct ssp_ini_tm_start_req sspTMCmd;
4414         int ret;
4415
4416         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4417         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4418         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4419         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4420         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4421         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4422         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4423         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4424         return ret;
4425 }
4426
4427 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4428         void *payload)
4429 {
4430         u32 opc = OPC_INB_GET_NVMD_DATA;
4431         u32 nvmd_type;
4432         int rc;
4433         u32 tag;
4434         struct pm8001_ccb_info *ccb;
4435         struct inbound_queue_table *circularQ;
4436         struct get_nvm_data_req nvmd_req;
4437         struct fw_control_ex *fw_control_context;
4438         struct pm8001_ioctl_payload *ioctl_payload = payload;
4439
4440         nvmd_type = ioctl_payload->minor_function;
4441         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4442         if (!fw_control_context)
4443                 return -ENOMEM;
4444         fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4445         fw_control_context->len = ioctl_payload->length;
4446         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4447         memset(&nvmd_req, 0, sizeof(nvmd_req));
4448         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4449         if (rc) {
4450                 kfree(fw_control_context);
4451                 return rc;
4452         }
4453         ccb = &pm8001_ha->ccb_info[tag];
4454         ccb->ccb_tag = tag;
4455         ccb->fw_control_context = fw_control_context;
4456         nvmd_req.tag = cpu_to_le32(tag);
4457
4458         switch (nvmd_type) {
4459         case TWI_DEVICE: {
4460                 u32 twi_addr, twi_page_size;
4461                 twi_addr = 0xa8;
4462                 twi_page_size = 2;
4463
4464                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4465                         twi_page_size << 8 | TWI_DEVICE);
4466                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4467                 nvmd_req.resp_addr_hi =
4468                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4469                 nvmd_req.resp_addr_lo =
4470                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4471                 break;
4472         }
4473         case C_SEEPROM: {
4474                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4475                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4476                 nvmd_req.resp_addr_hi =
4477                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4478                 nvmd_req.resp_addr_lo =
4479                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4480                 break;
4481         }
4482         case VPD_FLASH: {
4483                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4484                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4485                 nvmd_req.resp_addr_hi =
4486                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4487                 nvmd_req.resp_addr_lo =
4488                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4489                 break;
4490         }
4491         case EXPAN_ROM: {
4492                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4493                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4494                 nvmd_req.resp_addr_hi =
4495                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4496                 nvmd_req.resp_addr_lo =
4497                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4498                 break;
4499         }
4500         default:
4501                 break;
4502         }
4503         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4504         return rc;
4505 }
4506
4507 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4508         void *payload)
4509 {
4510         u32 opc = OPC_INB_SET_NVMD_DATA;
4511         u32 nvmd_type;
4512         int rc;
4513         u32 tag;
4514         struct pm8001_ccb_info *ccb;
4515         struct inbound_queue_table *circularQ;
4516         struct set_nvm_data_req nvmd_req;
4517         struct fw_control_ex *fw_control_context;
4518         struct pm8001_ioctl_payload *ioctl_payload = payload;
4519
4520         nvmd_type = ioctl_payload->minor_function;
4521         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4522         if (!fw_control_context)
4523                 return -ENOMEM;
4524         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4525         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4526                 ioctl_payload->func_specific,
4527                 ioctl_payload->length);
4528         memset(&nvmd_req, 0, sizeof(nvmd_req));
4529         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4530         if (rc) {
4531                 kfree(fw_control_context);
4532                 return rc;
4533         }
4534         ccb = &pm8001_ha->ccb_info[tag];
4535         ccb->fw_control_context = fw_control_context;
4536         ccb->ccb_tag = tag;
4537         nvmd_req.tag = cpu_to_le32(tag);
4538         switch (nvmd_type) {
4539         case TWI_DEVICE: {
4540                 u32 twi_addr, twi_page_size;
4541                 twi_addr = 0xa8;
4542                 twi_page_size = 2;
4543                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4544                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4545                         twi_page_size << 8 | TWI_DEVICE);
4546                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4547                 nvmd_req.resp_addr_hi =
4548                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4549                 nvmd_req.resp_addr_lo =
4550                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4551                 break;
4552         }
4553         case C_SEEPROM:
4554                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4555                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4556                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4557                 nvmd_req.resp_addr_hi =
4558                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4559                 nvmd_req.resp_addr_lo =
4560                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4561                 break;
4562         case VPD_FLASH:
4563                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4564                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4565                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4566                 nvmd_req.resp_addr_hi =
4567                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4568                 nvmd_req.resp_addr_lo =
4569                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4570                 break;
4571         case EXPAN_ROM:
4572                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4573                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4574                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4575                 nvmd_req.resp_addr_hi =
4576                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4577                 nvmd_req.resp_addr_lo =
4578                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4579                 break;
4580         default:
4581                 break;
4582         }
4583         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4584         return rc;
4585 }
4586
4587 /**
4588  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4589  * @pm8001_ha: our hba card information.
4590  * @fw_flash_updata_info: firmware flash update param
4591  */
4592 static int
4593 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4594         void *fw_flash_updata_info, u32 tag)
4595 {
4596         struct fw_flash_Update_req payload;
4597         struct fw_flash_updata_info *info;
4598         struct inbound_queue_table *circularQ;
4599         int ret;
4600         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4601
4602         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4603         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4604         info = fw_flash_updata_info;
4605         payload.tag = cpu_to_le32(tag);
4606         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4607         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4608         payload.total_image_len = cpu_to_le32(info->total_image_len);
4609         payload.len = info->sgl.im_len.len ;
4610         payload.sgl_addr_lo =
4611                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4612         payload.sgl_addr_hi =
4613                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4614         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4615         return ret;
4616 }
4617
4618 static int
4619 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4620         void *payload)
4621 {
4622         struct fw_flash_updata_info flash_update_info;
4623         struct fw_control_info *fw_control;
4624         struct fw_control_ex *fw_control_context;
4625         int rc;
4626         u32 tag;
4627         struct pm8001_ccb_info *ccb;
4628         void *buffer = NULL;
4629         dma_addr_t phys_addr;
4630         u32 phys_addr_hi;
4631         u32 phys_addr_lo;
4632         struct pm8001_ioctl_payload *ioctl_payload = payload;
4633
4634         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4635         if (!fw_control_context)
4636                 return -ENOMEM;
4637         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4638         if (fw_control->len != 0) {
4639                 if (pm8001_mem_alloc(pm8001_ha->pdev,
4640                         (void **)&buffer,
4641                         &phys_addr,
4642                         &phys_addr_hi,
4643                         &phys_addr_lo,
4644                         fw_control->len, 0) != 0) {
4645                                 PM8001_FAIL_DBG(pm8001_ha,
4646                                         pm8001_printk("Mem alloc failure\n"));
4647                                 kfree(fw_control_context);
4648                                 return -ENOMEM;
4649                 }
4650         }
4651         memcpy(buffer, fw_control->buffer, fw_control->len);
4652         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4653         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4654         flash_update_info.sgl.im_len.e = 0;
4655         flash_update_info.cur_image_offset = fw_control->offset;
4656         flash_update_info.cur_image_len = fw_control->len;
4657         flash_update_info.total_image_len = fw_control->size;
4658         fw_control_context->fw_control = fw_control;
4659         fw_control_context->virtAddr = buffer;
4660         fw_control_context->len = fw_control->len;
4661         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4662         if (rc) {
4663                 kfree(fw_control_context);
4664                 return rc;
4665         }
4666         ccb = &pm8001_ha->ccb_info[tag];
4667         ccb->fw_control_context = fw_control_context;
4668         ccb->ccb_tag = tag;
4669         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4670                 tag);
4671         return rc;
4672 }
4673
4674 static int
4675 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4676         struct pm8001_device *pm8001_dev, u32 state)
4677 {
4678         struct set_dev_state_req payload;
4679         struct inbound_queue_table *circularQ;
4680         struct pm8001_ccb_info *ccb;
4681         int rc;
4682         u32 tag;
4683         u32 opc = OPC_INB_SET_DEVICE_STATE;
4684         memset(&payload, 0, sizeof(payload));
4685         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4686         if (rc)
4687                 return -1;
4688         ccb = &pm8001_ha->ccb_info[tag];
4689         ccb->ccb_tag = tag;
4690         ccb->device = pm8001_dev;
4691         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4692         payload.tag = cpu_to_le32(tag);
4693         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4694         payload.nds = cpu_to_le32(state);
4695         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4696         return rc;
4697
4698 }
4699
4700 static int
4701 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4702 {
4703         struct sas_re_initialization_req payload;
4704         struct inbound_queue_table *circularQ;
4705         struct pm8001_ccb_info *ccb;
4706         int rc;
4707         u32 tag;
4708         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4709         memset(&payload, 0, sizeof(payload));
4710         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4711         if (rc)
4712                 return -1;
4713         ccb = &pm8001_ha->ccb_info[tag];
4714         ccb->ccb_tag = tag;
4715         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4716         payload.tag = cpu_to_le32(tag);
4717         payload.SSAHOLT = cpu_to_le32(0xd << 25);
4718         payload.sata_hol_tmo = cpu_to_le32(80);
4719         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4720         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4721         return rc;
4722
4723 }
4724
4725 const struct pm8001_dispatch pm8001_8001_dispatch = {
4726         .name                   = "pmc8001",
4727         .chip_init              = pm8001_chip_init,
4728         .chip_soft_rst          = pm8001_chip_soft_rst,
4729         .chip_rst               = pm8001_hw_chip_rst,
4730         .chip_iounmap           = pm8001_chip_iounmap,
4731         .isr                    = pm8001_chip_isr,
4732         .is_our_interupt        = pm8001_chip_is_our_interupt,
4733         .isr_process_oq         = process_oq,
4734         .interrupt_enable       = pm8001_chip_interrupt_enable,
4735         .interrupt_disable      = pm8001_chip_interrupt_disable,
4736         .make_prd               = pm8001_chip_make_sg,
4737         .smp_req                = pm8001_chip_smp_req,
4738         .ssp_io_req             = pm8001_chip_ssp_io_req,
4739         .sata_req               = pm8001_chip_sata_req,
4740         .phy_start_req          = pm8001_chip_phy_start_req,
4741         .phy_stop_req           = pm8001_chip_phy_stop_req,
4742         .reg_dev_req            = pm8001_chip_reg_dev_req,
4743         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4744         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
4745         .task_abort             = pm8001_chip_abort_task,
4746         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4747         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4748         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4749         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4750         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4751         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
4752 };