2 * Marvell 88SE64xx hardware specific
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
8 * This file is licensed under GPLv2.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
30 static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i)
32 void __iomem *regs = mvi->regs;
34 struct mvs_phy *phy = &mvi->phy[i];
36 /* TODO check & save device type */
37 reg = mr32(MVS_GBL_PORT_TYPE);
38 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
39 if (reg & MODE_SAS_SATA & (1 << i))
40 phy->phy_type |= PORT_TYPE_SAS;
42 phy->phy_type |= PORT_TYPE_SATA;
45 static void __devinit mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)
47 void __iomem *regs = mvi->regs;
51 if (mvi->chip->n_phy <= 4)
52 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);
54 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
58 static void __devinit mvs_64xx_phy_hacks(struct mvs_info *mvi)
60 void __iomem *regs = mvi->regs;
64 if (!(mvi->flags & MVF_FLAG_SOC)) {
65 /* TEST - for phy decoding error, adjust voltage levels */
66 mw32(MVS_P0_VSR_ADDR + 0, 0x8);
67 mw32(MVS_P0_VSR_DATA + 0, 0x2F0);
69 mw32(MVS_P0_VSR_ADDR + 8, 0x8);
70 mw32(MVS_P0_VSR_DATA + 8, 0x2F0);
72 mw32(MVS_P0_VSR_ADDR + 16, 0x8);
73 mw32(MVS_P0_VSR_DATA + 16, 0x2F0);
75 mw32(MVS_P0_VSR_ADDR + 24, 0x8);
76 mw32(MVS_P0_VSR_DATA + 24, 0x2F0);
79 /* disable auto port detection */
80 mw32(MVS_GBL_PORT_TYPE, 0);
81 for (i = 0; i < mvi->chip->n_phy; i++) {
82 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7);
83 mvs_write_port_vsr_data(mvi, i, 0x90000000);
84 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9);
85 mvs_write_port_vsr_data(mvi, i, 0x50f2);
86 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11);
87 mvs_write_port_vsr_data(mvi, i, 0x0e);
92 static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
94 void __iomem *regs = mvi->regs;
97 if (!(mvi->flags & MVF_FLAG_SOC)) {
99 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®);
101 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®);
104 reg = mr32(MVS_PHY_CTL);
108 tmp |= (1U << phy_id) << PCTL_LINK_OFFS;
110 tmp |= (1U << (phy_id - 4)) << PCTL_LINK_OFFS;
112 if (!(mvi->flags & MVF_FLAG_SOC)) {
114 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
116 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
118 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
120 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg);
123 mw32(MVS_PHY_CTL, tmp);
125 mw32(MVS_PHY_CTL, reg);
129 static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
132 tmp = mvs_read_port_irq_stat(mvi, phy_id);
133 tmp &= ~PHYEV_RDY_CH;
134 mvs_write_port_irq_stat(mvi, phy_id, tmp);
135 tmp = mvs_read_phy_ctl(mvi, phy_id);
140 mvs_write_phy_ctl(mvi, phy_id, tmp);
143 tmp = mvs_read_phy_ctl(mvi, phy_id);
144 } while (tmp & PHY_RST_HARD);
148 void mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
150 void __iomem *regs = mvi->regs;
153 tmp = mr32(MVS_INT_STAT_SRS_0);
155 printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp);
156 mw32(MVS_INT_STAT_SRS_0, tmp);
159 tmp = mr32(MVS_INT_STAT_SRS_0);
160 if (tmp & (1 << (reg_set % 32))) {
161 printk(KERN_DEBUG "register set 0x%x was stopped.\n",
163 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
168 static int __devinit mvs_64xx_chip_reset(struct mvs_info *mvi)
170 void __iomem *regs = mvi->regs;
174 /* make sure interrupts are masked immediately (paranoia) */
175 mw32(MVS_GBL_CTL, 0);
176 tmp = mr32(MVS_GBL_CTL);
178 /* Reset Controller */
179 if (!(tmp & HBA_RST)) {
180 if (mvi->flags & MVF_PHY_PWR_FIX) {
181 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
182 tmp &= ~PCTL_PWR_OFF;
183 tmp |= PCTL_PHY_DSBL;
184 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
186 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
187 tmp &= ~PCTL_PWR_OFF;
188 tmp |= PCTL_PHY_DSBL;
189 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
193 /* make sure interrupts are masked immediately (paranoia) */
194 mw32(MVS_GBL_CTL, 0);
195 tmp = mr32(MVS_GBL_CTL);
197 /* Reset Controller */
198 if (!(tmp & HBA_RST)) {
199 /* global reset, incl. COMRESET/H_RESET_N (self-clearing) */
200 mw32_f(MVS_GBL_CTL, HBA_RST);
203 /* wait for reset to finish; timeout is just a guess */
208 if (!(mr32(MVS_GBL_CTL) & HBA_RST))
211 if (mr32(MVS_GBL_CTL) & HBA_RST) {
212 dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n");
218 static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
220 void __iomem *regs = mvi->regs;
222 if (!(mvi->flags & MVF_FLAG_SOC)) {
230 pci_read_config_dword(mvi->pdev, offs, &tmp);
231 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
232 pci_write_config_dword(mvi->pdev, offs, tmp);
234 tmp = mr32(MVS_PHY_CTL);
235 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
236 mw32(MVS_PHY_CTL, tmp);
240 static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
242 void __iomem *regs = mvi->regs;
244 if (!(mvi->flags & MVF_FLAG_SOC)) {
252 pci_read_config_dword(mvi->pdev, offs, &tmp);
253 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
254 pci_write_config_dword(mvi->pdev, offs, tmp);
256 tmp = mr32(MVS_PHY_CTL);
257 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
258 mw32(MVS_PHY_CTL, tmp);
262 static int __devinit mvs_64xx_init(struct mvs_info *mvi)
264 void __iomem *regs = mvi->regs;
268 if (mvi->pdev && mvi->pdev->revision == 0)
269 mvi->flags |= MVF_PHY_PWR_FIX;
270 if (!(mvi->flags & MVF_FLAG_SOC)) {
271 mvs_show_pcie_usage(mvi);
272 tmp = mvs_64xx_chip_reset(mvi);
276 tmp = mr32(MVS_PHY_CTL);
277 tmp &= ~PCTL_PWR_OFF;
278 tmp |= PCTL_PHY_DSBL;
279 mw32(MVS_PHY_CTL, tmp);
283 /* make sure RST is set; HBA_RST /should/ have done that for us */
284 cctl = mr32(MVS_CTL) & 0xFFFF;
288 mw32_f(MVS_CTL, cctl | CCTL_RST);
290 if (!(mvi->flags & MVF_FLAG_SOC)) {
291 /* write to device control _AND_ device status register */
292 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
293 tmp &= ~PRD_REQ_MASK;
295 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
297 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
298 tmp &= ~PCTL_PWR_OFF;
299 tmp &= ~PCTL_PHY_DSBL;
300 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
302 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
304 tmp &= ~PCTL_PHY_DSBL;
305 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
307 tmp = mr32(MVS_PHY_CTL);
308 tmp &= ~PCTL_PWR_OFF;
310 tmp &= ~PCTL_PHY_DSBL;
311 tmp |= PCTL_LINK_RST;
312 mw32(MVS_PHY_CTL, tmp);
314 tmp &= ~PCTL_LINK_RST;
315 mw32(MVS_PHY_CTL, tmp);
320 mw32(MVS_PCS, 0); /* MVS_PCS */
322 mvs_64xx_phy_hacks(mvi);
324 /* enable auto port detection */
325 mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN);
327 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
328 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
330 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
331 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
333 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
334 mw32(MVS_TX_LO, mvi->tx_dma);
335 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
337 mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
338 mw32(MVS_RX_LO, mvi->rx_dma);
339 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
341 for (i = 0; i < mvi->chip->n_phy; i++) {
342 /* set phy local SAS address */
343 /* should set little endian SAS address to 64xx chip */
344 mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI,
345 cpu_to_be64(mvi->phy[i].dev_sas_addr));
347 mvs_64xx_enable_xmt(mvi, i);
349 mvs_64xx_phy_reset(mvi, i, 1);
351 mvs_64xx_detect_porttype(mvi, i);
353 if (mvi->flags & MVF_FLAG_SOC) {
354 /* set select registers */
355 writel(0x0E008000, regs + 0x000);
356 writel(0x59000008, regs + 0x004);
357 writel(0x20, regs + 0x008);
358 writel(0x20, regs + 0x00c);
359 writel(0x20, regs + 0x010);
360 writel(0x20, regs + 0x014);
361 writel(0x20, regs + 0x018);
362 writel(0x20, regs + 0x01c);
364 for (i = 0; i < mvi->chip->n_phy; i++) {
365 /* clear phy int status */
366 tmp = mvs_read_port_irq_stat(mvi, i);
367 tmp &= ~PHYEV_SIG_FIS;
368 mvs_write_port_irq_stat(mvi, i, tmp);
370 /* set phy int mask */
371 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS |
372 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR |
374 mvs_write_port_irq_mask(mvi, i, tmp);
377 mvs_update_phyinfo(mvi, i, 1);
380 /* FIXME: update wide port bitmaps */
382 /* little endian for open address and command table, etc. */
384 * it seems that ( from the spec ) turning on big-endian won't
385 * do us any good on big-endian machines, need further confirmation
387 cctl = mr32(MVS_CTL);
388 cctl |= CCTL_ENDIAN_CMD;
389 cctl |= CCTL_ENDIAN_DATA;
390 cctl &= ~CCTL_ENDIAN_OPEN;
391 cctl |= CCTL_ENDIAN_RSP;
392 mw32_f(MVS_CTL, cctl);
394 /* reset CMD queue */
398 /* interrupt coalescing may cause missing HW interrput in some case,
399 * and the max count is 0x1ff, while our max slot is 0x200,
400 * it will make count 0.
403 mw32(MVS_INT_COAL, tmp);
406 mw32(MVS_INT_COAL_TMOUT, tmp);
408 /* ladies and gentlemen, start your engines */
410 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
411 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
412 /* enable CMD/CMPL_Q/RESP mode */
413 mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN |
414 PCS_CMD_EN | PCS_CMD_STOP_ERR);
416 /* enable completion queue interrupt */
417 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
420 mw32(MVS_INT_MASK, tmp);
422 /* Enable SRS interrupt */
423 mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
428 static int mvs_64xx_ioremap(struct mvs_info *mvi)
430 if (!mvs_ioremap(mvi, 4, 2))
435 static void mvs_64xx_iounmap(struct mvs_info *mvi)
437 mvs_iounmap(mvi->regs);
438 mvs_iounmap(mvi->regs_ex);
441 static void mvs_64xx_interrupt_enable(struct mvs_info *mvi)
443 void __iomem *regs = mvi->regs;
446 tmp = mr32(MVS_GBL_CTL);
447 mw32(MVS_GBL_CTL, tmp | INT_EN);
450 static void mvs_64xx_interrupt_disable(struct mvs_info *mvi)
452 void __iomem *regs = mvi->regs;
455 tmp = mr32(MVS_GBL_CTL);
456 mw32(MVS_GBL_CTL, tmp & ~INT_EN);
459 static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq)
461 void __iomem *regs = mvi->regs;
464 if (!(mvi->flags & MVF_FLAG_SOC)) {
465 stat = mr32(MVS_GBL_INT_STAT);
467 if (stat == 0 || stat == 0xffffffff)
474 static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat)
476 void __iomem *regs = mvi->regs;
478 /* clear CMD_CMPLT ASAP */
479 mw32_f(MVS_INT_STAT, CINT_DONE);
480 #ifndef MVS_USE_TASKLET
481 spin_lock(&mvi->lock);
484 #ifndef MVS_USE_TASKLET
485 spin_unlock(&mvi->lock);
490 static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx)
493 mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));
494 mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));
496 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));
497 } while (tmp & 1 << (slot_idx % 32));
499 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));
500 } while (tmp & 1 << (slot_idx % 32));
503 static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
506 void __iomem *regs = mvi->regs;
509 if (type == PORT_TYPE_SATA) {
510 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
511 mw32(MVS_INT_STAT_SRS_0, tmp);
513 mw32(MVS_INT_STAT, CINT_CI_STOP);
514 tmp = mr32(MVS_PCS) | 0xFF00;
518 static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
520 void __iomem *regs = mvi->regs;
523 if (*tfs == MVS_ID_NOT_MAPPED)
526 offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
529 mw32(MVS_PCS, tmp & ~offs);
532 mw32(MVS_CTL, tmp & ~offs);
535 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);
537 mw32(MVS_INT_STAT_SRS_0, tmp);
539 *tfs = MVS_ID_NOT_MAPPED;
543 static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
547 void __iomem *regs = mvi->regs;
549 if (*tfs != MVS_ID_NOT_MAPPED)
554 for (i = 0; i < mvi->chip->srs_sz; i++) {
557 offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
562 mw32(MVS_PCS, tmp | offs);
564 mw32(MVS_CTL, tmp | offs);
565 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);
567 mw32(MVS_INT_STAT_SRS_0, tmp);
571 return MVS_ID_NOT_MAPPED;
574 void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
577 struct scatterlist *sg;
578 struct mvs_prd *buf_prd = prd;
579 for_each_sg(scatter, sg, nr, i) {
580 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
581 buf_prd->len = cpu_to_le32(sg_dma_len(sg));
586 static int mvs_64xx_oob_done(struct mvs_info *mvi, int i)
589 mvs_write_port_cfg_addr(mvi, i,
591 phy_st = mvs_read_port_cfg_data(mvi, i);
592 if (phy_st & PHY_OOB_DTCTD)
597 static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i,
598 struct sas_identify_frame *id)
601 struct mvs_phy *phy = &mvi->phy[i];
602 struct asd_sas_phy *sas_phy = &phy->sas_phy;
605 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
606 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
608 phy->minimum_linkrate =
610 PHY_MIN_SPP_PHYS_LINK_RATE_MASK) >> 8;
611 phy->maximum_linkrate =
613 PHY_MAX_SPP_PHYS_LINK_RATE_MASK) >> 12;
615 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
616 phy->dev_info = mvs_read_port_cfg_data(mvi, i);
618 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
619 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
621 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
622 phy->att_dev_sas_addr =
623 (u64) mvs_read_port_cfg_data(mvi, i) << 32;
624 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
625 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
626 phy->att_dev_sas_addr = SAS_ADDR(&phy->att_dev_sas_addr);
629 static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)
632 struct mvs_phy *phy = &mvi->phy[i];
633 /* workaround for HW phy decoding error on 1.5g disk drive */
634 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
635 tmp = mvs_read_port_vsr_data(mvi, i);
636 if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
637 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) ==
638 SAS_LINK_RATE_1_5_GBPS)
639 tmp &= ~PHY_MODE6_LATECLK;
641 tmp |= PHY_MODE6_LATECLK;
642 mvs_write_port_vsr_data(mvi, i, tmp);
645 void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
646 struct sas_phy_linkrates *rates)
648 u32 lrmin = 0, lrmax = 0;
651 tmp = mvs_read_phy_ctl(mvi, phy_id);
652 lrmin = (rates->minimum_linkrate << 8);
653 lrmax = (rates->maximum_linkrate << 12);
663 mvs_write_phy_ctl(mvi, phy_id, tmp);
664 mvs_64xx_phy_reset(mvi, phy_id, 1);
667 static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
670 void __iomem *regs = mvi->regs;
672 mw32(MVS_PCS, tmp & 0xFFFF);
675 mw32(MVS_CTL, tmp & 0xFFFF);
680 u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
682 void __iomem *regs = mvi->regs_ex;
683 return ior32(SPI_DATA_REG_64XX);
686 void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
688 void __iomem *regs = mvi->regs_ex;
689 iow32(SPI_DATA_REG_64XX, data);
693 int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
703 dwTmp = ((u32)cmd << 24) | ((u32)length << 19);
707 if (addr != MV_MAX_U32) {
709 dwTmp |= (addr & 0x0003FFFF);
717 int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
719 void __iomem *regs = mvi->regs_ex;
722 for (retry = 0; retry < 1; retry++) {
723 iow32(SPI_CTRL_REG_64XX, SPI_CTRL_VENDOR_ENABLE);
724 iow32(SPI_CMD_REG_64XX, cmd);
725 iow32(SPI_CTRL_REG_64XX,
726 SPI_CTRL_VENDOR_ENABLE | SPI_CTRL_SPISTART);
732 int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
734 void __iomem *regs = mvi->regs_ex;
737 for (i = 0; i < timeout; i++) {
738 dwTmp = ior32(SPI_CTRL_REG_64XX);
739 if (!(dwTmp & SPI_CTRL_SPISTART))
747 #ifndef DISABLE_HOTPLUG_DMA_FIX
748 void mvs_64xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
751 struct mvs_prd *buf_prd = prd;
753 for (i = 0; i < MAX_SG_ENTRY - from; i++) {
754 buf_prd->addr = cpu_to_le64(buf_dma);
755 buf_prd->len = cpu_to_le32(buf_len);
761 const struct mvs_dispatch mvs_64xx_dispatch = {
769 mvs_64xx_interrupt_enable,
770 mvs_64xx_interrupt_disable,
773 mvs_read_port_cfg_data,
774 mvs_write_port_cfg_data,
775 mvs_write_port_cfg_addr,
776 mvs_read_port_vsr_data,
777 mvs_write_port_vsr_data,
778 mvs_write_port_vsr_addr,
779 mvs_read_port_irq_stat,
780 mvs_write_port_irq_stat,
781 mvs_read_port_irq_mask,
782 mvs_write_port_irq_mask,
784 mvs_64xx_command_active,
785 mvs_64xx_clear_srs_irq,
790 mvs_64xx_assign_reg_set,
791 mvs_64xx_free_reg_set,
795 mvs_64xx_detect_porttype,
797 mvs_64xx_fix_phy_info,
798 mvs_64xx_phy_work_around,
799 mvs_64xx_phy_set_link_rate,
800 mvs_hw_max_link_rate,
801 mvs_64xx_phy_disable,
805 mvs_64xx_clear_active_cmds,
806 mvs_64xx_spi_read_data,
807 mvs_64xx_spi_write_data,
808 mvs_64xx_spi_buildcmd,
809 mvs_64xx_spi_issuecmd,
810 mvs_64xx_spi_waitdataready,
811 #ifndef DISABLE_HOTPLUG_DMA_FIX