1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2009 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
22 * associated with it (_SHIFT, _MASK, and _WORD).
23 * EG. For a bit field that is in the 7th bit of the "field4" field of a
24 * structure and is 2 bits in size the following #defines must exist:
30 * #define example_bit_field_SHIFT 7
31 * #define example_bit_field_MASK 0x03
32 * #define example_bit_field_WORD field4
35 * Then the macros below may be used to get or set the value of that field.
36 * EG. To get the value of the bit field from the above example:
38 * value = bf_get(example_bit_field, &t1);
39 * And then to set that bit field:
40 * bf_set(example_bit_field, &t1, 2);
41 * Or clear that bit field:
42 * bf_set(example_bit_field, &t1, 0);
44 #define bf_get_be32(name, ptr) \
45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
46 #define bf_get_le32(name, ptr) \
47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
48 #define bf_get(name, ptr) \
49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
50 #define bf_set_le32(name, ptr, value) \
51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
53 ~(name##_MASK << name##_SHIFT)))))
54 #define bf_set(name, ptr, value) \
55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
63 struct lpfc_sli_intf {
65 #define lpfc_sli_intf_valid_SHIFT 29
66 #define lpfc_sli_intf_valid_MASK 0x00000007
67 #define lpfc_sli_intf_valid_WORD word0
68 #define LPFC_SLI_INTF_VALID 6
69 #define lpfc_sli_intf_sli_hint2_SHIFT 24
70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
71 #define lpfc_sli_intf_sli_hint2_WORD word0
72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
73 #define lpfc_sli_intf_sli_hint1_SHIFT 16
74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
75 #define lpfc_sli_intf_sli_hint1_WORD word0
76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
77 #define LPFC_SLI_INTF_SLI_HINT1_1 1
78 #define LPFC_SLI_INTF_SLI_HINT1_2 2
79 #define lpfc_sli_intf_if_type_SHIFT 12
80 #define lpfc_sli_intf_if_type_MASK 0x0000000F
81 #define lpfc_sli_intf_if_type_WORD word0
82 #define LPFC_SLI_INTF_IF_TYPE_0 0
83 #define LPFC_SLI_INTF_IF_TYPE_1 1
84 #define LPFC_SLI_INTF_IF_TYPE_2 2
85 #define lpfc_sli_intf_sli_family_SHIFT 8
86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
87 #define lpfc_sli_intf_sli_family_WORD word0
88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
92 #define lpfc_sli_intf_slirev_SHIFT 4
93 #define lpfc_sli_intf_slirev_MASK 0x0000000F
94 #define lpfc_sli_intf_slirev_WORD word0
95 #define LPFC_SLI_INTF_REV_SLI3 3
96 #define LPFC_SLI_INTF_REV_SLI4 4
97 #define lpfc_sli_intf_func_type_SHIFT 0
98 #define lpfc_sli_intf_func_type_MASK 0x00000001
99 #define lpfc_sli_intf_func_type_WORD word0
100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1
104 #define LPFC_SLI4_MBX_EMBED true
105 #define LPFC_SLI4_MBX_NEMBED false
107 #define LPFC_SLI4_MB_WORD_COUNT 64
108 #define LPFC_MAX_MQ_PAGE 8
109 #define LPFC_MAX_WQ_PAGE 8
110 #define LPFC_MAX_CQ_PAGE 4
111 #define LPFC_MAX_EQ_PAGE 8
113 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
114 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
115 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
117 /* Define SLI4 Alignment requirements. */
118 #define LPFC_ALIGN_16_BYTE 16
119 #define LPFC_ALIGN_64_BYTE 64
121 /* Define SLI4 specific definitions. */
122 #define LPFC_MQ_CQE_BYTE_OFFSET 256
123 #define LPFC_MBX_CMD_HDR_LENGTH 16
124 #define LPFC_MBX_ERROR_RANGE 0x4000
125 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
126 #define LPFC_BMBX_BIT1_ADDR_LO 0
127 #define LPFC_RPI_HDR_COUNT 64
128 #define LPFC_HDR_TEMPLATE_SIZE 4096
129 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
130 #define LPFC_FCF_RECORD_WD_CNT 132
131 #define LPFC_ENTIRE_FCF_DATABASE 0
132 #define LPFC_DFLT_FCF_INDEX 0
134 /* Virtual function numbers */
168 /* PCI function numbers */
169 #define LPFC_PCI_FUNC0 0
170 #define LPFC_PCI_FUNC1 1
171 #define LPFC_PCI_FUNC2 2
172 #define LPFC_PCI_FUNC3 3
173 #define LPFC_PCI_FUNC4 4
175 /* SLI4 interface type-2 PDEV_CTL register */
176 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
177 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
178 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
179 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
180 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
181 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
182 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
183 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
185 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
187 /* Active interrupt test count */
188 #define LPFC_ACT_INTR_CNT 4
190 /* Delay Multiplier constant */
191 #define LPFC_DMULT_CONST 651042
192 #define LPFC_MIM_IMAX 636
193 #define LPFC_FP_DEF_IMAX 10000
194 #define LPFC_SP_DEF_IMAX 10000
196 /* PORT_CAPABILITIES constants. */
197 #define LPFC_MAX_SUPPORTED_PAGES 8
203 #ifdef __BIG_ENDIAN_BITFIELD
204 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
206 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
207 #else /* __LITTLE_ENDIAN_BITFIELD */
208 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
209 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
212 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
213 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
214 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
215 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
216 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
217 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
218 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
225 struct lpfc_sli4_flags {
227 #define lpfc_idx_rsrc_rdy_SHIFT 0
228 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
229 #define lpfc_idx_rsrc_rdy_WORD word0
230 #define LPFC_IDX_RSRC_RDY 1
231 #define lpfc_xri_rsrc_rdy_SHIFT 1
232 #define lpfc_xri_rsrc_rdy_MASK 0x00000001
233 #define lpfc_xri_rsrc_rdy_WORD word0
234 #define LPFC_XRI_RSRC_RDY 1
235 #define lpfc_rpi_rsrc_rdy_SHIFT 2
236 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
237 #define lpfc_rpi_rsrc_rdy_WORD word0
238 #define LPFC_RPI_RSRC_RDY 1
239 #define lpfc_vpi_rsrc_rdy_SHIFT 3
240 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
241 #define lpfc_vpi_rsrc_rdy_WORD word0
242 #define LPFC_VPI_RSRC_RDY 1
243 #define lpfc_vfi_rsrc_rdy_SHIFT 4
244 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
245 #define lpfc_vfi_rsrc_rdy_WORD word0
246 #define LPFC_VFI_RSRC_RDY 1
249 struct sli4_bls_rsp {
250 uint32_t word0_rsvd; /* Word0 must be reserved */
252 #define lpfc_abts_orig_SHIFT 0
253 #define lpfc_abts_orig_MASK 0x00000001
254 #define lpfc_abts_orig_WORD word1
255 #define LPFC_ABTS_UNSOL_RSP 1
256 #define LPFC_ABTS_UNSOL_INT 0
258 #define lpfc_abts_rxid_SHIFT 0
259 #define lpfc_abts_rxid_MASK 0x0000FFFF
260 #define lpfc_abts_rxid_WORD word2
261 #define lpfc_abts_oxid_SHIFT 16
262 #define lpfc_abts_oxid_MASK 0x0000FFFF
263 #define lpfc_abts_oxid_WORD word2
265 #define lpfc_vndr_code_SHIFT 0
266 #define lpfc_vndr_code_MASK 0x000000FF
267 #define lpfc_vndr_code_WORD word3
268 #define lpfc_rsn_expln_SHIFT 8
269 #define lpfc_rsn_expln_MASK 0x000000FF
270 #define lpfc_rsn_expln_WORD word3
271 #define lpfc_rsn_code_SHIFT 16
272 #define lpfc_rsn_code_MASK 0x000000FF
273 #define lpfc_rsn_code_WORD word3
276 uint32_t word5_rsvd; /* Word5 must be reserved */
279 /* event queue entry structure */
282 #define lpfc_eqe_resource_id_SHIFT 16
283 #define lpfc_eqe_resource_id_MASK 0x000000FF
284 #define lpfc_eqe_resource_id_WORD word0
285 #define lpfc_eqe_minor_code_SHIFT 4
286 #define lpfc_eqe_minor_code_MASK 0x00000FFF
287 #define lpfc_eqe_minor_code_WORD word0
288 #define lpfc_eqe_major_code_SHIFT 1
289 #define lpfc_eqe_major_code_MASK 0x00000007
290 #define lpfc_eqe_major_code_WORD word0
291 #define lpfc_eqe_valid_SHIFT 0
292 #define lpfc_eqe_valid_MASK 0x00000001
293 #define lpfc_eqe_valid_WORD word0
296 /* completion queue entry structure (common fields for all cqe types) */
302 #define lpfc_cqe_valid_SHIFT 31
303 #define lpfc_cqe_valid_MASK 0x00000001
304 #define lpfc_cqe_valid_WORD word3
305 #define lpfc_cqe_code_SHIFT 16
306 #define lpfc_cqe_code_MASK 0x000000FF
307 #define lpfc_cqe_code_WORD word3
310 /* Completion Queue Entry Status Codes */
311 #define CQE_STATUS_SUCCESS 0x0
312 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
313 #define CQE_STATUS_REMOTE_STOP 0x2
314 #define CQE_STATUS_LOCAL_REJECT 0x3
315 #define CQE_STATUS_NPORT_RJT 0x4
316 #define CQE_STATUS_FABRIC_RJT 0x5
317 #define CQE_STATUS_NPORT_BSY 0x6
318 #define CQE_STATUS_FABRIC_BSY 0x7
319 #define CQE_STATUS_INTERMED_RSP 0x8
320 #define CQE_STATUS_LS_RJT 0x9
321 #define CQE_STATUS_CMD_REJECT 0xb
322 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
323 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
325 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
326 #define CQE_HW_STATUS_NO_ERR 0x0
327 #define CQE_HW_STATUS_UNDERRUN 0x1
328 #define CQE_HW_STATUS_OVERRUN 0x2
330 /* Completion Queue Entry Codes */
331 #define CQE_CODE_COMPL_WQE 0x1
332 #define CQE_CODE_RELEASE_WQE 0x2
333 #define CQE_CODE_RECEIVE 0x4
334 #define CQE_CODE_XRI_ABORTED 0x5
335 #define CQE_CODE_RECEIVE_V1 0x9
337 /* completion queue entry for wqe completions */
338 struct lpfc_wcqe_complete {
340 #define lpfc_wcqe_c_request_tag_SHIFT 16
341 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
342 #define lpfc_wcqe_c_request_tag_WORD word0
343 #define lpfc_wcqe_c_status_SHIFT 8
344 #define lpfc_wcqe_c_status_MASK 0x000000FF
345 #define lpfc_wcqe_c_status_WORD word0
346 #define lpfc_wcqe_c_hw_status_SHIFT 0
347 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
348 #define lpfc_wcqe_c_hw_status_WORD word0
349 uint32_t total_data_placed;
352 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
353 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
354 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
355 #define lpfc_wcqe_c_xb_SHIFT 28
356 #define lpfc_wcqe_c_xb_MASK 0x00000001
357 #define lpfc_wcqe_c_xb_WORD word3
358 #define lpfc_wcqe_c_pv_SHIFT 27
359 #define lpfc_wcqe_c_pv_MASK 0x00000001
360 #define lpfc_wcqe_c_pv_WORD word3
361 #define lpfc_wcqe_c_priority_SHIFT 24
362 #define lpfc_wcqe_c_priority_MASK 0x00000007
363 #define lpfc_wcqe_c_priority_WORD word3
364 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
365 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
366 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
369 /* completion queue entry for wqe release */
370 struct lpfc_wcqe_release {
374 #define lpfc_wcqe_r_wq_id_SHIFT 16
375 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
376 #define lpfc_wcqe_r_wq_id_WORD word2
377 #define lpfc_wcqe_r_wqe_index_SHIFT 0
378 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
379 #define lpfc_wcqe_r_wqe_index_WORD word2
381 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
382 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
383 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
384 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
385 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
386 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
389 struct sli4_wcqe_xri_aborted {
391 #define lpfc_wcqe_xa_status_SHIFT 8
392 #define lpfc_wcqe_xa_status_MASK 0x000000FF
393 #define lpfc_wcqe_xa_status_WORD word0
396 #define lpfc_wcqe_xa_remote_xid_SHIFT 16
397 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
398 #define lpfc_wcqe_xa_remote_xid_WORD word2
399 #define lpfc_wcqe_xa_xri_SHIFT 0
400 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
401 #define lpfc_wcqe_xa_xri_WORD word2
403 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
404 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
405 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
406 #define lpfc_wcqe_xa_ia_SHIFT 30
407 #define lpfc_wcqe_xa_ia_MASK 0x00000001
408 #define lpfc_wcqe_xa_ia_WORD word3
409 #define CQE_XRI_ABORTED_IA_REMOTE 0
410 #define CQE_XRI_ABORTED_IA_LOCAL 1
411 #define lpfc_wcqe_xa_br_SHIFT 29
412 #define lpfc_wcqe_xa_br_MASK 0x00000001
413 #define lpfc_wcqe_xa_br_WORD word3
414 #define CQE_XRI_ABORTED_BR_BA_ACC 0
415 #define CQE_XRI_ABORTED_BR_BA_RJT 1
416 #define lpfc_wcqe_xa_eo_SHIFT 28
417 #define lpfc_wcqe_xa_eo_MASK 0x00000001
418 #define lpfc_wcqe_xa_eo_WORD word3
419 #define CQE_XRI_ABORTED_EO_REMOTE 0
420 #define CQE_XRI_ABORTED_EO_LOCAL 1
421 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
422 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
423 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
426 /* completion queue entry structure for rqe completion */
429 #define lpfc_rcqe_bindex_SHIFT 16
430 #define lpfc_rcqe_bindex_MASK 0x0000FFF
431 #define lpfc_rcqe_bindex_WORD word0
432 #define lpfc_rcqe_status_SHIFT 8
433 #define lpfc_rcqe_status_MASK 0x000000FF
434 #define lpfc_rcqe_status_WORD word0
435 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
436 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
437 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
438 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
440 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
441 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
442 #define lpfc_rcqe_fcf_id_v1_WORD word1
444 #define lpfc_rcqe_length_SHIFT 16
445 #define lpfc_rcqe_length_MASK 0x0000FFFF
446 #define lpfc_rcqe_length_WORD word2
447 #define lpfc_rcqe_rq_id_SHIFT 6
448 #define lpfc_rcqe_rq_id_MASK 0x000003FF
449 #define lpfc_rcqe_rq_id_WORD word2
450 #define lpfc_rcqe_fcf_id_SHIFT 0
451 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
452 #define lpfc_rcqe_fcf_id_WORD word2
453 #define lpfc_rcqe_rq_id_v1_SHIFT 0
454 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
455 #define lpfc_rcqe_rq_id_v1_WORD word2
457 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
458 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
459 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
460 #define lpfc_rcqe_port_SHIFT 30
461 #define lpfc_rcqe_port_MASK 0x00000001
462 #define lpfc_rcqe_port_WORD word3
463 #define lpfc_rcqe_hdr_length_SHIFT 24
464 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
465 #define lpfc_rcqe_hdr_length_WORD word3
466 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
467 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
468 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
469 #define lpfc_rcqe_eof_SHIFT 8
470 #define lpfc_rcqe_eof_MASK 0x000000FF
471 #define lpfc_rcqe_eof_WORD word3
472 #define FCOE_EOFn 0x41
473 #define FCOE_EOFt 0x42
474 #define FCOE_EOFni 0x49
475 #define FCOE_EOFa 0x50
476 #define lpfc_rcqe_sof_SHIFT 0
477 #define lpfc_rcqe_sof_MASK 0x000000FF
478 #define lpfc_rcqe_sof_WORD word3
479 #define FCOE_SOFi2 0x2d
480 #define FCOE_SOFi3 0x2e
481 #define FCOE_SOFn2 0x35
482 #define FCOE_SOFn3 0x36
490 /* buffer descriptors */
495 #define lpfc_bde4_last_SHIFT 31
496 #define lpfc_bde4_last_MASK 0x00000001
497 #define lpfc_bde4_last_WORD word2
498 #define lpfc_bde4_sge_offset_SHIFT 0
499 #define lpfc_bde4_sge_offset_MASK 0x000003FF
500 #define lpfc_bde4_sge_offset_WORD word2
502 #define lpfc_bde4_length_SHIFT 0
503 #define lpfc_bde4_length_MASK 0x000000FF
504 #define lpfc_bde4_length_WORD word3
507 struct lpfc_register {
511 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
512 #define LPFC_UERR_STATUS_HI 0x00A4
513 #define LPFC_UERR_STATUS_LO 0x00A0
514 #define LPFC_UE_MASK_HI 0x00AC
515 #define LPFC_UE_MASK_LO 0x00A8
517 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
518 #define LPFC_SLI_INTF 0x0058
520 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
521 #define lpfc_port_smphr_perr_SHIFT 31
522 #define lpfc_port_smphr_perr_MASK 0x1
523 #define lpfc_port_smphr_perr_WORD word0
524 #define lpfc_port_smphr_sfi_SHIFT 30
525 #define lpfc_port_smphr_sfi_MASK 0x1
526 #define lpfc_port_smphr_sfi_WORD word0
527 #define lpfc_port_smphr_nip_SHIFT 29
528 #define lpfc_port_smphr_nip_MASK 0x1
529 #define lpfc_port_smphr_nip_WORD word0
530 #define lpfc_port_smphr_ipc_SHIFT 28
531 #define lpfc_port_smphr_ipc_MASK 0x1
532 #define lpfc_port_smphr_ipc_WORD word0
533 #define lpfc_port_smphr_scr1_SHIFT 27
534 #define lpfc_port_smphr_scr1_MASK 0x1
535 #define lpfc_port_smphr_scr1_WORD word0
536 #define lpfc_port_smphr_scr2_SHIFT 26
537 #define lpfc_port_smphr_scr2_MASK 0x1
538 #define lpfc_port_smphr_scr2_WORD word0
539 #define lpfc_port_smphr_host_scratch_SHIFT 16
540 #define lpfc_port_smphr_host_scratch_MASK 0xFF
541 #define lpfc_port_smphr_host_scratch_WORD word0
542 #define lpfc_port_smphr_port_status_SHIFT 0
543 #define lpfc_port_smphr_port_status_MASK 0xFFFF
544 #define lpfc_port_smphr_port_status_WORD word0
546 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
547 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
548 #define LPFC_POST_STAGE_HOST_RDY 0x0002
549 #define LPFC_POST_STAGE_BE_RESET 0x0003
550 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
551 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
552 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
553 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
554 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
555 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
556 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
557 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
558 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
559 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
560 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
561 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
562 #define LPFC_POST_STAGE_ARMFW_START 0x0800
563 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
564 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
565 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
566 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
567 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
568 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
569 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
570 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
571 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
572 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
573 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
574 #define LPFC_POST_STAGE_RC_DONE 0x0B07
575 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
576 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
577 #define LPFC_POST_STAGE_PORT_READY 0xC000
578 #define LPFC_POST_STAGE_PORT_UE 0xF000
580 #define LPFC_CTL_PORT_STA_OFFSET 0x404
581 #define lpfc_sliport_status_err_SHIFT 31
582 #define lpfc_sliport_status_err_MASK 0x1
583 #define lpfc_sliport_status_err_WORD word0
584 #define lpfc_sliport_status_end_SHIFT 30
585 #define lpfc_sliport_status_end_MASK 0x1
586 #define lpfc_sliport_status_end_WORD word0
587 #define lpfc_sliport_status_oti_SHIFT 29
588 #define lpfc_sliport_status_oti_MASK 0x1
589 #define lpfc_sliport_status_oti_WORD word0
590 #define lpfc_sliport_status_rn_SHIFT 24
591 #define lpfc_sliport_status_rn_MASK 0x1
592 #define lpfc_sliport_status_rn_WORD word0
593 #define lpfc_sliport_status_rdy_SHIFT 23
594 #define lpfc_sliport_status_rdy_MASK 0x1
595 #define lpfc_sliport_status_rdy_WORD word0
596 #define MAX_IF_TYPE_2_RESETS 1000
598 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
599 #define lpfc_sliport_ctrl_end_SHIFT 30
600 #define lpfc_sliport_ctrl_end_MASK 0x1
601 #define lpfc_sliport_ctrl_end_WORD word0
602 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
603 #define LPFC_SLIPORT_BIG_ENDIAN 1
604 #define lpfc_sliport_ctrl_ip_SHIFT 27
605 #define lpfc_sliport_ctrl_ip_MASK 0x1
606 #define lpfc_sliport_ctrl_ip_WORD word0
607 #define LPFC_SLIPORT_INIT_PORT 1
609 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
610 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
612 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
615 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
617 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
618 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
620 #define LPFC_HST_ISR0 0x0C18
621 #define LPFC_HST_ISR1 0x0C1C
622 #define LPFC_HST_ISR2 0x0C20
623 #define LPFC_HST_ISR3 0x0C24
624 #define LPFC_HST_ISR4 0x0C28
626 #define LPFC_HST_IMR0 0x0C48
627 #define LPFC_HST_IMR1 0x0C4C
628 #define LPFC_HST_IMR2 0x0C50
629 #define LPFC_HST_IMR3 0x0C54
630 #define LPFC_HST_IMR4 0x0C58
632 #define LPFC_HST_ISCR0 0x0C78
633 #define LPFC_HST_ISCR1 0x0C7C
634 #define LPFC_HST_ISCR2 0x0C80
635 #define LPFC_HST_ISCR3 0x0C84
636 #define LPFC_HST_ISCR4 0x0C88
638 #define LPFC_SLI4_INTR0 BIT0
639 #define LPFC_SLI4_INTR1 BIT1
640 #define LPFC_SLI4_INTR2 BIT2
641 #define LPFC_SLI4_INTR3 BIT3
642 #define LPFC_SLI4_INTR4 BIT4
643 #define LPFC_SLI4_INTR5 BIT5
644 #define LPFC_SLI4_INTR6 BIT6
645 #define LPFC_SLI4_INTR7 BIT7
646 #define LPFC_SLI4_INTR8 BIT8
647 #define LPFC_SLI4_INTR9 BIT9
648 #define LPFC_SLI4_INTR10 BIT10
649 #define LPFC_SLI4_INTR11 BIT11
650 #define LPFC_SLI4_INTR12 BIT12
651 #define LPFC_SLI4_INTR13 BIT13
652 #define LPFC_SLI4_INTR14 BIT14
653 #define LPFC_SLI4_INTR15 BIT15
654 #define LPFC_SLI4_INTR16 BIT16
655 #define LPFC_SLI4_INTR17 BIT17
656 #define LPFC_SLI4_INTR18 BIT18
657 #define LPFC_SLI4_INTR19 BIT19
658 #define LPFC_SLI4_INTR20 BIT20
659 #define LPFC_SLI4_INTR21 BIT21
660 #define LPFC_SLI4_INTR22 BIT22
661 #define LPFC_SLI4_INTR23 BIT23
662 #define LPFC_SLI4_INTR24 BIT24
663 #define LPFC_SLI4_INTR25 BIT25
664 #define LPFC_SLI4_INTR26 BIT26
665 #define LPFC_SLI4_INTR27 BIT27
666 #define LPFC_SLI4_INTR28 BIT28
667 #define LPFC_SLI4_INTR29 BIT29
668 #define LPFC_SLI4_INTR30 BIT30
669 #define LPFC_SLI4_INTR31 BIT31
672 * The Doorbell registers defined here exist in different BAR
673 * register sets depending on the UCNA Port's reported if_type
674 * value. For UCNA ports running SLI4 and if_type 0, they reside in
675 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
676 * BAR0. The offsets are the same so the driver must account for
677 * any base address difference.
679 #define LPFC_RQ_DOORBELL 0x00A0
680 #define lpfc_rq_doorbell_num_posted_SHIFT 16
681 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF
682 #define lpfc_rq_doorbell_num_posted_WORD word0
683 #define lpfc_rq_doorbell_id_SHIFT 0
684 #define lpfc_rq_doorbell_id_MASK 0xFFFF
685 #define lpfc_rq_doorbell_id_WORD word0
687 #define LPFC_WQ_DOORBELL 0x0040
688 #define lpfc_wq_doorbell_num_posted_SHIFT 24
689 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF
690 #define lpfc_wq_doorbell_num_posted_WORD word0
691 #define lpfc_wq_doorbell_index_SHIFT 16
692 #define lpfc_wq_doorbell_index_MASK 0x00FF
693 #define lpfc_wq_doorbell_index_WORD word0
694 #define lpfc_wq_doorbell_id_SHIFT 0
695 #define lpfc_wq_doorbell_id_MASK 0xFFFF
696 #define lpfc_wq_doorbell_id_WORD word0
698 #define LPFC_EQCQ_DOORBELL 0x0120
699 #define lpfc_eqcq_doorbell_se_SHIFT 31
700 #define lpfc_eqcq_doorbell_se_MASK 0x0001
701 #define lpfc_eqcq_doorbell_se_WORD word0
702 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
703 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
704 #define lpfc_eqcq_doorbell_arm_SHIFT 29
705 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
706 #define lpfc_eqcq_doorbell_arm_WORD word0
707 #define lpfc_eqcq_doorbell_num_released_SHIFT 16
708 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
709 #define lpfc_eqcq_doorbell_num_released_WORD word0
710 #define lpfc_eqcq_doorbell_qt_SHIFT 10
711 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
712 #define lpfc_eqcq_doorbell_qt_WORD word0
713 #define LPFC_QUEUE_TYPE_COMPLETION 0
714 #define LPFC_QUEUE_TYPE_EVENT 1
715 #define lpfc_eqcq_doorbell_eqci_SHIFT 9
716 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
717 #define lpfc_eqcq_doorbell_eqci_WORD word0
718 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
719 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
720 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0
721 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11
722 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
723 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0
724 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
725 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
726 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0
727 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11
728 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
729 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0
730 #define LPFC_CQID_HI_FIELD_SHIFT 10
731 #define LPFC_EQID_HI_FIELD_SHIFT 9
733 #define LPFC_BMBX 0x0160
734 #define lpfc_bmbx_addr_SHIFT 2
735 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
736 #define lpfc_bmbx_addr_WORD word0
737 #define lpfc_bmbx_hi_SHIFT 1
738 #define lpfc_bmbx_hi_MASK 0x0001
739 #define lpfc_bmbx_hi_WORD word0
740 #define lpfc_bmbx_rdy_SHIFT 0
741 #define lpfc_bmbx_rdy_MASK 0x0001
742 #define lpfc_bmbx_rdy_WORD word0
744 #define LPFC_MQ_DOORBELL 0x0140
745 #define lpfc_mq_doorbell_num_posted_SHIFT 16
746 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
747 #define lpfc_mq_doorbell_num_posted_WORD word0
748 #define lpfc_mq_doorbell_id_SHIFT 0
749 #define lpfc_mq_doorbell_id_MASK 0xFFFF
750 #define lpfc_mq_doorbell_id_WORD word0
752 struct lpfc_sli4_cfg_mhdr {
754 #define lpfc_mbox_hdr_emb_SHIFT 0
755 #define lpfc_mbox_hdr_emb_MASK 0x00000001
756 #define lpfc_mbox_hdr_emb_WORD word1
757 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3
758 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
759 #define lpfc_mbox_hdr_sge_cnt_WORD word1
760 uint32_t payload_length;
766 union lpfc_sli4_cfg_shdr {
769 #define lpfc_mbox_hdr_opcode_SHIFT 0
770 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
771 #define lpfc_mbox_hdr_opcode_WORD word6
772 #define lpfc_mbox_hdr_subsystem_SHIFT 8
773 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
774 #define lpfc_mbox_hdr_subsystem_WORD word6
775 #define lpfc_mbox_hdr_port_number_SHIFT 16
776 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
777 #define lpfc_mbox_hdr_port_number_WORD word6
778 #define lpfc_mbox_hdr_domain_SHIFT 24
779 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
780 #define lpfc_mbox_hdr_domain_WORD word6
782 uint32_t request_length;
784 #define lpfc_mbox_hdr_version_SHIFT 0
785 #define lpfc_mbox_hdr_version_MASK 0x000000FF
786 #define lpfc_mbox_hdr_version_WORD word9
787 #define lpfc_mbox_hdr_pf_num_SHIFT 16
788 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
789 #define lpfc_mbox_hdr_pf_num_WORD word9
790 #define lpfc_mbox_hdr_vh_num_SHIFT 24
791 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
792 #define lpfc_mbox_hdr_vh_num_WORD word9
793 #define LPFC_Q_CREATE_VERSION_2 2
794 #define LPFC_Q_CREATE_VERSION_1 1
795 #define LPFC_Q_CREATE_VERSION_0 0
796 #define LPFC_OPCODE_VERSION_0 0
797 #define LPFC_OPCODE_VERSION_1 1
801 #define lpfc_mbox_hdr_opcode_SHIFT 0
802 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
803 #define lpfc_mbox_hdr_opcode_WORD word6
804 #define lpfc_mbox_hdr_subsystem_SHIFT 8
805 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
806 #define lpfc_mbox_hdr_subsystem_WORD word6
807 #define lpfc_mbox_hdr_domain_SHIFT 24
808 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
809 #define lpfc_mbox_hdr_domain_WORD word6
811 #define lpfc_mbox_hdr_status_SHIFT 0
812 #define lpfc_mbox_hdr_status_MASK 0x000000FF
813 #define lpfc_mbox_hdr_status_WORD word7
814 #define lpfc_mbox_hdr_add_status_SHIFT 8
815 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
816 #define lpfc_mbox_hdr_add_status_WORD word7
817 uint32_t response_length;
818 uint32_t actual_response_length;
822 /* Mailbox Header structures.
823 * struct mbox_header is defined for first generation SLI4_CFG mailbox
824 * calls deployed for BE-based ports.
826 * struct sli4_mbox_header is defined for second generation SLI4
827 * ports that don't deploy the SLI4_CFG mechanism.
830 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
831 union lpfc_sli4_cfg_shdr cfg_shdr;
834 #define LPFC_EXTENT_LOCAL 0
835 #define LPFC_TIMEOUT_DEFAULT 0
836 #define LPFC_EXTENT_VERSION_DEFAULT 0
838 /* Subsystem Definitions */
839 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
840 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
841 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
843 /* Device Specific Definitions */
845 /* The HOST ENDIAN defines are in Big Endian format. */
846 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
847 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
850 #define LPFC_MBOX_OPCODE_NA 0x00
851 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
852 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
853 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
854 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
855 #define LPFC_MBOX_OPCODE_NOP 0x21
856 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
857 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
858 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
859 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
860 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
861 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
862 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
863 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
864 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
865 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
866 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
867 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
868 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
869 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
870 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
871 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
872 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
873 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
874 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
875 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
876 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
877 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
880 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
881 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
882 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
883 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
884 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
885 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
886 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
887 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
888 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
889 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
890 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
891 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
892 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
893 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
895 /* Mailbox command structures */
898 #define lpfc_eq_context_size_SHIFT 31
899 #define lpfc_eq_context_size_MASK 0x00000001
900 #define lpfc_eq_context_size_WORD word0
901 #define LPFC_EQE_SIZE_4 0x0
902 #define LPFC_EQE_SIZE_16 0x1
903 #define lpfc_eq_context_valid_SHIFT 29
904 #define lpfc_eq_context_valid_MASK 0x00000001
905 #define lpfc_eq_context_valid_WORD word0
907 #define lpfc_eq_context_count_SHIFT 26
908 #define lpfc_eq_context_count_MASK 0x00000003
909 #define lpfc_eq_context_count_WORD word1
910 #define LPFC_EQ_CNT_256 0x0
911 #define LPFC_EQ_CNT_512 0x1
912 #define LPFC_EQ_CNT_1024 0x2
913 #define LPFC_EQ_CNT_2048 0x3
914 #define LPFC_EQ_CNT_4096 0x4
916 #define lpfc_eq_context_delay_multi_SHIFT 13
917 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
918 #define lpfc_eq_context_delay_multi_WORD word2
922 struct sgl_page_pairs {
923 uint32_t sgl_pg0_addr_lo;
924 uint32_t sgl_pg0_addr_hi;
925 uint32_t sgl_pg1_addr_lo;
926 uint32_t sgl_pg1_addr_hi;
929 struct lpfc_mbx_post_sgl_pages {
930 struct mbox_header header;
932 #define lpfc_post_sgl_pages_xri_SHIFT 0
933 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
934 #define lpfc_post_sgl_pages_xri_WORD word0
935 #define lpfc_post_sgl_pages_xricnt_SHIFT 16
936 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
937 #define lpfc_post_sgl_pages_xricnt_WORD word0
938 struct sgl_page_pairs sgl_pg_pairs[1];
941 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
942 struct lpfc_mbx_post_uembed_sgl_page1 {
943 union lpfc_sli4_cfg_shdr cfg_shdr;
945 struct sgl_page_pairs sgl_pg_pairs;
948 struct lpfc_mbx_sge {
954 struct lpfc_mbx_nembed_cmd {
955 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
956 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
957 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
960 struct lpfc_mbx_nembed_sge_virt {
961 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
964 struct lpfc_mbx_eq_create {
965 struct mbox_header header;
969 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
970 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
971 #define lpfc_mbx_eq_create_num_pages_WORD word0
972 struct eq_context context;
973 struct dma_address page[LPFC_MAX_EQ_PAGE];
977 #define lpfc_mbx_eq_create_q_id_SHIFT 0
978 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
979 #define lpfc_mbx_eq_create_q_id_WORD word0
984 struct lpfc_mbx_eq_destroy {
985 struct mbox_header header;
989 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
990 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
991 #define lpfc_mbx_eq_destroy_q_id_WORD word0
999 struct lpfc_mbx_nop {
1000 struct mbox_header header;
1001 uint32_t context[2];
1006 #define lpfc_cq_context_event_SHIFT 31
1007 #define lpfc_cq_context_event_MASK 0x00000001
1008 #define lpfc_cq_context_event_WORD word0
1009 #define lpfc_cq_context_valid_SHIFT 29
1010 #define lpfc_cq_context_valid_MASK 0x00000001
1011 #define lpfc_cq_context_valid_WORD word0
1012 #define lpfc_cq_context_count_SHIFT 27
1013 #define lpfc_cq_context_count_MASK 0x00000003
1014 #define lpfc_cq_context_count_WORD word0
1015 #define LPFC_CQ_CNT_256 0x0
1016 #define LPFC_CQ_CNT_512 0x1
1017 #define LPFC_CQ_CNT_1024 0x2
1019 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1020 #define lpfc_cq_eq_id_MASK 0x000000FF
1021 #define lpfc_cq_eq_id_WORD word1
1022 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1023 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1024 #define lpfc_cq_eq_id_2_WORD word1
1029 struct lpfc_mbx_cq_create {
1030 struct mbox_header header;
1034 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */
1035 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1036 #define lpfc_mbx_cq_create_page_size_WORD word0
1037 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1038 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1039 #define lpfc_mbx_cq_create_num_pages_WORD word0
1040 struct cq_context context;
1041 struct dma_address page[LPFC_MAX_CQ_PAGE];
1045 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1046 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1047 #define lpfc_mbx_cq_create_q_id_WORD word0
1052 struct lpfc_mbx_cq_destroy {
1053 struct mbox_header header;
1057 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1058 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1059 #define lpfc_mbx_cq_destroy_q_id_WORD word0
1074 struct lpfc_mbx_wq_create {
1075 struct mbox_header header;
1077 struct { /* Version 0 Request */
1079 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1080 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF
1081 #define lpfc_mbx_wq_create_num_pages_WORD word0
1082 #define lpfc_mbx_wq_create_cq_id_SHIFT 16
1083 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1084 #define lpfc_mbx_wq_create_cq_id_WORD word0
1085 struct dma_address page[LPFC_MAX_WQ_PAGE];
1087 struct { /* Version 1 Request */
1088 uint32_t word0; /* Word 0 is the same as in v0 */
1090 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1091 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1092 #define lpfc_mbx_wq_create_page_size_WORD word1
1093 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8
1094 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1095 #define lpfc_mbx_wq_create_wqe_size_WORD word1
1096 #define LPFC_WQ_WQE_SIZE_64 0x5
1097 #define LPFC_WQ_WQE_SIZE_128 0x6
1098 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16
1099 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1100 #define lpfc_mbx_wq_create_wqe_count_WORD word1
1102 struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1106 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1107 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1108 #define lpfc_mbx_wq_create_q_id_WORD word0
1113 struct lpfc_mbx_wq_destroy {
1114 struct mbox_header header;
1118 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1119 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1120 #define lpfc_mbx_wq_destroy_q_id_WORD word0
1128 #define LPFC_HDR_BUF_SIZE 128
1129 #define LPFC_DATA_BUF_SIZE 2048
1132 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1133 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1134 #define lpfc_rq_context_rqe_count_WORD word0
1135 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1136 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1137 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1138 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1139 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */
1140 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1141 #define lpfc_rq_context_rqe_count_1_WORD word0
1142 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */
1143 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1144 #define lpfc_rq_context_rqe_size_WORD word0
1145 #define LPFC_RQE_SIZE_8 2
1146 #define LPFC_RQE_SIZE_16 3
1147 #define LPFC_RQE_SIZE_32 4
1148 #define LPFC_RQE_SIZE_64 5
1149 #define LPFC_RQE_SIZE_128 6
1150 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1151 #define lpfc_rq_context_page_size_MASK 0x000000FF
1152 #define lpfc_rq_context_page_size_WORD word0
1155 #define lpfc_rq_context_cq_id_SHIFT 16
1156 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1157 #define lpfc_rq_context_cq_id_WORD word2
1158 #define lpfc_rq_context_buf_size_SHIFT 0
1159 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1160 #define lpfc_rq_context_buf_size_WORD word2
1161 uint32_t buffer_size; /* Version 1 Only */
1164 struct lpfc_mbx_rq_create {
1165 struct mbox_header header;
1169 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1170 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1171 #define lpfc_mbx_rq_create_num_pages_WORD word0
1172 struct rq_context context;
1173 struct dma_address page[LPFC_MAX_WQ_PAGE];
1177 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1178 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1179 #define lpfc_mbx_rq_create_q_id_WORD word0
1184 struct lpfc_mbx_rq_destroy {
1185 struct mbox_header header;
1189 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1190 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1191 #define lpfc_mbx_rq_destroy_q_id_WORD word0
1201 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1202 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1203 #define lpfc_mq_context_cq_id_WORD word0
1204 #define lpfc_mq_context_ring_size_SHIFT 16
1205 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1206 #define lpfc_mq_context_ring_size_WORD word0
1207 #define LPFC_MQ_RING_SIZE_16 0x5
1208 #define LPFC_MQ_RING_SIZE_32 0x6
1209 #define LPFC_MQ_RING_SIZE_64 0x7
1210 #define LPFC_MQ_RING_SIZE_128 0x8
1212 #define lpfc_mq_context_valid_SHIFT 31
1213 #define lpfc_mq_context_valid_MASK 0x00000001
1214 #define lpfc_mq_context_valid_WORD word1
1219 struct lpfc_mbx_mq_create {
1220 struct mbox_header header;
1224 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1225 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1226 #define lpfc_mbx_mq_create_num_pages_WORD word0
1227 struct mq_context context;
1228 struct dma_address page[LPFC_MAX_MQ_PAGE];
1232 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1233 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1234 #define lpfc_mbx_mq_create_q_id_WORD word0
1239 struct lpfc_mbx_mq_create_ext {
1240 struct mbox_header header;
1244 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1245 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1246 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0
1247 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */
1248 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1249 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0
1250 uint32_t async_evt_bmap;
1251 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1252 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1253 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1254 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1255 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1256 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1257 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1258 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1259 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1260 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1261 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1262 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1263 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1264 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1265 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1266 struct mq_context context;
1267 struct dma_address page[LPFC_MAX_MQ_PAGE];
1271 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1272 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1273 #define lpfc_mbx_mq_create_q_id_WORD word0
1276 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1277 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1278 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1281 struct lpfc_mbx_mq_destroy {
1282 struct mbox_header header;
1286 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1287 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1288 #define lpfc_mbx_mq_destroy_q_id_WORD word0
1296 /* Start Gen 2 SLI4 Mailbox definitions: */
1298 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1299 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1300 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1301 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1302 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1304 struct lpfc_mbx_get_rsrc_extent_info {
1305 struct mbox_header header;
1309 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1310 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1311 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4
1315 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1316 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1317 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4
1318 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16
1319 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1320 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4
1325 struct lpfc_id_range {
1327 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1328 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1329 #define lpfc_mbx_rsrc_id_word4_0_WORD word5
1330 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16
1331 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1332 #define lpfc_mbx_rsrc_id_word4_1_WORD word5
1335 struct lpfc_mbx_set_link_diag_state {
1336 struct mbox_header header;
1340 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1341 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1342 #define lpfc_mbx_set_diag_state_diag_WORD word0
1343 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16
1344 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1345 #define lpfc_mbx_set_diag_state_link_num_WORD word0
1346 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1347 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1348 #define lpfc_mbx_set_diag_state_link_type_WORD word0
1356 struct lpfc_mbx_set_link_diag_loopback {
1357 struct mbox_header header;
1361 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1362 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1363 #define lpfc_mbx_set_diag_lpbk_type_WORD word0
1364 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1365 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1366 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1367 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16
1368 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1369 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0
1370 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22
1371 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1372 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0
1380 struct lpfc_mbx_run_link_diag_test {
1381 struct mbox_header header;
1385 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16
1386 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1387 #define lpfc_mbx_run_diag_test_link_num_WORD word0
1388 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22
1389 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1390 #define lpfc_mbx_run_diag_test_link_type_WORD word0
1392 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1393 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1394 #define lpfc_mbx_run_diag_test_test_id_WORD word1
1395 #define lpfc_mbx_run_diag_test_loops_SHIFT 16
1396 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1397 #define lpfc_mbx_run_diag_test_loops_WORD word1
1399 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1400 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1401 #define lpfc_mbx_run_diag_test_test_ver_WORD word2
1402 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16
1403 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1404 #define lpfc_mbx_run_diag_test_err_act_WORD word2
1413 * struct lpfc_mbx_alloc_rsrc_extents:
1414 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1415 * 6 words of header + 4 words of shared subcommand header +
1416 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1418 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1419 * for extents payload.
1421 * 212/2 (bytes per extent) = 106 extents.
1422 * 106/2 (extents per word) = 53 words.
1423 * lpfc_id_range id is statically size to 53.
1425 * This mailbox definition is used for ALLOC or GET_ALLOCATED
1426 * extent ranges. For ALLOC, the type and cnt are required.
1427 * For GET_ALLOCATED, only the type is required.
1429 struct lpfc_mbx_alloc_rsrc_extents {
1430 struct mbox_header header;
1434 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1435 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1436 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4
1437 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16
1438 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1439 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4
1443 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1444 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
1445 #define lpfc_mbx_rsrc_cnt_WORD word4
1446 struct lpfc_id_range id[53];
1452 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1453 * structure shares the same SHIFT/MASK/WORD defines provided in the
1454 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1455 * the structures defined above. This non-embedded structure provides for the
1456 * maximum number of extents supported by the port.
1458 struct lpfc_mbx_nembed_rsrc_extent {
1459 union lpfc_sli4_cfg_shdr cfg_shdr;
1461 struct lpfc_id_range id;
1464 struct lpfc_mbx_dealloc_rsrc_extents {
1465 struct mbox_header header;
1468 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
1469 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
1470 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4
1475 /* Start SLI4 FCoE specific mbox structures. */
1477 struct lpfc_mbx_post_hdr_tmpl {
1478 struct mbox_header header;
1480 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1481 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1482 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
1483 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
1484 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1485 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
1486 uint32_t rpi_paddr_lo;
1487 uint32_t rpi_paddr_hi;
1490 struct sli4_sge { /* SLI-4 */
1495 #define lpfc_sli4_sge_offset_SHIFT 0
1496 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
1497 #define lpfc_sli4_sge_offset_WORD word2
1498 #define lpfc_sli4_sge_type_SHIFT 27
1499 #define lpfc_sli4_sge_type_MASK 0x0000000F
1500 #define lpfc_sli4_sge_type_WORD word2
1501 #define LPFC_SGE_TYPE_DATA 0x0
1502 #define LPFC_SGE_TYPE_DIF 0x4
1503 #define LPFC_SGE_TYPE_LSP 0x5
1504 #define LPFC_SGE_TYPE_PEDIF 0x6
1505 #define LPFC_SGE_TYPE_PESEED 0x7
1506 #define LPFC_SGE_TYPE_DISEED 0x8
1507 #define LPFC_SGE_TYPE_ENC 0x9
1508 #define LPFC_SGE_TYPE_ATM 0xA
1509 #define LPFC_SGE_TYPE_SKIP 0xC
1510 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */
1511 #define lpfc_sli4_sge_last_MASK 0x00000001
1512 #define lpfc_sli4_sge_last_WORD word2
1516 struct sli4_sge_diseed { /* SLI-4 */
1518 uint32_t ref_tag_tran;
1521 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
1522 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
1523 #define lpfc_sli4_sge_dif_apptran_WORD word2
1524 #define lpfc_sli4_sge_dif_af_SHIFT 24
1525 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
1526 #define lpfc_sli4_sge_dif_af_WORD word2
1527 #define lpfc_sli4_sge_dif_na_SHIFT 25
1528 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
1529 #define lpfc_sli4_sge_dif_na_WORD word2
1530 #define lpfc_sli4_sge_dif_hi_SHIFT 26
1531 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
1532 #define lpfc_sli4_sge_dif_hi_WORD word2
1533 #define lpfc_sli4_sge_dif_type_SHIFT 27
1534 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
1535 #define lpfc_sli4_sge_dif_type_WORD word2
1536 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */
1537 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
1538 #define lpfc_sli4_sge_dif_last_WORD word2
1540 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
1541 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
1542 #define lpfc_sli4_sge_dif_apptag_WORD word3
1543 #define lpfc_sli4_sge_dif_bs_SHIFT 16
1544 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
1545 #define lpfc_sli4_sge_dif_bs_WORD word3
1546 #define lpfc_sli4_sge_dif_ai_SHIFT 19
1547 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
1548 #define lpfc_sli4_sge_dif_ai_WORD word3
1549 #define lpfc_sli4_sge_dif_me_SHIFT 20
1550 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
1551 #define lpfc_sli4_sge_dif_me_WORD word3
1552 #define lpfc_sli4_sge_dif_re_SHIFT 21
1553 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
1554 #define lpfc_sli4_sge_dif_re_WORD word3
1555 #define lpfc_sli4_sge_dif_ce_SHIFT 22
1556 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
1557 #define lpfc_sli4_sge_dif_ce_WORD word3
1558 #define lpfc_sli4_sge_dif_nr_SHIFT 23
1559 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
1560 #define lpfc_sli4_sge_dif_nr_WORD word3
1561 #define lpfc_sli4_sge_dif_oprx_SHIFT 24
1562 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
1563 #define lpfc_sli4_sge_dif_oprx_WORD word3
1564 #define lpfc_sli4_sge_dif_optx_SHIFT 28
1565 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
1566 #define lpfc_sli4_sge_dif_optx_WORD word3
1567 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
1571 uint32_t max_rcv_size;
1572 uint32_t fka_adv_period;
1573 uint32_t fip_priority;
1575 #define lpfc_fcf_record_mac_0_SHIFT 0
1576 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
1577 #define lpfc_fcf_record_mac_0_WORD word3
1578 #define lpfc_fcf_record_mac_1_SHIFT 8
1579 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
1580 #define lpfc_fcf_record_mac_1_WORD word3
1581 #define lpfc_fcf_record_mac_2_SHIFT 16
1582 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
1583 #define lpfc_fcf_record_mac_2_WORD word3
1584 #define lpfc_fcf_record_mac_3_SHIFT 24
1585 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
1586 #define lpfc_fcf_record_mac_3_WORD word3
1588 #define lpfc_fcf_record_mac_4_SHIFT 0
1589 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
1590 #define lpfc_fcf_record_mac_4_WORD word4
1591 #define lpfc_fcf_record_mac_5_SHIFT 8
1592 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
1593 #define lpfc_fcf_record_mac_5_WORD word4
1594 #define lpfc_fcf_record_fcf_avail_SHIFT 16
1595 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
1596 #define lpfc_fcf_record_fcf_avail_WORD word4
1597 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24
1598 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
1599 #define lpfc_fcf_record_mac_addr_prov_WORD word4
1600 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
1601 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
1603 #define lpfc_fcf_record_fab_name_0_SHIFT 0
1604 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
1605 #define lpfc_fcf_record_fab_name_0_WORD word5
1606 #define lpfc_fcf_record_fab_name_1_SHIFT 8
1607 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
1608 #define lpfc_fcf_record_fab_name_1_WORD word5
1609 #define lpfc_fcf_record_fab_name_2_SHIFT 16
1610 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
1611 #define lpfc_fcf_record_fab_name_2_WORD word5
1612 #define lpfc_fcf_record_fab_name_3_SHIFT 24
1613 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
1614 #define lpfc_fcf_record_fab_name_3_WORD word5
1616 #define lpfc_fcf_record_fab_name_4_SHIFT 0
1617 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
1618 #define lpfc_fcf_record_fab_name_4_WORD word6
1619 #define lpfc_fcf_record_fab_name_5_SHIFT 8
1620 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
1621 #define lpfc_fcf_record_fab_name_5_WORD word6
1622 #define lpfc_fcf_record_fab_name_6_SHIFT 16
1623 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
1624 #define lpfc_fcf_record_fab_name_6_WORD word6
1625 #define lpfc_fcf_record_fab_name_7_SHIFT 24
1626 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
1627 #define lpfc_fcf_record_fab_name_7_WORD word6
1629 #define lpfc_fcf_record_fc_map_0_SHIFT 0
1630 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
1631 #define lpfc_fcf_record_fc_map_0_WORD word7
1632 #define lpfc_fcf_record_fc_map_1_SHIFT 8
1633 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
1634 #define lpfc_fcf_record_fc_map_1_WORD word7
1635 #define lpfc_fcf_record_fc_map_2_SHIFT 16
1636 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
1637 #define lpfc_fcf_record_fc_map_2_WORD word7
1638 #define lpfc_fcf_record_fcf_valid_SHIFT 24
1639 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF
1640 #define lpfc_fcf_record_fcf_valid_WORD word7
1642 #define lpfc_fcf_record_fcf_index_SHIFT 0
1643 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
1644 #define lpfc_fcf_record_fcf_index_WORD word8
1645 #define lpfc_fcf_record_fcf_state_SHIFT 16
1646 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
1647 #define lpfc_fcf_record_fcf_state_WORD word8
1648 uint8_t vlan_bitmap[512];
1650 #define lpfc_fcf_record_switch_name_0_SHIFT 0
1651 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
1652 #define lpfc_fcf_record_switch_name_0_WORD word137
1653 #define lpfc_fcf_record_switch_name_1_SHIFT 8
1654 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
1655 #define lpfc_fcf_record_switch_name_1_WORD word137
1656 #define lpfc_fcf_record_switch_name_2_SHIFT 16
1657 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
1658 #define lpfc_fcf_record_switch_name_2_WORD word137
1659 #define lpfc_fcf_record_switch_name_3_SHIFT 24
1660 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
1661 #define lpfc_fcf_record_switch_name_3_WORD word137
1663 #define lpfc_fcf_record_switch_name_4_SHIFT 0
1664 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
1665 #define lpfc_fcf_record_switch_name_4_WORD word138
1666 #define lpfc_fcf_record_switch_name_5_SHIFT 8
1667 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
1668 #define lpfc_fcf_record_switch_name_5_WORD word138
1669 #define lpfc_fcf_record_switch_name_6_SHIFT 16
1670 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
1671 #define lpfc_fcf_record_switch_name_6_WORD word138
1672 #define lpfc_fcf_record_switch_name_7_SHIFT 24
1673 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
1674 #define lpfc_fcf_record_switch_name_7_WORD word138
1677 struct lpfc_mbx_read_fcf_tbl {
1678 union lpfc_sli4_cfg_shdr cfg_shdr;
1682 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
1683 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
1684 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10
1691 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
1692 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
1693 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
1696 struct lpfc_mbx_add_fcf_tbl_entry {
1697 union lpfc_sli4_cfg_shdr cfg_shdr;
1699 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
1700 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
1701 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
1702 struct lpfc_mbx_sge fcf_sge;
1705 struct lpfc_mbx_del_fcf_tbl_entry {
1706 struct mbox_header header;
1708 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
1709 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
1710 #define lpfc_mbx_del_fcf_tbl_count_WORD word10
1711 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
1712 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
1713 #define lpfc_mbx_del_fcf_tbl_index_WORD word10
1716 struct lpfc_mbx_redisc_fcf_tbl {
1717 struct mbox_header header;
1719 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
1720 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
1721 #define lpfc_mbx_redisc_fcf_count_WORD word10
1724 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
1725 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
1726 #define lpfc_mbx_redisc_fcf_index_WORD word12
1729 struct lpfc_mbx_query_fw_cfg {
1730 struct mbox_header header;
1731 uint32_t config_number;
1734 uint32_t function_mode;
1735 /* firmware Function Mode */
1736 #define lpfc_function_mode_toe_SHIFT 0
1737 #define lpfc_function_mode_toe_MASK 0x00000001
1738 #define lpfc_function_mode_toe_WORD function_mode
1739 #define lpfc_function_mode_nic_SHIFT 1
1740 #define lpfc_function_mode_nic_MASK 0x00000001
1741 #define lpfc_function_mode_nic_WORD function_mode
1742 #define lpfc_function_mode_rdma_SHIFT 2
1743 #define lpfc_function_mode_rdma_MASK 0x00000001
1744 #define lpfc_function_mode_rdma_WORD function_mode
1745 #define lpfc_function_mode_vm_SHIFT 3
1746 #define lpfc_function_mode_vm_MASK 0x00000001
1747 #define lpfc_function_mode_vm_WORD function_mode
1748 #define lpfc_function_mode_iscsi_i_SHIFT 4
1749 #define lpfc_function_mode_iscsi_i_MASK 0x00000001
1750 #define lpfc_function_mode_iscsi_i_WORD function_mode
1751 #define lpfc_function_mode_iscsi_t_SHIFT 5
1752 #define lpfc_function_mode_iscsi_t_MASK 0x00000001
1753 #define lpfc_function_mode_iscsi_t_WORD function_mode
1754 #define lpfc_function_mode_fcoe_i_SHIFT 6
1755 #define lpfc_function_mode_fcoe_i_MASK 0x00000001
1756 #define lpfc_function_mode_fcoe_i_WORD function_mode
1757 #define lpfc_function_mode_fcoe_t_SHIFT 7
1758 #define lpfc_function_mode_fcoe_t_MASK 0x00000001
1759 #define lpfc_function_mode_fcoe_t_WORD function_mode
1760 #define lpfc_function_mode_dal_SHIFT 8
1761 #define lpfc_function_mode_dal_MASK 0x00000001
1762 #define lpfc_function_mode_dal_WORD function_mode
1763 #define lpfc_function_mode_lro_SHIFT 9
1764 #define lpfc_function_mode_lro_MASK 0x00000001
1765 #define lpfc_function_mode_lro_WORD function_mode
1766 #define lpfc_function_mode_flex10_SHIFT 10
1767 #define lpfc_function_mode_flex10_MASK 0x00000001
1768 #define lpfc_function_mode_flex10_WORD function_mode
1769 #define lpfc_function_mode_ncsi_SHIFT 11
1770 #define lpfc_function_mode_ncsi_MASK 0x00000001
1771 #define lpfc_function_mode_ncsi_WORD function_mode
1774 /* Status field for embedded SLI_CONFIG mailbox command */
1775 #define STATUS_SUCCESS 0x0
1776 #define STATUS_FAILED 0x1
1777 #define STATUS_ILLEGAL_REQUEST 0x2
1778 #define STATUS_ILLEGAL_FIELD 0x3
1779 #define STATUS_INSUFFICIENT_BUFFER 0x4
1780 #define STATUS_UNAUTHORIZED_REQUEST 0x5
1781 #define STATUS_FLASHROM_SAVE_FAILED 0x17
1782 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
1783 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
1784 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
1785 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
1786 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
1787 #define STATUS_ASSERT_FAILED 0x1e
1788 #define STATUS_INVALID_SESSION 0x1f
1789 #define STATUS_INVALID_CONNECTION 0x20
1790 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
1791 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
1792 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
1793 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
1794 #define STATUS_FLASHROM_READ_FAILED 0x27
1795 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
1796 #define STATUS_ERROR_ACITMAIN 0x2a
1797 #define STATUS_REBOOT_REQUIRED 0x2c
1798 #define STATUS_FCF_IN_USE 0x3a
1799 #define STATUS_FCF_TABLE_EMPTY 0x43
1801 struct lpfc_mbx_sli4_config {
1802 struct mbox_header header;
1805 struct lpfc_mbx_init_vfi {
1807 #define lpfc_init_vfi_vr_SHIFT 31
1808 #define lpfc_init_vfi_vr_MASK 0x00000001
1809 #define lpfc_init_vfi_vr_WORD word1
1810 #define lpfc_init_vfi_vt_SHIFT 30
1811 #define lpfc_init_vfi_vt_MASK 0x00000001
1812 #define lpfc_init_vfi_vt_WORD word1
1813 #define lpfc_init_vfi_vf_SHIFT 29
1814 #define lpfc_init_vfi_vf_MASK 0x00000001
1815 #define lpfc_init_vfi_vf_WORD word1
1816 #define lpfc_init_vfi_vp_SHIFT 28
1817 #define lpfc_init_vfi_vp_MASK 0x00000001
1818 #define lpfc_init_vfi_vp_WORD word1
1819 #define lpfc_init_vfi_vfi_SHIFT 0
1820 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
1821 #define lpfc_init_vfi_vfi_WORD word1
1823 #define lpfc_init_vfi_vpi_SHIFT 16
1824 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
1825 #define lpfc_init_vfi_vpi_WORD word2
1826 #define lpfc_init_vfi_fcfi_SHIFT 0
1827 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
1828 #define lpfc_init_vfi_fcfi_WORD word2
1830 #define lpfc_init_vfi_pri_SHIFT 13
1831 #define lpfc_init_vfi_pri_MASK 0x00000007
1832 #define lpfc_init_vfi_pri_WORD word3
1833 #define lpfc_init_vfi_vf_id_SHIFT 1
1834 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
1835 #define lpfc_init_vfi_vf_id_WORD word3
1837 #define lpfc_init_vfi_hop_count_SHIFT 24
1838 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
1839 #define lpfc_init_vfi_hop_count_WORD word4
1841 #define MBX_VFI_IN_USE 0x9F02
1844 struct lpfc_mbx_reg_vfi {
1846 #define lpfc_reg_vfi_vp_SHIFT 28
1847 #define lpfc_reg_vfi_vp_MASK 0x00000001
1848 #define lpfc_reg_vfi_vp_WORD word1
1849 #define lpfc_reg_vfi_vfi_SHIFT 0
1850 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
1851 #define lpfc_reg_vfi_vfi_WORD word1
1853 #define lpfc_reg_vfi_vpi_SHIFT 16
1854 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
1855 #define lpfc_reg_vfi_vpi_WORD word2
1856 #define lpfc_reg_vfi_fcfi_SHIFT 0
1857 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
1858 #define lpfc_reg_vfi_fcfi_WORD word2
1860 struct ulp_bde64 bde;
1864 #define lpfc_reg_vfi_nport_id_SHIFT 0
1865 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
1866 #define lpfc_reg_vfi_nport_id_WORD word10
1869 struct lpfc_mbx_init_vpi {
1871 #define lpfc_init_vpi_vfi_SHIFT 16
1872 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
1873 #define lpfc_init_vpi_vfi_WORD word1
1874 #define lpfc_init_vpi_vpi_SHIFT 0
1875 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
1876 #define lpfc_init_vpi_vpi_WORD word1
1879 struct lpfc_mbx_read_vpi {
1880 uint32_t word1_rsvd;
1882 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
1883 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
1884 #define lpfc_mbx_read_vpi_vnportid_WORD word2
1885 uint32_t word3_rsvd;
1887 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
1888 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
1889 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4
1890 #define lpfc_mbx_read_vpi_pb_SHIFT 15
1891 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
1892 #define lpfc_mbx_read_vpi_pb_WORD word4
1893 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
1894 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
1895 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4
1896 #define lpfc_mbx_read_vpi_ns_SHIFT 30
1897 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
1898 #define lpfc_mbx_read_vpi_ns_WORD word4
1899 #define lpfc_mbx_read_vpi_hl_SHIFT 31
1900 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
1901 #define lpfc_mbx_read_vpi_hl_WORD word4
1902 uint32_t word5_rsvd;
1904 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
1905 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
1906 #define lpfc_mbx_read_vpi_vpi_WORD word6
1908 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
1909 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
1910 #define lpfc_mbx_read_vpi_mac_0_WORD word7
1911 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8
1912 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
1913 #define lpfc_mbx_read_vpi_mac_1_WORD word7
1914 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16
1915 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
1916 #define lpfc_mbx_read_vpi_mac_2_WORD word7
1917 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24
1918 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
1919 #define lpfc_mbx_read_vpi_mac_3_WORD word7
1921 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
1922 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
1923 #define lpfc_mbx_read_vpi_mac_4_WORD word8
1924 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8
1925 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
1926 #define lpfc_mbx_read_vpi_mac_5_WORD word8
1927 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
1928 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
1929 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8
1930 #define lpfc_mbx_read_vpi_vv_SHIFT 28
1931 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
1932 #define lpfc_mbx_read_vpi_vv_WORD word8
1935 struct lpfc_mbx_unreg_vfi {
1936 uint32_t word1_rsvd;
1938 #define lpfc_unreg_vfi_vfi_SHIFT 0
1939 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
1940 #define lpfc_unreg_vfi_vfi_WORD word2
1943 struct lpfc_mbx_resume_rpi {
1945 #define lpfc_resume_rpi_index_SHIFT 0
1946 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
1947 #define lpfc_resume_rpi_index_WORD word1
1948 #define lpfc_resume_rpi_ii_SHIFT 30
1949 #define lpfc_resume_rpi_ii_MASK 0x00000003
1950 #define lpfc_resume_rpi_ii_WORD word1
1951 #define RESUME_INDEX_RPI 0
1952 #define RESUME_INDEX_VPI 1
1953 #define RESUME_INDEX_VFI 2
1954 #define RESUME_INDEX_FCFI 3
1958 #define REG_FCF_INVALID_QID 0xFFFF
1959 struct lpfc_mbx_reg_fcfi {
1961 #define lpfc_reg_fcfi_info_index_SHIFT 0
1962 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
1963 #define lpfc_reg_fcfi_info_index_WORD word1
1964 #define lpfc_reg_fcfi_fcfi_SHIFT 16
1965 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
1966 #define lpfc_reg_fcfi_fcfi_WORD word1
1968 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
1969 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
1970 #define lpfc_reg_fcfi_rq_id1_WORD word2
1971 #define lpfc_reg_fcfi_rq_id0_SHIFT 16
1972 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
1973 #define lpfc_reg_fcfi_rq_id0_WORD word2
1975 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
1976 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
1977 #define lpfc_reg_fcfi_rq_id3_WORD word3
1978 #define lpfc_reg_fcfi_rq_id2_SHIFT 16
1979 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
1980 #define lpfc_reg_fcfi_rq_id2_WORD word3
1982 #define lpfc_reg_fcfi_type_match0_SHIFT 24
1983 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
1984 #define lpfc_reg_fcfi_type_match0_WORD word4
1985 #define lpfc_reg_fcfi_type_mask0_SHIFT 16
1986 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
1987 #define lpfc_reg_fcfi_type_mask0_WORD word4
1988 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1989 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
1990 #define lpfc_reg_fcfi_rctl_match0_WORD word4
1991 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
1992 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
1993 #define lpfc_reg_fcfi_rctl_mask0_WORD word4
1995 #define lpfc_reg_fcfi_type_match1_SHIFT 24
1996 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
1997 #define lpfc_reg_fcfi_type_match1_WORD word5
1998 #define lpfc_reg_fcfi_type_mask1_SHIFT 16
1999 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2000 #define lpfc_reg_fcfi_type_mask1_WORD word5
2001 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2002 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2003 #define lpfc_reg_fcfi_rctl_match1_WORD word5
2004 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2005 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2006 #define lpfc_reg_fcfi_rctl_mask1_WORD word5
2008 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2009 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2010 #define lpfc_reg_fcfi_type_match2_WORD word6
2011 #define lpfc_reg_fcfi_type_mask2_SHIFT 16
2012 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2013 #define lpfc_reg_fcfi_type_mask2_WORD word6
2014 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2015 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2016 #define lpfc_reg_fcfi_rctl_match2_WORD word6
2017 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2018 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2019 #define lpfc_reg_fcfi_rctl_mask2_WORD word6
2021 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2022 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2023 #define lpfc_reg_fcfi_type_match3_WORD word7
2024 #define lpfc_reg_fcfi_type_mask3_SHIFT 16
2025 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2026 #define lpfc_reg_fcfi_type_mask3_WORD word7
2027 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2028 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2029 #define lpfc_reg_fcfi_rctl_match3_WORD word7
2030 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2031 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2032 #define lpfc_reg_fcfi_rctl_mask3_WORD word7
2034 #define lpfc_reg_fcfi_mam_SHIFT 13
2035 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2036 #define lpfc_reg_fcfi_mam_WORD word8
2037 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2038 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
2039 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
2040 #define lpfc_reg_fcfi_vv_SHIFT 12
2041 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2042 #define lpfc_reg_fcfi_vv_WORD word8
2043 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2044 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2045 #define lpfc_reg_fcfi_vlan_tag_WORD word8
2048 struct lpfc_mbx_unreg_fcfi {
2051 #define lpfc_unreg_fcfi_SHIFT 0
2052 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2053 #define lpfc_unreg_fcfi_WORD word2
2056 struct lpfc_mbx_read_rev {
2058 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
2059 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2060 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1
2061 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20
2062 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2063 #define lpfc_mbx_rd_rev_fcoe_WORD word1
2064 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
2065 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2066 #define lpfc_mbx_rd_rev_cee_ver_WORD word1
2067 #define LPFC_PREDCBX_CEE_MODE 0
2068 #define LPFC_DCBX_CEE_MODE 1
2069 #define lpfc_mbx_rd_rev_vpd_SHIFT 29
2070 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2071 #define lpfc_mbx_rd_rev_vpd_WORD word1
2072 uint32_t first_hw_rev;
2073 uint32_t second_hw_rev;
2074 uint32_t word4_rsvd;
2075 uint32_t third_hw_rev;
2077 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2078 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2079 #define lpfc_mbx_rd_rev_fcph_low_WORD word6
2080 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
2081 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2082 #define lpfc_mbx_rd_rev_fcph_high_WORD word6
2083 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
2084 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2085 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
2086 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
2087 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2088 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
2089 uint32_t word7_rsvd;
2091 uint8_t fw_name[16];
2092 uint32_t ulp_fw_id_rev;
2093 uint8_t ulp_fw_name[16];
2094 uint32_t word18_47_rsvd[30];
2096 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2097 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2098 #define lpfc_mbx_rd_rev_avail_len_WORD word48
2099 uint32_t vpd_paddr_low;
2100 uint32_t vpd_paddr_high;
2101 uint32_t avail_vpd_len;
2102 uint32_t rsvd_52_63[12];
2105 struct lpfc_mbx_read_config {
2107 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31
2108 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2109 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1
2111 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2112 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2113 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2
2114 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6
2115 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2116 #define lpfc_mbx_rd_conf_lnk_type_WORD word2
2117 #define LPFC_LNK_TYPE_GE 0
2118 #define LPFC_LNK_TYPE_FC 1
2119 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8
2120 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2121 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2
2122 #define lpfc_mbx_rd_conf_topology_SHIFT 24
2123 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2124 #define lpfc_mbx_rd_conf_topology_WORD word2
2127 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2128 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2129 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4
2132 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2133 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2134 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6
2138 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2139 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2140 #define lpfc_mbx_rd_conf_lmt_WORD word9
2144 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2145 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2146 #define lpfc_mbx_rd_conf_xri_base_WORD word12
2147 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16
2148 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2149 #define lpfc_mbx_rd_conf_xri_count_WORD word12
2151 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2152 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2153 #define lpfc_mbx_rd_conf_rpi_base_WORD word13
2154 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
2155 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2156 #define lpfc_mbx_rd_conf_rpi_count_WORD word13
2158 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2159 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2160 #define lpfc_mbx_rd_conf_vpi_base_WORD word14
2161 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
2162 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2163 #define lpfc_mbx_rd_conf_vpi_count_WORD word14
2165 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2166 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2167 #define lpfc_mbx_rd_conf_vfi_base_WORD word15
2168 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
2169 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2170 #define lpfc_mbx_rd_conf_vfi_count_WORD word15
2172 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
2173 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2174 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16
2176 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2177 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2178 #define lpfc_mbx_rd_conf_rq_count_WORD word17
2179 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16
2180 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2181 #define lpfc_mbx_rd_conf_eq_count_WORD word17
2183 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2184 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2185 #define lpfc_mbx_rd_conf_wq_count_WORD word18
2186 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16
2187 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2188 #define lpfc_mbx_rd_conf_cq_count_WORD word18
2191 struct lpfc_mbx_request_features {
2193 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2194 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2195 #define lpfc_mbx_rq_ftr_qry_WORD word1
2197 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2198 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2199 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
2200 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
2201 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2202 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
2203 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
2204 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2205 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2
2206 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
2207 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2208 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2
2209 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
2210 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2211 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
2212 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
2213 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2214 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
2215 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
2216 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2217 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
2218 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
2219 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2220 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
2221 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11
2222 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2223 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2
2225 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2226 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2227 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
2228 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
2229 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2230 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
2231 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
2232 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2233 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
2234 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
2235 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2236 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
2237 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
2238 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2239 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
2240 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
2241 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2242 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
2243 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
2244 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2245 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
2246 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
2247 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2248 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
2249 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11
2250 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2251 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3
2254 struct lpfc_mbx_supp_pages {
2257 #define qs_MASK 0x00000001
2258 #define qs_WORD word1
2260 #define wr_MASK 0x00000001
2261 #define wr_WORD word1
2263 #define pf_MASK 0x000000ff
2264 #define pf_WORD word1
2265 #define cpn_SHIFT 16
2266 #define cpn_MASK 0x000000ff
2267 #define cpn_WORD word1
2269 #define list_offset_SHIFT 0
2270 #define list_offset_MASK 0x000000ff
2271 #define list_offset_WORD word2
2272 #define next_offset_SHIFT 8
2273 #define next_offset_MASK 0x000000ff
2274 #define next_offset_WORD word2
2275 #define elem_cnt_SHIFT 16
2276 #define elem_cnt_MASK 0x000000ff
2277 #define elem_cnt_WORD word2
2279 #define pn_0_SHIFT 24
2280 #define pn_0_MASK 0x000000ff
2281 #define pn_0_WORD word3
2282 #define pn_1_SHIFT 16
2283 #define pn_1_MASK 0x000000ff
2284 #define pn_1_WORD word3
2285 #define pn_2_SHIFT 8
2286 #define pn_2_MASK 0x000000ff
2287 #define pn_2_WORD word3
2288 #define pn_3_SHIFT 0
2289 #define pn_3_MASK 0x000000ff
2290 #define pn_3_WORD word3
2292 #define pn_4_SHIFT 24
2293 #define pn_4_MASK 0x000000ff
2294 #define pn_4_WORD word4
2295 #define pn_5_SHIFT 16
2296 #define pn_5_MASK 0x000000ff
2297 #define pn_5_WORD word4
2298 #define pn_6_SHIFT 8
2299 #define pn_6_MASK 0x000000ff
2300 #define pn_6_WORD word4
2301 #define pn_7_SHIFT 0
2302 #define pn_7_MASK 0x000000ff
2303 #define pn_7_WORD word4
2305 #define LPFC_SUPP_PAGES 0
2306 #define LPFC_BLOCK_GUARD_PROFILES 1
2307 #define LPFC_SLI4_PARAMETERS 2
2310 struct lpfc_mbx_pc_sli4_params {
2313 #define qs_MASK 0x00000001
2314 #define qs_WORD word1
2316 #define wr_MASK 0x00000001
2317 #define wr_WORD word1
2319 #define pf_MASK 0x000000ff
2320 #define pf_WORD word1
2321 #define cpn_SHIFT 16
2322 #define cpn_MASK 0x000000ff
2323 #define cpn_WORD word1
2325 #define if_type_SHIFT 0
2326 #define if_type_MASK 0x00000007
2327 #define if_type_WORD word2
2328 #define sli_rev_SHIFT 4
2329 #define sli_rev_MASK 0x0000000f
2330 #define sli_rev_WORD word2
2331 #define sli_family_SHIFT 8
2332 #define sli_family_MASK 0x000000ff
2333 #define sli_family_WORD word2
2334 #define featurelevel_1_SHIFT 16
2335 #define featurelevel_1_MASK 0x000000ff
2336 #define featurelevel_1_WORD word2
2337 #define featurelevel_2_SHIFT 24
2338 #define featurelevel_2_MASK 0x0000001f
2339 #define featurelevel_2_WORD word2
2341 #define fcoe_SHIFT 0
2342 #define fcoe_MASK 0x00000001
2343 #define fcoe_WORD word3
2345 #define fc_MASK 0x00000001
2346 #define fc_WORD word3
2348 #define nic_MASK 0x00000001
2349 #define nic_WORD word3
2350 #define iscsi_SHIFT 3
2351 #define iscsi_MASK 0x00000001
2352 #define iscsi_WORD word3
2353 #define rdma_SHIFT 4
2354 #define rdma_MASK 0x00000001
2355 #define rdma_WORD word3
2356 uint32_t sge_supp_len;
2357 #define SLI4_PAGE_SIZE 4096
2359 #define if_page_sz_SHIFT 0
2360 #define if_page_sz_MASK 0x0000ffff
2361 #define if_page_sz_WORD word5
2362 #define loopbk_scope_SHIFT 24
2363 #define loopbk_scope_MASK 0x0000000f
2364 #define loopbk_scope_WORD word5
2365 #define rq_db_window_SHIFT 28
2366 #define rq_db_window_MASK 0x0000000f
2367 #define rq_db_window_WORD word5
2369 #define eq_pages_SHIFT 0
2370 #define eq_pages_MASK 0x0000000f
2371 #define eq_pages_WORD word6
2372 #define eqe_size_SHIFT 8
2373 #define eqe_size_MASK 0x000000ff
2374 #define eqe_size_WORD word6
2376 #define cq_pages_SHIFT 0
2377 #define cq_pages_MASK 0x0000000f
2378 #define cq_pages_WORD word7
2379 #define cqe_size_SHIFT 8
2380 #define cqe_size_MASK 0x000000ff
2381 #define cqe_size_WORD word7
2383 #define mq_pages_SHIFT 0
2384 #define mq_pages_MASK 0x0000000f
2385 #define mq_pages_WORD word8
2386 #define mqe_size_SHIFT 8
2387 #define mqe_size_MASK 0x000000ff
2388 #define mqe_size_WORD word8
2389 #define mq_elem_cnt_SHIFT 16
2390 #define mq_elem_cnt_MASK 0x000000ff
2391 #define mq_elem_cnt_WORD word8
2393 #define wq_pages_SHIFT 0
2394 #define wq_pages_MASK 0x0000ffff
2395 #define wq_pages_WORD word9
2396 #define wqe_size_SHIFT 8
2397 #define wqe_size_MASK 0x000000ff
2398 #define wqe_size_WORD word9
2400 #define rq_pages_SHIFT 0
2401 #define rq_pages_MASK 0x0000ffff
2402 #define rq_pages_WORD word10
2403 #define rqe_size_SHIFT 8
2404 #define rqe_size_MASK 0x000000ff
2405 #define rqe_size_WORD word10
2407 #define hdr_pages_SHIFT 0
2408 #define hdr_pages_MASK 0x0000000f
2409 #define hdr_pages_WORD word11
2410 #define hdr_size_SHIFT 8
2411 #define hdr_size_MASK 0x0000000f
2412 #define hdr_size_WORD word11
2413 #define hdr_pp_align_SHIFT 16
2414 #define hdr_pp_align_MASK 0x0000ffff
2415 #define hdr_pp_align_WORD word11
2417 #define sgl_pages_SHIFT 0
2418 #define sgl_pages_MASK 0x0000000f
2419 #define sgl_pages_WORD word12
2420 #define sgl_pp_align_SHIFT 16
2421 #define sgl_pp_align_MASK 0x0000ffff
2422 #define sgl_pp_align_WORD word12
2423 uint32_t rsvd_13_63[51];
2425 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
2426 &(~((SLI4_PAGE_SIZE)-1)))
2428 struct lpfc_sli4_parameters {
2430 #define cfg_prot_type_SHIFT 0
2431 #define cfg_prot_type_MASK 0x000000FF
2432 #define cfg_prot_type_WORD word0
2434 #define cfg_ft_SHIFT 0
2435 #define cfg_ft_MASK 0x00000001
2436 #define cfg_ft_WORD word1
2437 #define cfg_sli_rev_SHIFT 4
2438 #define cfg_sli_rev_MASK 0x0000000f
2439 #define cfg_sli_rev_WORD word1
2440 #define cfg_sli_family_SHIFT 8
2441 #define cfg_sli_family_MASK 0x0000000f
2442 #define cfg_sli_family_WORD word1
2443 #define cfg_if_type_SHIFT 12
2444 #define cfg_if_type_MASK 0x0000000f
2445 #define cfg_if_type_WORD word1
2446 #define cfg_sli_hint_1_SHIFT 16
2447 #define cfg_sli_hint_1_MASK 0x000000ff
2448 #define cfg_sli_hint_1_WORD word1
2449 #define cfg_sli_hint_2_SHIFT 24
2450 #define cfg_sli_hint_2_MASK 0x0000001f
2451 #define cfg_sli_hint_2_WORD word1
2455 #define cfg_cqv_SHIFT 14
2456 #define cfg_cqv_MASK 0x00000003
2457 #define cfg_cqv_WORD word4
2460 #define cfg_mqv_SHIFT 14
2461 #define cfg_mqv_MASK 0x00000003
2462 #define cfg_mqv_WORD word6
2465 #define cfg_wqv_SHIFT 14
2466 #define cfg_wqv_MASK 0x00000003
2467 #define cfg_wqv_WORD word8
2470 #define cfg_rqv_SHIFT 14
2471 #define cfg_rqv_MASK 0x00000003
2472 #define cfg_rqv_WORD word10
2474 #define cfg_rq_db_window_SHIFT 28
2475 #define cfg_rq_db_window_MASK 0x0000000f
2476 #define cfg_rq_db_window_WORD word11
2478 #define cfg_fcoe_SHIFT 0
2479 #define cfg_fcoe_MASK 0x00000001
2480 #define cfg_fcoe_WORD word12
2481 #define cfg_ext_SHIFT 1
2482 #define cfg_ext_MASK 0x00000001
2483 #define cfg_ext_WORD word12
2484 #define cfg_hdrr_SHIFT 2
2485 #define cfg_hdrr_MASK 0x00000001
2486 #define cfg_hdrr_WORD word12
2487 #define cfg_phwq_SHIFT 15
2488 #define cfg_phwq_MASK 0x00000001
2489 #define cfg_phwq_WORD word12
2490 #define cfg_loopbk_scope_SHIFT 28
2491 #define cfg_loopbk_scope_MASK 0x0000000f
2492 #define cfg_loopbk_scope_WORD word12
2493 uint32_t sge_supp_len;
2495 #define cfg_sgl_page_cnt_SHIFT 0
2496 #define cfg_sgl_page_cnt_MASK 0x0000000f
2497 #define cfg_sgl_page_cnt_WORD word14
2498 #define cfg_sgl_page_size_SHIFT 8
2499 #define cfg_sgl_page_size_MASK 0x000000ff
2500 #define cfg_sgl_page_size_WORD word14
2501 #define cfg_sgl_pp_align_SHIFT 16
2502 #define cfg_sgl_pp_align_MASK 0x000000ff
2503 #define cfg_sgl_pp_align_WORD word14
2511 struct lpfc_mbx_get_sli4_parameters {
2512 struct mbox_header header;
2513 struct lpfc_sli4_parameters sli4_parameters;
2516 struct lpfc_rscr_desc_generic {
2517 #define LPFC_RSRC_DESC_WSIZE 18
2518 uint32_t desc[LPFC_RSRC_DESC_WSIZE];
2521 struct lpfc_rsrc_desc_pcie {
2523 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
2524 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
2525 #define lpfc_rsrc_desc_pcie_type_WORD word0
2526 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
2528 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
2529 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
2530 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1
2533 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
2534 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
2535 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3
2536 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8
2537 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
2538 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3
2539 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16
2540 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
2541 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3
2543 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
2544 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
2545 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4
2548 struct lpfc_rsrc_desc_fcfcoe {
2550 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
2551 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
2552 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0
2553 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
2555 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
2556 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
2557 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1
2558 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16
2559 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
2560 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1
2562 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
2563 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
2564 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2
2565 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16
2566 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
2567 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2
2569 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
2570 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
2571 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3
2572 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16
2573 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
2574 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3
2576 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
2577 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
2578 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4
2579 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16
2580 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
2581 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4
2583 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
2584 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
2585 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5
2586 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16
2587 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
2588 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5
2597 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
2598 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
2599 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13
2600 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6
2601 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
2602 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13
2603 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8
2604 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
2605 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13
2606 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9
2607 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
2608 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13
2609 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16
2610 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
2611 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13
2614 struct lpfc_func_cfg {
2615 #define LPFC_RSRC_DESC_MAX_NUM 2
2616 uint32_t rsrc_desc_count;
2617 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
2620 struct lpfc_mbx_get_func_cfg {
2621 struct mbox_header header;
2622 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
2623 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
2624 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
2625 struct lpfc_func_cfg func_cfg;
2628 struct lpfc_prof_cfg {
2629 #define LPFC_RSRC_DESC_MAX_NUM 2
2630 uint32_t rsrc_desc_count;
2631 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
2634 struct lpfc_mbx_get_prof_cfg {
2635 struct mbox_header header;
2636 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
2637 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
2638 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
2642 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
2643 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
2644 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10
2645 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8
2646 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
2647 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10
2650 struct lpfc_prof_cfg prof_cfg;
2655 struct lpfc_controller_attribute {
2656 uint32_t version_string[8];
2657 uint32_t manufacturer_name[8];
2658 uint32_t supported_modes;
2660 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
2661 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
2662 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17
2663 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8
2664 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
2665 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17
2666 uint32_t mbx_da_struct_ver;
2667 uint32_t ep_fw_da_struct_ver;
2668 uint32_t ncsi_ver_str[3];
2669 uint32_t dflt_ext_timeout;
2670 uint32_t model_number[8];
2671 uint32_t description[16];
2672 uint32_t serial_number[8];
2673 uint32_t ip_ver_str[8];
2674 uint32_t fw_ver_str[8];
2675 uint32_t bios_ver_str[8];
2676 uint32_t redboot_ver_str[8];
2677 uint32_t driver_ver_str[8];
2678 uint32_t flash_fw_ver_str[8];
2679 uint32_t functionality;
2681 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
2682 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
2683 #define lpfc_cntl_attr_max_cbd_len_WORD word105
2684 #define lpfc_cntl_attr_asic_rev_SHIFT 16
2685 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
2686 #define lpfc_cntl_attr_asic_rev_WORD word105
2687 #define lpfc_cntl_attr_gen_guid0_SHIFT 24
2688 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
2689 #define lpfc_cntl_attr_gen_guid0_WORD word105
2690 uint32_t gen_guid1_12[3];
2692 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
2693 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
2694 #define lpfc_cntl_attr_gen_guid13_14_WORD word109
2695 #define lpfc_cntl_attr_gen_guid15_SHIFT 16
2696 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
2697 #define lpfc_cntl_attr_gen_guid15_WORD word109
2698 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24
2699 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
2700 #define lpfc_cntl_attr_hba_port_cnt_WORD word109
2702 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
2703 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
2704 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110
2705 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24
2706 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
2707 #define lpfc_cntl_attr_multi_func_dev_WORD word110
2709 #define lpfc_cntl_attr_cache_valid_SHIFT 0
2710 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
2711 #define lpfc_cntl_attr_cache_valid_WORD word111
2712 #define lpfc_cntl_attr_hba_status_SHIFT 8
2713 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
2714 #define lpfc_cntl_attr_hba_status_WORD word111
2715 #define lpfc_cntl_attr_max_domain_SHIFT 16
2716 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
2717 #define lpfc_cntl_attr_max_domain_WORD word111
2718 #define lpfc_cntl_attr_lnk_numb_SHIFT 24
2719 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
2720 #define lpfc_cntl_attr_lnk_numb_WORD word111
2721 #define lpfc_cntl_attr_lnk_type_SHIFT 30
2722 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
2723 #define lpfc_cntl_attr_lnk_type_WORD word111
2724 uint32_t fw_post_status;
2725 uint32_t hba_mtu[8];
2727 uint32_t reserved1[3];
2729 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
2730 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
2731 #define lpfc_cntl_attr_pci_vendor_id_WORD word125
2732 #define lpfc_cntl_attr_pci_device_id_SHIFT 16
2733 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
2734 #define lpfc_cntl_attr_pci_device_id_WORD word125
2736 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
2737 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
2738 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126
2739 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16
2740 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
2741 #define lpfc_cntl_attr_pci_subsys_id_WORD word126
2743 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
2744 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
2745 #define lpfc_cntl_attr_pci_bus_num_WORD word127
2746 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8
2747 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
2748 #define lpfc_cntl_attr_pci_dev_num_WORD word127
2749 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16
2750 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
2751 #define lpfc_cntl_attr_pci_fnc_num_WORD word127
2752 #define lpfc_cntl_attr_inf_type_SHIFT 24
2753 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
2754 #define lpfc_cntl_attr_inf_type_WORD word127
2755 uint32_t unique_id[2];
2757 #define lpfc_cntl_attr_num_netfil_SHIFT 0
2758 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
2759 #define lpfc_cntl_attr_num_netfil_WORD word130
2760 uint32_t reserved2[4];
2763 struct lpfc_mbx_get_cntl_attributes {
2764 union lpfc_sli4_cfg_shdr cfg_shdr;
2765 struct lpfc_controller_attribute cntl_attr;
2768 struct lpfc_mbx_get_port_name {
2769 struct mbox_header header;
2773 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
2774 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
2775 #define lpfc_mbx_get_port_name_lnk_type_WORD word4
2779 #define lpfc_mbx_get_port_name_name0_SHIFT 0
2780 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
2781 #define lpfc_mbx_get_port_name_name0_WORD word4
2782 #define lpfc_mbx_get_port_name_name1_SHIFT 8
2783 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
2784 #define lpfc_mbx_get_port_name_name1_WORD word4
2785 #define lpfc_mbx_get_port_name_name2_SHIFT 16
2786 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
2787 #define lpfc_mbx_get_port_name_name2_WORD word4
2788 #define lpfc_mbx_get_port_name_name3_SHIFT 24
2789 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
2790 #define lpfc_mbx_get_port_name_name3_WORD word4
2791 #define LPFC_LINK_NUMBER_0 0
2792 #define LPFC_LINK_NUMBER_1 1
2793 #define LPFC_LINK_NUMBER_2 2
2794 #define LPFC_LINK_NUMBER_3 3
2799 /* Mailbox Completion Queue Error Messages */
2800 #define MB_CQE_STATUS_SUCCESS 0x0
2801 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
2802 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
2803 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
2804 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
2805 #define MB_CQE_STATUS_DMA_FAILED 0x5
2807 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8
2808 struct lpfc_mbx_wr_object {
2809 struct mbox_header header;
2813 #define lpfc_wr_object_eof_SHIFT 31
2814 #define lpfc_wr_object_eof_MASK 0x00000001
2815 #define lpfc_wr_object_eof_WORD word4
2816 #define lpfc_wr_object_write_length_SHIFT 0
2817 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
2818 #define lpfc_wr_object_write_length_WORD word4
2819 uint32_t write_offset;
2820 uint32_t object_name[26];
2822 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
2825 uint32_t actual_write_length;
2830 /* mailbox queue entry structure */
2833 #define lpfc_mqe_status_SHIFT 16
2834 #define lpfc_mqe_status_MASK 0x0000FFFF
2835 #define lpfc_mqe_status_WORD word0
2836 #define lpfc_mqe_command_SHIFT 8
2837 #define lpfc_mqe_command_MASK 0x000000FF
2838 #define lpfc_mqe_command_WORD word0
2840 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
2841 /* sli4 mailbox commands */
2842 struct lpfc_mbx_sli4_config sli4_config;
2843 struct lpfc_mbx_init_vfi init_vfi;
2844 struct lpfc_mbx_reg_vfi reg_vfi;
2845 struct lpfc_mbx_reg_vfi unreg_vfi;
2846 struct lpfc_mbx_init_vpi init_vpi;
2847 struct lpfc_mbx_resume_rpi resume_rpi;
2848 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
2849 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
2850 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
2851 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
2852 struct lpfc_mbx_reg_fcfi reg_fcfi;
2853 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
2854 struct lpfc_mbx_mq_create mq_create;
2855 struct lpfc_mbx_mq_create_ext mq_create_ext;
2856 struct lpfc_mbx_eq_create eq_create;
2857 struct lpfc_mbx_cq_create cq_create;
2858 struct lpfc_mbx_wq_create wq_create;
2859 struct lpfc_mbx_rq_create rq_create;
2860 struct lpfc_mbx_mq_destroy mq_destroy;
2861 struct lpfc_mbx_eq_destroy eq_destroy;
2862 struct lpfc_mbx_cq_destroy cq_destroy;
2863 struct lpfc_mbx_wq_destroy wq_destroy;
2864 struct lpfc_mbx_rq_destroy rq_destroy;
2865 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
2866 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
2867 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
2868 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
2869 struct lpfc_mbx_nembed_cmd nembed_cmd;
2870 struct lpfc_mbx_read_rev read_rev;
2871 struct lpfc_mbx_read_vpi read_vpi;
2872 struct lpfc_mbx_read_config rd_config;
2873 struct lpfc_mbx_request_features req_ftrs;
2874 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
2875 struct lpfc_mbx_query_fw_cfg query_fw_cfg;
2876 struct lpfc_mbx_supp_pages supp_pages;
2877 struct lpfc_mbx_pc_sli4_params sli4_params;
2878 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
2879 struct lpfc_mbx_set_link_diag_state link_diag_state;
2880 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
2881 struct lpfc_mbx_run_link_diag_test link_diag_test;
2882 struct lpfc_mbx_get_func_cfg get_func_cfg;
2883 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
2884 struct lpfc_mbx_wr_object wr_object;
2885 struct lpfc_mbx_get_port_name get_port_name;
2886 struct lpfc_mbx_nop nop;
2892 #define lpfc_mcqe_status_SHIFT 0
2893 #define lpfc_mcqe_status_MASK 0x0000FFFF
2894 #define lpfc_mcqe_status_WORD word0
2895 #define lpfc_mcqe_ext_status_SHIFT 16
2896 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
2897 #define lpfc_mcqe_ext_status_WORD word0
2901 #define lpfc_trailer_valid_SHIFT 31
2902 #define lpfc_trailer_valid_MASK 0x00000001
2903 #define lpfc_trailer_valid_WORD trailer
2904 #define lpfc_trailer_async_SHIFT 30
2905 #define lpfc_trailer_async_MASK 0x00000001
2906 #define lpfc_trailer_async_WORD trailer
2907 #define lpfc_trailer_hpi_SHIFT 29
2908 #define lpfc_trailer_hpi_MASK 0x00000001
2909 #define lpfc_trailer_hpi_WORD trailer
2910 #define lpfc_trailer_completed_SHIFT 28
2911 #define lpfc_trailer_completed_MASK 0x00000001
2912 #define lpfc_trailer_completed_WORD trailer
2913 #define lpfc_trailer_consumed_SHIFT 27
2914 #define lpfc_trailer_consumed_MASK 0x00000001
2915 #define lpfc_trailer_consumed_WORD trailer
2916 #define lpfc_trailer_type_SHIFT 16
2917 #define lpfc_trailer_type_MASK 0x000000FF
2918 #define lpfc_trailer_type_WORD trailer
2919 #define lpfc_trailer_code_SHIFT 8
2920 #define lpfc_trailer_code_MASK 0x000000FF
2921 #define lpfc_trailer_code_WORD trailer
2922 #define LPFC_TRAILER_CODE_LINK 0x1
2923 #define LPFC_TRAILER_CODE_FCOE 0x2
2924 #define LPFC_TRAILER_CODE_DCBX 0x3
2925 #define LPFC_TRAILER_CODE_GRP5 0x5
2926 #define LPFC_TRAILER_CODE_FC 0x10
2927 #define LPFC_TRAILER_CODE_SLI 0x11
2930 struct lpfc_acqe_link {
2932 #define lpfc_acqe_link_speed_SHIFT 24
2933 #define lpfc_acqe_link_speed_MASK 0x000000FF
2934 #define lpfc_acqe_link_speed_WORD word0
2935 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
2936 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
2937 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
2938 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
2939 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
2940 #define lpfc_acqe_link_duplex_SHIFT 16
2941 #define lpfc_acqe_link_duplex_MASK 0x000000FF
2942 #define lpfc_acqe_link_duplex_WORD word0
2943 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
2944 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
2945 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
2946 #define lpfc_acqe_link_status_SHIFT 8
2947 #define lpfc_acqe_link_status_MASK 0x000000FF
2948 #define lpfc_acqe_link_status_WORD word0
2949 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
2950 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
2951 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
2952 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
2953 #define lpfc_acqe_link_type_SHIFT 6
2954 #define lpfc_acqe_link_type_MASK 0x00000003
2955 #define lpfc_acqe_link_type_WORD word0
2956 #define lpfc_acqe_link_number_SHIFT 0
2957 #define lpfc_acqe_link_number_MASK 0x0000003F
2958 #define lpfc_acqe_link_number_WORD word0
2960 #define lpfc_acqe_link_fault_SHIFT 0
2961 #define lpfc_acqe_link_fault_MASK 0x000000FF
2962 #define lpfc_acqe_link_fault_WORD word1
2963 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
2964 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
2965 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
2966 #define lpfc_acqe_logical_link_speed_SHIFT 16
2967 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
2968 #define lpfc_acqe_logical_link_speed_WORD word1
2971 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
2972 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
2975 struct lpfc_acqe_fip {
2978 #define lpfc_acqe_fip_fcf_count_SHIFT 0
2979 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
2980 #define lpfc_acqe_fip_fcf_count_WORD word1
2981 #define lpfc_acqe_fip_event_type_SHIFT 16
2982 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
2983 #define lpfc_acqe_fip_event_type_WORD word1
2986 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
2987 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
2988 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
2989 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
2990 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
2993 struct lpfc_acqe_dcbx {
3000 struct lpfc_acqe_grp5 {
3002 #define lpfc_acqe_grp5_type_SHIFT 6
3003 #define lpfc_acqe_grp5_type_MASK 0x00000003
3004 #define lpfc_acqe_grp5_type_WORD word0
3005 #define lpfc_acqe_grp5_number_SHIFT 0
3006 #define lpfc_acqe_grp5_number_MASK 0x0000003F
3007 #define lpfc_acqe_grp5_number_WORD word0
3009 #define lpfc_acqe_grp5_llink_spd_SHIFT 16
3010 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
3011 #define lpfc_acqe_grp5_llink_spd_WORD word1
3016 struct lpfc_acqe_fc_la {
3018 #define lpfc_acqe_fc_la_speed_SHIFT 24
3019 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
3020 #define lpfc_acqe_fc_la_speed_WORD word0
3021 #define LPFC_FC_LA_SPEED_UNKOWN 0x0
3022 #define LPFC_FC_LA_SPEED_1G 0x1
3023 #define LPFC_FC_LA_SPEED_2G 0x2
3024 #define LPFC_FC_LA_SPEED_4G 0x4
3025 #define LPFC_FC_LA_SPEED_8G 0x8
3026 #define LPFC_FC_LA_SPEED_10G 0xA
3027 #define LPFC_FC_LA_SPEED_16G 0x10
3028 #define lpfc_acqe_fc_la_topology_SHIFT 16
3029 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
3030 #define lpfc_acqe_fc_la_topology_WORD word0
3031 #define LPFC_FC_LA_TOP_UNKOWN 0x0
3032 #define LPFC_FC_LA_TOP_P2P 0x1
3033 #define LPFC_FC_LA_TOP_FCAL 0x2
3034 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
3035 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
3036 #define lpfc_acqe_fc_la_att_type_SHIFT 8
3037 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
3038 #define lpfc_acqe_fc_la_att_type_WORD word0
3039 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
3040 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
3041 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
3042 #define lpfc_acqe_fc_la_port_type_SHIFT 6
3043 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
3044 #define lpfc_acqe_fc_la_port_type_WORD word0
3045 #define LPFC_LINK_TYPE_ETHERNET 0x0
3046 #define LPFC_LINK_TYPE_FC 0x1
3047 #define lpfc_acqe_fc_la_port_number_SHIFT 0
3048 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
3049 #define lpfc_acqe_fc_la_port_number_WORD word0
3051 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16
3052 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
3053 #define lpfc_acqe_fc_la_llink_spd_WORD word1
3054 #define lpfc_acqe_fc_la_fault_SHIFT 0
3055 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
3056 #define lpfc_acqe_fc_la_fault_WORD word1
3057 #define LPFC_FC_LA_FAULT_NONE 0x0
3058 #define LPFC_FC_LA_FAULT_LOCAL 0x1
3059 #define LPFC_FC_LA_FAULT_REMOTE 0x2
3062 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
3063 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
3066 struct lpfc_acqe_sli {
3067 uint32_t event_data1;
3068 uint32_t event_data2;
3071 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
3072 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
3073 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
3074 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
3075 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
3079 * Define the bootstrap mailbox (bmbx) region used to communicate
3080 * mailbox command between the host and port. The mailbox consists
3081 * of a payload area of 256 bytes and a completion queue of length
3084 struct lpfc_bmbx_create {
3085 struct lpfc_mqe mqe;
3086 struct lpfc_mcqe mcqe;
3089 #define SGL_ALIGN_SZ 64
3090 #define SGL_PAGE_SIZE 4096
3091 /* align SGL addr on a size boundary - adjust address up */
3092 #define NO_XRI 0xffff
3096 #define wqe_xri_tag_SHIFT 0
3097 #define wqe_xri_tag_MASK 0x0000FFFF
3098 #define wqe_xri_tag_WORD word6
3099 #define wqe_ctxt_tag_SHIFT 16
3100 #define wqe_ctxt_tag_MASK 0x0000FFFF
3101 #define wqe_ctxt_tag_WORD word6
3103 #define wqe_dif_SHIFT 0
3104 #define wqe_dif_MASK 0x00000003
3105 #define wqe_dif_WORD word7
3106 #define wqe_ct_SHIFT 2
3107 #define wqe_ct_MASK 0x00000003
3108 #define wqe_ct_WORD word7
3109 #define wqe_status_SHIFT 4
3110 #define wqe_status_MASK 0x0000000f
3111 #define wqe_status_WORD word7
3112 #define wqe_cmnd_SHIFT 8
3113 #define wqe_cmnd_MASK 0x000000ff
3114 #define wqe_cmnd_WORD word7
3115 #define wqe_class_SHIFT 16
3116 #define wqe_class_MASK 0x00000007
3117 #define wqe_class_WORD word7
3118 #define wqe_ar_SHIFT 19
3119 #define wqe_ar_MASK 0x00000001
3120 #define wqe_ar_WORD word7
3121 #define wqe_ag_SHIFT wqe_ar_SHIFT
3122 #define wqe_ag_MASK wqe_ar_MASK
3123 #define wqe_ag_WORD wqe_ar_WORD
3124 #define wqe_pu_SHIFT 20
3125 #define wqe_pu_MASK 0x00000003
3126 #define wqe_pu_WORD word7
3127 #define wqe_erp_SHIFT 22
3128 #define wqe_erp_MASK 0x00000001
3129 #define wqe_erp_WORD word7
3130 #define wqe_conf_SHIFT wqe_erp_SHIFT
3131 #define wqe_conf_MASK wqe_erp_MASK
3132 #define wqe_conf_WORD wqe_erp_WORD
3133 #define wqe_lnk_SHIFT 23
3134 #define wqe_lnk_MASK 0x00000001
3135 #define wqe_lnk_WORD word7
3136 #define wqe_tmo_SHIFT 24
3137 #define wqe_tmo_MASK 0x000000ff
3138 #define wqe_tmo_WORD word7
3139 uint32_t abort_tag; /* word 8 in WQE */
3141 #define wqe_reqtag_SHIFT 0
3142 #define wqe_reqtag_MASK 0x0000FFFF
3143 #define wqe_reqtag_WORD word9
3144 #define wqe_temp_rpi_SHIFT 16
3145 #define wqe_temp_rpi_MASK 0x0000FFFF
3146 #define wqe_temp_rpi_WORD word9
3147 #define wqe_rcvoxid_SHIFT 16
3148 #define wqe_rcvoxid_MASK 0x0000FFFF
3149 #define wqe_rcvoxid_WORD word9
3151 #define wqe_ebde_cnt_SHIFT 0
3152 #define wqe_ebde_cnt_MASK 0x0000000f
3153 #define wqe_ebde_cnt_WORD word10
3154 #define wqe_lenloc_SHIFT 7
3155 #define wqe_lenloc_MASK 0x00000003
3156 #define wqe_lenloc_WORD word10
3157 #define LPFC_WQE_LENLOC_NONE 0
3158 #define LPFC_WQE_LENLOC_WORD3 1
3159 #define LPFC_WQE_LENLOC_WORD12 2
3160 #define LPFC_WQE_LENLOC_WORD4 3
3161 #define wqe_qosd_SHIFT 9
3162 #define wqe_qosd_MASK 0x00000001
3163 #define wqe_qosd_WORD word10
3164 #define wqe_xbl_SHIFT 11
3165 #define wqe_xbl_MASK 0x00000001
3166 #define wqe_xbl_WORD word10
3167 #define wqe_iod_SHIFT 13
3168 #define wqe_iod_MASK 0x00000001
3169 #define wqe_iod_WORD word10
3170 #define LPFC_WQE_IOD_WRITE 0
3171 #define LPFC_WQE_IOD_READ 1
3172 #define wqe_dbde_SHIFT 14
3173 #define wqe_dbde_MASK 0x00000001
3174 #define wqe_dbde_WORD word10
3175 #define wqe_wqes_SHIFT 15
3176 #define wqe_wqes_MASK 0x00000001
3177 #define wqe_wqes_WORD word10
3178 /* Note that this field overlaps above fields */
3179 #define wqe_wqid_SHIFT 1
3180 #define wqe_wqid_MASK 0x00007fff
3181 #define wqe_wqid_WORD word10
3182 #define wqe_pri_SHIFT 16
3183 #define wqe_pri_MASK 0x00000007
3184 #define wqe_pri_WORD word10
3185 #define wqe_pv_SHIFT 19
3186 #define wqe_pv_MASK 0x00000001
3187 #define wqe_pv_WORD word10
3188 #define wqe_xc_SHIFT 21
3189 #define wqe_xc_MASK 0x00000001
3190 #define wqe_xc_WORD word10
3191 #define wqe_sr_SHIFT 22
3192 #define wqe_sr_MASK 0x00000001
3193 #define wqe_sr_WORD word10
3194 #define wqe_ccpe_SHIFT 23
3195 #define wqe_ccpe_MASK 0x00000001
3196 #define wqe_ccpe_WORD word10
3197 #define wqe_ccp_SHIFT 24
3198 #define wqe_ccp_MASK 0x000000ff
3199 #define wqe_ccp_WORD word10
3201 #define wqe_cmd_type_SHIFT 0
3202 #define wqe_cmd_type_MASK 0x0000000f
3203 #define wqe_cmd_type_WORD word11
3204 #define wqe_els_id_SHIFT 4
3205 #define wqe_els_id_MASK 0x00000003
3206 #define wqe_els_id_WORD word11
3207 #define LPFC_ELS_ID_FLOGI 3
3208 #define LPFC_ELS_ID_FDISC 2
3209 #define LPFC_ELS_ID_LOGO 1
3210 #define LPFC_ELS_ID_DEFAULT 0
3211 #define wqe_wqec_SHIFT 7
3212 #define wqe_wqec_MASK 0x00000001
3213 #define wqe_wqec_WORD word11
3214 #define wqe_cqid_SHIFT 16
3215 #define wqe_cqid_MASK 0x0000ffff
3216 #define wqe_cqid_WORD word11
3217 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
3222 #define wqe_els_did_SHIFT 0
3223 #define wqe_els_did_MASK 0x00FFFFFF
3224 #define wqe_els_did_WORD word5
3225 #define wqe_xmit_bls_pt_SHIFT 28
3226 #define wqe_xmit_bls_pt_MASK 0x00000003
3227 #define wqe_xmit_bls_pt_WORD word5
3228 #define wqe_xmit_bls_ar_SHIFT 30
3229 #define wqe_xmit_bls_ar_MASK 0x00000001
3230 #define wqe_xmit_bls_ar_WORD word5
3231 #define wqe_xmit_bls_xo_SHIFT 31
3232 #define wqe_xmit_bls_xo_MASK 0x00000001
3233 #define wqe_xmit_bls_xo_WORD word5
3236 struct lpfc_wqe_generic{
3237 struct ulp_bde64 bde;
3241 struct wqe_common wqe_com;
3242 uint32_t payload[4];
3245 struct els_request64_wqe {
3246 struct ulp_bde64 bde;
3247 uint32_t payload_len;
3249 #define els_req64_sid_SHIFT 0
3250 #define els_req64_sid_MASK 0x00FFFFFF
3251 #define els_req64_sid_WORD word4
3252 #define els_req64_sp_SHIFT 24
3253 #define els_req64_sp_MASK 0x00000001
3254 #define els_req64_sp_WORD word4
3255 #define els_req64_vf_SHIFT 25
3256 #define els_req64_vf_MASK 0x00000001
3257 #define els_req64_vf_WORD word4
3258 struct wqe_did wqe_dest;
3259 struct wqe_common wqe_com; /* words 6-11 */
3261 #define els_req64_vfid_SHIFT 1
3262 #define els_req64_vfid_MASK 0x00000FFF
3263 #define els_req64_vfid_WORD word12
3264 #define els_req64_pri_SHIFT 13
3265 #define els_req64_pri_MASK 0x00000007
3266 #define els_req64_pri_WORD word12
3268 #define els_req64_hopcnt_SHIFT 24
3269 #define els_req64_hopcnt_MASK 0x000000ff
3270 #define els_req64_hopcnt_WORD word13
3271 uint32_t reserved[2];
3274 struct xmit_els_rsp64_wqe {
3275 struct ulp_bde64 bde;
3276 uint32_t response_payload_len;
3278 struct wqe_did wqe_dest;
3279 struct wqe_common wqe_com; /* words 6-11 */
3281 #define wqe_rsp_temp_rpi_SHIFT 0
3282 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
3283 #define wqe_rsp_temp_rpi_WORD word12
3284 uint32_t rsvd_13_15[3];
3287 struct xmit_bls_rsp64_wqe {
3289 /* Payload0 for BA_ACC */
3290 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16
3291 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
3292 #define xmit_bls_rsp64_acc_seq_id_WORD payload0
3293 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
3294 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
3295 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
3296 /* Payload0 for BA_RJT */
3297 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
3298 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
3299 #define xmit_bls_rsp64_rjt_vspec_WORD payload0
3300 #define xmit_bls_rsp64_rjt_expc_SHIFT 8
3301 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
3302 #define xmit_bls_rsp64_rjt_expc_WORD payload0
3303 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
3304 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
3305 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0
3307 #define xmit_bls_rsp64_rxid_SHIFT 0
3308 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
3309 #define xmit_bls_rsp64_rxid_WORD word1
3310 #define xmit_bls_rsp64_oxid_SHIFT 16
3311 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
3312 #define xmit_bls_rsp64_oxid_WORD word1
3314 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
3315 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
3316 #define xmit_bls_rsp64_seqcnthi_WORD word2
3317 #define xmit_bls_rsp64_seqcntlo_SHIFT 16
3318 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
3319 #define xmit_bls_rsp64_seqcntlo_WORD word2
3322 struct wqe_did wqe_dest;
3323 struct wqe_common wqe_com; /* words 6-11 */
3325 #define xmit_bls_rsp64_temprpi_SHIFT 0
3326 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
3327 #define xmit_bls_rsp64_temprpi_WORD word12
3328 uint32_t rsvd_13_15[3];
3331 struct wqe_rctl_dfctl {
3333 #define wqe_si_SHIFT 2
3334 #define wqe_si_MASK 0x000000001
3335 #define wqe_si_WORD word5
3336 #define wqe_la_SHIFT 3
3337 #define wqe_la_MASK 0x000000001
3338 #define wqe_la_WORD word5
3339 #define wqe_xo_SHIFT 6
3340 #define wqe_xo_MASK 0x000000001
3341 #define wqe_xo_WORD word5
3342 #define wqe_ls_SHIFT 7
3343 #define wqe_ls_MASK 0x000000001
3344 #define wqe_ls_WORD word5
3345 #define wqe_dfctl_SHIFT 8
3346 #define wqe_dfctl_MASK 0x0000000ff
3347 #define wqe_dfctl_WORD word5
3348 #define wqe_type_SHIFT 16
3349 #define wqe_type_MASK 0x0000000ff
3350 #define wqe_type_WORD word5
3351 #define wqe_rctl_SHIFT 24
3352 #define wqe_rctl_MASK 0x0000000ff
3353 #define wqe_rctl_WORD word5
3356 struct xmit_seq64_wqe {
3357 struct ulp_bde64 bde;
3359 uint32_t relative_offset;
3360 struct wqe_rctl_dfctl wge_ctl;
3361 struct wqe_common wqe_com; /* words 6-11 */
3363 uint32_t rsvd_12_15[3];
3365 struct xmit_bcast64_wqe {
3366 struct ulp_bde64 bde;
3367 uint32_t seq_payload_len;
3369 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3370 struct wqe_common wqe_com; /* words 6-11 */
3371 uint32_t rsvd_12_15[4];
3374 struct gen_req64_wqe {
3375 struct ulp_bde64 bde;
3376 uint32_t request_payload_len;
3377 uint32_t relative_offset;
3378 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3379 struct wqe_common wqe_com; /* words 6-11 */
3380 uint32_t rsvd_12_15[4];
3383 struct create_xri_wqe {
3384 uint32_t rsrvd[5]; /* words 0-4 */
3385 struct wqe_did wqe_dest; /* word 5 */
3386 struct wqe_common wqe_com; /* words 6-11 */
3387 uint32_t rsvd_12_15[4]; /* word 12-15 */
3390 #define T_REQUEST_TAG 3
3393 struct abort_cmd_wqe {
3396 #define abort_cmd_ia_SHIFT 0
3397 #define abort_cmd_ia_MASK 0x000000001
3398 #define abort_cmd_ia_WORD word3
3399 #define abort_cmd_criteria_SHIFT 8
3400 #define abort_cmd_criteria_MASK 0x0000000ff
3401 #define abort_cmd_criteria_WORD word3
3404 struct wqe_common wqe_com; /* words 6-11 */
3405 uint32_t rsvd_12_15[4]; /* word 12-15 */
3408 struct fcp_iwrite64_wqe {
3409 struct ulp_bde64 bde;
3410 uint32_t payload_offset_len;
3411 uint32_t total_xfer_len;
3412 uint32_t initial_xfer_len;
3413 struct wqe_common wqe_com; /* words 6-11 */
3415 struct ulp_bde64 ph_bde; /* words 13-15 */
3418 struct fcp_iread64_wqe {
3419 struct ulp_bde64 bde;
3420 uint32_t payload_offset_len; /* word 3 */
3421 uint32_t total_xfer_len; /* word 4 */
3422 uint32_t rsrvd5; /* word 5 */
3423 struct wqe_common wqe_com; /* words 6-11 */
3425 struct ulp_bde64 ph_bde; /* words 13-15 */
3428 struct fcp_icmnd64_wqe {
3429 struct ulp_bde64 bde; /* words 0-2 */
3430 uint32_t rsrvd3; /* word 3 */
3431 uint32_t rsrvd4; /* word 4 */
3432 uint32_t rsrvd5; /* word 5 */
3433 struct wqe_common wqe_com; /* words 6-11 */
3434 uint32_t rsvd_12_15[4]; /* word 12-15 */
3440 struct lpfc_wqe_generic generic;
3441 struct fcp_icmnd64_wqe fcp_icmd;
3442 struct fcp_iread64_wqe fcp_iread;
3443 struct fcp_iwrite64_wqe fcp_iwrite;
3444 struct abort_cmd_wqe abort_cmd;
3445 struct create_xri_wqe create_xri;
3446 struct xmit_bcast64_wqe xmit_bcast64;
3447 struct xmit_seq64_wqe xmit_sequence;
3448 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
3449 struct xmit_els_rsp64_wqe xmit_els_rsp;
3450 struct els_request64_wqe els_req;
3451 struct gen_req64_wqe gen_req;
3454 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001
3455 #define LPFC_FILE_TYPE_GROUP 0xf7
3456 #define LPFC_FILE_ID_GROUP 0xa2
3457 struct lpfc_grp_hdr {
3459 uint32_t magic_number;
3461 #define lpfc_grp_hdr_file_type_SHIFT 24
3462 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
3463 #define lpfc_grp_hdr_file_type_WORD word2
3464 #define lpfc_grp_hdr_id_SHIFT 16
3465 #define lpfc_grp_hdr_id_MASK 0x000000FF
3466 #define lpfc_grp_hdr_id_WORD word2
3467 uint8_t rev_name[128];
3469 uint8_t revision[32];
3472 #define FCP_COMMAND 0x0
3473 #define FCP_COMMAND_DATA_OUT 0x1
3474 #define ELS_COMMAND_NON_FIP 0xC
3475 #define ELS_COMMAND_FIP 0xD
3476 #define OTHER_COMMAND 0x8
3478 #define LPFC_FW_DUMP 1
3479 #define LPFC_FW_RESET 2
3480 #define LPFC_DV_RESET 3