1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2009 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
22 * associated with it (_SHIFT, _MASK, and _WORD).
23 * EG. For a bit field that is in the 7th bit of the "field4" field of a
24 * structure and is 2 bits in size the following #defines must exist:
30 * #define example_bit_field_SHIFT 7
31 * #define example_bit_field_MASK 0x03
32 * #define example_bit_field_WORD field4
35 * Then the macros below may be used to get or set the value of that field.
36 * EG. To get the value of the bit field from the above example:
38 * value = bf_get(example_bit_field, &t1);
39 * And then to set that bit field:
40 * bf_set(example_bit_field, &t1, 2);
41 * Or clear that bit field:
42 * bf_set(example_bit_field, &t1, 0);
44 #define bf_get(name, ptr) \
45 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
46 #define bf_set(name, ptr, value) \
47 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
48 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
55 #define LPFC_SLIREV_CONF_WORD 0x58
56 struct lpfc_sli_intf {
58 #define lpfc_sli_intf_iftype_MASK 0x00000007
59 #define lpfc_sli_intf_iftype_SHIFT 0
60 #define lpfc_sli_intf_iftype_WORD word0
61 #define lpfc_sli_intf_rev_MASK 0x0000000f
62 #define lpfc_sli_intf_rev_SHIFT 4
63 #define lpfc_sli_intf_rev_WORD word0
64 #define LPFC_SLIREV_CONF_SLI4 4
65 #define lpfc_sli_intf_family_MASK 0x000000ff
66 #define lpfc_sli_intf_family_SHIFT 8
67 #define lpfc_sli_intf_family_WORD word0
68 #define lpfc_sli_intf_feat1_MASK 0x000000ff
69 #define lpfc_sli_intf_feat1_SHIFT 16
70 #define lpfc_sli_intf_feat1_WORD word0
71 #define lpfc_sli_intf_feat2_MASK 0x0000001f
72 #define lpfc_sli_intf_feat2_SHIFT 24
73 #define lpfc_sli_intf_feat2_WORD word0
74 #define lpfc_sli_intf_valid_MASK 0x00000007
75 #define lpfc_sli_intf_valid_SHIFT 29
76 #define lpfc_sli_intf_valid_WORD word0
77 #define LPFC_SLI_INTF_VALID 6
80 #define LPFC_SLI4_BAR0 1
81 #define LPFC_SLI4_BAR1 2
82 #define LPFC_SLI4_BAR2 4
84 #define LPFC_SLI4_MBX_EMBED true
85 #define LPFC_SLI4_MBX_NEMBED false
87 #define LPFC_SLI4_MB_WORD_COUNT 64
88 #define LPFC_MAX_MQ_PAGE 8
89 #define LPFC_MAX_WQ_PAGE 8
90 #define LPFC_MAX_CQ_PAGE 4
91 #define LPFC_MAX_EQ_PAGE 8
93 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
94 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
95 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
97 /* Define SLI4 Alignment requirements. */
98 #define LPFC_ALIGN_16_BYTE 16
99 #define LPFC_ALIGN_64_BYTE 64
101 /* Define SLI4 specific definitions. */
102 #define LPFC_MQ_CQE_BYTE_OFFSET 256
103 #define LPFC_MBX_CMD_HDR_LENGTH 16
104 #define LPFC_MBX_ERROR_RANGE 0x4000
105 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
106 #define LPFC_BMBX_BIT1_ADDR_LO 0
107 #define LPFC_RPI_HDR_COUNT 64
108 #define LPFC_HDR_TEMPLATE_SIZE 4096
109 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
110 #define LPFC_FCF_RECORD_WD_CNT 132
111 #define LPFC_ENTIRE_FCF_DATABASE 0
112 #define LPFC_DFLT_FCF_INDEX 0
114 /* Virtual function numbers */
148 /* PCI function numbers */
149 #define LPFC_PCI_FUNC0 0
150 #define LPFC_PCI_FUNC1 1
151 #define LPFC_PCI_FUNC2 2
152 #define LPFC_PCI_FUNC3 3
153 #define LPFC_PCI_FUNC4 4
155 /* Active interrupt test count */
156 #define LPFC_ACT_INTR_CNT 4
158 /* Delay Multiplier constant */
159 #define LPFC_DMULT_CONST 651042
160 #define LPFC_MIM_IMAX 636
161 #define LPFC_FP_DEF_IMAX 10000
162 #define LPFC_SP_DEF_IMAX 10000
168 #ifdef __BIG_ENDIAN_BITFIELD
169 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
171 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
172 #else /* __LITTLE_ENDIAN_BITFIELD */
173 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
174 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
177 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
178 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
179 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
180 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
181 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
182 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
183 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
190 struct lpfc_sli4_flags {
192 #define lpfc_fip_flag_SHIFT 0
193 #define lpfc_fip_flag_MASK 0x00000001
194 #define lpfc_fip_flag_WORD word0
197 /* event queue entry structure */
200 #define lpfc_eqe_resource_id_SHIFT 16
201 #define lpfc_eqe_resource_id_MASK 0x000000FF
202 #define lpfc_eqe_resource_id_WORD word0
203 #define lpfc_eqe_minor_code_SHIFT 4
204 #define lpfc_eqe_minor_code_MASK 0x00000FFF
205 #define lpfc_eqe_minor_code_WORD word0
206 #define lpfc_eqe_major_code_SHIFT 1
207 #define lpfc_eqe_major_code_MASK 0x00000007
208 #define lpfc_eqe_major_code_WORD word0
209 #define lpfc_eqe_valid_SHIFT 0
210 #define lpfc_eqe_valid_MASK 0x00000001
211 #define lpfc_eqe_valid_WORD word0
214 /* completion queue entry structure (common fields for all cqe types) */
220 #define lpfc_cqe_valid_SHIFT 31
221 #define lpfc_cqe_valid_MASK 0x00000001
222 #define lpfc_cqe_valid_WORD word3
223 #define lpfc_cqe_code_SHIFT 16
224 #define lpfc_cqe_code_MASK 0x000000FF
225 #define lpfc_cqe_code_WORD word3
228 /* Completion Queue Entry Status Codes */
229 #define CQE_STATUS_SUCCESS 0x0
230 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
231 #define CQE_STATUS_REMOTE_STOP 0x2
232 #define CQE_STATUS_LOCAL_REJECT 0x3
233 #define CQE_STATUS_NPORT_RJT 0x4
234 #define CQE_STATUS_FABRIC_RJT 0x5
235 #define CQE_STATUS_NPORT_BSY 0x6
236 #define CQE_STATUS_FABRIC_BSY 0x7
237 #define CQE_STATUS_INTERMED_RSP 0x8
238 #define CQE_STATUS_LS_RJT 0x9
239 #define CQE_STATUS_CMD_REJECT 0xb
240 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
241 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
243 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
244 #define CQE_HW_STATUS_NO_ERR 0x0
245 #define CQE_HW_STATUS_UNDERRUN 0x1
246 #define CQE_HW_STATUS_OVERRUN 0x2
248 /* Completion Queue Entry Codes */
249 #define CQE_CODE_COMPL_WQE 0x1
250 #define CQE_CODE_RELEASE_WQE 0x2
251 #define CQE_CODE_RECEIVE 0x4
252 #define CQE_CODE_XRI_ABORTED 0x5
254 /* completion queue entry for wqe completions */
255 struct lpfc_wcqe_complete {
257 #define lpfc_wcqe_c_request_tag_SHIFT 16
258 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
259 #define lpfc_wcqe_c_request_tag_WORD word0
260 #define lpfc_wcqe_c_status_SHIFT 8
261 #define lpfc_wcqe_c_status_MASK 0x000000FF
262 #define lpfc_wcqe_c_status_WORD word0
263 #define lpfc_wcqe_c_hw_status_SHIFT 0
264 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
265 #define lpfc_wcqe_c_hw_status_WORD word0
266 uint32_t total_data_placed;
269 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
270 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
271 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
272 #define lpfc_wcqe_c_xb_SHIFT 28
273 #define lpfc_wcqe_c_xb_MASK 0x00000001
274 #define lpfc_wcqe_c_xb_WORD word3
275 #define lpfc_wcqe_c_pv_SHIFT 27
276 #define lpfc_wcqe_c_pv_MASK 0x00000001
277 #define lpfc_wcqe_c_pv_WORD word3
278 #define lpfc_wcqe_c_priority_SHIFT 24
279 #define lpfc_wcqe_c_priority_MASK 0x00000007
280 #define lpfc_wcqe_c_priority_WORD word3
281 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
282 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
283 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
286 /* completion queue entry for wqe release */
287 struct lpfc_wcqe_release {
291 #define lpfc_wcqe_r_wq_id_SHIFT 16
292 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
293 #define lpfc_wcqe_r_wq_id_WORD word2
294 #define lpfc_wcqe_r_wqe_index_SHIFT 0
295 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
296 #define lpfc_wcqe_r_wqe_index_WORD word2
298 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
299 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
300 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
301 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
302 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
303 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
306 struct sli4_wcqe_xri_aborted {
308 #define lpfc_wcqe_xa_status_SHIFT 8
309 #define lpfc_wcqe_xa_status_MASK 0x000000FF
310 #define lpfc_wcqe_xa_status_WORD word0
313 #define lpfc_wcqe_xa_remote_xid_SHIFT 16
314 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
315 #define lpfc_wcqe_xa_remote_xid_WORD word2
316 #define lpfc_wcqe_xa_xri_SHIFT 0
317 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
318 #define lpfc_wcqe_xa_xri_WORD word2
320 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
321 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
322 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
323 #define lpfc_wcqe_xa_ia_SHIFT 30
324 #define lpfc_wcqe_xa_ia_MASK 0x00000001
325 #define lpfc_wcqe_xa_ia_WORD word3
326 #define CQE_XRI_ABORTED_IA_REMOTE 0
327 #define CQE_XRI_ABORTED_IA_LOCAL 1
328 #define lpfc_wcqe_xa_br_SHIFT 29
329 #define lpfc_wcqe_xa_br_MASK 0x00000001
330 #define lpfc_wcqe_xa_br_WORD word3
331 #define CQE_XRI_ABORTED_BR_BA_ACC 0
332 #define CQE_XRI_ABORTED_BR_BA_RJT 1
333 #define lpfc_wcqe_xa_eo_SHIFT 28
334 #define lpfc_wcqe_xa_eo_MASK 0x00000001
335 #define lpfc_wcqe_xa_eo_WORD word3
336 #define CQE_XRI_ABORTED_EO_REMOTE 0
337 #define CQE_XRI_ABORTED_EO_LOCAL 1
338 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
339 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
340 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
343 /* completion queue entry structure for rqe completion */
346 #define lpfc_rcqe_bindex_SHIFT 16
347 #define lpfc_rcqe_bindex_MASK 0x0000FFF
348 #define lpfc_rcqe_bindex_WORD word0
349 #define lpfc_rcqe_status_SHIFT 8
350 #define lpfc_rcqe_status_MASK 0x000000FF
351 #define lpfc_rcqe_status_WORD word0
352 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
353 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
354 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
355 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
358 #define lpfc_rcqe_length_SHIFT 16
359 #define lpfc_rcqe_length_MASK 0x0000FFFF
360 #define lpfc_rcqe_length_WORD word2
361 #define lpfc_rcqe_rq_id_SHIFT 6
362 #define lpfc_rcqe_rq_id_MASK 0x000003FF
363 #define lpfc_rcqe_rq_id_WORD word2
364 #define lpfc_rcqe_fcf_id_SHIFT 0
365 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
366 #define lpfc_rcqe_fcf_id_WORD word2
368 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
369 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
370 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
371 #define lpfc_rcqe_port_SHIFT 30
372 #define lpfc_rcqe_port_MASK 0x00000001
373 #define lpfc_rcqe_port_WORD word3
374 #define lpfc_rcqe_hdr_length_SHIFT 24
375 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
376 #define lpfc_rcqe_hdr_length_WORD word3
377 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
378 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
379 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
380 #define lpfc_rcqe_eof_SHIFT 8
381 #define lpfc_rcqe_eof_MASK 0x000000FF
382 #define lpfc_rcqe_eof_WORD word3
383 #define FCOE_EOFn 0x41
384 #define FCOE_EOFt 0x42
385 #define FCOE_EOFni 0x49
386 #define FCOE_EOFa 0x50
387 #define lpfc_rcqe_sof_SHIFT 0
388 #define lpfc_rcqe_sof_MASK 0x000000FF
389 #define lpfc_rcqe_sof_WORD word3
390 #define FCOE_SOFi2 0x2d
391 #define FCOE_SOFi3 0x2e
392 #define FCOE_SOFn2 0x35
393 #define FCOE_SOFn3 0x36
396 struct lpfc_wqe_generic{
397 struct ulp_bde64 bde;
402 #define lpfc_wqe_gen_context_SHIFT 16
403 #define lpfc_wqe_gen_context_MASK 0x0000FFFF
404 #define lpfc_wqe_gen_context_WORD word6
405 #define lpfc_wqe_gen_xri_SHIFT 0
406 #define lpfc_wqe_gen_xri_MASK 0x0000FFFF
407 #define lpfc_wqe_gen_xri_WORD word6
409 #define lpfc_wqe_gen_lnk_SHIFT 23
410 #define lpfc_wqe_gen_lnk_MASK 0x00000001
411 #define lpfc_wqe_gen_lnk_WORD word7
412 #define lpfc_wqe_gen_erp_SHIFT 22
413 #define lpfc_wqe_gen_erp_MASK 0x00000001
414 #define lpfc_wqe_gen_erp_WORD word7
415 #define lpfc_wqe_gen_pu_SHIFT 20
416 #define lpfc_wqe_gen_pu_MASK 0x00000003
417 #define lpfc_wqe_gen_pu_WORD word7
418 #define lpfc_wqe_gen_class_SHIFT 16
419 #define lpfc_wqe_gen_class_MASK 0x00000007
420 #define lpfc_wqe_gen_class_WORD word7
421 #define lpfc_wqe_gen_command_SHIFT 8
422 #define lpfc_wqe_gen_command_MASK 0x000000FF
423 #define lpfc_wqe_gen_command_WORD word7
424 #define lpfc_wqe_gen_status_SHIFT 4
425 #define lpfc_wqe_gen_status_MASK 0x0000000F
426 #define lpfc_wqe_gen_status_WORD word7
427 #define lpfc_wqe_gen_ct_SHIFT 2
428 #define lpfc_wqe_gen_ct_MASK 0x00000003
429 #define lpfc_wqe_gen_ct_WORD word7
432 #define lpfc_wqe_gen_request_tag_SHIFT 0
433 #define lpfc_wqe_gen_request_tag_MASK 0x0000FFFF
434 #define lpfc_wqe_gen_request_tag_WORD word9
436 #define lpfc_wqe_gen_ccp_SHIFT 24
437 #define lpfc_wqe_gen_ccp_MASK 0x000000FF
438 #define lpfc_wqe_gen_ccp_WORD word10
439 #define lpfc_wqe_gen_ccpe_SHIFT 23
440 #define lpfc_wqe_gen_ccpe_MASK 0x00000001
441 #define lpfc_wqe_gen_ccpe_WORD word10
442 #define lpfc_wqe_gen_pv_SHIFT 19
443 #define lpfc_wqe_gen_pv_MASK 0x00000001
444 #define lpfc_wqe_gen_pv_WORD word10
445 #define lpfc_wqe_gen_pri_SHIFT 16
446 #define lpfc_wqe_gen_pri_MASK 0x00000007
447 #define lpfc_wqe_gen_pri_WORD word10
449 #define lpfc_wqe_gen_cq_id_SHIFT 16
450 #define lpfc_wqe_gen_cq_id_MASK 0x0000FFFF
451 #define lpfc_wqe_gen_cq_id_WORD word11
452 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
453 #define lpfc_wqe_gen_wqec_SHIFT 7
454 #define lpfc_wqe_gen_wqec_MASK 0x00000001
455 #define lpfc_wqe_gen_wqec_WORD word11
456 #define ELS_ID_FLOGI 3
457 #define ELS_ID_FDISC 2
458 #define ELS_ID_LOGO 1
459 #define ELS_ID_DEFAULT 0
460 #define lpfc_wqe_gen_els_id_SHIFT 4
461 #define lpfc_wqe_gen_els_id_MASK 0x00000003
462 #define lpfc_wqe_gen_els_id_WORD word11
463 #define lpfc_wqe_gen_cmd_type_SHIFT 0
464 #define lpfc_wqe_gen_cmd_type_MASK 0x0000000F
465 #define lpfc_wqe_gen_cmd_type_WORD word11
474 /* buffer descriptors */
479 #define lpfc_bde4_last_SHIFT 31
480 #define lpfc_bde4_last_MASK 0x00000001
481 #define lpfc_bde4_last_WORD word2
482 #define lpfc_bde4_sge_offset_SHIFT 0
483 #define lpfc_bde4_sge_offset_MASK 0x000003FF
484 #define lpfc_bde4_sge_offset_WORD word2
486 #define lpfc_bde4_length_SHIFT 0
487 #define lpfc_bde4_length_MASK 0x000000FF
488 #define lpfc_bde4_length_WORD word3
491 struct lpfc_register {
495 #define LPFC_UERR_STATUS_HI 0x00A4
496 #define LPFC_UERR_STATUS_LO 0x00A0
497 #define LPFC_ONLINE0 0x00B0
498 #define LPFC_ONLINE1 0x00B4
499 #define LPFC_SCRATCHPAD 0x0058
502 #define LPFC_HST_STATE 0x00AC
503 #define lpfc_hst_state_perr_SHIFT 31
504 #define lpfc_hst_state_perr_MASK 0x1
505 #define lpfc_hst_state_perr_WORD word0
506 #define lpfc_hst_state_sfi_SHIFT 30
507 #define lpfc_hst_state_sfi_MASK 0x1
508 #define lpfc_hst_state_sfi_WORD word0
509 #define lpfc_hst_state_nip_SHIFT 29
510 #define lpfc_hst_state_nip_MASK 0x1
511 #define lpfc_hst_state_nip_WORD word0
512 #define lpfc_hst_state_ipc_SHIFT 28
513 #define lpfc_hst_state_ipc_MASK 0x1
514 #define lpfc_hst_state_ipc_WORD word0
515 #define lpfc_hst_state_xrom_SHIFT 27
516 #define lpfc_hst_state_xrom_MASK 0x1
517 #define lpfc_hst_state_xrom_WORD word0
518 #define lpfc_hst_state_dl_SHIFT 26
519 #define lpfc_hst_state_dl_MASK 0x1
520 #define lpfc_hst_state_dl_WORD word0
521 #define lpfc_hst_state_port_status_SHIFT 0
522 #define lpfc_hst_state_port_status_MASK 0xFFFF
523 #define lpfc_hst_state_port_status_WORD word0
525 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
526 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
527 #define LPFC_POST_STAGE_HOST_RDY 0x0002
528 #define LPFC_POST_STAGE_BE_RESET 0x0003
529 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
530 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
531 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
532 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
533 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
534 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
535 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
536 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
537 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
538 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
539 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
540 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
541 #define LPFC_POST_STAGE_ARMFW_START 0x0800
542 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
543 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
544 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
545 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
546 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
547 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
548 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
549 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
550 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
551 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
552 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
553 #define LPFC_POST_STAGE_RC_DONE 0x0B07
554 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
555 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
556 #define LPFC_POST_STAGE_ARMFW_READY 0xC000
557 #define LPFC_POST_STAGE_ARMFW_UE 0xF000
559 #define lpfc_scratchpad_slirev_SHIFT 4
560 #define lpfc_scratchpad_slirev_MASK 0xF
561 #define lpfc_scratchpad_slirev_WORD word0
562 #define lpfc_scratchpad_chiptype_SHIFT 8
563 #define lpfc_scratchpad_chiptype_MASK 0xFF
564 #define lpfc_scratchpad_chiptype_WORD word0
565 #define lpfc_scratchpad_featurelevel1_SHIFT 16
566 #define lpfc_scratchpad_featurelevel1_MASK 0xFF
567 #define lpfc_scratchpad_featurelevel1_WORD word0
568 #define lpfc_scratchpad_featurelevel2_SHIFT 24
569 #define lpfc_scratchpad_featurelevel2_MASK 0xFF
570 #define lpfc_scratchpad_featurelevel2_WORD word0
573 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
574 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
576 #define LPFC_HST_ISR0 0x0C18
577 #define LPFC_HST_ISR1 0x0C1C
578 #define LPFC_HST_ISR2 0x0C20
579 #define LPFC_HST_ISR3 0x0C24
580 #define LPFC_HST_ISR4 0x0C28
582 #define LPFC_HST_IMR0 0x0C48
583 #define LPFC_HST_IMR1 0x0C4C
584 #define LPFC_HST_IMR2 0x0C50
585 #define LPFC_HST_IMR3 0x0C54
586 #define LPFC_HST_IMR4 0x0C58
588 #define LPFC_HST_ISCR0 0x0C78
589 #define LPFC_HST_ISCR1 0x0C7C
590 #define LPFC_HST_ISCR2 0x0C80
591 #define LPFC_HST_ISCR3 0x0C84
592 #define LPFC_HST_ISCR4 0x0C88
594 #define LPFC_SLI4_INTR0 BIT0
595 #define LPFC_SLI4_INTR1 BIT1
596 #define LPFC_SLI4_INTR2 BIT2
597 #define LPFC_SLI4_INTR3 BIT3
598 #define LPFC_SLI4_INTR4 BIT4
599 #define LPFC_SLI4_INTR5 BIT5
600 #define LPFC_SLI4_INTR6 BIT6
601 #define LPFC_SLI4_INTR7 BIT7
602 #define LPFC_SLI4_INTR8 BIT8
603 #define LPFC_SLI4_INTR9 BIT9
604 #define LPFC_SLI4_INTR10 BIT10
605 #define LPFC_SLI4_INTR11 BIT11
606 #define LPFC_SLI4_INTR12 BIT12
607 #define LPFC_SLI4_INTR13 BIT13
608 #define LPFC_SLI4_INTR14 BIT14
609 #define LPFC_SLI4_INTR15 BIT15
610 #define LPFC_SLI4_INTR16 BIT16
611 #define LPFC_SLI4_INTR17 BIT17
612 #define LPFC_SLI4_INTR18 BIT18
613 #define LPFC_SLI4_INTR19 BIT19
614 #define LPFC_SLI4_INTR20 BIT20
615 #define LPFC_SLI4_INTR21 BIT21
616 #define LPFC_SLI4_INTR22 BIT22
617 #define LPFC_SLI4_INTR23 BIT23
618 #define LPFC_SLI4_INTR24 BIT24
619 #define LPFC_SLI4_INTR25 BIT25
620 #define LPFC_SLI4_INTR26 BIT26
621 #define LPFC_SLI4_INTR27 BIT27
622 #define LPFC_SLI4_INTR28 BIT28
623 #define LPFC_SLI4_INTR29 BIT29
624 #define LPFC_SLI4_INTR30 BIT30
625 #define LPFC_SLI4_INTR31 BIT31
628 #define LPFC_RQ_DOORBELL 0x00A0
629 #define lpfc_rq_doorbell_num_posted_SHIFT 16
630 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF
631 #define lpfc_rq_doorbell_num_posted_WORD word0
632 #define LPFC_RQ_POST_BATCH 8 /* RQEs to post at one time */
633 #define lpfc_rq_doorbell_id_SHIFT 0
634 #define lpfc_rq_doorbell_id_MASK 0x03FF
635 #define lpfc_rq_doorbell_id_WORD word0
637 #define LPFC_WQ_DOORBELL 0x0040
638 #define lpfc_wq_doorbell_num_posted_SHIFT 24
639 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF
640 #define lpfc_wq_doorbell_num_posted_WORD word0
641 #define lpfc_wq_doorbell_index_SHIFT 16
642 #define lpfc_wq_doorbell_index_MASK 0x00FF
643 #define lpfc_wq_doorbell_index_WORD word0
644 #define lpfc_wq_doorbell_id_SHIFT 0
645 #define lpfc_wq_doorbell_id_MASK 0xFFFF
646 #define lpfc_wq_doorbell_id_WORD word0
648 #define LPFC_EQCQ_DOORBELL 0x0120
649 #define lpfc_eqcq_doorbell_arm_SHIFT 29
650 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
651 #define lpfc_eqcq_doorbell_arm_WORD word0
652 #define lpfc_eqcq_doorbell_num_released_SHIFT 16
653 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
654 #define lpfc_eqcq_doorbell_num_released_WORD word0
655 #define lpfc_eqcq_doorbell_qt_SHIFT 10
656 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
657 #define lpfc_eqcq_doorbell_qt_WORD word0
658 #define LPFC_QUEUE_TYPE_COMPLETION 0
659 #define LPFC_QUEUE_TYPE_EVENT 1
660 #define lpfc_eqcq_doorbell_eqci_SHIFT 9
661 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
662 #define lpfc_eqcq_doorbell_eqci_WORD word0
663 #define lpfc_eqcq_doorbell_cqid_SHIFT 0
664 #define lpfc_eqcq_doorbell_cqid_MASK 0x03FF
665 #define lpfc_eqcq_doorbell_cqid_WORD word0
666 #define lpfc_eqcq_doorbell_eqid_SHIFT 0
667 #define lpfc_eqcq_doorbell_eqid_MASK 0x01FF
668 #define lpfc_eqcq_doorbell_eqid_WORD word0
670 #define LPFC_BMBX 0x0160
671 #define lpfc_bmbx_addr_SHIFT 2
672 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
673 #define lpfc_bmbx_addr_WORD word0
674 #define lpfc_bmbx_hi_SHIFT 1
675 #define lpfc_bmbx_hi_MASK 0x0001
676 #define lpfc_bmbx_hi_WORD word0
677 #define lpfc_bmbx_rdy_SHIFT 0
678 #define lpfc_bmbx_rdy_MASK 0x0001
679 #define lpfc_bmbx_rdy_WORD word0
681 #define LPFC_MQ_DOORBELL 0x0140
682 #define lpfc_mq_doorbell_num_posted_SHIFT 16
683 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
684 #define lpfc_mq_doorbell_num_posted_WORD word0
685 #define lpfc_mq_doorbell_id_SHIFT 0
686 #define lpfc_mq_doorbell_id_MASK 0x03FF
687 #define lpfc_mq_doorbell_id_WORD word0
689 struct lpfc_sli4_cfg_mhdr {
691 #define lpfc_mbox_hdr_emb_SHIFT 0
692 #define lpfc_mbox_hdr_emb_MASK 0x00000001
693 #define lpfc_mbox_hdr_emb_WORD word1
694 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3
695 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
696 #define lpfc_mbox_hdr_sge_cnt_WORD word1
697 uint32_t payload_length;
703 union lpfc_sli4_cfg_shdr {
706 #define lpfc_mbox_hdr_opcode_SHIFT 0
707 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
708 #define lpfc_mbox_hdr_opcode_WORD word6
709 #define lpfc_mbox_hdr_subsystem_SHIFT 8
710 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
711 #define lpfc_mbox_hdr_subsystem_WORD word6
712 #define lpfc_mbox_hdr_port_number_SHIFT 16
713 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
714 #define lpfc_mbox_hdr_port_number_WORD word6
715 #define lpfc_mbox_hdr_domain_SHIFT 24
716 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
717 #define lpfc_mbox_hdr_domain_WORD word6
719 uint32_t request_length;
724 #define lpfc_mbox_hdr_opcode_SHIFT 0
725 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
726 #define lpfc_mbox_hdr_opcode_WORD word6
727 #define lpfc_mbox_hdr_subsystem_SHIFT 8
728 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
729 #define lpfc_mbox_hdr_subsystem_WORD word6
730 #define lpfc_mbox_hdr_domain_SHIFT 24
731 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
732 #define lpfc_mbox_hdr_domain_WORD word6
734 #define lpfc_mbox_hdr_status_SHIFT 0
735 #define lpfc_mbox_hdr_status_MASK 0x000000FF
736 #define lpfc_mbox_hdr_status_WORD word7
737 #define lpfc_mbox_hdr_add_status_SHIFT 8
738 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
739 #define lpfc_mbox_hdr_add_status_WORD word7
740 uint32_t response_length;
741 uint32_t actual_response_length;
745 /* Mailbox structures */
747 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
748 union lpfc_sli4_cfg_shdr cfg_shdr;
751 /* Subsystem Definitions */
752 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
753 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
755 /* Device Specific Definitions */
757 /* The HOST ENDIAN defines are in Big Endian format. */
758 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
759 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
762 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
763 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
764 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
765 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
766 #define LPFC_MBOX_OPCODE_NOP 0x21
767 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
768 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
769 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
770 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
771 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
774 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
775 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
776 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
777 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
778 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
779 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
780 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
781 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
782 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
783 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
785 /* Mailbox command structures */
788 #define lpfc_eq_context_size_SHIFT 31
789 #define lpfc_eq_context_size_MASK 0x00000001
790 #define lpfc_eq_context_size_WORD word0
791 #define LPFC_EQE_SIZE_4 0x0
792 #define LPFC_EQE_SIZE_16 0x1
793 #define lpfc_eq_context_valid_SHIFT 29
794 #define lpfc_eq_context_valid_MASK 0x00000001
795 #define lpfc_eq_context_valid_WORD word0
797 #define lpfc_eq_context_count_SHIFT 26
798 #define lpfc_eq_context_count_MASK 0x00000003
799 #define lpfc_eq_context_count_WORD word1
800 #define LPFC_EQ_CNT_256 0x0
801 #define LPFC_EQ_CNT_512 0x1
802 #define LPFC_EQ_CNT_1024 0x2
803 #define LPFC_EQ_CNT_2048 0x3
804 #define LPFC_EQ_CNT_4096 0x4
806 #define lpfc_eq_context_delay_multi_SHIFT 13
807 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
808 #define lpfc_eq_context_delay_multi_WORD word2
812 struct sgl_page_pairs {
813 uint32_t sgl_pg0_addr_lo;
814 uint32_t sgl_pg0_addr_hi;
815 uint32_t sgl_pg1_addr_lo;
816 uint32_t sgl_pg1_addr_hi;
819 struct lpfc_mbx_post_sgl_pages {
820 struct mbox_header header;
822 #define lpfc_post_sgl_pages_xri_SHIFT 0
823 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
824 #define lpfc_post_sgl_pages_xri_WORD word0
825 #define lpfc_post_sgl_pages_xricnt_SHIFT 16
826 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
827 #define lpfc_post_sgl_pages_xricnt_WORD word0
828 struct sgl_page_pairs sgl_pg_pairs[1];
831 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
832 struct lpfc_mbx_post_uembed_sgl_page1 {
833 union lpfc_sli4_cfg_shdr cfg_shdr;
835 struct sgl_page_pairs sgl_pg_pairs;
838 struct lpfc_mbx_sge {
844 struct lpfc_mbx_nembed_cmd {
845 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
846 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
847 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
850 struct lpfc_mbx_nembed_sge_virt {
851 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
854 struct lpfc_mbx_eq_create {
855 struct mbox_header header;
859 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
860 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
861 #define lpfc_mbx_eq_create_num_pages_WORD word0
862 struct eq_context context;
863 struct dma_address page[LPFC_MAX_EQ_PAGE];
867 #define lpfc_mbx_eq_create_q_id_SHIFT 0
868 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
869 #define lpfc_mbx_eq_create_q_id_WORD word0
874 struct lpfc_mbx_eq_destroy {
875 struct mbox_header header;
879 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
880 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
881 #define lpfc_mbx_eq_destroy_q_id_WORD word0
889 struct lpfc_mbx_nop {
890 struct mbox_header header;
896 #define lpfc_cq_context_event_SHIFT 31
897 #define lpfc_cq_context_event_MASK 0x00000001
898 #define lpfc_cq_context_event_WORD word0
899 #define lpfc_cq_context_valid_SHIFT 29
900 #define lpfc_cq_context_valid_MASK 0x00000001
901 #define lpfc_cq_context_valid_WORD word0
902 #define lpfc_cq_context_count_SHIFT 27
903 #define lpfc_cq_context_count_MASK 0x00000003
904 #define lpfc_cq_context_count_WORD word0
905 #define LPFC_CQ_CNT_256 0x0
906 #define LPFC_CQ_CNT_512 0x1
907 #define LPFC_CQ_CNT_1024 0x2
909 #define lpfc_cq_eq_id_SHIFT 22
910 #define lpfc_cq_eq_id_MASK 0x000000FF
911 #define lpfc_cq_eq_id_WORD word1
916 struct lpfc_mbx_cq_create {
917 struct mbox_header header;
921 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
922 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
923 #define lpfc_mbx_cq_create_num_pages_WORD word0
924 struct cq_context context;
925 struct dma_address page[LPFC_MAX_CQ_PAGE];
929 #define lpfc_mbx_cq_create_q_id_SHIFT 0
930 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
931 #define lpfc_mbx_cq_create_q_id_WORD word0
936 struct lpfc_mbx_cq_destroy {
937 struct mbox_header header;
941 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
942 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
943 #define lpfc_mbx_cq_destroy_q_id_WORD word0
958 struct lpfc_mbx_wq_create {
959 struct mbox_header header;
963 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
964 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF
965 #define lpfc_mbx_wq_create_num_pages_WORD word0
966 #define lpfc_mbx_wq_create_cq_id_SHIFT 16
967 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
968 #define lpfc_mbx_wq_create_cq_id_WORD word0
969 struct dma_address page[LPFC_MAX_WQ_PAGE];
973 #define lpfc_mbx_wq_create_q_id_SHIFT 0
974 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
975 #define lpfc_mbx_wq_create_q_id_WORD word0
980 struct lpfc_mbx_wq_destroy {
981 struct mbox_header header;
985 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
986 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
987 #define lpfc_mbx_wq_destroy_q_id_WORD word0
995 #define LPFC_HDR_BUF_SIZE 128
996 #define LPFC_DATA_BUF_SIZE 4096
999 #define lpfc_rq_context_rq_size_SHIFT 16
1000 #define lpfc_rq_context_rq_size_MASK 0x0000000F
1001 #define lpfc_rq_context_rq_size_WORD word0
1002 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1003 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1004 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1005 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1008 #define lpfc_rq_context_cq_id_SHIFT 16
1009 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1010 #define lpfc_rq_context_cq_id_WORD word2
1011 #define lpfc_rq_context_buf_size_SHIFT 0
1012 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1013 #define lpfc_rq_context_buf_size_WORD word2
1017 struct lpfc_mbx_rq_create {
1018 struct mbox_header header;
1022 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1023 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1024 #define lpfc_mbx_rq_create_num_pages_WORD word0
1025 struct rq_context context;
1026 struct dma_address page[LPFC_MAX_WQ_PAGE];
1030 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1031 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1032 #define lpfc_mbx_rq_create_q_id_WORD word0
1037 struct lpfc_mbx_rq_destroy {
1038 struct mbox_header header;
1042 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1043 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1044 #define lpfc_mbx_rq_destroy_q_id_WORD word0
1054 #define lpfc_mq_context_cq_id_SHIFT 22
1055 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1056 #define lpfc_mq_context_cq_id_WORD word0
1057 #define lpfc_mq_context_count_SHIFT 16
1058 #define lpfc_mq_context_count_MASK 0x0000000F
1059 #define lpfc_mq_context_count_WORD word0
1060 #define LPFC_MQ_CNT_16 0x5
1061 #define LPFC_MQ_CNT_32 0x6
1062 #define LPFC_MQ_CNT_64 0x7
1063 #define LPFC_MQ_CNT_128 0x8
1065 #define lpfc_mq_context_valid_SHIFT 31
1066 #define lpfc_mq_context_valid_MASK 0x00000001
1067 #define lpfc_mq_context_valid_WORD word1
1072 struct lpfc_mbx_mq_create {
1073 struct mbox_header header;
1077 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1078 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1079 #define lpfc_mbx_mq_create_num_pages_WORD word0
1080 struct mq_context context;
1081 struct dma_address page[LPFC_MAX_MQ_PAGE];
1085 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1086 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1087 #define lpfc_mbx_mq_create_q_id_WORD word0
1092 struct lpfc_mbx_mq_destroy {
1093 struct mbox_header header;
1097 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1098 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1099 #define lpfc_mbx_mq_destroy_q_id_WORD word0
1107 struct lpfc_mbx_post_hdr_tmpl {
1108 struct mbox_header header;
1110 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1111 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1112 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
1113 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
1114 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1115 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
1116 uint32_t rpi_paddr_lo;
1117 uint32_t rpi_paddr_hi;
1120 struct sli4_sge { /* SLI-4 */
1125 #define lpfc_sli4_sge_offset_SHIFT 0 /* Offset of buffer - Not used*/
1126 #define lpfc_sli4_sge_offset_MASK 0x00FFFFFF
1127 #define lpfc_sli4_sge_offset_WORD word2
1128 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets
1130 #define lpfc_sli4_sge_last_MASK 0x00000001
1131 #define lpfc_sli4_sge_last_WORD word2
1133 #define lpfc_sli4_sge_len_SHIFT 0
1134 #define lpfc_sli4_sge_len_MASK 0x0001FFFF
1135 #define lpfc_sli4_sge_len_WORD word3
1139 uint32_t max_rcv_size;
1140 uint32_t fka_adv_period;
1141 uint32_t fip_priority;
1143 #define lpfc_fcf_record_mac_0_SHIFT 0
1144 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
1145 #define lpfc_fcf_record_mac_0_WORD word3
1146 #define lpfc_fcf_record_mac_1_SHIFT 8
1147 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
1148 #define lpfc_fcf_record_mac_1_WORD word3
1149 #define lpfc_fcf_record_mac_2_SHIFT 16
1150 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
1151 #define lpfc_fcf_record_mac_2_WORD word3
1152 #define lpfc_fcf_record_mac_3_SHIFT 24
1153 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
1154 #define lpfc_fcf_record_mac_3_WORD word3
1156 #define lpfc_fcf_record_mac_4_SHIFT 0
1157 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
1158 #define lpfc_fcf_record_mac_4_WORD word4
1159 #define lpfc_fcf_record_mac_5_SHIFT 8
1160 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
1161 #define lpfc_fcf_record_mac_5_WORD word4
1162 #define lpfc_fcf_record_fcf_avail_SHIFT 16
1163 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
1164 #define lpfc_fcf_record_fcf_avail_WORD word4
1165 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24
1166 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
1167 #define lpfc_fcf_record_mac_addr_prov_WORD word4
1168 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
1169 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
1171 #define lpfc_fcf_record_fab_name_0_SHIFT 0
1172 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
1173 #define lpfc_fcf_record_fab_name_0_WORD word5
1174 #define lpfc_fcf_record_fab_name_1_SHIFT 8
1175 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
1176 #define lpfc_fcf_record_fab_name_1_WORD word5
1177 #define lpfc_fcf_record_fab_name_2_SHIFT 16
1178 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
1179 #define lpfc_fcf_record_fab_name_2_WORD word5
1180 #define lpfc_fcf_record_fab_name_3_SHIFT 24
1181 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
1182 #define lpfc_fcf_record_fab_name_3_WORD word5
1184 #define lpfc_fcf_record_fab_name_4_SHIFT 0
1185 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
1186 #define lpfc_fcf_record_fab_name_4_WORD word6
1187 #define lpfc_fcf_record_fab_name_5_SHIFT 8
1188 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
1189 #define lpfc_fcf_record_fab_name_5_WORD word6
1190 #define lpfc_fcf_record_fab_name_6_SHIFT 16
1191 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
1192 #define lpfc_fcf_record_fab_name_6_WORD word6
1193 #define lpfc_fcf_record_fab_name_7_SHIFT 24
1194 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
1195 #define lpfc_fcf_record_fab_name_7_WORD word6
1197 #define lpfc_fcf_record_fc_map_0_SHIFT 0
1198 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
1199 #define lpfc_fcf_record_fc_map_0_WORD word7
1200 #define lpfc_fcf_record_fc_map_1_SHIFT 8
1201 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
1202 #define lpfc_fcf_record_fc_map_1_WORD word7
1203 #define lpfc_fcf_record_fc_map_2_SHIFT 16
1204 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
1205 #define lpfc_fcf_record_fc_map_2_WORD word7
1206 #define lpfc_fcf_record_fcf_valid_SHIFT 24
1207 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF
1208 #define lpfc_fcf_record_fcf_valid_WORD word7
1210 #define lpfc_fcf_record_fcf_index_SHIFT 0
1211 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
1212 #define lpfc_fcf_record_fcf_index_WORD word8
1213 #define lpfc_fcf_record_fcf_state_SHIFT 16
1214 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
1215 #define lpfc_fcf_record_fcf_state_WORD word8
1216 uint8_t vlan_bitmap[512];
1218 #define lpfc_fcf_record_switch_name_0_SHIFT 0
1219 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
1220 #define lpfc_fcf_record_switch_name_0_WORD word137
1221 #define lpfc_fcf_record_switch_name_1_SHIFT 8
1222 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
1223 #define lpfc_fcf_record_switch_name_1_WORD word137
1224 #define lpfc_fcf_record_switch_name_2_SHIFT 16
1225 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
1226 #define lpfc_fcf_record_switch_name_2_WORD word137
1227 #define lpfc_fcf_record_switch_name_3_SHIFT 24
1228 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
1229 #define lpfc_fcf_record_switch_name_3_WORD word137
1231 #define lpfc_fcf_record_switch_name_4_SHIFT 0
1232 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
1233 #define lpfc_fcf_record_switch_name_4_WORD word138
1234 #define lpfc_fcf_record_switch_name_5_SHIFT 8
1235 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
1236 #define lpfc_fcf_record_switch_name_5_WORD word138
1237 #define lpfc_fcf_record_switch_name_6_SHIFT 16
1238 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
1239 #define lpfc_fcf_record_switch_name_6_WORD word138
1240 #define lpfc_fcf_record_switch_name_7_SHIFT 24
1241 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
1242 #define lpfc_fcf_record_switch_name_7_WORD word138
1245 struct lpfc_mbx_read_fcf_tbl {
1246 union lpfc_sli4_cfg_shdr cfg_shdr;
1250 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
1251 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
1252 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10
1259 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
1260 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
1261 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
1264 struct lpfc_mbx_add_fcf_tbl_entry {
1265 union lpfc_sli4_cfg_shdr cfg_shdr;
1267 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
1268 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
1269 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
1270 struct lpfc_mbx_sge fcf_sge;
1273 struct lpfc_mbx_del_fcf_tbl_entry {
1274 struct mbox_header header;
1276 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
1277 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
1278 #define lpfc_mbx_del_fcf_tbl_count_WORD word10
1279 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
1280 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
1281 #define lpfc_mbx_del_fcf_tbl_index_WORD word10
1284 struct lpfc_mbx_query_fw_cfg {
1285 struct mbox_header header;
1286 uint32_t config_number;
1289 uint32_t function_mode;
1290 /* firmware Function Mode */
1291 #define lpfc_function_mode_toe_SHIFT 0
1292 #define lpfc_function_mode_toe_MASK 0x00000001
1293 #define lpfc_function_mode_toe_WORD function_mode
1294 #define lpfc_function_mode_nic_SHIFT 1
1295 #define lpfc_function_mode_nic_MASK 0x00000001
1296 #define lpfc_function_mode_nic_WORD function_mode
1297 #define lpfc_function_mode_rdma_SHIFT 2
1298 #define lpfc_function_mode_rdma_MASK 0x00000001
1299 #define lpfc_function_mode_rdma_WORD function_mode
1300 #define lpfc_function_mode_vm_SHIFT 3
1301 #define lpfc_function_mode_vm_MASK 0x00000001
1302 #define lpfc_function_mode_vm_WORD function_mode
1303 #define lpfc_function_mode_iscsi_i_SHIFT 4
1304 #define lpfc_function_mode_iscsi_i_MASK 0x00000001
1305 #define lpfc_function_mode_iscsi_i_WORD function_mode
1306 #define lpfc_function_mode_iscsi_t_SHIFT 5
1307 #define lpfc_function_mode_iscsi_t_MASK 0x00000001
1308 #define lpfc_function_mode_iscsi_t_WORD function_mode
1309 #define lpfc_function_mode_fcoe_i_SHIFT 6
1310 #define lpfc_function_mode_fcoe_i_MASK 0x00000001
1311 #define lpfc_function_mode_fcoe_i_WORD function_mode
1312 #define lpfc_function_mode_fcoe_t_SHIFT 7
1313 #define lpfc_function_mode_fcoe_t_MASK 0x00000001
1314 #define lpfc_function_mode_fcoe_t_WORD function_mode
1315 #define lpfc_function_mode_dal_SHIFT 8
1316 #define lpfc_function_mode_dal_MASK 0x00000001
1317 #define lpfc_function_mode_dal_WORD function_mode
1318 #define lpfc_function_mode_lro_SHIFT 9
1319 #define lpfc_function_mode_lro_MASK 0x00000001
1320 #define lpfc_function_mode_lro_WORD function_mode9
1321 #define lpfc_function_mode_flex10_SHIFT 10
1322 #define lpfc_function_mode_flex10_MASK 0x00000001
1323 #define lpfc_function_mode_flex10_WORD function_mode
1324 #define lpfc_function_mode_ncsi_SHIFT 11
1325 #define lpfc_function_mode_ncsi_MASK 0x00000001
1326 #define lpfc_function_mode_ncsi_WORD function_mode
1329 /* Status field for embedded SLI_CONFIG mailbox command */
1330 #define STATUS_SUCCESS 0x0
1331 #define STATUS_FAILED 0x1
1332 #define STATUS_ILLEGAL_REQUEST 0x2
1333 #define STATUS_ILLEGAL_FIELD 0x3
1334 #define STATUS_INSUFFICIENT_BUFFER 0x4
1335 #define STATUS_UNAUTHORIZED_REQUEST 0x5
1336 #define STATUS_FLASHROM_SAVE_FAILED 0x17
1337 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
1338 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
1339 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
1340 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
1341 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
1342 #define STATUS_ASSERT_FAILED 0x1e
1343 #define STATUS_INVALID_SESSION 0x1f
1344 #define STATUS_INVALID_CONNECTION 0x20
1345 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
1346 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
1347 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
1348 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
1349 #define STATUS_FLASHROM_READ_FAILED 0x27
1350 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
1351 #define STATUS_ERROR_ACITMAIN 0x2a
1352 #define STATUS_REBOOT_REQUIRED 0x2c
1353 #define STATUS_FCF_IN_USE 0x3a
1355 struct lpfc_mbx_sli4_config {
1356 struct mbox_header header;
1359 struct lpfc_mbx_init_vfi {
1361 #define lpfc_init_vfi_vr_SHIFT 31
1362 #define lpfc_init_vfi_vr_MASK 0x00000001
1363 #define lpfc_init_vfi_vr_WORD word1
1364 #define lpfc_init_vfi_vt_SHIFT 30
1365 #define lpfc_init_vfi_vt_MASK 0x00000001
1366 #define lpfc_init_vfi_vt_WORD word1
1367 #define lpfc_init_vfi_vf_SHIFT 29
1368 #define lpfc_init_vfi_vf_MASK 0x00000001
1369 #define lpfc_init_vfi_vf_WORD word1
1370 #define lpfc_init_vfi_vfi_SHIFT 0
1371 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
1372 #define lpfc_init_vfi_vfi_WORD word1
1374 #define lpfc_init_vfi_fcfi_SHIFT 0
1375 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
1376 #define lpfc_init_vfi_fcfi_WORD word2
1378 #define lpfc_init_vfi_pri_SHIFT 13
1379 #define lpfc_init_vfi_pri_MASK 0x00000007
1380 #define lpfc_init_vfi_pri_WORD word3
1381 #define lpfc_init_vfi_vf_id_SHIFT 1
1382 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
1383 #define lpfc_init_vfi_vf_id_WORD word3
1385 #define lpfc_init_vfi_hop_count_SHIFT 24
1386 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
1387 #define lpfc_init_vfi_hop_count_WORD word4
1390 struct lpfc_mbx_reg_vfi {
1392 #define lpfc_reg_vfi_vp_SHIFT 28
1393 #define lpfc_reg_vfi_vp_MASK 0x00000001
1394 #define lpfc_reg_vfi_vp_WORD word1
1395 #define lpfc_reg_vfi_vfi_SHIFT 0
1396 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
1397 #define lpfc_reg_vfi_vfi_WORD word1
1399 #define lpfc_reg_vfi_vpi_SHIFT 16
1400 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
1401 #define lpfc_reg_vfi_vpi_WORD word2
1402 #define lpfc_reg_vfi_fcfi_SHIFT 0
1403 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
1404 #define lpfc_reg_vfi_fcfi_WORD word2
1406 struct ulp_bde64 bde;
1407 uint32_t word8_rsvd;
1408 uint32_t word9_rsvd;
1410 #define lpfc_reg_vfi_nport_id_SHIFT 0
1411 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
1412 #define lpfc_reg_vfi_nport_id_WORD word10
1415 struct lpfc_mbx_init_vpi {
1417 #define lpfc_init_vpi_vfi_SHIFT 16
1418 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
1419 #define lpfc_init_vpi_vfi_WORD word1
1420 #define lpfc_init_vpi_vpi_SHIFT 0
1421 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
1422 #define lpfc_init_vpi_vpi_WORD word1
1425 struct lpfc_mbx_read_vpi {
1426 uint32_t word1_rsvd;
1428 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
1429 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
1430 #define lpfc_mbx_read_vpi_vnportid_WORD word2
1431 uint32_t word3_rsvd;
1433 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
1434 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
1435 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4
1436 #define lpfc_mbx_read_vpi_pb_SHIFT 15
1437 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
1438 #define lpfc_mbx_read_vpi_pb_WORD word4
1439 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
1440 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
1441 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4
1442 #define lpfc_mbx_read_vpi_ns_SHIFT 30
1443 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
1444 #define lpfc_mbx_read_vpi_ns_WORD word4
1445 #define lpfc_mbx_read_vpi_hl_SHIFT 31
1446 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
1447 #define lpfc_mbx_read_vpi_hl_WORD word4
1448 uint32_t word5_rsvd;
1450 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
1451 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
1452 #define lpfc_mbx_read_vpi_vpi_WORD word6
1454 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
1455 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
1456 #define lpfc_mbx_read_vpi_mac_0_WORD word7
1457 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8
1458 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
1459 #define lpfc_mbx_read_vpi_mac_1_WORD word7
1460 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16
1461 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
1462 #define lpfc_mbx_read_vpi_mac_2_WORD word7
1463 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24
1464 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
1465 #define lpfc_mbx_read_vpi_mac_3_WORD word7
1467 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
1468 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
1469 #define lpfc_mbx_read_vpi_mac_4_WORD word8
1470 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8
1471 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
1472 #define lpfc_mbx_read_vpi_mac_5_WORD word8
1473 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
1474 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
1475 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8
1476 #define lpfc_mbx_read_vpi_vv_SHIFT 28
1477 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
1478 #define lpfc_mbx_read_vpi_vv_WORD word8
1481 struct lpfc_mbx_unreg_vfi {
1482 uint32_t word1_rsvd;
1484 #define lpfc_unreg_vfi_vfi_SHIFT 0
1485 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
1486 #define lpfc_unreg_vfi_vfi_WORD word2
1489 struct lpfc_mbx_resume_rpi {
1491 #define lpfc_resume_rpi_index_SHIFT 0
1492 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
1493 #define lpfc_resume_rpi_index_WORD word1
1494 #define lpfc_resume_rpi_ii_SHIFT 30
1495 #define lpfc_resume_rpi_ii_MASK 0x00000003
1496 #define lpfc_resume_rpi_ii_WORD word1
1497 #define RESUME_INDEX_RPI 0
1498 #define RESUME_INDEX_VPI 1
1499 #define RESUME_INDEX_VFI 2
1500 #define RESUME_INDEX_FCFI 3
1504 #define REG_FCF_INVALID_QID 0xFFFF
1505 struct lpfc_mbx_reg_fcfi {
1507 #define lpfc_reg_fcfi_info_index_SHIFT 0
1508 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
1509 #define lpfc_reg_fcfi_info_index_WORD word1
1510 #define lpfc_reg_fcfi_fcfi_SHIFT 16
1511 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
1512 #define lpfc_reg_fcfi_fcfi_WORD word1
1514 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
1515 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
1516 #define lpfc_reg_fcfi_rq_id1_WORD word2
1517 #define lpfc_reg_fcfi_rq_id0_SHIFT 16
1518 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
1519 #define lpfc_reg_fcfi_rq_id0_WORD word2
1521 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
1522 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
1523 #define lpfc_reg_fcfi_rq_id3_WORD word3
1524 #define lpfc_reg_fcfi_rq_id2_SHIFT 16
1525 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
1526 #define lpfc_reg_fcfi_rq_id2_WORD word3
1528 #define lpfc_reg_fcfi_type_match0_SHIFT 24
1529 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
1530 #define lpfc_reg_fcfi_type_match0_WORD word4
1531 #define lpfc_reg_fcfi_type_mask0_SHIFT 16
1532 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
1533 #define lpfc_reg_fcfi_type_mask0_WORD word4
1534 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1535 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
1536 #define lpfc_reg_fcfi_rctl_match0_WORD word4
1537 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
1538 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
1539 #define lpfc_reg_fcfi_rctl_mask0_WORD word4
1541 #define lpfc_reg_fcfi_type_match1_SHIFT 24
1542 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
1543 #define lpfc_reg_fcfi_type_match1_WORD word5
1544 #define lpfc_reg_fcfi_type_mask1_SHIFT 16
1545 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
1546 #define lpfc_reg_fcfi_type_mask1_WORD word5
1547 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
1548 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
1549 #define lpfc_reg_fcfi_rctl_match1_WORD word5
1550 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
1551 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
1552 #define lpfc_reg_fcfi_rctl_mask1_WORD word5
1554 #define lpfc_reg_fcfi_type_match2_SHIFT 24
1555 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
1556 #define lpfc_reg_fcfi_type_match2_WORD word6
1557 #define lpfc_reg_fcfi_type_mask2_SHIFT 16
1558 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
1559 #define lpfc_reg_fcfi_type_mask2_WORD word6
1560 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
1561 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
1562 #define lpfc_reg_fcfi_rctl_match2_WORD word6
1563 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
1564 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
1565 #define lpfc_reg_fcfi_rctl_mask2_WORD word6
1567 #define lpfc_reg_fcfi_type_match3_SHIFT 24
1568 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
1569 #define lpfc_reg_fcfi_type_match3_WORD word7
1570 #define lpfc_reg_fcfi_type_mask3_SHIFT 16
1571 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
1572 #define lpfc_reg_fcfi_type_mask3_WORD word7
1573 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
1574 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
1575 #define lpfc_reg_fcfi_rctl_match3_WORD word7
1576 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
1577 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
1578 #define lpfc_reg_fcfi_rctl_mask3_WORD word7
1580 #define lpfc_reg_fcfi_mam_SHIFT 13
1581 #define lpfc_reg_fcfi_mam_MASK 0x00000003
1582 #define lpfc_reg_fcfi_mam_WORD word8
1583 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
1584 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
1585 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
1586 #define lpfc_reg_fcfi_vv_SHIFT 12
1587 #define lpfc_reg_fcfi_vv_MASK 0x00000001
1588 #define lpfc_reg_fcfi_vv_WORD word8
1589 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
1590 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
1591 #define lpfc_reg_fcfi_vlan_tag_WORD word8
1594 struct lpfc_mbx_unreg_fcfi {
1597 #define lpfc_unreg_fcfi_SHIFT 0
1598 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
1599 #define lpfc_unreg_fcfi_WORD word2
1602 struct lpfc_mbx_read_rev {
1604 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
1605 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
1606 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1
1607 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20
1608 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
1609 #define lpfc_mbx_rd_rev_fcoe_WORD word1
1610 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
1611 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
1612 #define lpfc_mbx_rd_rev_cee_ver_WORD word1
1613 #define LPFC_PREDCBX_CEE_MODE 0
1614 #define LPFC_DCBX_CEE_MODE 1
1615 #define lpfc_mbx_rd_rev_vpd_SHIFT 29
1616 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
1617 #define lpfc_mbx_rd_rev_vpd_WORD word1
1618 uint32_t first_hw_rev;
1619 uint32_t second_hw_rev;
1620 uint32_t word4_rsvd;
1621 uint32_t third_hw_rev;
1623 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
1624 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
1625 #define lpfc_mbx_rd_rev_fcph_low_WORD word6
1626 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
1627 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
1628 #define lpfc_mbx_rd_rev_fcph_high_WORD word6
1629 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
1630 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
1631 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
1632 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
1633 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
1634 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
1635 uint32_t word7_rsvd;
1637 uint8_t fw_name[16];
1638 uint32_t ulp_fw_id_rev;
1639 uint8_t ulp_fw_name[16];
1640 uint32_t word18_47_rsvd[30];
1642 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
1643 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
1644 #define lpfc_mbx_rd_rev_avail_len_WORD word48
1645 uint32_t vpd_paddr_low;
1646 uint32_t vpd_paddr_high;
1647 uint32_t avail_vpd_len;
1648 uint32_t rsvd_52_63[12];
1651 struct lpfc_mbx_read_config {
1653 #define lpfc_mbx_rd_conf_max_bbc_SHIFT 0
1654 #define lpfc_mbx_rd_conf_max_bbc_MASK 0x000000FF
1655 #define lpfc_mbx_rd_conf_max_bbc_WORD word1
1656 #define lpfc_mbx_rd_conf_init_bbc_SHIFT 8
1657 #define lpfc_mbx_rd_conf_init_bbc_MASK 0x000000FF
1658 #define lpfc_mbx_rd_conf_init_bbc_WORD word1
1660 #define lpfc_mbx_rd_conf_nport_did_SHIFT 0
1661 #define lpfc_mbx_rd_conf_nport_did_MASK 0x00FFFFFF
1662 #define lpfc_mbx_rd_conf_nport_did_WORD word2
1663 #define lpfc_mbx_rd_conf_topology_SHIFT 24
1664 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
1665 #define lpfc_mbx_rd_conf_topology_WORD word2
1667 #define lpfc_mbx_rd_conf_ao_SHIFT 0
1668 #define lpfc_mbx_rd_conf_ao_MASK 0x00000001
1669 #define lpfc_mbx_rd_conf_ao_WORD word3
1670 #define lpfc_mbx_rd_conf_bb_scn_SHIFT 8
1671 #define lpfc_mbx_rd_conf_bb_scn_MASK 0x0000000F
1672 #define lpfc_mbx_rd_conf_bb_scn_WORD word3
1673 #define lpfc_mbx_rd_conf_cbb_scn_SHIFT 12
1674 #define lpfc_mbx_rd_conf_cbb_scn_MASK 0x0000000F
1675 #define lpfc_mbx_rd_conf_cbb_scn_WORD word3
1676 #define lpfc_mbx_rd_conf_mc_SHIFT 29
1677 #define lpfc_mbx_rd_conf_mc_MASK 0x00000001
1678 #define lpfc_mbx_rd_conf_mc_WORD word3
1680 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
1681 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
1682 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4
1684 #define lpfc_mbx_rd_conf_lp_tov_SHIFT 0
1685 #define lpfc_mbx_rd_conf_lp_tov_MASK 0x0000FFFF
1686 #define lpfc_mbx_rd_conf_lp_tov_WORD word5
1688 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
1689 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
1690 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6
1692 #define lpfc_mbx_rd_conf_r_t_tov_SHIFT 0
1693 #define lpfc_mbx_rd_conf_r_t_tov_MASK 0x000000FF
1694 #define lpfc_mbx_rd_conf_r_t_tov_WORD word7
1696 #define lpfc_mbx_rd_conf_al_tov_SHIFT 0
1697 #define lpfc_mbx_rd_conf_al_tov_MASK 0x0000000F
1698 #define lpfc_mbx_rd_conf_al_tov_WORD word8
1700 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
1701 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
1702 #define lpfc_mbx_rd_conf_lmt_WORD word9
1704 #define lpfc_mbx_rd_conf_max_alpa_SHIFT 0
1705 #define lpfc_mbx_rd_conf_max_alpa_MASK 0x000000FF
1706 #define lpfc_mbx_rd_conf_max_alpa_WORD word10
1707 uint32_t word11_rsvd;
1709 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
1710 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
1711 #define lpfc_mbx_rd_conf_xri_base_WORD word12
1712 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16
1713 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
1714 #define lpfc_mbx_rd_conf_xri_count_WORD word12
1716 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
1717 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
1718 #define lpfc_mbx_rd_conf_rpi_base_WORD word13
1719 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
1720 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
1721 #define lpfc_mbx_rd_conf_rpi_count_WORD word13
1723 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
1724 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
1725 #define lpfc_mbx_rd_conf_vpi_base_WORD word14
1726 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
1727 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
1728 #define lpfc_mbx_rd_conf_vpi_count_WORD word14
1730 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
1731 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
1732 #define lpfc_mbx_rd_conf_vfi_base_WORD word15
1733 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
1734 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
1735 #define lpfc_mbx_rd_conf_vfi_count_WORD word15
1737 #define lpfc_mbx_rd_conf_fcfi_base_SHIFT 0
1738 #define lpfc_mbx_rd_conf_fcfi_base_MASK 0x0000FFFF
1739 #define lpfc_mbx_rd_conf_fcfi_base_WORD word16
1740 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
1741 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
1742 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16
1744 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
1745 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
1746 #define lpfc_mbx_rd_conf_rq_count_WORD word17
1747 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16
1748 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
1749 #define lpfc_mbx_rd_conf_eq_count_WORD word17
1751 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
1752 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
1753 #define lpfc_mbx_rd_conf_wq_count_WORD word18
1754 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16
1755 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
1756 #define lpfc_mbx_rd_conf_cq_count_WORD word18
1759 struct lpfc_mbx_request_features {
1761 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
1762 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
1763 #define lpfc_mbx_rq_ftr_qry_WORD word1
1765 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
1766 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
1767 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
1768 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
1769 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
1770 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
1771 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
1772 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
1773 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2
1774 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
1775 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
1776 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2
1777 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
1778 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
1779 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
1780 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
1781 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
1782 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
1783 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
1784 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
1785 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
1786 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
1787 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
1788 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
1790 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
1791 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
1792 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
1793 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
1794 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
1795 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
1796 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
1797 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
1798 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
1799 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
1800 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
1801 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
1802 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
1803 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
1804 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
1805 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
1806 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
1807 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
1808 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
1809 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
1810 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
1811 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
1812 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
1813 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
1816 /* Mailbox Completion Queue Error Messages */
1817 #define MB_CQE_STATUS_SUCCESS 0x0
1818 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
1819 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
1820 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
1821 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
1822 #define MB_CQE_STATUS_DMA_FAILED 0x5
1824 /* mailbox queue entry structure */
1827 #define lpfc_mqe_status_SHIFT 16
1828 #define lpfc_mqe_status_MASK 0x0000FFFF
1829 #define lpfc_mqe_status_WORD word0
1830 #define lpfc_mqe_command_SHIFT 8
1831 #define lpfc_mqe_command_MASK 0x000000FF
1832 #define lpfc_mqe_command_WORD word0
1834 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
1835 /* sli4 mailbox commands */
1836 struct lpfc_mbx_sli4_config sli4_config;
1837 struct lpfc_mbx_init_vfi init_vfi;
1838 struct lpfc_mbx_reg_vfi reg_vfi;
1839 struct lpfc_mbx_reg_vfi unreg_vfi;
1840 struct lpfc_mbx_init_vpi init_vpi;
1841 struct lpfc_mbx_resume_rpi resume_rpi;
1842 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
1843 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
1844 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
1845 struct lpfc_mbx_reg_fcfi reg_fcfi;
1846 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
1847 struct lpfc_mbx_mq_create mq_create;
1848 struct lpfc_mbx_eq_create eq_create;
1849 struct lpfc_mbx_cq_create cq_create;
1850 struct lpfc_mbx_wq_create wq_create;
1851 struct lpfc_mbx_rq_create rq_create;
1852 struct lpfc_mbx_mq_destroy mq_destroy;
1853 struct lpfc_mbx_eq_destroy eq_destroy;
1854 struct lpfc_mbx_cq_destroy cq_destroy;
1855 struct lpfc_mbx_wq_destroy wq_destroy;
1856 struct lpfc_mbx_rq_destroy rq_destroy;
1857 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
1858 struct lpfc_mbx_nembed_cmd nembed_cmd;
1859 struct lpfc_mbx_read_rev read_rev;
1860 struct lpfc_mbx_read_vpi read_vpi;
1861 struct lpfc_mbx_read_config rd_config;
1862 struct lpfc_mbx_request_features req_ftrs;
1863 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
1864 struct lpfc_mbx_query_fw_cfg query_fw_cfg;
1865 struct lpfc_mbx_nop nop;
1871 #define lpfc_mcqe_status_SHIFT 0
1872 #define lpfc_mcqe_status_MASK 0x0000FFFF
1873 #define lpfc_mcqe_status_WORD word0
1874 #define lpfc_mcqe_ext_status_SHIFT 16
1875 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
1876 #define lpfc_mcqe_ext_status_WORD word0
1880 #define lpfc_trailer_valid_SHIFT 31
1881 #define lpfc_trailer_valid_MASK 0x00000001
1882 #define lpfc_trailer_valid_WORD trailer
1883 #define lpfc_trailer_async_SHIFT 30
1884 #define lpfc_trailer_async_MASK 0x00000001
1885 #define lpfc_trailer_async_WORD trailer
1886 #define lpfc_trailer_hpi_SHIFT 29
1887 #define lpfc_trailer_hpi_MASK 0x00000001
1888 #define lpfc_trailer_hpi_WORD trailer
1889 #define lpfc_trailer_completed_SHIFT 28
1890 #define lpfc_trailer_completed_MASK 0x00000001
1891 #define lpfc_trailer_completed_WORD trailer
1892 #define lpfc_trailer_consumed_SHIFT 27
1893 #define lpfc_trailer_consumed_MASK 0x00000001
1894 #define lpfc_trailer_consumed_WORD trailer
1895 #define lpfc_trailer_type_SHIFT 16
1896 #define lpfc_trailer_type_MASK 0x000000FF
1897 #define lpfc_trailer_type_WORD trailer
1898 #define lpfc_trailer_code_SHIFT 8
1899 #define lpfc_trailer_code_MASK 0x000000FF
1900 #define lpfc_trailer_code_WORD trailer
1901 #define LPFC_TRAILER_CODE_LINK 0x1
1902 #define LPFC_TRAILER_CODE_FCOE 0x2
1903 #define LPFC_TRAILER_CODE_DCBX 0x3
1906 struct lpfc_acqe_link {
1908 #define lpfc_acqe_link_speed_SHIFT 24
1909 #define lpfc_acqe_link_speed_MASK 0x000000FF
1910 #define lpfc_acqe_link_speed_WORD word0
1911 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
1912 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
1913 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
1914 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
1915 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
1916 #define lpfc_acqe_link_duplex_SHIFT 16
1917 #define lpfc_acqe_link_duplex_MASK 0x000000FF
1918 #define lpfc_acqe_link_duplex_WORD word0
1919 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
1920 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
1921 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
1922 #define lpfc_acqe_link_status_SHIFT 8
1923 #define lpfc_acqe_link_status_MASK 0x000000FF
1924 #define lpfc_acqe_link_status_WORD word0
1925 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
1926 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
1927 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
1928 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
1929 #define lpfc_acqe_link_physical_SHIFT 0
1930 #define lpfc_acqe_link_physical_MASK 0x000000FF
1931 #define lpfc_acqe_link_physical_WORD word0
1932 #define LPFC_ASYNC_LINK_PORT_A 0x0
1933 #define LPFC_ASYNC_LINK_PORT_B 0x1
1935 #define lpfc_acqe_link_fault_SHIFT 0
1936 #define lpfc_acqe_link_fault_MASK 0x000000FF
1937 #define lpfc_acqe_link_fault_WORD word1
1938 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
1939 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
1940 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
1945 struct lpfc_acqe_fcoe {
1948 #define lpfc_acqe_fcoe_fcf_count_SHIFT 0
1949 #define lpfc_acqe_fcoe_fcf_count_MASK 0x0000FFFF
1950 #define lpfc_acqe_fcoe_fcf_count_WORD word1
1951 #define lpfc_acqe_fcoe_event_type_SHIFT 16
1952 #define lpfc_acqe_fcoe_event_type_MASK 0x0000FFFF
1953 #define lpfc_acqe_fcoe_event_type_WORD word1
1954 #define LPFC_FCOE_EVENT_TYPE_NEW_FCF 0x1
1955 #define LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL 0x2
1956 #define LPFC_FCOE_EVENT_TYPE_FCF_DEAD 0x3
1957 #define LPFC_FCOE_EVENT_TYPE_CVL 0x4
1962 struct lpfc_acqe_dcbx {
1970 * Define the bootstrap mailbox (bmbx) region used to communicate
1971 * mailbox command between the host and port. The mailbox consists
1972 * of a payload area of 256 bytes and a completion queue of length
1975 struct lpfc_bmbx_create {
1976 struct lpfc_mqe mqe;
1977 struct lpfc_mcqe mcqe;
1980 #define SGL_ALIGN_SZ 64
1981 #define SGL_PAGE_SIZE 4096
1982 /* align SGL addr on a size boundary - adjust address up */
1983 #define NO_XRI ((uint16_t)-1)
1986 #define wqe_xri_tag_SHIFT 0
1987 #define wqe_xri_tag_MASK 0x0000FFFF
1988 #define wqe_xri_tag_WORD word6
1989 #define wqe_ctxt_tag_SHIFT 16
1990 #define wqe_ctxt_tag_MASK 0x0000FFFF
1991 #define wqe_ctxt_tag_WORD word6
1993 #define wqe_ct_SHIFT 2
1994 #define wqe_ct_MASK 0x00000003
1995 #define wqe_ct_WORD word7
1996 #define wqe_status_SHIFT 4
1997 #define wqe_status_MASK 0x0000000f
1998 #define wqe_status_WORD word7
1999 #define wqe_cmnd_SHIFT 8
2000 #define wqe_cmnd_MASK 0x000000ff
2001 #define wqe_cmnd_WORD word7
2002 #define wqe_class_SHIFT 16
2003 #define wqe_class_MASK 0x00000007
2004 #define wqe_class_WORD word7
2005 #define wqe_pu_SHIFT 20
2006 #define wqe_pu_MASK 0x00000003
2007 #define wqe_pu_WORD word7
2008 #define wqe_erp_SHIFT 22
2009 #define wqe_erp_MASK 0x00000001
2010 #define wqe_erp_WORD word7
2011 #define wqe_lnk_SHIFT 23
2012 #define wqe_lnk_MASK 0x00000001
2013 #define wqe_lnk_WORD word7
2014 #define wqe_tmo_SHIFT 24
2015 #define wqe_tmo_MASK 0x000000ff
2016 #define wqe_tmo_WORD word7
2017 uint32_t abort_tag; /* word 8 in WQE */
2019 #define wqe_reqtag_SHIFT 0
2020 #define wqe_reqtag_MASK 0x0000FFFF
2021 #define wqe_reqtag_WORD word9
2022 #define wqe_rcvoxid_SHIFT 16
2023 #define wqe_rcvoxid_MASK 0x0000FFFF
2024 #define wqe_rcvoxid_WORD word9
2026 #define wqe_pri_SHIFT 16
2027 #define wqe_pri_MASK 0x00000007
2028 #define wqe_pri_WORD word10
2029 #define wqe_pv_SHIFT 19
2030 #define wqe_pv_MASK 0x00000001
2031 #define wqe_pv_WORD word10
2032 #define wqe_xc_SHIFT 21
2033 #define wqe_xc_MASK 0x00000001
2034 #define wqe_xc_WORD word10
2035 #define wqe_ccpe_SHIFT 23
2036 #define wqe_ccpe_MASK 0x00000001
2037 #define wqe_ccpe_WORD word10
2038 #define wqe_ccp_SHIFT 24
2039 #define wqe_ccp_MASK 0x000000ff
2040 #define wqe_ccp_WORD word10
2042 #define wqe_cmd_type_SHIFT 0
2043 #define wqe_cmd_type_MASK 0x0000000f
2044 #define wqe_cmd_type_WORD word11
2045 #define wqe_wqec_SHIFT 7
2046 #define wqe_wqec_MASK 0x00000001
2047 #define wqe_wqec_WORD word11
2048 #define wqe_cqid_SHIFT 16
2049 #define wqe_cqid_MASK 0x0000ffff
2050 #define wqe_cqid_WORD word11
2055 #define wqe_els_did_SHIFT 0
2056 #define wqe_els_did_MASK 0x00FFFFFF
2057 #define wqe_els_did_WORD word5
2058 #define wqe_xmit_bls_pt_SHIFT 28
2059 #define wqe_xmit_bls_pt_MASK 0x00000003
2060 #define wqe_xmit_bls_pt_WORD word5
2061 #define wqe_xmit_bls_ar_SHIFT 30
2062 #define wqe_xmit_bls_ar_MASK 0x00000001
2063 #define wqe_xmit_bls_ar_WORD word5
2064 #define wqe_xmit_bls_xo_SHIFT 31
2065 #define wqe_xmit_bls_xo_MASK 0x00000001
2066 #define wqe_xmit_bls_xo_WORD word5
2069 struct els_request64_wqe {
2070 struct ulp_bde64 bde;
2071 uint32_t payload_len;
2073 #define els_req64_sid_SHIFT 0
2074 #define els_req64_sid_MASK 0x00FFFFFF
2075 #define els_req64_sid_WORD word4
2076 #define els_req64_sp_SHIFT 24
2077 #define els_req64_sp_MASK 0x00000001
2078 #define els_req64_sp_WORD word4
2079 #define els_req64_vf_SHIFT 25
2080 #define els_req64_vf_MASK 0x00000001
2081 #define els_req64_vf_WORD word4
2082 struct wqe_did wqe_dest;
2083 struct wqe_common wqe_com; /* words 6-11 */
2085 #define els_req64_vfid_SHIFT 1
2086 #define els_req64_vfid_MASK 0x00000FFF
2087 #define els_req64_vfid_WORD word12
2088 #define els_req64_pri_SHIFT 13
2089 #define els_req64_pri_MASK 0x00000007
2090 #define els_req64_pri_WORD word12
2092 #define els_req64_hopcnt_SHIFT 24
2093 #define els_req64_hopcnt_MASK 0x000000ff
2094 #define els_req64_hopcnt_WORD word13
2095 uint32_t reserved[2];
2098 struct xmit_els_rsp64_wqe {
2099 struct ulp_bde64 bde;
2102 struct wqe_did wqe_dest;
2103 struct wqe_common wqe_com; /* words 6-11 */
2104 uint32_t rsvd_12_15[4];
2107 struct xmit_bls_rsp64_wqe {
2109 /* Payload0 for BA_ACC */
2110 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16
2111 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
2112 #define xmit_bls_rsp64_acc_seq_id_WORD payload0
2113 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
2114 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
2115 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
2116 /* Payload0 for BA_RJT */
2117 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
2118 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
2119 #define xmit_bls_rsp64_rjt_vspec_WORD payload0
2120 #define xmit_bls_rsp64_rjt_expc_SHIFT 8
2121 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
2122 #define xmit_bls_rsp64_rjt_expc_WORD payload0
2123 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
2124 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
2125 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0
2127 #define xmit_bls_rsp64_rxid_SHIFT 0
2128 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
2129 #define xmit_bls_rsp64_rxid_WORD word1
2130 #define xmit_bls_rsp64_oxid_SHIFT 16
2131 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
2132 #define xmit_bls_rsp64_oxid_WORD word1
2134 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
2135 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
2136 #define xmit_bls_rsp64_seqcnthi_WORD word2
2137 #define xmit_bls_rsp64_seqcntlo_SHIFT 16
2138 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
2139 #define xmit_bls_rsp64_seqcntlo_WORD word2
2142 struct wqe_did wqe_dest;
2143 struct wqe_common wqe_com; /* words 6-11 */
2144 uint32_t rsvd_12_15[4];
2147 struct wqe_rctl_dfctl {
2149 #define wqe_si_SHIFT 2
2150 #define wqe_si_MASK 0x000000001
2151 #define wqe_si_WORD word5
2152 #define wqe_la_SHIFT 3
2153 #define wqe_la_MASK 0x000000001
2154 #define wqe_la_WORD word5
2155 #define wqe_ls_SHIFT 7
2156 #define wqe_ls_MASK 0x000000001
2157 #define wqe_ls_WORD word5
2158 #define wqe_dfctl_SHIFT 8
2159 #define wqe_dfctl_MASK 0x0000000ff
2160 #define wqe_dfctl_WORD word5
2161 #define wqe_type_SHIFT 16
2162 #define wqe_type_MASK 0x0000000ff
2163 #define wqe_type_WORD word5
2164 #define wqe_rctl_SHIFT 24
2165 #define wqe_rctl_MASK 0x0000000ff
2166 #define wqe_rctl_WORD word5
2169 struct xmit_seq64_wqe {
2170 struct ulp_bde64 bde;
2171 uint32_t paylaod_offset;
2172 uint32_t relative_offset;
2173 struct wqe_rctl_dfctl wge_ctl;
2174 struct wqe_common wqe_com; /* words 6-11 */
2175 /* Note: word10 different REVISIT */
2177 uint32_t rsvd_12_15[3];
2179 struct xmit_bcast64_wqe {
2180 struct ulp_bde64 bde;
2181 uint32_t paylaod_len;
2183 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2184 struct wqe_common wqe_com; /* words 6-11 */
2185 uint32_t rsvd_12_15[4];
2188 struct gen_req64_wqe {
2189 struct ulp_bde64 bde;
2190 uint32_t command_len;
2191 uint32_t payload_len;
2192 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2193 struct wqe_common wqe_com; /* words 6-11 */
2194 uint32_t rsvd_12_15[4];
2197 struct create_xri_wqe {
2198 uint32_t rsrvd[5]; /* words 0-4 */
2199 struct wqe_did wqe_dest; /* word 5 */
2200 struct wqe_common wqe_com; /* words 6-11 */
2201 uint32_t rsvd_12_15[4]; /* word 12-15 */
2204 #define T_REQUEST_TAG 3
2207 struct abort_cmd_wqe {
2210 #define abort_cmd_ia_SHIFT 0
2211 #define abort_cmd_ia_MASK 0x000000001
2212 #define abort_cmd_ia_WORD word3
2213 #define abort_cmd_criteria_SHIFT 8
2214 #define abort_cmd_criteria_MASK 0x0000000ff
2215 #define abort_cmd_criteria_WORD word3
2218 struct wqe_common wqe_com; /* words 6-11 */
2219 uint32_t rsvd_12_15[4]; /* word 12-15 */
2222 struct fcp_iwrite64_wqe {
2223 struct ulp_bde64 bde;
2224 uint32_t payload_len;
2225 uint32_t total_xfer_len;
2226 uint32_t initial_xfer_len;
2227 struct wqe_common wqe_com; /* words 6-11 */
2228 uint32_t rsvd_12_15[4]; /* word 12-15 */
2231 struct fcp_iread64_wqe {
2232 struct ulp_bde64 bde;
2233 uint32_t payload_len; /* word 3 */
2234 uint32_t total_xfer_len; /* word 4 */
2235 uint32_t rsrvd5; /* word 5 */
2236 struct wqe_common wqe_com; /* words 6-11 */
2237 uint32_t rsvd_12_15[4]; /* word 12-15 */
2240 struct fcp_icmnd64_wqe {
2241 struct ulp_bde64 bde; /* words 0-2 */
2242 uint32_t rsrvd[3]; /* words 3-5 */
2243 struct wqe_common wqe_com; /* words 6-11 */
2244 uint32_t rsvd_12_15[4]; /* word 12-15 */
2250 struct lpfc_wqe_generic generic;
2251 struct fcp_icmnd64_wqe fcp_icmd;
2252 struct fcp_iread64_wqe fcp_iread;
2253 struct fcp_iwrite64_wqe fcp_iwrite;
2254 struct abort_cmd_wqe abort_cmd;
2255 struct create_xri_wqe create_xri;
2256 struct xmit_bcast64_wqe xmit_bcast64;
2257 struct xmit_seq64_wqe xmit_sequence;
2258 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
2259 struct xmit_els_rsp64_wqe xmit_els_rsp;
2260 struct els_request64_wqe els_req;
2261 struct gen_req64_wqe gen_req;
2264 #define FCP_COMMAND 0x0
2265 #define FCP_COMMAND_DATA_OUT 0x1
2266 #define ELS_COMMAND_NON_FIP 0xC
2267 #define ELS_COMMAND_FIP 0xD
2268 #define OTHER_COMMAND 0x8