Pileus Git - ~andy/linux/blob - drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2009 Emulex.  All rights reserved.                *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  22  * associated with it (_SHIFT, _MASK, and _WORD).
  23  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  24  * structure and is 2 bits in size the following #defines must exist:
  25  *      struct temp {
  26  *              uint32_t        field1;
  27  *              uint32_t        field2;
  28  *              uint32_t        field3;
  29  *              uint32_t        field4;
  30  *      #define example_bit_field_SHIFT         7
  31  *      #define example_bit_field_MASK          0x03
  32  *      #define example_bit_field_WORD          field4
  33  *              uint32_t        field5;
  34  *      };
  35  * Then the macros below may be used to get or set the value of that field.
  36  * EG. To get the value of the bit field from the above example:
  37  *      struct temp t1;
  38  *      value = bf_get(example_bit_field, &t1);
  39  * And then to set that bit field:
  40  *      bf_set(example_bit_field, &t1, 2);
  41  * Or clear that bit field:
  42  *      bf_set(example_bit_field, &t1, 0);
  43  */
  44 #define bf_get(name, ptr) \
  45         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  46 #define bf_set(name, ptr, value) \
  47         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  48                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  49
  50 struct dma_address {
  51         uint32_t addr_lo;
  52         uint32_t addr_hi;
  53 };
  54
  55 #define LPFC_SLI4_BAR0          1
  56 #define LPFC_SLI4_BAR1          2
  57 #define LPFC_SLI4_BAR2          4
  58
  59 #define LPFC_SLI4_MBX_EMBED     true
  60 #define LPFC_SLI4_MBX_NEMBED    false
  61
  62 #define LPFC_SLI4_MB_WORD_COUNT         64
  63 #define LPFC_MAX_MQ_PAGE                8
  64 #define LPFC_MAX_WQ_PAGE                8
  65 #define LPFC_MAX_CQ_PAGE                4
  66 #define LPFC_MAX_EQ_PAGE                8
  67
  68 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
  69 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
  70 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
  71
  72 /* Define SLI4 Alignment requirements. */
  73 #define LPFC_ALIGN_16_BYTE      16
  74 #define LPFC_ALIGN_64_BYTE      64
  75
  76 /* Define SLI4 specific definitions. */
  77 #define LPFC_MQ_CQE_BYTE_OFFSET 256
  78 #define LPFC_MBX_CMD_HDR_LENGTH 16
  79 #define LPFC_MBX_ERROR_RANGE    0x4000
  80 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
  81 #define LPFC_BMBX_BIT1_ADDR_LO  0
  82 #define LPFC_RPI_HDR_COUNT      64
  83 #define LPFC_HDR_TEMPLATE_SIZE  4096
  84 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
  85 #define LPFC_FCF_RECORD_WD_CNT  132
  86 #define LPFC_ENTIRE_FCF_DATABASE 0
  87 #define LPFC_DFLT_FCF_INDEX      0
  88
  89 /* Virtual function numbers */
  90 #define LPFC_VF0                0
  91 #define LPFC_VF1                1
  92 #define LPFC_VF2                2
  93 #define LPFC_VF3                3
  94 #define LPFC_VF4                4
  95 #define LPFC_VF5                5
  96 #define LPFC_VF6                6
  97 #define LPFC_VF7                7
  98 #define LPFC_VF8                8
  99 #define LPFC_VF9                9
 100 #define LPFC_VF10               10
 101 #define LPFC_VF11               11
 102 #define LPFC_VF12               12
 103 #define LPFC_VF13               13
 104 #define LPFC_VF14               14
 105 #define LPFC_VF15               15
 106 #define LPFC_VF16               16
 107 #define LPFC_VF17               17
 108 #define LPFC_VF18               18
 109 #define LPFC_VF19               19
 110 #define LPFC_VF20               20
 111 #define LPFC_VF21               21
 112 #define LPFC_VF22               22
 113 #define LPFC_VF23               23
 114 #define LPFC_VF24               24
 115 #define LPFC_VF25               25
 116 #define LPFC_VF26               26
 117 #define LPFC_VF27               27
 118 #define LPFC_VF28               28
 119 #define LPFC_VF29               29
 120 #define LPFC_VF30               30
 121 #define LPFC_VF31               31
 122
 123 /* PCI function numbers */
 124 #define LPFC_PCI_FUNC0          0
 125 #define LPFC_PCI_FUNC1          1
 126 #define LPFC_PCI_FUNC2          2
 127 #define LPFC_PCI_FUNC3          3
 128 #define LPFC_PCI_FUNC4          4
 129
 130 /* Active interrupt test count */
 131 #define LPFC_ACT_INTR_CNT       4
 132
 133 /* Delay Multiplier constant */
 134 #define LPFC_DMULT_CONST       651042
 135 #define LPFC_MIM_IMAX          636
 136 #define LPFC_FP_DEF_IMAX       10000
 137 #define LPFC_SP_DEF_IMAX       10000
 138
 139 struct ulp_bde64 {
 140         union ULP_BDE_TUS {
 141                 uint32_t w;
 142                 struct {
 143 #ifdef __BIG_ENDIAN_BITFIELD
 144                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 145                                                    VALUE !! */
 146                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 147 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 148                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 149                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 150                                                    VALUE !! */
 151 #endif
 152 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 153 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 154 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 155 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 156 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 157 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 158 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 159                 } f;
 160         } tus;
 161         uint32_t addrLow;
 162         uint32_t addrHigh;
 163 };
 164
 165 struct lpfc_sli4_flags {
 166         uint32_t word0;
 167 #define lpfc_fip_flag_SHIFT 0
 168 #define lpfc_fip_flag_MASK 0x00000001
 169 #define lpfc_fip_flag_WORD word0
 170 };
 171
 172 /* event queue entry structure */
 173 struct lpfc_eqe {
 174         uint32_t word0;
 175 #define lpfc_eqe_resource_id_SHIFT      16
 176 #define lpfc_eqe_resource_id_MASK       0x000000FF
 177 #define lpfc_eqe_resource_id_WORD       word0
 178 #define lpfc_eqe_minor_code_SHIFT       4
 179 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 180 #define lpfc_eqe_minor_code_WORD        word0
 181 #define lpfc_eqe_major_code_SHIFT       1
 182 #define lpfc_eqe_major_code_MASK        0x00000007
 183 #define lpfc_eqe_major_code_WORD        word0
 184 #define lpfc_eqe_valid_SHIFT            0
 185 #define lpfc_eqe_valid_MASK             0x00000001
 186 #define lpfc_eqe_valid_WORD             word0
 187 };
 188
 189 /* completion queue entry structure (common fields for all cqe types) */
 190 struct lpfc_cqe {
 191         uint32_t reserved0;
 192         uint32_t reserved1;
 193         uint32_t reserved2;
 194         uint32_t word3;
 195 #define lpfc_cqe_valid_SHIFT            31
 196 #define lpfc_cqe_valid_MASK             0x00000001
 197 #define lpfc_cqe_valid_WORD             word3
 198 #define lpfc_cqe_code_SHIFT             16
 199 #define lpfc_cqe_code_MASK              0x000000FF
 200 #define lpfc_cqe_code_WORD              word3
 201 };
 202
 203 /* Completion Queue Entry Status Codes */
 204 #define CQE_STATUS_SUCCESS              0x0
 205 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 206 #define CQE_STATUS_REMOTE_STOP          0x2
 207 #define CQE_STATUS_LOCAL_REJECT         0x3
 208 #define CQE_STATUS_NPORT_RJT            0x4
 209 #define CQE_STATUS_FABRIC_RJT           0x5
 210 #define CQE_STATUS_NPORT_BSY            0x6
 211 #define CQE_STATUS_FABRIC_BSY           0x7
 212 #define CQE_STATUS_INTERMED_RSP         0x8
 213 #define CQE_STATUS_LS_RJT               0x9
 214 #define CQE_STATUS_CMD_REJECT           0xb
 215 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 216 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 217
 218 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 219 #define CQE_HW_STATUS_NO_ERR            0x0
 220 #define CQE_HW_STATUS_UNDERRUN          0x1
 221 #define CQE_HW_STATUS_OVERRUN           0x2
 222
 223 /* Completion Queue Entry Codes */
 224 #define CQE_CODE_COMPL_WQE              0x1
 225 #define CQE_CODE_RELEASE_WQE            0x2
 226 #define CQE_CODE_RECEIVE                0x4
 227 #define CQE_CODE_XRI_ABORTED            0x5
 228
 229 /* completion queue entry for wqe completions */
 230 struct lpfc_wcqe_complete {
 231         uint32_t word0;
 232 #define lpfc_wcqe_c_request_tag_SHIFT   16
 233 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 234 #define lpfc_wcqe_c_request_tag_WORD    word0
 235 #define lpfc_wcqe_c_status_SHIFT        8
 236 #define lpfc_wcqe_c_status_MASK         0x000000FF
 237 #define lpfc_wcqe_c_status_WORD         word0
 238 #define lpfc_wcqe_c_hw_status_SHIFT     0
 239 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 240 #define lpfc_wcqe_c_hw_status_WORD      word0
 241         uint32_t total_data_placed;
 242         uint32_t parameter;
 243         uint32_t word3;
 244 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 245 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 246 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 247 #define lpfc_wcqe_c_xb_SHIFT            28
 248 #define lpfc_wcqe_c_xb_MASK             0x00000001
 249 #define lpfc_wcqe_c_xb_WORD             word3
 250 #define lpfc_wcqe_c_pv_SHIFT            27
 251 #define lpfc_wcqe_c_pv_MASK             0x00000001
 252 #define lpfc_wcqe_c_pv_WORD             word3
 253 #define lpfc_wcqe_c_priority_SHIFT      24
 254 #define lpfc_wcqe_c_priority_MASK               0x00000007
 255 #define lpfc_wcqe_c_priority_WORD               word3
 256 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 257 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 258 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 259 };
 260
 261 /* completion queue entry for wqe release */
 262 struct lpfc_wcqe_release {
 263         uint32_t reserved0;
 264         uint32_t reserved1;
 265         uint32_t word2;
 266 #define lpfc_wcqe_r_wq_id_SHIFT         16
 267 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 268 #define lpfc_wcqe_r_wq_id_WORD          word2
 269 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 270 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 271 #define lpfc_wcqe_r_wqe_index_WORD      word2
 272         uint32_t word3;
 273 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 274 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 275 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 276 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 277 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 278 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 279 };
 280
 281 struct sli4_wcqe_xri_aborted {
 282         uint32_t word0;
 283 #define lpfc_wcqe_xa_status_SHIFT               8
 284 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 285 #define lpfc_wcqe_xa_status_WORD                word0
 286         uint32_t parameter;
 287         uint32_t word2;
 288 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 289 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 290 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 291 #define lpfc_wcqe_xa_xri_SHIFT          0
 292 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 293 #define lpfc_wcqe_xa_xri_WORD           word2
 294         uint32_t word3;
 295 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 296 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 297 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 298 #define lpfc_wcqe_xa_ia_SHIFT           30
 299 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 300 #define lpfc_wcqe_xa_ia_WORD            word3
 301 #define CQE_XRI_ABORTED_IA_REMOTE       0
 302 #define CQE_XRI_ABORTED_IA_LOCAL        1
 303 #define lpfc_wcqe_xa_br_SHIFT           29
 304 #define lpfc_wcqe_xa_br_MASK            0x00000001
 305 #define lpfc_wcqe_xa_br_WORD            word3
 306 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 307 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 308 #define lpfc_wcqe_xa_eo_SHIFT           28
 309 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 310 #define lpfc_wcqe_xa_eo_WORD            word3
 311 #define CQE_XRI_ABORTED_EO_REMOTE       0
 312 #define CQE_XRI_ABORTED_EO_LOCAL        1
 313 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 314 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 315 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 316 };
 317
 318 /* completion queue entry structure for rqe completion */
 319 struct lpfc_rcqe {
 320         uint32_t word0;
 321 #define lpfc_rcqe_bindex_SHIFT          16
 322 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 323 #define lpfc_rcqe_bindex_WORD           word0
 324 #define lpfc_rcqe_status_SHIFT          8
 325 #define lpfc_rcqe_status_MASK           0x000000FF
 326 #define lpfc_rcqe_status_WORD           word0
 327 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 328 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 329 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 330 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 331         uint32_t reserved1;
 332         uint32_t word2;
 333 #define lpfc_rcqe_length_SHIFT          16
 334 #define lpfc_rcqe_length_MASK           0x0000FFFF
 335 #define lpfc_rcqe_length_WORD           word2
 336 #define lpfc_rcqe_rq_id_SHIFT           6
 337 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 338 #define lpfc_rcqe_rq_id_WORD            word2
 339 #define lpfc_rcqe_fcf_id_SHIFT          0
 340 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 341 #define lpfc_rcqe_fcf_id_WORD           word2
 342         uint32_t word3;
 343 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 344 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 345 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 346 #define lpfc_rcqe_port_SHIFT            30
 347 #define lpfc_rcqe_port_MASK             0x00000001
 348 #define lpfc_rcqe_port_WORD             word3
 349 #define lpfc_rcqe_hdr_length_SHIFT      24
 350 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 351 #define lpfc_rcqe_hdr_length_WORD       word3
 352 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 353 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 354 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 355 #define lpfc_rcqe_eof_SHIFT             8
 356 #define lpfc_rcqe_eof_MASK              0x000000FF
 357 #define lpfc_rcqe_eof_WORD              word3
 358 #define FCOE_EOFn       0x41
 359 #define FCOE_EOFt       0x42
 360 #define FCOE_EOFni      0x49
 361 #define FCOE_EOFa       0x50
 362 #define lpfc_rcqe_sof_SHIFT             0
 363 #define lpfc_rcqe_sof_MASK              0x000000FF
 364 #define lpfc_rcqe_sof_WORD              word3
 365 #define FCOE_SOFi2      0x2d
 366 #define FCOE_SOFi3      0x2e
 367 #define FCOE_SOFn2      0x35
 368 #define FCOE_SOFn3      0x36
 369 };
 370
 371 struct lpfc_wqe_generic{
 372         struct ulp_bde64 bde;
 373         uint32_t word3;
 374         uint32_t word4;
 375         uint32_t word5;
 376         uint32_t word6;
 377 #define lpfc_wqe_gen_context_SHIFT      16
 378 #define lpfc_wqe_gen_context_MASK       0x0000FFFF
 379 #define lpfc_wqe_gen_context_WORD       word6
 380 #define lpfc_wqe_gen_xri_SHIFT          0
 381 #define lpfc_wqe_gen_xri_MASK           0x0000FFFF
 382 #define lpfc_wqe_gen_xri_WORD           word6
 383         uint32_t word7;
 384 #define lpfc_wqe_gen_lnk_SHIFT          23
 385 #define lpfc_wqe_gen_lnk_MASK           0x00000001
 386 #define lpfc_wqe_gen_lnk_WORD           word7
 387 #define lpfc_wqe_gen_erp_SHIFT          22
 388 #define lpfc_wqe_gen_erp_MASK           0x00000001
 389 #define lpfc_wqe_gen_erp_WORD           word7
 390 #define lpfc_wqe_gen_pu_SHIFT           20
 391 #define lpfc_wqe_gen_pu_MASK            0x00000003
 392 #define lpfc_wqe_gen_pu_WORD            word7
 393 #define lpfc_wqe_gen_class_SHIFT        16
 394 #define lpfc_wqe_gen_class_MASK         0x00000007
 395 #define lpfc_wqe_gen_class_WORD         word7
 396 #define lpfc_wqe_gen_command_SHIFT      8
 397 #define lpfc_wqe_gen_command_MASK       0x000000FF
 398 #define lpfc_wqe_gen_command_WORD       word7
 399 #define lpfc_wqe_gen_status_SHIFT       4
 400 #define lpfc_wqe_gen_status_MASK        0x0000000F
 401 #define lpfc_wqe_gen_status_WORD        word7
 402 #define lpfc_wqe_gen_ct_SHIFT           2
 403 #define lpfc_wqe_gen_ct_MASK            0x00000007
 404 #define lpfc_wqe_gen_ct_WORD            word7
 405         uint32_t abort_tag;
 406         uint32_t word9;
 407 #define lpfc_wqe_gen_request_tag_SHIFT  0
 408 #define lpfc_wqe_gen_request_tag_MASK   0x0000FFFF
 409 #define lpfc_wqe_gen_request_tag_WORD   word9
 410         uint32_t word10;
 411 #define lpfc_wqe_gen_ccp_SHIFT          24
 412 #define lpfc_wqe_gen_ccp_MASK           0x000000FF
 413 #define lpfc_wqe_gen_ccp_WORD           word10
 414 #define lpfc_wqe_gen_ccpe_SHIFT         23
 415 #define lpfc_wqe_gen_ccpe_MASK          0x00000001
 416 #define lpfc_wqe_gen_ccpe_WORD          word10
 417 #define lpfc_wqe_gen_pv_SHIFT           19
 418 #define lpfc_wqe_gen_pv_MASK            0x00000001
 419 #define lpfc_wqe_gen_pv_WORD            word10
 420 #define lpfc_wqe_gen_pri_SHIFT          16
 421 #define lpfc_wqe_gen_pri_MASK           0x00000007
 422 #define lpfc_wqe_gen_pri_WORD           word10
 423         uint32_t word11;
 424 #define lpfc_wqe_gen_cq_id_SHIFT        16
 425 #define lpfc_wqe_gen_cq_id_MASK         0x000003FF
 426 #define lpfc_wqe_gen_cq_id_WORD         word11
 427 #define LPFC_WQE_CQ_ID_DEFAULT  0x3ff
 428 #define lpfc_wqe_gen_wqec_SHIFT         7
 429 #define lpfc_wqe_gen_wqec_MASK          0x00000001
 430 #define lpfc_wqe_gen_wqec_WORD          word11
 431 #define lpfc_wqe_gen_cmd_type_SHIFT     0
 432 #define lpfc_wqe_gen_cmd_type_MASK      0x0000000F
 433 #define lpfc_wqe_gen_cmd_type_WORD      word11
 434         uint32_t payload[4];
 435 };
 436
 437 struct lpfc_rqe {
 438         uint32_t address_hi;
 439         uint32_t address_lo;
 440 };
 441
 442 /* buffer descriptors */
 443 struct lpfc_bde4 {
 444         uint32_t addr_hi;
 445         uint32_t addr_lo;
 446         uint32_t word2;
 447 #define lpfc_bde4_last_SHIFT            31
 448 #define lpfc_bde4_last_MASK             0x00000001
 449 #define lpfc_bde4_last_WORD             word2
 450 #define lpfc_bde4_sge_offset_SHIFT      0
 451 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 452 #define lpfc_bde4_sge_offset_WORD       word2
 453         uint32_t word3;
 454 #define lpfc_bde4_length_SHIFT          0
 455 #define lpfc_bde4_length_MASK           0x000000FF
 456 #define lpfc_bde4_length_WORD           word3
 457 };
 458
 459 struct lpfc_register {
 460         uint32_t word0;
 461 };
 462
 463 #define LPFC_UERR_STATUS_HI             0x00A4
 464 #define LPFC_UERR_STATUS_LO             0x00A0
 465 #define LPFC_ONLINE0                    0x00B0
 466 #define LPFC_ONLINE1                    0x00B4
 467 #define LPFC_SCRATCHPAD                 0x0058
 468
 469 /* BAR0 Registers */
 470 #define LPFC_HST_STATE                  0x00AC
 471 #define lpfc_hst_state_perr_SHIFT       31
 472 #define lpfc_hst_state_perr_MASK        0x1
 473 #define lpfc_hst_state_perr_WORD        word0
 474 #define lpfc_hst_state_sfi_SHIFT        30
 475 #define lpfc_hst_state_sfi_MASK         0x1
 476 #define lpfc_hst_state_sfi_WORD         word0
 477 #define lpfc_hst_state_nip_SHIFT        29
 478 #define lpfc_hst_state_nip_MASK         0x1
 479 #define lpfc_hst_state_nip_WORD         word0
 480 #define lpfc_hst_state_ipc_SHIFT        28
 481 #define lpfc_hst_state_ipc_MASK         0x1
 482 #define lpfc_hst_state_ipc_WORD         word0
 483 #define lpfc_hst_state_xrom_SHIFT       27
 484 #define lpfc_hst_state_xrom_MASK        0x1
 485 #define lpfc_hst_state_xrom_WORD        word0
 486 #define lpfc_hst_state_dl_SHIFT         26
 487 #define lpfc_hst_state_dl_MASK          0x1
 488 #define lpfc_hst_state_dl_WORD          word0
 489 #define lpfc_hst_state_port_status_SHIFT        0
 490 #define lpfc_hst_state_port_status_MASK         0xFFFF
 491 #define lpfc_hst_state_port_status_WORD         word0
 492
 493 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 494 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 495 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 496 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 497 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 498 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 499 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 500 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 501 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 502 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 503 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 504 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 505 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 506 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 507 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 508 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 509 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 510 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 511 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 512 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 513 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 514 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 515 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 516 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 517 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 518 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 519 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 520 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 521 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 522 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 523 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 524 #define LPFC_POST_STAGE_ARMFW_READY                     0xC000
 525 #define LPFC_POST_STAGE_ARMFW_UE                        0xF000
 526
 527 #define lpfc_scratchpad_slirev_SHIFT                    4
 528 #define lpfc_scratchpad_slirev_MASK                     0xF
 529 #define lpfc_scratchpad_slirev_WORD                     word0
 530 #define lpfc_scratchpad_chiptype_SHIFT                  8
 531 #define lpfc_scratchpad_chiptype_MASK                   0xFF
 532 #define lpfc_scratchpad_chiptype_WORD                   word0
 533 #define lpfc_scratchpad_featurelevel1_SHIFT             16
 534 #define lpfc_scratchpad_featurelevel1_MASK              0xFF
 535 #define lpfc_scratchpad_featurelevel1_WORD              word0
 536 #define lpfc_scratchpad_featurelevel2_SHIFT             24
 537 #define lpfc_scratchpad_featurelevel2_MASK              0xFF
 538 #define lpfc_scratchpad_featurelevel2_WORD              word0
 539
 540 /* BAR1 Registers */
 541 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 542 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 543
 544 #define LPFC_HST_ISR0           0x0C18
 545 #define LPFC_HST_ISR1           0x0C1C
 546 #define LPFC_HST_ISR2           0x0C20
 547 #define LPFC_HST_ISR3           0x0C24
 548 #define LPFC_HST_ISR4           0x0C28
 549
 550 #define LPFC_HST_IMR0           0x0C48
 551 #define LPFC_HST_IMR1           0x0C4C
 552 #define LPFC_HST_IMR2           0x0C50
 553 #define LPFC_HST_IMR3           0x0C54
 554 #define LPFC_HST_IMR4           0x0C58
 555
 556 #define LPFC_HST_ISCR0          0x0C78
 557 #define LPFC_HST_ISCR1          0x0C7C
 558 #define LPFC_HST_ISCR2          0x0C80
 559 #define LPFC_HST_ISCR3          0x0C84
 560 #define LPFC_HST_ISCR4          0x0C88
 561
 562 #define LPFC_SLI4_INTR0                 BIT0
 563 #define LPFC_SLI4_INTR1                 BIT1
 564 #define LPFC_SLI4_INTR2                 BIT2
 565 #define LPFC_SLI4_INTR3                 BIT3
 566 #define LPFC_SLI4_INTR4                 BIT4
 567 #define LPFC_SLI4_INTR5                 BIT5
 568 #define LPFC_SLI4_INTR6                 BIT6
 569 #define LPFC_SLI4_INTR7                 BIT7
 570 #define LPFC_SLI4_INTR8                 BIT8
 571 #define LPFC_SLI4_INTR9                 BIT9
 572 #define LPFC_SLI4_INTR10                BIT10
 573 #define LPFC_SLI4_INTR11                BIT11
 574 #define LPFC_SLI4_INTR12                BIT12
 575 #define LPFC_SLI4_INTR13                BIT13
 576 #define LPFC_SLI4_INTR14                BIT14
 577 #define LPFC_SLI4_INTR15                BIT15
 578 #define LPFC_SLI4_INTR16                BIT16
 579 #define LPFC_SLI4_INTR17                BIT17
 580 #define LPFC_SLI4_INTR18                BIT18
 581 #define LPFC_SLI4_INTR19                BIT19
 582 #define LPFC_SLI4_INTR20                BIT20
 583 #define LPFC_SLI4_INTR21                BIT21
 584 #define LPFC_SLI4_INTR22                BIT22
 585 #define LPFC_SLI4_INTR23                BIT23
 586 #define LPFC_SLI4_INTR24                BIT24
 587 #define LPFC_SLI4_INTR25                BIT25
 588 #define LPFC_SLI4_INTR26                BIT26
 589 #define LPFC_SLI4_INTR27                BIT27
 590 #define LPFC_SLI4_INTR28                BIT28
 591 #define LPFC_SLI4_INTR29                BIT29
 592 #define LPFC_SLI4_INTR30                BIT30
 593 #define LPFC_SLI4_INTR31                BIT31
 594
 595 /* BAR2 Registers */
 596 #define LPFC_RQ_DOORBELL                0x00A0
 597 #define lpfc_rq_doorbell_num_posted_SHIFT       16
 598 #define lpfc_rq_doorbell_num_posted_MASK        0x3FFF
 599 #define lpfc_rq_doorbell_num_posted_WORD        word0
 600 #define LPFC_RQ_POST_BATCH              8       /* RQEs to post at one time */
 601 #define lpfc_rq_doorbell_id_SHIFT               0
 602 #define lpfc_rq_doorbell_id_MASK                0x03FF
 603 #define lpfc_rq_doorbell_id_WORD                word0
 604
 605 #define LPFC_WQ_DOORBELL                0x0040
 606 #define lpfc_wq_doorbell_num_posted_SHIFT       24
 607 #define lpfc_wq_doorbell_num_posted_MASK        0x00FF
 608 #define lpfc_wq_doorbell_num_posted_WORD        word0
 609 #define lpfc_wq_doorbell_index_SHIFT            16
 610 #define lpfc_wq_doorbell_index_MASK             0x00FF
 611 #define lpfc_wq_doorbell_index_WORD             word0
 612 #define lpfc_wq_doorbell_id_SHIFT               0
 613 #define lpfc_wq_doorbell_id_MASK                0xFFFF
 614 #define lpfc_wq_doorbell_id_WORD                word0
 615
 616 #define LPFC_EQCQ_DOORBELL              0x0120
 617 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 618 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 619 #define lpfc_eqcq_doorbell_arm_WORD             word0
 620 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 621 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 622 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 623 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 624 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 625 #define lpfc_eqcq_doorbell_qt_WORD              word0
 626 #define LPFC_QUEUE_TYPE_COMPLETION      0
 627 #define LPFC_QUEUE_TYPE_EVENT           1
 628 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 629 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 630 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 631 #define lpfc_eqcq_doorbell_cqid_SHIFT           0
 632 #define lpfc_eqcq_doorbell_cqid_MASK            0x03FF
 633 #define lpfc_eqcq_doorbell_cqid_WORD            word0
 634 #define lpfc_eqcq_doorbell_eqid_SHIFT           0
 635 #define lpfc_eqcq_doorbell_eqid_MASK            0x01FF
 636 #define lpfc_eqcq_doorbell_eqid_WORD            word0
 637
 638 #define LPFC_BMBX                       0x0160
 639 #define lpfc_bmbx_addr_SHIFT            2
 640 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 641 #define lpfc_bmbx_addr_WORD             word0
 642 #define lpfc_bmbx_hi_SHIFT              1
 643 #define lpfc_bmbx_hi_MASK               0x0001
 644 #define lpfc_bmbx_hi_WORD               word0
 645 #define lpfc_bmbx_rdy_SHIFT             0
 646 #define lpfc_bmbx_rdy_MASK              0x0001
 647 #define lpfc_bmbx_rdy_WORD              word0
 648
 649 #define LPFC_MQ_DOORBELL                        0x0140
 650 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 651 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 652 #define lpfc_mq_doorbell_num_posted_WORD        word0
 653 #define lpfc_mq_doorbell_id_SHIFT               0
 654 #define lpfc_mq_doorbell_id_MASK                0x03FF
 655 #define lpfc_mq_doorbell_id_WORD                word0
 656
 657 struct lpfc_sli4_cfg_mhdr {
 658         uint32_t word1;
 659 #define lpfc_mbox_hdr_emb_SHIFT         0
 660 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 661 #define lpfc_mbox_hdr_emb_WORD          word1
 662 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 663 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 664 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 665         uint32_t payload_length;
 666         uint32_t tag_lo;
 667         uint32_t tag_hi;
 668         uint32_t reserved5;
 669 };
 670
 671 union lpfc_sli4_cfg_shdr {
 672         struct {
 673                 uint32_t word6;
 674 #define lpfc_mbox_hdr_opcode_SHIFT              0
 675 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 676 #define lpfc_mbox_hdr_opcode_WORD               word6
 677 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 678 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 679 #define lpfc_mbox_hdr_subsystem_WORD            word6
 680 #define lpfc_mbox_hdr_port_number_SHIFT         16
 681 #define lpfc_mbox_hdr_port_number_MASK          0x000000FF
 682 #define lpfc_mbox_hdr_port_number_WORD          word6
 683 #define lpfc_mbox_hdr_domain_SHIFT              24
 684 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 685 #define lpfc_mbox_hdr_domain_WORD               word6
 686                 uint32_t timeout;
 687                 uint32_t request_length;
 688                 uint32_t reserved9;
 689         } request;
 690         struct {
 691                 uint32_t word6;
 692 #define lpfc_mbox_hdr_opcode_SHIFT              0
 693 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 694 #define lpfc_mbox_hdr_opcode_WORD               word6
 695 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 696 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 697 #define lpfc_mbox_hdr_subsystem_WORD            word6
 698 #define lpfc_mbox_hdr_domain_SHIFT              24
 699 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 700 #define lpfc_mbox_hdr_domain_WORD               word6
 701                 uint32_t word7;
 702 #define lpfc_mbox_hdr_status_SHIFT              0
 703 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 704 #define lpfc_mbox_hdr_status_WORD               word7
 705 #define lpfc_mbox_hdr_add_status_SHIFT          8
 706 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 707 #define lpfc_mbox_hdr_add_status_WORD           word7
 708                 uint32_t response_length;
 709                 uint32_t actual_response_length;
 710         } response;
 711 };
 712
 713 /* Mailbox structures */
 714 struct mbox_header {
 715         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 716         union  lpfc_sli4_cfg_shdr cfg_shdr;
 717 };
 718
 719 /* Subsystem Definitions */
 720 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
 721 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
 722
 723 /* Device Specific Definitions */
 724
 725 /* The HOST ENDIAN defines are in Big Endian format. */
 726 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
 727 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
 728
 729 /* Common Opcodes */
 730 #define LPFC_MBOX_OPCODE_CQ_CREATE              0x0C
 731 #define LPFC_MBOX_OPCODE_EQ_CREATE              0x0D
 732 #define LPFC_MBOX_OPCODE_MQ_CREATE              0x15
 733 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES    0x20
 734 #define LPFC_MBOX_OPCODE_NOP                    0x21
 735 #define LPFC_MBOX_OPCODE_MQ_DESTROY             0x35
 736 #define LPFC_MBOX_OPCODE_CQ_DESTROY             0x36
 737 #define LPFC_MBOX_OPCODE_EQ_DESTROY             0x37
 738 #define LPFC_MBOX_OPCODE_FUNCTION_RESET         0x3D
 739
 740 /* FCoE Opcodes */
 741 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
 742 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
 743 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
 744 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
 745 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
 746 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
 747 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
 748 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
 749 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
 750 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
 751
 752 /* Mailbox command structures */
 753 struct eq_context {
 754         uint32_t word0;
 755 #define lpfc_eq_context_size_SHIFT      31
 756 #define lpfc_eq_context_size_MASK       0x00000001
 757 #define lpfc_eq_context_size_WORD       word0
 758 #define LPFC_EQE_SIZE_4                 0x0
 759 #define LPFC_EQE_SIZE_16                0x1
 760 #define lpfc_eq_context_valid_SHIFT     29
 761 #define lpfc_eq_context_valid_MASK      0x00000001
 762 #define lpfc_eq_context_valid_WORD      word0
 763         uint32_t word1;
 764 #define lpfc_eq_context_count_SHIFT     26
 765 #define lpfc_eq_context_count_MASK      0x00000003
 766 #define lpfc_eq_context_count_WORD      word1
 767 #define LPFC_EQ_CNT_256         0x0
 768 #define LPFC_EQ_CNT_512         0x1
 769 #define LPFC_EQ_CNT_1024        0x2
 770 #define LPFC_EQ_CNT_2048        0x3
 771 #define LPFC_EQ_CNT_4096        0x4
 772         uint32_t word2;
 773 #define lpfc_eq_context_delay_multi_SHIFT       13
 774 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
 775 #define lpfc_eq_context_delay_multi_WORD        word2
 776         uint32_t reserved3;
 777 };
 778
 779 struct sgl_page_pairs {
 780         uint32_t sgl_pg0_addr_lo;
 781         uint32_t sgl_pg0_addr_hi;
 782         uint32_t sgl_pg1_addr_lo;
 783         uint32_t sgl_pg1_addr_hi;
 784 };
 785
 786 struct lpfc_mbx_post_sgl_pages {
 787         struct mbox_header header;
 788         uint32_t word0;
 789 #define lpfc_post_sgl_pages_xri_SHIFT   0
 790 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
 791 #define lpfc_post_sgl_pages_xri_WORD    word0
 792 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
 793 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
 794 #define lpfc_post_sgl_pages_xricnt_WORD word0
 795         struct sgl_page_pairs  sgl_pg_pairs[1];
 796 };
 797
 798 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
 799 struct lpfc_mbx_post_uembed_sgl_page1 {
 800         union  lpfc_sli4_cfg_shdr cfg_shdr;
 801         uint32_t word0;
 802         struct sgl_page_pairs sgl_pg_pairs;
 803 };
 804
 805 struct lpfc_mbx_sge {
 806         uint32_t pa_lo;
 807         uint32_t pa_hi;
 808         uint32_t length;
 809 };
 810
 811 struct lpfc_mbx_nembed_cmd {
 812         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 813 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
 814         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 815 };
 816
 817 struct lpfc_mbx_nembed_sge_virt {
 818         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 819 };
 820
 821 struct lpfc_mbx_eq_create {
 822         struct mbox_header header;
 823         union {
 824                 struct {
 825                         uint32_t word0;
 826 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
 827 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
 828 #define lpfc_mbx_eq_create_num_pages_WORD       word0
 829                         struct eq_context context;
 830                         struct dma_address page[LPFC_MAX_EQ_PAGE];
 831                 } request;
 832                 struct {
 833                         uint32_t word0;
 834 #define lpfc_mbx_eq_create_q_id_SHIFT   0
 835 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
 836 #define lpfc_mbx_eq_create_q_id_WORD    word0
 837                 } response;
 838         } u;
 839 };
 840
 841 struct lpfc_mbx_eq_destroy {
 842         struct mbox_header header;
 843         union {
 844                 struct {
 845                         uint32_t word0;
 846 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
 847 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
 848 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
 849                 } request;
 850                 struct {
 851                         uint32_t word0;
 852                 } response;
 853         } u;
 854 };
 855
 856 struct lpfc_mbx_nop {
 857         struct mbox_header header;
 858         uint32_t context[2];
 859 };
 860
 861 struct cq_context {
 862         uint32_t word0;
 863 #define lpfc_cq_context_event_SHIFT     31
 864 #define lpfc_cq_context_event_MASK      0x00000001
 865 #define lpfc_cq_context_event_WORD      word0
 866 #define lpfc_cq_context_valid_SHIFT     29
 867 #define lpfc_cq_context_valid_MASK      0x00000001
 868 #define lpfc_cq_context_valid_WORD      word0
 869 #define lpfc_cq_context_count_SHIFT     27
 870 #define lpfc_cq_context_count_MASK      0x00000003
 871 #define lpfc_cq_context_count_WORD      word0
 872 #define LPFC_CQ_CNT_256         0x0
 873 #define LPFC_CQ_CNT_512         0x1
 874 #define LPFC_CQ_CNT_1024        0x2
 875         uint32_t word1;
 876 #define lpfc_cq_eq_id_SHIFT             22
 877 #define lpfc_cq_eq_id_MASK              0x000000FF
 878 #define lpfc_cq_eq_id_WORD              word1
 879         uint32_t reserved0;
 880         uint32_t reserved1;
 881 };
 882
 883 struct lpfc_mbx_cq_create {
 884         struct mbox_header header;
 885         union {
 886                 struct {
 887                         uint32_t word0;
 888 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
 889 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
 890 #define lpfc_mbx_cq_create_num_pages_WORD       word0
 891                         struct cq_context context;
 892                         struct dma_address page[LPFC_MAX_CQ_PAGE];
 893                 } request;
 894                 struct {
 895                         uint32_t word0;
 896 #define lpfc_mbx_cq_create_q_id_SHIFT   0
 897 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
 898 #define lpfc_mbx_cq_create_q_id_WORD    word0
 899                 } response;
 900         } u;
 901 };
 902
 903 struct lpfc_mbx_cq_destroy {
 904         struct mbox_header header;
 905         union {
 906                 struct {
 907                         uint32_t word0;
 908 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
 909 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
 910 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
 911                 } request;
 912                 struct {
 913                         uint32_t word0;
 914                 } response;
 915         } u;
 916 };
 917
 918 struct wq_context {
 919         uint32_t reserved0;
 920         uint32_t reserved1;
 921         uint32_t reserved2;
 922         uint32_t reserved3;
 923 };
 924
 925 struct lpfc_mbx_wq_create {
 926         struct mbox_header header;
 927         union {
 928                 struct {
 929                         uint32_t word0;
 930 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
 931 #define lpfc_mbx_wq_create_num_pages_MASK       0x0000FFFF
 932 #define lpfc_mbx_wq_create_num_pages_WORD       word0
 933 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
 934 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
 935 #define lpfc_mbx_wq_create_cq_id_WORD           word0
 936                         struct dma_address page[LPFC_MAX_WQ_PAGE];
 937                 } request;
 938                 struct {
 939                         uint32_t word0;
 940 #define lpfc_mbx_wq_create_q_id_SHIFT   0
 941 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
 942 #define lpfc_mbx_wq_create_q_id_WORD    word0
 943                 } response;
 944         } u;
 945 };
 946
 947 struct lpfc_mbx_wq_destroy {
 948         struct mbox_header header;
 949         union {
 950                 struct {
 951                         uint32_t word0;
 952 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
 953 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
 954 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
 955                 } request;
 956                 struct {
 957                         uint32_t word0;
 958                 } response;
 959         } u;
 960 };
 961
 962 #define LPFC_HDR_BUF_SIZE 128
 963 #define LPFC_DATA_BUF_SIZE 4096
 964 struct rq_context {
 965         uint32_t word0;
 966 #define lpfc_rq_context_rq_size_SHIFT   16
 967 #define lpfc_rq_context_rq_size_MASK    0x0000000F
 968 #define lpfc_rq_context_rq_size_WORD    word0
 969 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
 970 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
 971 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
 972 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
 973         uint32_t reserved1;
 974         uint32_t word2;
 975 #define lpfc_rq_context_cq_id_SHIFT     16
 976 #define lpfc_rq_context_cq_id_MASK      0x000003FF
 977 #define lpfc_rq_context_cq_id_WORD      word2
 978 #define lpfc_rq_context_buf_size_SHIFT  0
 979 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
 980 #define lpfc_rq_context_buf_size_WORD   word2
 981         uint32_t reserved3;
 982 };
 983
 984 struct lpfc_mbx_rq_create {
 985         struct mbox_header header;
 986         union {
 987                 struct {
 988                         uint32_t word0;
 989 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
 990 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
 991 #define lpfc_mbx_rq_create_num_pages_WORD       word0
 992                         struct rq_context context;
 993                         struct dma_address page[LPFC_MAX_WQ_PAGE];
 994                 } request;
 995                 struct {
 996                         uint32_t word0;
 997 #define lpfc_mbx_rq_create_q_id_SHIFT   0
 998 #define lpfc_mbx_rq_create_q_id_MASK    0x0000FFFF
 999 #define lpfc_mbx_rq_create_q_id_WORD    word0
1000                 } response;
1001         } u;
1002 };
1003
1004 struct lpfc_mbx_rq_destroy {
1005         struct mbox_header header;
1006         union {
1007                 struct {
1008                         uint32_t word0;
1009 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1010 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1011 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1012                 } request;
1013                 struct {
1014                         uint32_t word0;
1015                 } response;
1016         } u;
1017 };
1018
1019 struct mq_context {
1020         uint32_t word0;
1021 #define lpfc_mq_context_cq_id_SHIFT     22
1022 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1023 #define lpfc_mq_context_cq_id_WORD      word0
1024 #define lpfc_mq_context_count_SHIFT     16
1025 #define lpfc_mq_context_count_MASK      0x0000000F
1026 #define lpfc_mq_context_count_WORD      word0
1027 #define LPFC_MQ_CNT_16          0x5
1028 #define LPFC_MQ_CNT_32          0x6
1029 #define LPFC_MQ_CNT_64          0x7
1030 #define LPFC_MQ_CNT_128         0x8
1031         uint32_t word1;
1032 #define lpfc_mq_context_valid_SHIFT     31
1033 #define lpfc_mq_context_valid_MASK      0x00000001
1034 #define lpfc_mq_context_valid_WORD      word1
1035         uint32_t reserved2;
1036         uint32_t reserved3;
1037 };
1038
1039 struct lpfc_mbx_mq_create {
1040         struct mbox_header header;
1041         union {
1042                 struct {
1043                         uint32_t word0;
1044 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1045 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1046 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1047                         struct mq_context context;
1048                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1049                 } request;
1050                 struct {
1051                         uint32_t word0;
1052 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1053 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1054 #define lpfc_mbx_mq_create_q_id_WORD    word0
1055                 } response;
1056         } u;
1057 };
1058
1059 struct lpfc_mbx_mq_destroy {
1060         struct mbox_header header;
1061         union {
1062                 struct {
1063                         uint32_t word0;
1064 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1065 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1066 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1067                 } request;
1068                 struct {
1069                         uint32_t word0;
1070                 } response;
1071         } u;
1072 };
1073
1074 struct lpfc_mbx_post_hdr_tmpl {
1075         struct mbox_header header;
1076         uint32_t word10;
1077 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
1078 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
1079 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
1080 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
1081 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
1082 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
1083         uint32_t rpi_paddr_lo;
1084         uint32_t rpi_paddr_hi;
1085 };
1086
1087 struct sli4_sge {       /* SLI-4 */
1088         uint32_t addr_hi;
1089         uint32_t addr_lo;
1090
1091         uint32_t word2;
1092 #define lpfc_sli4_sge_offset_SHIFT      0 /* Offset of buffer - Not used*/
1093 #define lpfc_sli4_sge_offset_MASK       0x00FFFFFF
1094 #define lpfc_sli4_sge_offset_WORD       word2
1095 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets
1096                                                 this  flag !! */
1097 #define lpfc_sli4_sge_last_MASK         0x00000001
1098 #define lpfc_sli4_sge_last_WORD         word2
1099         uint32_t word3;
1100 #define lpfc_sli4_sge_len_SHIFT         0
1101 #define lpfc_sli4_sge_len_MASK          0x0001FFFF
1102 #define lpfc_sli4_sge_len_WORD          word3
1103 };
1104
1105 struct fcf_record {
1106         uint32_t max_rcv_size;
1107         uint32_t fka_adv_period;
1108         uint32_t fip_priority;
1109         uint32_t word3;
1110 #define lpfc_fcf_record_mac_0_SHIFT             0
1111 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
1112 #define lpfc_fcf_record_mac_0_WORD              word3
1113 #define lpfc_fcf_record_mac_1_SHIFT             8
1114 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
1115 #define lpfc_fcf_record_mac_1_WORD              word3
1116 #define lpfc_fcf_record_mac_2_SHIFT             16
1117 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
1118 #define lpfc_fcf_record_mac_2_WORD              word3
1119 #define lpfc_fcf_record_mac_3_SHIFT             24
1120 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
1121 #define lpfc_fcf_record_mac_3_WORD              word3
1122         uint32_t word4;
1123 #define lpfc_fcf_record_mac_4_SHIFT             0
1124 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
1125 #define lpfc_fcf_record_mac_4_WORD              word4
1126 #define lpfc_fcf_record_mac_5_SHIFT             8
1127 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
1128 #define lpfc_fcf_record_mac_5_WORD              word4
1129 #define lpfc_fcf_record_fcf_avail_SHIFT         16
1130 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
1131 #define lpfc_fcf_record_fc_avail_WORD           word4
1132 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
1133 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
1134 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
1135 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
1136 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
1137         uint32_t word5;
1138 #define lpfc_fcf_record_fab_name_0_SHIFT        0
1139 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
1140 #define lpfc_fcf_record_fab_name_0_WORD         word5
1141 #define lpfc_fcf_record_fab_name_1_SHIFT        8
1142 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
1143 #define lpfc_fcf_record_fab_name_1_WORD         word5
1144 #define lpfc_fcf_record_fab_name_2_SHIFT        16
1145 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
1146 #define lpfc_fcf_record_fab_name_2_WORD         word5
1147 #define lpfc_fcf_record_fab_name_3_SHIFT        24
1148 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
1149 #define lpfc_fcf_record_fab_name_3_WORD         word5
1150         uint32_t word6;
1151 #define lpfc_fcf_record_fab_name_4_SHIFT        0
1152 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
1153 #define lpfc_fcf_record_fab_name_4_WORD         word6
1154 #define lpfc_fcf_record_fab_name_5_SHIFT        8
1155 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
1156 #define lpfc_fcf_record_fab_name_5_WORD         word6
1157 #define lpfc_fcf_record_fab_name_6_SHIFT        16
1158 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
1159 #define lpfc_fcf_record_fab_name_6_WORD         word6
1160 #define lpfc_fcf_record_fab_name_7_SHIFT        24
1161 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
1162 #define lpfc_fcf_record_fab_name_7_WORD         word6
1163         uint32_t word7;
1164 #define lpfc_fcf_record_fc_map_0_SHIFT          0
1165 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
1166 #define lpfc_fcf_record_fc_map_0_WORD           word7
1167 #define lpfc_fcf_record_fc_map_1_SHIFT          8
1168 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
1169 #define lpfc_fcf_record_fc_map_1_WORD           word7
1170 #define lpfc_fcf_record_fc_map_2_SHIFT          16
1171 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
1172 #define lpfc_fcf_record_fc_map_2_WORD           word7
1173 #define lpfc_fcf_record_fcf_valid_SHIFT         24
1174 #define lpfc_fcf_record_fcf_valid_MASK          0x000000FF
1175 #define lpfc_fcf_record_fcf_valid_WORD          word7
1176         uint32_t word8;
1177 #define lpfc_fcf_record_fcf_index_SHIFT         0
1178 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
1179 #define lpfc_fcf_record_fcf_index_WORD          word8
1180 #define lpfc_fcf_record_fcf_state_SHIFT         16
1181 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
1182 #define lpfc_fcf_record_fcf_state_WORD          word8
1183         uint8_t vlan_bitmap[512];
1184 };
1185
1186 struct lpfc_mbx_read_fcf_tbl {
1187         union lpfc_sli4_cfg_shdr cfg_shdr;
1188         union {
1189                 struct {
1190                         uint32_t word10;
1191 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
1192 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
1193 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
1194                 } request;
1195                 struct {
1196                         uint32_t eventag;
1197                 } response;
1198         } u;
1199         uint32_t word11;
1200 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
1201 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
1202 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
1203 };
1204
1205 struct lpfc_mbx_add_fcf_tbl_entry {
1206         union lpfc_sli4_cfg_shdr cfg_shdr;
1207         uint32_t word10;
1208 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
1209 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
1210 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
1211         struct lpfc_mbx_sge fcf_sge;
1212 };
1213
1214 struct lpfc_mbx_del_fcf_tbl_entry {
1215         struct mbox_header header;
1216         uint32_t word10;
1217 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
1218 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
1219 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
1220 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
1221 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
1222 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
1223 };
1224
1225 /* Status field for embedded SLI_CONFIG mailbox command */
1226 #define STATUS_SUCCESS                                  0x0
1227 #define STATUS_FAILED                                   0x1
1228 #define STATUS_ILLEGAL_REQUEST                          0x2
1229 #define STATUS_ILLEGAL_FIELD                            0x3
1230 #define STATUS_INSUFFICIENT_BUFFER                      0x4
1231 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
1232 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
1233 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
1234 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
1235 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
1236 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
1237 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
1238 #define STATUS_ASSERT_FAILED                            0x1e
1239 #define STATUS_INVALID_SESSION                          0x1f
1240 #define STATUS_INVALID_CONNECTION                       0x20
1241 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
1242 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
1243 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
1244 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
1245 #define STATUS_FLASHROM_READ_FAILED                     0x27
1246 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
1247 #define STATUS_ERROR_ACITMAIN                           0x2a
1248 #define STATUS_REBOOT_REQUIRED                          0x2c
1249 #define STATUS_FCF_IN_USE                               0x3a
1250
1251 struct lpfc_mbx_sli4_config {
1252         struct mbox_header header;
1253 };
1254
1255 struct lpfc_mbx_init_vfi {
1256         uint32_t word1;
1257 #define lpfc_init_vfi_vr_SHIFT          31
1258 #define lpfc_init_vfi_vr_MASK           0x00000001
1259 #define lpfc_init_vfi_vr_WORD           word1
1260 #define lpfc_init_vfi_vt_SHIFT          30
1261 #define lpfc_init_vfi_vt_MASK           0x00000001
1262 #define lpfc_init_vfi_vt_WORD           word1
1263 #define lpfc_init_vfi_vf_SHIFT          29
1264 #define lpfc_init_vfi_vf_MASK           0x00000001
1265 #define lpfc_init_vfi_vf_WORD           word1
1266 #define lpfc_init_vfi_vfi_SHIFT         0
1267 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
1268 #define lpfc_init_vfi_vfi_WORD          word1
1269         uint32_t word2;
1270 #define lpfc_init_vfi_fcfi_SHIFT        0
1271 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
1272 #define lpfc_init_vfi_fcfi_WORD         word2
1273         uint32_t word3;
1274 #define lpfc_init_vfi_pri_SHIFT         13
1275 #define lpfc_init_vfi_pri_MASK          0x00000007
1276 #define lpfc_init_vfi_pri_WORD          word3
1277 #define lpfc_init_vfi_vf_id_SHIFT       1
1278 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
1279 #define lpfc_init_vfi_vf_id_WORD        word3
1280         uint32_t word4;
1281 #define lpfc_init_vfi_hop_count_SHIFT   24
1282 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
1283 #define lpfc_init_vfi_hop_count_WORD    word4
1284 };
1285
1286 struct lpfc_mbx_reg_vfi {
1287         uint32_t word1;
1288 #define lpfc_reg_vfi_vp_SHIFT           28
1289 #define lpfc_reg_vfi_vp_MASK            0x00000001
1290 #define lpfc_reg_vfi_vp_WORD            word1
1291 #define lpfc_reg_vfi_vfi_SHIFT          0
1292 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
1293 #define lpfc_reg_vfi_vfi_WORD           word1
1294         uint32_t word2;
1295 #define lpfc_reg_vfi_vpi_SHIFT          16
1296 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
1297 #define lpfc_reg_vfi_vpi_WORD           word2
1298 #define lpfc_reg_vfi_fcfi_SHIFT         0
1299 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
1300 #define lpfc_reg_vfi_fcfi_WORD          word2
1301         uint32_t word3_rsvd;
1302         uint32_t word4_rsvd;
1303         struct ulp_bde64 bde;
1304         uint32_t word8_rsvd;
1305         uint32_t word9_rsvd;
1306         uint32_t word10;
1307 #define lpfc_reg_vfi_nport_id_SHIFT             0
1308 #define lpfc_reg_vfi_nport_id_MASK              0x00FFFFFF
1309 #define lpfc_reg_vfi_nport_id_WORD              word10
1310 };
1311
1312 struct lpfc_mbx_init_vpi {
1313         uint32_t word1;
1314 #define lpfc_init_vpi_vfi_SHIFT         16
1315 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
1316 #define lpfc_init_vpi_vfi_WORD          word1
1317 #define lpfc_init_vpi_vpi_SHIFT         0
1318 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
1319 #define lpfc_init_vpi_vpi_WORD          word1
1320 };
1321
1322 struct lpfc_mbx_read_vpi {
1323         uint32_t word1_rsvd;
1324         uint32_t word2;
1325 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
1326 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
1327 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
1328         uint32_t word3_rsvd;
1329         uint32_t word4;
1330 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
1331 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
1332 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
1333 #define lpfc_mbx_read_vpi_pb_SHIFT              15
1334 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
1335 #define lpfc_mbx_read_vpi_pb_WORD               word4
1336 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
1337 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
1338 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
1339 #define lpfc_mbx_read_vpi_ns_SHIFT              30
1340 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
1341 #define lpfc_mbx_read_vpi_ns_WORD               word4
1342 #define lpfc_mbx_read_vpi_hl_SHIFT              31
1343 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
1344 #define lpfc_mbx_read_vpi_hl_WORD               word4
1345         uint32_t word5_rsvd;
1346         uint32_t word6;
1347 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
1348 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
1349 #define lpfc_mbx_read_vpi_vpi_WORD              word6
1350         uint32_t word7;
1351 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
1352 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
1353 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
1354 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
1355 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
1356 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
1357 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
1358 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
1359 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
1360 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
1361 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
1362 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
1363         uint32_t word8;
1364 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
1365 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
1366 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
1367 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
1368 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
1369 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
1370 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
1371 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
1372 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
1373 #define lpfc_mbx_read_vpi_vv_SHIFT              28
1374 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
1375 #define lpfc_mbx_read_vpi_vv_WORD               word8
1376 };
1377
1378 struct lpfc_mbx_unreg_vfi {
1379         uint32_t word1_rsvd;
1380         uint32_t word2;
1381 #define lpfc_unreg_vfi_vfi_SHIFT        0
1382 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
1383 #define lpfc_unreg_vfi_vfi_WORD         word2
1384 };
1385
1386 struct lpfc_mbx_resume_rpi {
1387         uint32_t word1;
1388 #define lpfc_resume_rpi_rpi_SHIFT       0
1389 #define lpfc_resume_rpi_rpi_MASK        0x0000FFFF
1390 #define lpfc_resume_rpi_rpi_WORD        word1
1391         uint32_t event_tag;
1392         uint32_t word3_rsvd;
1393         uint32_t word4_rsvd;
1394         uint32_t word5_rsvd;
1395         uint32_t word6;
1396 #define lpfc_resume_rpi_vpi_SHIFT       0
1397 #define lpfc_resume_rpi_vpi_MASK        0x0000FFFF
1398 #define lpfc_resume_rpi_vpi_WORD        word6
1399 #define lpfc_resume_rpi_vfi_SHIFT       16
1400 #define lpfc_resume_rpi_vfi_MASK        0x0000FFFF
1401 #define lpfc_resume_rpi_vfi_WORD        word6
1402 };
1403
1404 #define REG_FCF_INVALID_QID     0xFFFF
1405 struct lpfc_mbx_reg_fcfi {
1406         uint32_t word1;
1407 #define lpfc_reg_fcfi_info_index_SHIFT  0
1408 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
1409 #define lpfc_reg_fcfi_info_index_WORD   word1
1410 #define lpfc_reg_fcfi_fcfi_SHIFT        16
1411 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
1412 #define lpfc_reg_fcfi_fcfi_WORD         word1
1413         uint32_t word2;
1414 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
1415 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
1416 #define lpfc_reg_fcfi_rq_id1_WORD       word2
1417 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
1418 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
1419 #define lpfc_reg_fcfi_rq_id0_WORD       word2
1420         uint32_t word3;
1421 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
1422 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
1423 #define lpfc_reg_fcfi_rq_id3_WORD       word3
1424 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
1425 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
1426 #define lpfc_reg_fcfi_rq_id2_WORD       word3
1427         uint32_t word4;
1428 #define lpfc_reg_fcfi_type_match0_SHIFT 24
1429 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
1430 #define lpfc_reg_fcfi_type_match0_WORD  word4
1431 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
1432 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
1433 #define lpfc_reg_fcfi_type_mask0_WORD   word4
1434 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1435 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
1436 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
1437 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
1438 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
1439 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
1440         uint32_t word5;
1441 #define lpfc_reg_fcfi_type_match1_SHIFT 24
1442 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
1443 #define lpfc_reg_fcfi_type_match1_WORD  word5
1444 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
1445 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
1446 #define lpfc_reg_fcfi_type_mask1_WORD   word5
1447 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
1448 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
1449 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
1450 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
1451 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
1452 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
1453         uint32_t word6;
1454 #define lpfc_reg_fcfi_type_match2_SHIFT 24
1455 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
1456 #define lpfc_reg_fcfi_type_match2_WORD  word6
1457 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
1458 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
1459 #define lpfc_reg_fcfi_type_mask2_WORD   word6
1460 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
1461 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
1462 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
1463 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
1464 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
1465 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
1466         uint32_t word7;
1467 #define lpfc_reg_fcfi_type_match3_SHIFT 24
1468 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
1469 #define lpfc_reg_fcfi_type_match3_WORD  word7
1470 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
1471 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
1472 #define lpfc_reg_fcfi_type_mask3_WORD   word7
1473 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
1474 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
1475 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
1476 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
1477 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
1478 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
1479         uint32_t word8;
1480 #define lpfc_reg_fcfi_mam_SHIFT         13
1481 #define lpfc_reg_fcfi_mam_MASK          0x00000003
1482 #define lpfc_reg_fcfi_mam_WORD          word8
1483 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
1484 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
1485 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
1486 #define lpfc_reg_fcfi_vv_SHIFT          12
1487 #define lpfc_reg_fcfi_vv_MASK           0x00000001
1488 #define lpfc_reg_fcfi_vv_WORD           word8
1489 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
1490 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
1491 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
1492 };
1493
1494 struct lpfc_mbx_unreg_fcfi {
1495         uint32_t word1_rsv;
1496         uint32_t word2;
1497 #define lpfc_unreg_fcfi_SHIFT           0
1498 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
1499 #define lpfc_unreg_fcfi_WORD            word2
1500 };
1501
1502 struct lpfc_mbx_read_rev {
1503         uint32_t word1;
1504 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
1505 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
1506 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
1507 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
1508 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
1509 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
1510 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
1511 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
1512 #define lpfc_mbx_rd_rev_vpd_WORD                word1
1513         uint32_t first_hw_rev;
1514         uint32_t second_hw_rev;
1515         uint32_t word4_rsvd;
1516         uint32_t third_hw_rev;
1517         uint32_t word6;
1518 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
1519 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
1520 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
1521 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
1522 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
1523 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
1524 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
1525 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
1526 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
1527 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
1528 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
1529 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
1530         uint32_t word7_rsvd;
1531         uint32_t fw_id_rev;
1532         uint8_t  fw_name[16];
1533         uint32_t ulp_fw_id_rev;
1534         uint8_t  ulp_fw_name[16];
1535         uint32_t word18_47_rsvd[30];
1536         uint32_t word48;
1537 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
1538 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
1539 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
1540         uint32_t vpd_paddr_low;
1541         uint32_t vpd_paddr_high;
1542         uint32_t avail_vpd_len;
1543         uint32_t rsvd_52_63[12];
1544 };
1545
1546 struct lpfc_mbx_read_config {
1547         uint32_t word1;
1548 #define lpfc_mbx_rd_conf_max_bbc_SHIFT          0
1549 #define lpfc_mbx_rd_conf_max_bbc_MASK           0x000000FF
1550 #define lpfc_mbx_rd_conf_max_bbc_WORD           word1
1551 #define lpfc_mbx_rd_conf_init_bbc_SHIFT         8
1552 #define lpfc_mbx_rd_conf_init_bbc_MASK          0x000000FF
1553 #define lpfc_mbx_rd_conf_init_bbc_WORD          word1
1554         uint32_t word2;
1555 #define lpfc_mbx_rd_conf_nport_did_SHIFT        0
1556 #define lpfc_mbx_rd_conf_nport_did_MASK         0x00FFFFFF
1557 #define lpfc_mbx_rd_conf_nport_did_WORD         word2
1558 #define lpfc_mbx_rd_conf_topology_SHIFT         24
1559 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
1560 #define lpfc_mbx_rd_conf_topology_WORD          word2
1561         uint32_t word3;
1562 #define lpfc_mbx_rd_conf_ao_SHIFT               0
1563 #define lpfc_mbx_rd_conf_ao_MASK                0x00000001
1564 #define lpfc_mbx_rd_conf_ao_WORD                word3
1565 #define lpfc_mbx_rd_conf_bb_scn_SHIFT           8
1566 #define lpfc_mbx_rd_conf_bb_scn_MASK            0x0000000F
1567 #define lpfc_mbx_rd_conf_bb_scn_WORD            word3
1568 #define lpfc_mbx_rd_conf_cbb_scn_SHIFT          12
1569 #define lpfc_mbx_rd_conf_cbb_scn_MASK           0x0000000F
1570 #define lpfc_mbx_rd_conf_cbb_scn_WORD           word3
1571 #define lpfc_mbx_rd_conf_mc_SHIFT               29
1572 #define lpfc_mbx_rd_conf_mc_MASK                0x00000001
1573 #define lpfc_mbx_rd_conf_mc_WORD                word3
1574         uint32_t word4;
1575 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
1576 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
1577 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
1578         uint32_t word5;
1579 #define lpfc_mbx_rd_conf_lp_tov_SHIFT           0
1580 #define lpfc_mbx_rd_conf_lp_tov_MASK            0x0000FFFF
1581 #define lpfc_mbx_rd_conf_lp_tov_WORD            word5
1582         uint32_t word6;
1583 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
1584 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
1585 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
1586         uint32_t word7;
1587 #define lpfc_mbx_rd_conf_r_t_tov_SHIFT          0
1588 #define lpfc_mbx_rd_conf_r_t_tov_MASK           0x000000FF
1589 #define lpfc_mbx_rd_conf_r_t_tov_WORD           word7
1590         uint32_t word8;
1591 #define lpfc_mbx_rd_conf_al_tov_SHIFT           0
1592 #define lpfc_mbx_rd_conf_al_tov_MASK            0x0000000F
1593 #define lpfc_mbx_rd_conf_al_tov_WORD            word8
1594         uint32_t word9;
1595 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
1596 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
1597 #define lpfc_mbx_rd_conf_lmt_WORD               word9
1598         uint32_t word10;
1599 #define lpfc_mbx_rd_conf_max_alpa_SHIFT         0
1600 #define lpfc_mbx_rd_conf_max_alpa_MASK          0x000000FF
1601 #define lpfc_mbx_rd_conf_max_alpa_WORD          word10
1602         uint32_t word11_rsvd;
1603         uint32_t word12;
1604 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
1605 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
1606 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
1607 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
1608 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
1609 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
1610         uint32_t word13;
1611 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
1612 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
1613 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
1614 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
1615 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
1616 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
1617         uint32_t word14;
1618 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
1619 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
1620 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
1621 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
1622 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
1623 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
1624         uint32_t word15;
1625 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
1626 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
1627 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
1628 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
1629 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
1630 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
1631         uint32_t word16;
1632 #define lpfc_mbx_rd_conf_fcfi_base_SHIFT        0
1633 #define lpfc_mbx_rd_conf_fcfi_base_MASK         0x0000FFFF
1634 #define lpfc_mbx_rd_conf_fcfi_base_WORD         word16
1635 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
1636 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
1637 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
1638         uint32_t word17;
1639 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
1640 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
1641 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
1642 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
1643 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
1644 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
1645         uint32_t word18;
1646 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
1647 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
1648 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
1649 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
1650 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
1651 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
1652 };
1653
1654 struct lpfc_mbx_request_features {
1655         uint32_t word1;
1656 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
1657 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
1658 #define lpfc_mbx_rq_ftr_qry_WORD                word1
1659         uint32_t word2;
1660 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
1661 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
1662 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
1663 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
1664 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
1665 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
1666 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
1667 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
1668 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
1669 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
1670 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
1671 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
1672 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
1673 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
1674 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
1675 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
1676 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
1677 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
1678 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
1679 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
1680 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
1681 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
1682 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
1683 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
1684         uint32_t word3;
1685 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
1686 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
1687 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
1688 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
1689 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
1690 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
1691 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
1692 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
1693 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
1694 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
1695 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
1696 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
1697 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
1698 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
1699 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
1700 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
1701 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
1702 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
1703 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
1704 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
1705 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
1706 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
1707 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
1708 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
1709 };
1710
1711 /* Mailbox Completion Queue Error Messages */
1712 #define MB_CQE_STATUS_SUCCESS                   0x0
1713 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
1714 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
1715 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
1716 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
1717 #define MB_CQE_STATUS_DMA_FAILED                0x5
1718
1719 /* mailbox queue entry structure */
1720 struct lpfc_mqe {
1721         uint32_t word0;
1722 #define lpfc_mqe_status_SHIFT           16
1723 #define lpfc_mqe_status_MASK            0x0000FFFF
1724 #define lpfc_mqe_status_WORD            word0
1725 #define lpfc_mqe_command_SHIFT          8
1726 #define lpfc_mqe_command_MASK           0x000000FF
1727 #define lpfc_mqe_command_WORD           word0
1728         union {
1729                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
1730                 /* sli4 mailbox commands */
1731                 struct lpfc_mbx_sli4_config sli4_config;
1732                 struct lpfc_mbx_init_vfi init_vfi;
1733                 struct lpfc_mbx_reg_vfi reg_vfi;
1734                 struct lpfc_mbx_reg_vfi unreg_vfi;
1735                 struct lpfc_mbx_init_vpi init_vpi;
1736                 struct lpfc_mbx_resume_rpi resume_rpi;
1737                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
1738                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
1739                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
1740                 struct lpfc_mbx_reg_fcfi reg_fcfi;
1741                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
1742                 struct lpfc_mbx_mq_create mq_create;
1743                 struct lpfc_mbx_eq_create eq_create;
1744                 struct lpfc_mbx_cq_create cq_create;
1745                 struct lpfc_mbx_wq_create wq_create;
1746                 struct lpfc_mbx_rq_create rq_create;
1747                 struct lpfc_mbx_mq_destroy mq_destroy;
1748                 struct lpfc_mbx_eq_destroy eq_destroy;
1749                 struct lpfc_mbx_cq_destroy cq_destroy;
1750                 struct lpfc_mbx_wq_destroy wq_destroy;
1751                 struct lpfc_mbx_rq_destroy rq_destroy;
1752                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
1753                 struct lpfc_mbx_nembed_cmd nembed_cmd;
1754                 struct lpfc_mbx_read_rev read_rev;
1755                 struct lpfc_mbx_read_vpi read_vpi;
1756                 struct lpfc_mbx_read_config rd_config;
1757                 struct lpfc_mbx_request_features req_ftrs;
1758                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
1759                 struct lpfc_mbx_nop nop;
1760         } un;
1761 };
1762
1763 struct lpfc_mcqe {
1764         uint32_t word0;
1765 #define lpfc_mcqe_status_SHIFT          0
1766 #define lpfc_mcqe_status_MASK           0x0000FFFF
1767 #define lpfc_mcqe_status_WORD           word0
1768 #define lpfc_mcqe_ext_status_SHIFT      16
1769 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
1770 #define lpfc_mcqe_ext_status_WORD       word0
1771         uint32_t mcqe_tag0;
1772         uint32_t mcqe_tag1;
1773         uint32_t trailer;
1774 #define lpfc_trailer_valid_SHIFT        31
1775 #define lpfc_trailer_valid_MASK         0x00000001
1776 #define lpfc_trailer_valid_WORD         trailer
1777 #define lpfc_trailer_async_SHIFT        30
1778 #define lpfc_trailer_async_MASK         0x00000001
1779 #define lpfc_trailer_async_WORD         trailer
1780 #define lpfc_trailer_hpi_SHIFT          29
1781 #define lpfc_trailer_hpi_MASK           0x00000001
1782 #define lpfc_trailer_hpi_WORD           trailer
1783 #define lpfc_trailer_completed_SHIFT    28
1784 #define lpfc_trailer_completed_MASK     0x00000001
1785 #define lpfc_trailer_completed_WORD     trailer
1786 #define lpfc_trailer_consumed_SHIFT     27
1787 #define lpfc_trailer_consumed_MASK      0x00000001
1788 #define lpfc_trailer_consumed_WORD      trailer
1789 #define lpfc_trailer_type_SHIFT         16
1790 #define lpfc_trailer_type_MASK          0x000000FF
1791 #define lpfc_trailer_type_WORD          trailer
1792 #define lpfc_trailer_code_SHIFT         8
1793 #define lpfc_trailer_code_MASK          0x000000FF
1794 #define lpfc_trailer_code_WORD          trailer
1795 #define LPFC_TRAILER_CODE_LINK  0x1
1796 #define LPFC_TRAILER_CODE_FCOE  0x2
1797 #define LPFC_TRAILER_CODE_DCBX  0x3
1798 };
1799
1800 struct lpfc_acqe_link {
1801         uint32_t word0;
1802 #define lpfc_acqe_link_speed_SHIFT              24
1803 #define lpfc_acqe_link_speed_MASK               0x000000FF
1804 #define lpfc_acqe_link_speed_WORD               word0
1805 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
1806 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
1807 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
1808 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
1809 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
1810 #define lpfc_acqe_link_duplex_SHIFT             16
1811 #define lpfc_acqe_link_duplex_MASK              0x000000FF
1812 #define lpfc_acqe_link_duplex_WORD              word0
1813 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
1814 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
1815 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
1816 #define lpfc_acqe_link_status_SHIFT             8
1817 #define lpfc_acqe_link_status_MASK              0x000000FF
1818 #define lpfc_acqe_link_status_WORD              word0
1819 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
1820 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
1821 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
1822 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
1823 #define lpfc_acqe_link_physical_SHIFT           0
1824 #define lpfc_acqe_link_physical_MASK            0x000000FF
1825 #define lpfc_acqe_link_physical_WORD            word0
1826 #define LPFC_ASYNC_LINK_PORT_A                  0x0
1827 #define LPFC_ASYNC_LINK_PORT_B                  0x1
1828         uint32_t word1;
1829 #define lpfc_acqe_link_fault_SHIFT      0
1830 #define lpfc_acqe_link_fault_MASK       0x000000FF
1831 #define lpfc_acqe_link_fault_WORD       word1
1832 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
1833 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
1834 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
1835         uint32_t event_tag;
1836         uint32_t trailer;
1837 };
1838
1839 struct lpfc_acqe_fcoe {
1840         uint32_t fcf_index;
1841         uint32_t word1;
1842 #define lpfc_acqe_fcoe_fcf_count_SHIFT          0
1843 #define lpfc_acqe_fcoe_fcf_count_MASK           0x0000FFFF
1844 #define lpfc_acqe_fcoe_fcf_count_WORD           word1
1845 #define lpfc_acqe_fcoe_event_type_SHIFT         16
1846 #define lpfc_acqe_fcoe_event_type_MASK          0x0000FFFF
1847 #define lpfc_acqe_fcoe_event_type_WORD          word1
1848 #define LPFC_FCOE_EVENT_TYPE_NEW_FCF            0x1
1849 #define LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL     0x2
1850 #define LPFC_FCOE_EVENT_TYPE_FCF_DEAD           0x3
1851         uint32_t event_tag;
1852         uint32_t trailer;
1853 };
1854
1855 struct lpfc_acqe_dcbx {
1856         uint32_t tlv_ttl;
1857         uint32_t reserved;
1858         uint32_t event_tag;
1859         uint32_t trailer;
1860 };
1861
1862 /*
1863  * Define the bootstrap mailbox (bmbx) region used to communicate
1864  * mailbox command between the host and port. The mailbox consists
1865  * of a payload area of 256 bytes and a completion queue of length
1866  * 16 bytes.
1867  */
1868 struct lpfc_bmbx_create {
1869         struct lpfc_mqe mqe;
1870         struct lpfc_mcqe mcqe;
1871 };
1872
1873 #define SGL_ALIGN_SZ 64
1874 #define SGL_PAGE_SIZE 4096
1875 /* align SGL addr on a size boundary - adjust address up */
1876 #define NO_XRI ((uint16_t)-1)
1877 struct wqe_common {
1878         uint32_t word6;
1879 #define wqe_xri_SHIFT         0
1880 #define wqe_xri_MASK          0x0000FFFF
1881 #define wqe_xri_WORD          word6
1882 #define wqe_ctxt_tag_SHIFT    16
1883 #define wqe_ctxt_tag_MASK     0x0000FFFF
1884 #define wqe_ctxt_tag_WORD     word6
1885         uint32_t word7;
1886 #define wqe_ct_SHIFT          2
1887 #define wqe_ct_MASK           0x00000003
1888 #define wqe_ct_WORD           word7
1889 #define wqe_status_SHIFT      4
1890 #define wqe_status_MASK       0x0000000f
1891 #define wqe_status_WORD       word7
1892 #define wqe_cmnd_SHIFT        8
1893 #define wqe_cmnd_MASK         0x000000ff
1894 #define wqe_cmnd_WORD         word7
1895 #define wqe_class_SHIFT       16
1896 #define wqe_class_MASK        0x00000007
1897 #define wqe_class_WORD        word7
1898 #define wqe_pu_SHIFT          20
1899 #define wqe_pu_MASK           0x00000003
1900 #define wqe_pu_WORD           word7
1901 #define wqe_erp_SHIFT         22
1902 #define wqe_erp_MASK          0x00000001
1903 #define wqe_erp_WORD          word7
1904 #define wqe_lnk_SHIFT         23
1905 #define wqe_lnk_MASK          0x00000001
1906 #define wqe_lnk_WORD          word7
1907 #define wqe_tmo_SHIFT         24
1908 #define wqe_tmo_MASK          0x000000ff
1909 #define wqe_tmo_WORD          word7
1910         uint32_t abort_tag; /* word 8 in WQE */
1911         uint32_t word9;
1912 #define wqe_reqtag_SHIFT      0
1913 #define wqe_reqtag_MASK       0x0000FFFF
1914 #define wqe_reqtag_WORD       word9
1915 #define wqe_rcvoxid_SHIFT     16
1916 #define wqe_rcvoxid_MASK       0x0000FFFF
1917 #define wqe_rcvoxid_WORD       word9
1918         uint32_t word10;
1919 #define wqe_pri_SHIFT         16
1920 #define wqe_pri_MASK          0x00000007
1921 #define wqe_pri_WORD          word10
1922 #define wqe_pv_SHIFT          19
1923 #define wqe_pv_MASK           0x00000001
1924 #define wqe_pv_WORD           word10
1925 #define wqe_xc_SHIFT          21
1926 #define wqe_xc_MASK           0x00000001
1927 #define wqe_xc_WORD           word10
1928 #define wqe_ccpe_SHIFT        23
1929 #define wqe_ccpe_MASK         0x00000001
1930 #define wqe_ccpe_WORD         word10
1931 #define wqe_ccp_SHIFT         24
1932 #define wqe_ccp_MASK         0x000000ff
1933 #define wqe_ccp_WORD         word10
1934         uint32_t word11;
1935 #define wqe_cmd_type_SHIFT  0
1936 #define wqe_cmd_type_MASK   0x0000000f
1937 #define wqe_cmd_type_WORD   word11
1938 #define wqe_wqec_SHIFT      7
1939 #define wqe_wqec_MASK       0x00000001
1940 #define wqe_wqec_WORD       word11
1941 #define wqe_cqid_SHIFT      16
1942 #define wqe_cqid_MASK       0x000003ff
1943 #define wqe_cqid_WORD       word11
1944 };
1945
1946 struct wqe_did {
1947         uint32_t word5;
1948 #define wqe_els_did_SHIFT         0
1949 #define wqe_els_did_MASK          0x00FFFFFF
1950 #define wqe_els_did_WORD          word5
1951 #define wqe_xmit_bls_ar_SHIFT         30
1952 #define wqe_xmit_bls_ar_MASK          0x00000001
1953 #define wqe_xmit_bls_ar_WORD          word5
1954 #define wqe_xmit_bls_xo_SHIFT         31
1955 #define wqe_xmit_bls_xo_MASK          0x00000001
1956 #define wqe_xmit_bls_xo_WORD          word5
1957 };
1958
1959 struct els_request64_wqe {
1960         struct ulp_bde64 bde;
1961         uint32_t payload_len;
1962         uint32_t word4;
1963 #define els_req64_sid_SHIFT         0
1964 #define els_req64_sid_MASK          0x00FFFFFF
1965 #define els_req64_sid_WORD          word4
1966 #define els_req64_sp_SHIFT          24
1967 #define els_req64_sp_MASK           0x00000001
1968 #define els_req64_sp_WORD           word4
1969 #define els_req64_vf_SHIFT          25
1970 #define els_req64_vf_MASK           0x00000001
1971 #define els_req64_vf_WORD           word4
1972         struct wqe_did  wqe_dest;
1973         struct wqe_common wqe_com; /* words 6-11 */
1974         uint32_t word12;
1975 #define els_req64_vfid_SHIFT        1
1976 #define els_req64_vfid_MASK         0x00000FFF
1977 #define els_req64_vfid_WORD         word12
1978 #define els_req64_pri_SHIFT         13
1979 #define els_req64_pri_MASK          0x00000007
1980 #define els_req64_pri_WORD          word12
1981         uint32_t word13;
1982 #define els_req64_hopcnt_SHIFT      24
1983 #define els_req64_hopcnt_MASK       0x000000ff
1984 #define els_req64_hopcnt_WORD       word13
1985         uint32_t reserved[2];
1986 };
1987
1988 struct xmit_els_rsp64_wqe {
1989         struct ulp_bde64 bde;
1990         uint32_t rsvd3;
1991         uint32_t rsvd4;
1992         struct wqe_did  wqe_dest;
1993         struct wqe_common wqe_com; /* words 6-11 */
1994         uint32_t rsvd_12_15[4];
1995 };
1996
1997 struct xmit_bls_rsp64_wqe {
1998         uint32_t payload0;
1999         uint32_t word1;
2000 #define xmit_bls_rsp64_rxid_SHIFT  0
2001 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
2002 #define xmit_bls_rsp64_rxid_WORD   word1
2003 #define xmit_bls_rsp64_oxid_SHIFT  16
2004 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
2005 #define xmit_bls_rsp64_oxid_WORD   word1
2006         uint32_t word2;
2007 #define xmit_bls_rsp64_seqcntlo_SHIFT  0
2008 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
2009 #define xmit_bls_rsp64_seqcntlo_WORD   word2
2010 #define xmit_bls_rsp64_seqcnthi_SHIFT  16
2011 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
2012 #define xmit_bls_rsp64_seqcnthi_WORD   word2
2013         uint32_t rsrvd3;
2014         uint32_t rsrvd4;
2015         struct wqe_did  wqe_dest;
2016         struct wqe_common wqe_com; /* words 6-11 */
2017         uint32_t rsvd_12_15[4];
2018 };
2019 struct wqe_rctl_dfctl {
2020         uint32_t word5;
2021 #define wqe_si_SHIFT 2
2022 #define wqe_si_MASK  0x000000001
2023 #define wqe_si_WORD  word5
2024 #define wqe_la_SHIFT 3
2025 #define wqe_la_MASK  0x000000001
2026 #define wqe_la_WORD  word5
2027 #define wqe_ls_SHIFT 7
2028 #define wqe_ls_MASK  0x000000001
2029 #define wqe_ls_WORD  word5
2030 #define wqe_dfctl_SHIFT 8
2031 #define wqe_dfctl_MASK  0x0000000ff
2032 #define wqe_dfctl_WORD  word5
2033 #define wqe_type_SHIFT 16
2034 #define wqe_type_MASK  0x0000000ff
2035 #define wqe_type_WORD  word5
2036 #define wqe_rctl_SHIFT 24
2037 #define wqe_rctl_MASK  0x0000000ff
2038 #define wqe_rctl_WORD  word5
2039 };
2040
2041 struct xmit_seq64_wqe {
2042         struct ulp_bde64 bde;
2043         uint32_t paylaod_offset;
2044         uint32_t relative_offset;
2045         struct wqe_rctl_dfctl wge_ctl;
2046         struct wqe_common wqe_com; /* words 6-11 */
2047         /* Note: word10 different REVISIT */
2048         uint32_t xmit_len;
2049         uint32_t rsvd_12_15[3];
2050 };
2051 struct xmit_bcast64_wqe {
2052         struct ulp_bde64 bde;
2053         uint32_t paylaod_len;
2054         uint32_t rsvd4;
2055         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2056         struct wqe_common wqe_com;     /* words 6-11 */
2057         uint32_t rsvd_12_15[4];
2058 };
2059
2060 struct gen_req64_wqe {
2061         struct ulp_bde64 bde;
2062         uint32_t command_len;
2063         uint32_t payload_len;
2064         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2065         struct wqe_common wqe_com;     /* words 6-11 */
2066         uint32_t rsvd_12_15[4];
2067 };
2068
2069 struct create_xri_wqe {
2070         uint32_t rsrvd[5];           /* words 0-4 */
2071         struct wqe_did  wqe_dest;  /* word 5 */
2072         struct wqe_common wqe_com; /* words 6-11 */
2073         uint32_t rsvd_12_15[4];         /* word 12-15 */
2074 };
2075
2076 #define T_REQUEST_TAG 3
2077 #define T_XRI_TAG 1
2078
2079 struct abort_cmd_wqe {
2080         uint32_t rsrvd[3];
2081         uint32_t word3;
2082 #define abort_cmd_ia_SHIFT  0
2083 #define abort_cmd_ia_MASK  0x000000001
2084 #define abort_cmd_ia_WORD  word3
2085 #define abort_cmd_criteria_SHIFT  8
2086 #define abort_cmd_criteria_MASK  0x0000000ff
2087 #define abort_cmd_criteria_WORD  word3
2088         uint32_t rsrvd4;
2089         uint32_t rsrvd5;
2090         struct wqe_common wqe_com;     /* words 6-11 */
2091         uint32_t rsvd_12_15[4];         /* word 12-15 */
2092 };
2093
2094 struct fcp_iwrite64_wqe {
2095         struct ulp_bde64 bde;
2096         uint32_t payload_len;
2097         uint32_t total_xfer_len;
2098         uint32_t initial_xfer_len;
2099         struct wqe_common wqe_com;     /* words 6-11 */
2100         uint32_t rsvd_12_15[4];         /* word 12-15 */
2101 };
2102
2103 struct fcp_iread64_wqe {
2104         struct ulp_bde64 bde;
2105         uint32_t payload_len;          /* word 3 */
2106         uint32_t total_xfer_len;       /* word 4 */
2107         uint32_t rsrvd5;               /* word 5 */
2108         struct wqe_common wqe_com;     /* words 6-11 */
2109         uint32_t rsvd_12_15[4];         /* word 12-15 */
2110 };
2111
2112 struct fcp_icmnd64_wqe {
2113         struct ulp_bde64 bde;    /* words 0-2 */
2114         uint32_t rsrvd[3];             /* words 3-5 */
2115         struct wqe_common wqe_com;     /* words 6-11 */
2116         uint32_t rsvd_12_15[4];         /* word 12-15 */
2117 };
2118
2119
2120 union lpfc_wqe {
2121         uint32_t words[16];
2122         struct lpfc_wqe_generic generic;
2123         struct fcp_icmnd64_wqe fcp_icmd;
2124         struct fcp_iread64_wqe fcp_iread;
2125         struct fcp_iwrite64_wqe fcp_iwrite;
2126         struct abort_cmd_wqe abort_cmd;
2127         struct create_xri_wqe create_xri;
2128         struct xmit_bcast64_wqe xmit_bcast64;
2129         struct xmit_seq64_wqe xmit_sequence;
2130         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
2131         struct xmit_els_rsp64_wqe xmit_els_rsp;
2132         struct els_request64_wqe els_req;
2133         struct gen_req64_wqe gen_req;
2134 };
2135
2136 #define FCP_COMMAND 0x0
2137 #define FCP_COMMAND_DATA_OUT 0x1
2138 #define ELS_COMMAND_NON_FIP 0xC
2139 #define ELS_COMMAND_FIP 0xD
2140 #define OTHER_COMMAND 0x8
2141