Pileus Git - ~andy/linux/blob - drivers/scsi/isci/host.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55 #include <linux/circ_buf.h>
  56 #include <linux/device.h>
  57 #include <scsi/sas.h>
  58 #include "host.h"
  59 #include "isci.h"
  60 #include "port.h"
  61 #include "probe_roms.h"
  62 #include "remote_device.h"
  63 #include "request.h"
  64 #include "scu_completion_codes.h"
  65 #include "scu_event_codes.h"
  66 #include "registers.h"
  67 #include "scu_remote_node_context.h"
  68 #include "scu_task_context.h"
  69
  70 #define SCU_CONTEXT_RAM_INIT_STALL_TIME      200
  71
  72 #define smu_max_ports(dcc_value) \
  73         (\
  74                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
  75                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
  76         )
  77
  78 #define smu_max_task_contexts(dcc_value)        \
  79         (\
  80                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
  81                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
  82         )
  83
  84 #define smu_max_rncs(dcc_value) \
  85         (\
  86                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
  87                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
  88         )
  89
  90 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT      100
  91
  92 /**
  93  *
  94  *
  95  * The number of milliseconds to wait while a given phy is consuming power
  96  * before allowing another set of phys to consume power. Ultimately, this will
  97  * be specified by OEM parameter.
  98  */
  99 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
 100
 101 /**
 102  * NORMALIZE_PUT_POINTER() -
 103  *
 104  * This macro will normalize the completion queue put pointer so its value can
 105  * be used as an array inde
 106  */
 107 #define NORMALIZE_PUT_POINTER(x) \
 108         ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
 109
 110
 111 /**
 112  * NORMALIZE_EVENT_POINTER() -
 113  *
 114  * This macro will normalize the completion queue event entry so its value can
 115  * be used as an index.
 116  */
 117 #define NORMALIZE_EVENT_POINTER(x) \
 118         (\
 119                 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
 120                 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
 121         )
 122
 123 /**
 124  * NORMALIZE_GET_POINTER() -
 125  *
 126  * This macro will normalize the completion queue get pointer so its value can
 127  * be used as an index into an array
 128  */
 129 #define NORMALIZE_GET_POINTER(x) \
 130         ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
 131
 132 /**
 133  * NORMALIZE_GET_POINTER_CYCLE_BIT() -
 134  *
 135  * This macro will normalize the completion queue cycle pointer so it matches
 136  * the completion queue cycle bit
 137  */
 138 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
 139         ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
 140
 141 /**
 142  * COMPLETION_QUEUE_CYCLE_BIT() -
 143  *
 144  * This macro will return the cycle bit of the completion queue entry
 145  */
 146 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
 147
 148 /* Init the state machine and call the state entry function (if any) */
 149 void sci_init_sm(struct sci_base_state_machine *sm,
 150                  const struct sci_base_state *state_table, u32 initial_state)
 151 {
 152         sci_state_transition_t handler;
 153
 154         sm->initial_state_id    = initial_state;
 155         sm->previous_state_id   = initial_state;
 156         sm->current_state_id    = initial_state;
 157         sm->state_table         = state_table;
 158
 159         handler = sm->state_table[initial_state].enter_state;
 160         if (handler)
 161                 handler(sm);
 162 }
 163
 164 /* Call the state exit fn, update the current state, call the state entry fn */
 165 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
 166 {
 167         sci_state_transition_t handler;
 168
 169         handler = sm->state_table[sm->current_state_id].exit_state;
 170         if (handler)
 171                 handler(sm);
 172
 173         sm->previous_state_id = sm->current_state_id;
 174         sm->current_state_id = next_state;
 175
 176         handler = sm->state_table[sm->current_state_id].enter_state;
 177         if (handler)
 178                 handler(sm);
 179 }
 180
 181 static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
 182 {
 183         u32 get_value = ihost->completion_queue_get;
 184         u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
 185
 186         if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
 187             COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
 188                 return true;
 189
 190         return false;
 191 }
 192
 193 static bool sci_controller_isr(struct isci_host *ihost)
 194 {
 195         if (sci_controller_completion_queue_has_entries(ihost)) {
 196                 return true;
 197         } else {
 198                 /*
 199                  * we have a spurious interrupt it could be that we have already
 200                  * emptied the completion queue from a previous interrupt */
 201                 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
 202
 203                 /*
 204                  * There is a race in the hardware that could cause us not to be notified
 205                  * of an interrupt completion if we do not take this step.  We will mask
 206                  * then unmask the interrupts so if there is another interrupt pending
 207                  * the clearing of the interrupt source we get the next interrupt message. */
 208                 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
 209                 writel(0, &ihost->smu_registers->interrupt_mask);
 210         }
 211
 212         return false;
 213 }
 214
 215 irqreturn_t isci_msix_isr(int vec, void *data)
 216 {
 217         struct isci_host *ihost = data;
 218
 219         if (sci_controller_isr(ihost))
 220                 tasklet_schedule(&ihost->completion_tasklet);
 221
 222         return IRQ_HANDLED;
 223 }
 224
 225 static bool sci_controller_error_isr(struct isci_host *ihost)
 226 {
 227         u32 interrupt_status;
 228
 229         interrupt_status =
 230                 readl(&ihost->smu_registers->interrupt_status);
 231         interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
 232
 233         if (interrupt_status != 0) {
 234                 /*
 235                  * There is an error interrupt pending so let it through and handle
 236                  * in the callback */
 237                 return true;
 238         }
 239
 240         /*
 241          * There is a race in the hardware that could cause us not to be notified
 242          * of an interrupt completion if we do not take this step.  We will mask
 243          * then unmask the error interrupts so if there was another interrupt
 244          * pending we will be notified.
 245          * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
 246         writel(0xff, &ihost->smu_registers->interrupt_mask);
 247         writel(0, &ihost->smu_registers->interrupt_mask);
 248
 249         return false;
 250 }
 251
 252 static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
 253 {
 254         u32 index = SCU_GET_COMPLETION_INDEX(ent);
 255         struct isci_request *ireq = ihost->reqs[index];
 256
 257         /* Make sure that we really want to process this IO request */
 258         if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
 259             ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
 260             ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
 261                 /* Yep this is a valid io request pass it along to the
 262                  * io request handler
 263                  */
 264                 sci_io_request_tc_completion(ireq, ent);
 265 }
 266
 267 static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
 268 {
 269         u32 index;
 270         struct isci_request *ireq;
 271         struct isci_remote_device *idev;
 272
 273         index = SCU_GET_COMPLETION_INDEX(ent);
 274
 275         switch (scu_get_command_request_type(ent)) {
 276         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
 277         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
 278                 ireq = ihost->reqs[index];
 279                 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
 280                          __func__, ent, ireq);
 281                 /* @todo For a post TC operation we need to fail the IO
 282                  * request
 283                  */
 284                 break;
 285         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
 286         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
 287         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
 288                 idev = ihost->device_table[index];
 289                 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
 290                          __func__, ent, idev);
 291                 /* @todo For a port RNC operation we need to fail the
 292                  * device
 293                  */
 294                 break;
 295         default:
 296                 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
 297                          __func__, ent);
 298                 break;
 299         }
 300 }
 301
 302 static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
 303 {
 304         u32 index;
 305         u32 frame_index;
 306
 307         struct scu_unsolicited_frame_header *frame_header;
 308         struct isci_phy *iphy;
 309         struct isci_remote_device *idev;
 310
 311         enum sci_status result = SCI_FAILURE;
 312
 313         frame_index = SCU_GET_FRAME_INDEX(ent);
 314
 315         frame_header = ihost->uf_control.buffers.array[frame_index].header;
 316         ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
 317
 318         if (SCU_GET_FRAME_ERROR(ent)) {
 319                 /*
 320                  * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
 321                  * /       this cause a problem? We expect the phy initialization will
 322                  * /       fail if there is an error in the frame. */
 323                 sci_controller_release_frame(ihost, frame_index);
 324                 return;
 325         }
 326
 327         if (frame_header->is_address_frame) {
 328                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 329                 iphy = &ihost->phys[index];
 330                 result = sci_phy_frame_handler(iphy, frame_index);
 331         } else {
 332
 333                 index = SCU_GET_COMPLETION_INDEX(ent);
 334
 335                 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
 336                         /*
 337                          * This is a signature fis or a frame from a direct attached SATA
 338                          * device that has not yet been created.  In either case forwared
 339                          * the frame to the PE and let it take care of the frame data. */
 340                         index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 341                         iphy = &ihost->phys[index];
 342                         result = sci_phy_frame_handler(iphy, frame_index);
 343                 } else {
 344                         if (index < ihost->remote_node_entries)
 345                                 idev = ihost->device_table[index];
 346                         else
 347                                 idev = NULL;
 348
 349                         if (idev != NULL)
 350                                 result = sci_remote_device_frame_handler(idev, frame_index);
 351                         else
 352                                 sci_controller_release_frame(ihost, frame_index);
 353                 }
 354         }
 355
 356         if (result != SCI_SUCCESS) {
 357                 /*
 358                  * / @todo Is there any reason to report some additional error message
 359                  * /       when we get this failure notifiction? */
 360         }
 361 }
 362
 363 static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
 364 {
 365         struct isci_remote_device *idev;
 366         struct isci_request *ireq;
 367         struct isci_phy *iphy;
 368         u32 index;
 369
 370         index = SCU_GET_COMPLETION_INDEX(ent);
 371
 372         switch (scu_get_event_type(ent)) {
 373         case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
 374                 /* / @todo The driver did something wrong and we need to fix the condtion. */
 375                 dev_err(&ihost->pdev->dev,
 376                         "%s: SCIC Controller 0x%p received SMU command error "
 377                         "0x%x\n",
 378                         __func__,
 379                         ihost,
 380                         ent);
 381                 break;
 382
 383         case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
 384         case SCU_EVENT_TYPE_SMU_ERROR:
 385         case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
 386                 /*
 387                  * / @todo This is a hardware failure and its likely that we want to
 388                  * /       reset the controller. */
 389                 dev_err(&ihost->pdev->dev,
 390                         "%s: SCIC Controller 0x%p received fatal controller "
 391                         "event  0x%x\n",
 392                         __func__,
 393                         ihost,
 394                         ent);
 395                 break;
 396
 397         case SCU_EVENT_TYPE_TRANSPORT_ERROR:
 398                 ireq = ihost->reqs[index];
 399                 sci_io_request_event_handler(ireq, ent);
 400                 break;
 401
 402         case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
 403                 switch (scu_get_event_specifier(ent)) {
 404                 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
 405                 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
 406                         ireq = ihost->reqs[index];
 407                         if (ireq != NULL)
 408                                 sci_io_request_event_handler(ireq, ent);
 409                         else
 410                                 dev_warn(&ihost->pdev->dev,
 411                                          "%s: SCIC Controller 0x%p received "
 412                                          "event 0x%x for io request object "
 413                                          "that doesnt exist.\n",
 414                                          __func__,
 415                                          ihost,
 416                                          ent);
 417
 418                         break;
 419
 420                 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
 421                         idev = ihost->device_table[index];
 422                         if (idev != NULL)
 423                                 sci_remote_device_event_handler(idev, ent);
 424                         else
 425                                 dev_warn(&ihost->pdev->dev,
 426                                          "%s: SCIC Controller 0x%p received "
 427                                          "event 0x%x for remote device object "
 428                                          "that doesnt exist.\n",
 429                                          __func__,
 430                                          ihost,
 431                                          ent);
 432
 433                         break;
 434                 }
 435                 break;
 436
 437         case SCU_EVENT_TYPE_BROADCAST_CHANGE:
 438         /*
 439          * direct the broadcast change event to the phy first and then let
 440          * the phy redirect the broadcast change to the port object */
 441         case SCU_EVENT_TYPE_ERR_CNT_EVENT:
 442         /*
 443          * direct error counter event to the phy object since that is where
 444          * we get the event notification.  This is a type 4 event. */
 445         case SCU_EVENT_TYPE_OSSP_EVENT:
 446                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 447                 iphy = &ihost->phys[index];
 448                 sci_phy_event_handler(iphy, ent);
 449                 break;
 450
 451         case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
 452         case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
 453         case SCU_EVENT_TYPE_RNC_OPS_MISC:
 454                 if (index < ihost->remote_node_entries) {
 455                         idev = ihost->device_table[index];
 456
 457                         if (idev != NULL)
 458                                 sci_remote_device_event_handler(idev, ent);
 459                 } else
 460                         dev_err(&ihost->pdev->dev,
 461                                 "%s: SCIC Controller 0x%p received event 0x%x "
 462                                 "for remote device object 0x%0x that doesnt "
 463                                 "exist.\n",
 464                                 __func__,
 465                                 ihost,
 466                                 ent,
 467                                 index);
 468
 469                 break;
 470
 471         default:
 472                 dev_warn(&ihost->pdev->dev,
 473                          "%s: SCIC Controller received unknown event code %x\n",
 474                          __func__,
 475                          ent);
 476                 break;
 477         }
 478 }
 479
 480 static void sci_controller_process_completions(struct isci_host *ihost)
 481 {
 482         u32 completion_count = 0;
 483         u32 ent;
 484         u32 get_index;
 485         u32 get_cycle;
 486         u32 event_get;
 487         u32 event_cycle;
 488
 489         dev_dbg(&ihost->pdev->dev,
 490                 "%s: completion queue begining get:0x%08x\n",
 491                 __func__,
 492                 ihost->completion_queue_get);
 493
 494         /* Get the component parts of the completion queue */
 495         get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
 496         get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
 497
 498         event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
 499         event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
 500
 501         while (
 502                 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
 503                 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
 504                 ) {
 505                 completion_count++;
 506
 507                 ent = ihost->completion_queue[get_index];
 508
 509                 /* increment the get pointer and check for rollover to toggle the cycle bit */
 510                 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
 511                              (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
 512                 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
 513
 514                 dev_dbg(&ihost->pdev->dev,
 515                         "%s: completion queue entry:0x%08x\n",
 516                         __func__,
 517                         ent);
 518
 519                 switch (SCU_GET_COMPLETION_TYPE(ent)) {
 520                 case SCU_COMPLETION_TYPE_TASK:
 521                         sci_controller_task_completion(ihost, ent);
 522                         break;
 523
 524                 case SCU_COMPLETION_TYPE_SDMA:
 525                         sci_controller_sdma_completion(ihost, ent);
 526                         break;
 527
 528                 case SCU_COMPLETION_TYPE_UFI:
 529                         sci_controller_unsolicited_frame(ihost, ent);
 530                         break;
 531
 532                 case SCU_COMPLETION_TYPE_EVENT:
 533                         sci_controller_event_completion(ihost, ent);
 534                         break;
 535
 536                 case SCU_COMPLETION_TYPE_NOTIFY: {
 537                         event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
 538                                        (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
 539                         event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
 540
 541                         sci_controller_event_completion(ihost, ent);
 542                         break;
 543                 }
 544                 default:
 545                         dev_warn(&ihost->pdev->dev,
 546                                  "%s: SCIC Controller received unknown "
 547                                  "completion type %x\n",
 548                                  __func__,
 549                                  ent);
 550                         break;
 551                 }
 552         }
 553
 554         /* Update the get register if we completed one or more entries */
 555         if (completion_count > 0) {
 556                 ihost->completion_queue_get =
 557                         SMU_CQGR_GEN_BIT(ENABLE) |
 558                         SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
 559                         event_cycle |
 560                         SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
 561                         get_cycle |
 562                         SMU_CQGR_GEN_VAL(POINTER, get_index);
 563
 564                 writel(ihost->completion_queue_get,
 565                        &ihost->smu_registers->completion_queue_get);
 566
 567         }
 568
 569         dev_dbg(&ihost->pdev->dev,
 570                 "%s: completion queue ending get:0x%08x\n",
 571                 __func__,
 572                 ihost->completion_queue_get);
 573
 574 }
 575
 576 static void sci_controller_error_handler(struct isci_host *ihost)
 577 {
 578         u32 interrupt_status;
 579
 580         interrupt_status =
 581                 readl(&ihost->smu_registers->interrupt_status);
 582
 583         if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
 584             sci_controller_completion_queue_has_entries(ihost)) {
 585
 586                 sci_controller_process_completions(ihost);
 587                 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
 588         } else {
 589                 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
 590                         interrupt_status);
 591
 592                 sci_change_state(&ihost->sm, SCIC_FAILED);
 593
 594                 return;
 595         }
 596
 597         /* If we dont process any completions I am not sure that we want to do this.
 598          * We are in the middle of a hardware fault and should probably be reset.
 599          */
 600         writel(0, &ihost->smu_registers->interrupt_mask);
 601 }
 602
 603 irqreturn_t isci_intx_isr(int vec, void *data)
 604 {
 605         irqreturn_t ret = IRQ_NONE;
 606         struct isci_host *ihost = data;
 607
 608         if (sci_controller_isr(ihost)) {
 609                 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
 610                 tasklet_schedule(&ihost->completion_tasklet);
 611                 ret = IRQ_HANDLED;
 612         } else if (sci_controller_error_isr(ihost)) {
 613                 spin_lock(&ihost->scic_lock);
 614                 sci_controller_error_handler(ihost);
 615                 spin_unlock(&ihost->scic_lock);
 616                 ret = IRQ_HANDLED;
 617         }
 618
 619         return ret;
 620 }
 621
 622 irqreturn_t isci_error_isr(int vec, void *data)
 623 {
 624         struct isci_host *ihost = data;
 625
 626         if (sci_controller_error_isr(ihost))
 627                 sci_controller_error_handler(ihost);
 628
 629         return IRQ_HANDLED;
 630 }
 631
 632 /**
 633  * isci_host_start_complete() - This function is called by the core library,
 634  *    through the ISCI Module, to indicate controller start status.
 635  * @isci_host: This parameter specifies the ISCI host object
 636  * @completion_status: This parameter specifies the completion status from the
 637  *    core library.
 638  *
 639  */
 640 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
 641 {
 642         if (completion_status != SCI_SUCCESS)
 643                 dev_info(&ihost->pdev->dev,
 644                         "controller start timed out, continuing...\n");
 645         clear_bit(IHOST_START_PENDING, &ihost->flags);
 646         wake_up(&ihost->eventq);
 647 }
 648
 649 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
 650 {
 651         struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost);
 652         struct isci_host *ihost = ha->lldd_ha;
 653
 654         if (test_bit(IHOST_START_PENDING, &ihost->flags))
 655                 return 0;
 656
 657         sas_drain_work(ha);
 658
 659         return 1;
 660 }
 661
 662 /**
 663  * sci_controller_get_suggested_start_timeout() - This method returns the
 664  *    suggested sci_controller_start() timeout amount.  The user is free to
 665  *    use any timeout value, but this method provides the suggested minimum
 666  *    start timeout value.  The returned value is based upon empirical
 667  *    information determined as a result of interoperability testing.
 668  * @controller: the handle to the controller object for which to return the
 669  *    suggested start timeout.
 670  *
 671  * This method returns the number of milliseconds for the suggested start
 672  * operation timeout.
 673  */
 674 static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
 675 {
 676         /* Validate the user supplied parameters. */
 677         if (!ihost)
 678                 return 0;
 679
 680         /*
 681          * The suggested minimum timeout value for a controller start operation:
 682          *
 683          *     Signature FIS Timeout
 684          *   + Phy Start Timeout
 685          *   + Number of Phy Spin Up Intervals
 686          *   ---------------------------------
 687          *   Number of milliseconds for the controller start operation.
 688          *
 689          * NOTE: The number of phy spin up intervals will be equivalent
 690          *       to the number of phys divided by the number phys allowed
 691          *       per interval - 1 (once OEM parameters are supported).
 692          *       Currently we assume only 1 phy per interval. */
 693
 694         return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
 695                 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
 696                 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
 697 }
 698
 699 static void sci_controller_enable_interrupts(struct isci_host *ihost)
 700 {
 701         BUG_ON(ihost->smu_registers == NULL);
 702         writel(0, &ihost->smu_registers->interrupt_mask);
 703 }
 704
 705 void sci_controller_disable_interrupts(struct isci_host *ihost)
 706 {
 707         BUG_ON(ihost->smu_registers == NULL);
 708         writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
 709 }
 710
 711 static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
 712 {
 713         u32 port_task_scheduler_value;
 714
 715         port_task_scheduler_value =
 716                 readl(&ihost->scu_registers->peg0.ptsg.control);
 717         port_task_scheduler_value |=
 718                 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
 719                  SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
 720         writel(port_task_scheduler_value,
 721                &ihost->scu_registers->peg0.ptsg.control);
 722 }
 723
 724 static void sci_controller_assign_task_entries(struct isci_host *ihost)
 725 {
 726         u32 task_assignment;
 727
 728         /*
 729          * Assign all the TCs to function 0
 730          * TODO: Do we actually need to read this register to write it back?
 731          */
 732
 733         task_assignment =
 734                 readl(&ihost->smu_registers->task_context_assignment[0]);
 735
 736         task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
 737                 (SMU_TCA_GEN_VAL(ENDING,  ihost->task_context_entries - 1)) |
 738                 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
 739
 740         writel(task_assignment,
 741                 &ihost->smu_registers->task_context_assignment[0]);
 742
 743 }
 744
 745 static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
 746 {
 747         u32 index;
 748         u32 completion_queue_control_value;
 749         u32 completion_queue_get_value;
 750         u32 completion_queue_put_value;
 751
 752         ihost->completion_queue_get = 0;
 753
 754         completion_queue_control_value =
 755                 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
 756                  SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
 757
 758         writel(completion_queue_control_value,
 759                &ihost->smu_registers->completion_queue_control);
 760
 761
 762         /* Set the completion queue get pointer and enable the queue */
 763         completion_queue_get_value = (
 764                 (SMU_CQGR_GEN_VAL(POINTER, 0))
 765                 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
 766                 | (SMU_CQGR_GEN_BIT(ENABLE))
 767                 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
 768                 );
 769
 770         writel(completion_queue_get_value,
 771                &ihost->smu_registers->completion_queue_get);
 772
 773         /* Set the completion queue put pointer */
 774         completion_queue_put_value = (
 775                 (SMU_CQPR_GEN_VAL(POINTER, 0))
 776                 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
 777                 );
 778
 779         writel(completion_queue_put_value,
 780                &ihost->smu_registers->completion_queue_put);
 781
 782         /* Initialize the cycle bit of the completion queue entries */
 783         for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
 784                 /*
 785                  * If get.cycle_bit != completion_queue.cycle_bit
 786                  * its not a valid completion queue entry
 787                  * so at system start all entries are invalid */
 788                 ihost->completion_queue[index] = 0x80000000;
 789         }
 790 }
 791
 792 static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
 793 {
 794         u32 frame_queue_control_value;
 795         u32 frame_queue_get_value;
 796         u32 frame_queue_put_value;
 797
 798         /* Write the queue size */
 799         frame_queue_control_value =
 800                 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
 801
 802         writel(frame_queue_control_value,
 803                &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
 804
 805         /* Setup the get pointer for the unsolicited frame queue */
 806         frame_queue_get_value = (
 807                 SCU_UFQGP_GEN_VAL(POINTER, 0)
 808                 |  SCU_UFQGP_GEN_BIT(ENABLE_BIT)
 809                 );
 810
 811         writel(frame_queue_get_value,
 812                &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
 813         /* Setup the put pointer for the unsolicited frame queue */
 814         frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
 815         writel(frame_queue_put_value,
 816                &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
 817 }
 818
 819 static void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
 820 {
 821         if (ihost->sm.current_state_id == SCIC_STARTING) {
 822                 /*
 823                  * We move into the ready state, because some of the phys/ports
 824                  * may be up and operational.
 825                  */
 826                 sci_change_state(&ihost->sm, SCIC_READY);
 827
 828                 isci_host_start_complete(ihost, status);
 829         }
 830 }
 831
 832 static bool is_phy_starting(struct isci_phy *iphy)
 833 {
 834         enum sci_phy_states state;
 835
 836         state = iphy->sm.current_state_id;
 837         switch (state) {
 838         case SCI_PHY_STARTING:
 839         case SCI_PHY_SUB_INITIAL:
 840         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 841         case SCI_PHY_SUB_AWAIT_IAF_UF:
 842         case SCI_PHY_SUB_AWAIT_SAS_POWER:
 843         case SCI_PHY_SUB_AWAIT_SATA_POWER:
 844         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 845         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 846         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 847         case SCI_PHY_SUB_FINAL:
 848                 return true;
 849         default:
 850                 return false;
 851         }
 852 }
 853
 854 /**
 855  * sci_controller_start_next_phy - start phy
 856  * @scic: controller
 857  *
 858  * If all the phys have been started, then attempt to transition the
 859  * controller to the READY state and inform the user
 860  * (sci_cb_controller_start_complete()).
 861  */
 862 static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
 863 {
 864         struct sci_oem_params *oem = &ihost->oem_parameters;
 865         struct isci_phy *iphy;
 866         enum sci_status status;
 867
 868         status = SCI_SUCCESS;
 869
 870         if (ihost->phy_startup_timer_pending)
 871                 return status;
 872
 873         if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
 874                 bool is_controller_start_complete = true;
 875                 u32 state;
 876                 u8 index;
 877
 878                 for (index = 0; index < SCI_MAX_PHYS; index++) {
 879                         iphy = &ihost->phys[index];
 880                         state = iphy->sm.current_state_id;
 881
 882                         if (!phy_get_non_dummy_port(iphy))
 883                                 continue;
 884
 885                         /* The controller start operation is complete iff:
 886                          * - all links have been given an opportunity to start
 887                          * - have no indication of a connected device
 888                          * - have an indication of a connected device and it has
 889                          *   finished the link training process.
 890                          */
 891                         if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
 892                             (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
 893                             (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
 894                             (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask)) {
 895                                 is_controller_start_complete = false;
 896                                 break;
 897                         }
 898                 }
 899
 900                 /*
 901                  * The controller has successfully finished the start process.
 902                  * Inform the SCI Core user and transition to the READY state. */
 903                 if (is_controller_start_complete == true) {
 904                         sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
 905                         sci_del_timer(&ihost->phy_timer);
 906                         ihost->phy_startup_timer_pending = false;
 907                 }
 908         } else {
 909                 iphy = &ihost->phys[ihost->next_phy_to_start];
 910
 911                 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
 912                         if (phy_get_non_dummy_port(iphy) == NULL) {
 913                                 ihost->next_phy_to_start++;
 914
 915                                 /* Caution recursion ahead be forwarned
 916                                  *
 917                                  * The PHY was never added to a PORT in MPC mode
 918                                  * so start the next phy in sequence This phy
 919                                  * will never go link up and will not draw power
 920                                  * the OEM parameters either configured the phy
 921                                  * incorrectly for the PORT or it was never
 922                                  * assigned to a PORT
 923                                  */
 924                                 return sci_controller_start_next_phy(ihost);
 925                         }
 926                 }
 927
 928                 status = sci_phy_start(iphy);
 929
 930                 if (status == SCI_SUCCESS) {
 931                         sci_mod_timer(&ihost->phy_timer,
 932                                       SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
 933                         ihost->phy_startup_timer_pending = true;
 934                 } else {
 935                         dev_warn(&ihost->pdev->dev,
 936                                  "%s: Controller stop operation failed "
 937                                  "to stop phy %d because of status "
 938                                  "%d.\n",
 939                                  __func__,
 940                                  ihost->phys[ihost->next_phy_to_start].phy_index,
 941                                  status);
 942                 }
 943
 944                 ihost->next_phy_to_start++;
 945         }
 946
 947         return status;
 948 }
 949
 950 static void phy_startup_timeout(unsigned long data)
 951 {
 952         struct sci_timer *tmr = (struct sci_timer *)data;
 953         struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
 954         unsigned long flags;
 955         enum sci_status status;
 956
 957         spin_lock_irqsave(&ihost->scic_lock, flags);
 958
 959         if (tmr->cancel)
 960                 goto done;
 961
 962         ihost->phy_startup_timer_pending = false;
 963
 964         do {
 965                 status = sci_controller_start_next_phy(ihost);
 966         } while (status != SCI_SUCCESS);
 967
 968 done:
 969         spin_unlock_irqrestore(&ihost->scic_lock, flags);
 970 }
 971
 972 static u16 isci_tci_active(struct isci_host *ihost)
 973 {
 974         return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
 975 }
 976
 977 static enum sci_status sci_controller_start(struct isci_host *ihost,
 978                                              u32 timeout)
 979 {
 980         enum sci_status result;
 981         u16 index;
 982
 983         if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
 984                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
 985                          __func__, ihost->sm.current_state_id);
 986                 return SCI_FAILURE_INVALID_STATE;
 987         }
 988
 989         /* Build the TCi free pool */
 990         BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
 991         ihost->tci_head = 0;
 992         ihost->tci_tail = 0;
 993         for (index = 0; index < ihost->task_context_entries; index++)
 994                 isci_tci_free(ihost, index);
 995
 996         /* Build the RNi free pool */
 997         sci_remote_node_table_initialize(&ihost->available_remote_nodes,
 998                                          ihost->remote_node_entries);
 999
1000         /*
1001          * Before anything else lets make sure we will not be
1002          * interrupted by the hardware.
1003          */
1004         sci_controller_disable_interrupts(ihost);
1005
1006         /* Enable the port task scheduler */
1007         sci_controller_enable_port_task_scheduler(ihost);
1008
1009         /* Assign all the task entries to ihost physical function */
1010         sci_controller_assign_task_entries(ihost);
1011
1012         /* Now initialize the completion queue */
1013         sci_controller_initialize_completion_queue(ihost);
1014
1015         /* Initialize the unsolicited frame queue for use */
1016         sci_controller_initialize_unsolicited_frame_queue(ihost);
1017
1018         /* Start all of the ports on this controller */
1019         for (index = 0; index < ihost->logical_port_entries; index++) {
1020                 struct isci_port *iport = &ihost->ports[index];
1021
1022                 result = sci_port_start(iport);
1023                 if (result)
1024                         return result;
1025         }
1026
1027         sci_controller_start_next_phy(ihost);
1028
1029         sci_mod_timer(&ihost->timer, timeout);
1030
1031         sci_change_state(&ihost->sm, SCIC_STARTING);
1032
1033         return SCI_SUCCESS;
1034 }
1035
1036 void isci_host_scan_start(struct Scsi_Host *shost)
1037 {
1038         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1039         unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
1040
1041         set_bit(IHOST_START_PENDING, &ihost->flags);
1042
1043         spin_lock_irq(&ihost->scic_lock);
1044         sci_controller_start(ihost, tmo);
1045         sci_controller_enable_interrupts(ihost);
1046         spin_unlock_irq(&ihost->scic_lock);
1047 }
1048
1049 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1050 {
1051         sci_controller_disable_interrupts(ihost);
1052         clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1053         wake_up(&ihost->eventq);
1054 }
1055
1056 static void sci_controller_completion_handler(struct isci_host *ihost)
1057 {
1058         /* Empty out the completion queue */
1059         if (sci_controller_completion_queue_has_entries(ihost))
1060                 sci_controller_process_completions(ihost);
1061
1062         /* Clear the interrupt and enable all interrupts again */
1063         writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
1064         /* Could we write the value of SMU_ISR_COMPLETION? */
1065         writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
1066         writel(0, &ihost->smu_registers->interrupt_mask);
1067 }
1068
1069 /**
1070  * isci_host_completion_routine() - This function is the delayed service
1071  *    routine that calls the sci core library's completion handler. It's
1072  *    scheduled as a tasklet from the interrupt service routine when interrupts
1073  *    in use, or set as the timeout function in polled mode.
1074  * @data: This parameter specifies the ISCI host object
1075  *
1076  */
1077 void isci_host_completion_routine(unsigned long data)
1078 {
1079         struct isci_host *ihost = (struct isci_host *)data;
1080         struct list_head    completed_request_list;
1081         struct list_head    errored_request_list;
1082         struct list_head    *current_position;
1083         struct list_head    *next_position;
1084         struct isci_request *request;
1085         struct isci_request *next_request;
1086         struct sas_task     *task;
1087         u16 active;
1088
1089         INIT_LIST_HEAD(&completed_request_list);
1090         INIT_LIST_HEAD(&errored_request_list);
1091
1092         spin_lock_irq(&ihost->scic_lock);
1093
1094         sci_controller_completion_handler(ihost);
1095
1096         /* Take the lists of completed I/Os from the host. */
1097
1098         list_splice_init(&ihost->requests_to_complete,
1099                          &completed_request_list);
1100
1101         /* Take the list of errored I/Os from the host. */
1102         list_splice_init(&ihost->requests_to_errorback,
1103                          &errored_request_list);
1104
1105         spin_unlock_irq(&ihost->scic_lock);
1106
1107         /* Process any completions in the lists. */
1108         list_for_each_safe(current_position, next_position,
1109                            &completed_request_list) {
1110
1111                 request = list_entry(current_position, struct isci_request,
1112                                      completed_node);
1113                 task = isci_request_access_task(request);
1114
1115                 /* Normal notification (task_done) */
1116                 dev_dbg(&ihost->pdev->dev,
1117                         "%s: Normal - request/task = %p/%p\n",
1118                         __func__,
1119                         request,
1120                         task);
1121
1122                 /* Return the task to libsas */
1123                 if (task != NULL) {
1124
1125                         task->lldd_task = NULL;
1126                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1127
1128                                 /* If the task is already in the abort path,
1129                                 * the task_done callback cannot be called.
1130                                 */
1131                                 task->task_done(task);
1132                         }
1133                 }
1134
1135                 spin_lock_irq(&ihost->scic_lock);
1136                 isci_free_tag(ihost, request->io_tag);
1137                 spin_unlock_irq(&ihost->scic_lock);
1138         }
1139         list_for_each_entry_safe(request, next_request, &errored_request_list,
1140                                  completed_node) {
1141
1142                 task = isci_request_access_task(request);
1143
1144                 /* Use sas_task_abort */
1145                 dev_warn(&ihost->pdev->dev,
1146                          "%s: Error - request/task = %p/%p\n",
1147                          __func__,
1148                          request,
1149                          task);
1150
1151                 if (task != NULL) {
1152
1153                         /* Put the task into the abort path if it's not there
1154                          * already.
1155                          */
1156                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1157                                 sas_task_abort(task);
1158
1159                 } else {
1160                         /* This is a case where the request has completed with a
1161                          * status such that it needed further target servicing,
1162                          * but the sas_task reference has already been removed
1163                          * from the request.  Since it was errored, it was not
1164                          * being aborted, so there is nothing to do except free
1165                          * it.
1166                          */
1167
1168                         spin_lock_irq(&ihost->scic_lock);
1169                         /* Remove the request from the remote device's list
1170                         * of pending requests.
1171                         */
1172                         list_del_init(&request->dev_node);
1173                         isci_free_tag(ihost, request->io_tag);
1174                         spin_unlock_irq(&ihost->scic_lock);
1175                 }
1176         }
1177
1178         /* the coalesence timeout doubles at each encoding step, so
1179          * update it based on the ilog2 value of the outstanding requests
1180          */
1181         active = isci_tci_active(ihost);
1182         writel(SMU_ICC_GEN_VAL(NUMBER, active) |
1183                SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
1184                &ihost->smu_registers->interrupt_coalesce_control);
1185 }
1186
1187 /**
1188  * sci_controller_stop() - This method will stop an individual controller
1189  *    object.This method will invoke the associated user callback upon
1190  *    completion.  The completion callback is called when the following
1191  *    conditions are met: -# the method return status is SCI_SUCCESS. -# the
1192  *    controller has been quiesced. This method will ensure that all IO
1193  *    requests are quiesced, phys are stopped, and all additional operation by
1194  *    the hardware is halted.
1195  * @controller: the handle to the controller object to stop.
1196  * @timeout: This parameter specifies the number of milliseconds in which the
1197  *    stop operation should complete.
1198  *
1199  * The controller must be in the STARTED or STOPPED state. Indicate if the
1200  * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1201  * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1202  * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1203  * controller is not either in the STARTED or STOPPED states.
1204  */
1205 static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
1206 {
1207         if (ihost->sm.current_state_id != SCIC_READY) {
1208                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
1209                          __func__, ihost->sm.current_state_id);
1210                 return SCI_FAILURE_INVALID_STATE;
1211         }
1212
1213         sci_mod_timer(&ihost->timer, timeout);
1214         sci_change_state(&ihost->sm, SCIC_STOPPING);
1215         return SCI_SUCCESS;
1216 }
1217
1218 /**
1219  * sci_controller_reset() - This method will reset the supplied core
1220  *    controller regardless of the state of said controller.  This operation is
1221  *    considered destructive.  In other words, all current operations are wiped
1222  *    out.  No IO completions for outstanding devices occur.  Outstanding IO
1223  *    requests are not aborted or completed at the actual remote device.
1224  * @controller: the handle to the controller object to reset.
1225  *
1226  * Indicate if the controller reset method succeeded or failed in some way.
1227  * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1228  * the controller reset operation is unable to complete.
1229  */
1230 static enum sci_status sci_controller_reset(struct isci_host *ihost)
1231 {
1232         switch (ihost->sm.current_state_id) {
1233         case SCIC_RESET:
1234         case SCIC_READY:
1235         case SCIC_STOPPED:
1236         case SCIC_FAILED:
1237                 /*
1238                  * The reset operation is not a graceful cleanup, just
1239                  * perform the state transition.
1240                  */
1241                 sci_change_state(&ihost->sm, SCIC_RESETTING);
1242                 return SCI_SUCCESS;
1243         default:
1244                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
1245                          __func__, ihost->sm.current_state_id);
1246                 return SCI_FAILURE_INVALID_STATE;
1247         }
1248 }
1249
1250 void isci_host_deinit(struct isci_host *ihost)
1251 {
1252         int i;
1253
1254         /* disable output data selects */
1255         for (i = 0; i < isci_gpio_count(ihost); i++)
1256                 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
1257
1258         for (i = 0; i < SCI_MAX_PORTS; i++) {
1259                 struct isci_port *iport = &ihost->ports[i];
1260                 struct isci_remote_device *idev, *d;
1261
1262                 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
1263                         if (test_bit(IDEV_ALLOCATED, &idev->flags))
1264                                 isci_remote_device_stop(ihost, idev);
1265                 }
1266         }
1267
1268         set_bit(IHOST_STOP_PENDING, &ihost->flags);
1269
1270         spin_lock_irq(&ihost->scic_lock);
1271         sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
1272         spin_unlock_irq(&ihost->scic_lock);
1273
1274         wait_for_stop(ihost);
1275
1276         /* disable sgpio: where the above wait should give time for the
1277          * enclosure to sample the gpios going inactive
1278          */
1279         writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
1280
1281         sci_controller_reset(ihost);
1282
1283         /* Cancel any/all outstanding port timers */
1284         for (i = 0; i < ihost->logical_port_entries; i++) {
1285                 struct isci_port *iport = &ihost->ports[i];
1286                 del_timer_sync(&iport->timer.timer);
1287         }
1288
1289         /* Cancel any/all outstanding phy timers */
1290         for (i = 0; i < SCI_MAX_PHYS; i++) {
1291                 struct isci_phy *iphy = &ihost->phys[i];
1292                 del_timer_sync(&iphy->sata_timer.timer);
1293         }
1294
1295         del_timer_sync(&ihost->port_agent.timer.timer);
1296
1297         del_timer_sync(&ihost->power_control.timer.timer);
1298
1299         del_timer_sync(&ihost->timer.timer);
1300
1301         del_timer_sync(&ihost->phy_timer.timer);
1302 }
1303
1304 static void __iomem *scu_base(struct isci_host *isci_host)
1305 {
1306         struct pci_dev *pdev = isci_host->pdev;
1307         int id = isci_host->id;
1308
1309         return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1310 }
1311
1312 static void __iomem *smu_base(struct isci_host *isci_host)
1313 {
1314         struct pci_dev *pdev = isci_host->pdev;
1315         int id = isci_host->id;
1316
1317         return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1318 }
1319
1320 static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
1321 {
1322         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1323
1324         sci_change_state(&ihost->sm, SCIC_RESET);
1325 }
1326
1327 static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
1328 {
1329         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1330
1331         sci_del_timer(&ihost->timer);
1332 }
1333
1334 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1335 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1336 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US                    2700000
1337 #define INTERRUPT_COALESCE_NUMBER_MAX                        256
1338 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN                7
1339 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX                28
1340
1341 /**
1342  * sci_controller_set_interrupt_coalescence() - This method allows the user to
1343  *    configure the interrupt coalescence.
1344  * @controller: This parameter represents the handle to the controller object
1345  *    for which its interrupt coalesce register is overridden.
1346  * @coalesce_number: Used to control the number of entries in the Completion
1347  *    Queue before an interrupt is generated. If the number of entries exceed
1348  *    this number, an interrupt will be generated. The valid range of the input
1349  *    is [0, 256]. A setting of 0 results in coalescing being disabled.
1350  * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1351  *    input is [0, 2700000] . A setting of 0 is allowed and results in no
1352  *    interrupt coalescing timeout.
1353  *
1354  * Indicate if the user successfully set the interrupt coalesce parameters.
1355  * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1356  * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1357  */
1358 static enum sci_status
1359 sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
1360                                          u32 coalesce_number,
1361                                          u32 coalesce_timeout)
1362 {
1363         u8 timeout_encode = 0;
1364         u32 min = 0;
1365         u32 max = 0;
1366
1367         /* Check if the input parameters fall in the range. */
1368         if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1369                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1370
1371         /*
1372          *  Defined encoding for interrupt coalescing timeout:
1373          *              Value   Min      Max     Units
1374          *              -----   ---      ---     -----
1375          *              0       -        -       Disabled
1376          *              1       13.3     20.0    ns
1377          *              2       26.7     40.0
1378          *              3       53.3     80.0
1379          *              4       106.7    160.0
1380          *              5       213.3    320.0
1381          *              6       426.7    640.0
1382          *              7       853.3    1280.0
1383          *              8       1.7      2.6     us
1384          *              9       3.4      5.1
1385          *              10      6.8      10.2
1386          *              11      13.7     20.5
1387          *              12      27.3     41.0
1388          *              13      54.6     81.9
1389          *              14      109.2    163.8
1390          *              15      218.5    327.7
1391          *              16      436.9    655.4
1392          *              17      873.8    1310.7
1393          *              18      1.7      2.6     ms
1394          *              19      3.5      5.2
1395          *              20      7.0      10.5
1396          *              21      14.0     21.0
1397          *              22      28.0     41.9
1398          *              23      55.9     83.9
1399          *              24      111.8    167.8
1400          *              25      223.7    335.5
1401          *              26      447.4    671.1
1402          *              27      894.8    1342.2
1403          *              28      1.8      2.7     s
1404          *              Others Undefined */
1405
1406         /*
1407          * Use the table above to decide the encode of interrupt coalescing timeout
1408          * value for register writing. */
1409         if (coalesce_timeout == 0)
1410                 timeout_encode = 0;
1411         else{
1412                 /* make the timeout value in unit of (10 ns). */
1413                 coalesce_timeout = coalesce_timeout * 100;
1414                 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1415                 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1416
1417                 /* get the encode of timeout for register writing. */
1418                 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1419                       timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1420                       timeout_encode++) {
1421                         if (min <= coalesce_timeout &&  max > coalesce_timeout)
1422                                 break;
1423                         else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1424                                  && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1425                                 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1426                                         break;
1427                                 else{
1428                                         timeout_encode++;
1429                                         break;
1430                                 }
1431                         } else {
1432                                 max = max * 2;
1433                                 min = min * 2;
1434                         }
1435                 }
1436
1437                 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1438                         /* the value is out of range. */
1439                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1440         }
1441
1442         writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1443                SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1444                &ihost->smu_registers->interrupt_coalesce_control);
1445
1446
1447         ihost->interrupt_coalesce_number = (u16)coalesce_number;
1448         ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
1449
1450         return SCI_SUCCESS;
1451 }
1452
1453
1454 static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
1455 {
1456         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1457         u32 val;
1458
1459         /* enable clock gating for power control of the scu unit */
1460         val = readl(&ihost->smu_registers->clock_gating_control);
1461         val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) |
1462                  SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) |
1463                  SMU_CGUCR_GEN_BIT(XCLK_ENABLE));
1464         val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE);
1465         writel(val, &ihost->smu_registers->clock_gating_control);
1466
1467         /* set the default interrupt coalescence number and timeout value. */
1468         sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1469 }
1470
1471 static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
1472 {
1473         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1474
1475         /* disable interrupt coalescence. */
1476         sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1477 }
1478
1479 static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
1480 {
1481         u32 index;
1482         enum sci_status status;
1483         enum sci_status phy_status;
1484
1485         status = SCI_SUCCESS;
1486
1487         for (index = 0; index < SCI_MAX_PHYS; index++) {
1488                 phy_status = sci_phy_stop(&ihost->phys[index]);
1489
1490                 if (phy_status != SCI_SUCCESS &&
1491                     phy_status != SCI_FAILURE_INVALID_STATE) {
1492                         status = SCI_FAILURE;
1493
1494                         dev_warn(&ihost->pdev->dev,
1495                                  "%s: Controller stop operation failed to stop "
1496                                  "phy %d because of status %d.\n",
1497                                  __func__,
1498                                  ihost->phys[index].phy_index, phy_status);
1499                 }
1500         }
1501
1502         return status;
1503 }
1504
1505 static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
1506 {
1507         u32 index;
1508         enum sci_status port_status;
1509         enum sci_status status = SCI_SUCCESS;
1510
1511         for (index = 0; index < ihost->logical_port_entries; index++) {
1512                 struct isci_port *iport = &ihost->ports[index];
1513
1514                 port_status = sci_port_stop(iport);
1515
1516                 if ((port_status != SCI_SUCCESS) &&
1517                     (port_status != SCI_FAILURE_INVALID_STATE)) {
1518                         status = SCI_FAILURE;
1519
1520                         dev_warn(&ihost->pdev->dev,
1521                                  "%s: Controller stop operation failed to "
1522                                  "stop port %d because of status %d.\n",
1523                                  __func__,
1524                                  iport->logical_port_index,
1525                                  port_status);
1526                 }
1527         }
1528
1529         return status;
1530 }
1531
1532 static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
1533 {
1534         u32 index;
1535         enum sci_status status;
1536         enum sci_status device_status;
1537
1538         status = SCI_SUCCESS;
1539
1540         for (index = 0; index < ihost->remote_node_entries; index++) {
1541                 if (ihost->device_table[index] != NULL) {
1542                         /* / @todo What timeout value do we want to provide to this request? */
1543                         device_status = sci_remote_device_stop(ihost->device_table[index], 0);
1544
1545                         if ((device_status != SCI_SUCCESS) &&
1546                             (device_status != SCI_FAILURE_INVALID_STATE)) {
1547                                 dev_warn(&ihost->pdev->dev,
1548                                          "%s: Controller stop operation failed "
1549                                          "to stop device 0x%p because of "
1550                                          "status %d.\n",
1551                                          __func__,
1552                                          ihost->device_table[index], device_status);
1553                         }
1554                 }
1555         }
1556
1557         return status;
1558 }
1559
1560 static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1561 {
1562         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1563
1564         /* Stop all of the components for this controller */
1565         sci_controller_stop_phys(ihost);
1566         sci_controller_stop_ports(ihost);
1567         sci_controller_stop_devices(ihost);
1568 }
1569
1570 static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1571 {
1572         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1573
1574         sci_del_timer(&ihost->timer);
1575 }
1576
1577 static void sci_controller_reset_hardware(struct isci_host *ihost)
1578 {
1579         /* Disable interrupts so we dont take any spurious interrupts */
1580         sci_controller_disable_interrupts(ihost);
1581
1582         /* Reset the SCU */
1583         writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
1584
1585         /* Delay for 1ms to before clearing the CQP and UFQPR. */
1586         udelay(1000);
1587
1588         /* The write to the CQGR clears the CQP */
1589         writel(0x00000000, &ihost->smu_registers->completion_queue_get);
1590
1591         /* The write to the UFQGP clears the UFQPR */
1592         writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
1593 }
1594
1595 static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1596 {
1597         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1598
1599         sci_controller_reset_hardware(ihost);
1600         sci_change_state(&ihost->sm, SCIC_RESET);
1601 }
1602
1603 static const struct sci_base_state sci_controller_state_table[] = {
1604         [SCIC_INITIAL] = {
1605                 .enter_state = sci_controller_initial_state_enter,
1606         },
1607         [SCIC_RESET] = {},
1608         [SCIC_INITIALIZING] = {},
1609         [SCIC_INITIALIZED] = {},
1610         [SCIC_STARTING] = {
1611                 .exit_state  = sci_controller_starting_state_exit,
1612         },
1613         [SCIC_READY] = {
1614                 .enter_state = sci_controller_ready_state_enter,
1615                 .exit_state  = sci_controller_ready_state_exit,
1616         },
1617         [SCIC_RESETTING] = {
1618                 .enter_state = sci_controller_resetting_state_enter,
1619         },
1620         [SCIC_STOPPING] = {
1621                 .enter_state = sci_controller_stopping_state_enter,
1622                 .exit_state = sci_controller_stopping_state_exit,
1623         },
1624         [SCIC_STOPPED] = {},
1625         [SCIC_FAILED] = {}
1626 };
1627
1628 static void controller_timeout(unsigned long data)
1629 {
1630         struct sci_timer *tmr = (struct sci_timer *)data;
1631         struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
1632         struct sci_base_state_machine *sm = &ihost->sm;
1633         unsigned long flags;
1634
1635         spin_lock_irqsave(&ihost->scic_lock, flags);
1636
1637         if (tmr->cancel)
1638                 goto done;
1639
1640         if (sm->current_state_id == SCIC_STARTING)
1641                 sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
1642         else if (sm->current_state_id == SCIC_STOPPING) {
1643                 sci_change_state(sm, SCIC_FAILED);
1644                 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1645         } else  /* / @todo Now what do we want to do in this case? */
1646                 dev_err(&ihost->pdev->dev,
1647                         "%s: Controller timer fired when controller was not "
1648                         "in a state being timed.\n",
1649                         __func__);
1650
1651 done:
1652         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1653 }
1654
1655 static enum sci_status sci_controller_construct(struct isci_host *ihost,
1656                                                 void __iomem *scu_base,
1657                                                 void __iomem *smu_base)
1658 {
1659         u8 i;
1660
1661         sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
1662
1663         ihost->scu_registers = scu_base;
1664         ihost->smu_registers = smu_base;
1665
1666         sci_port_configuration_agent_construct(&ihost->port_agent);
1667
1668         /* Construct the ports for this controller */
1669         for (i = 0; i < SCI_MAX_PORTS; i++)
1670                 sci_port_construct(&ihost->ports[i], i, ihost);
1671         sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
1672
1673         /* Construct the phys for this controller */
1674         for (i = 0; i < SCI_MAX_PHYS; i++) {
1675                 /* Add all the PHYs to the dummy port */
1676                 sci_phy_construct(&ihost->phys[i],
1677                                   &ihost->ports[SCI_MAX_PORTS], i);
1678         }
1679
1680         ihost->invalid_phy_mask = 0;
1681
1682         sci_init_timer(&ihost->timer, controller_timeout);
1683
1684         return sci_controller_reset(ihost);
1685 }
1686
1687 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
1688 {
1689         int i;
1690
1691         for (i = 0; i < SCI_MAX_PORTS; i++)
1692                 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1693                         return -EINVAL;
1694
1695         for (i = 0; i < SCI_MAX_PHYS; i++)
1696                 if (oem->phys[i].sas_address.high == 0 &&
1697                     oem->phys[i].sas_address.low == 0)
1698                         return -EINVAL;
1699
1700         if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1701                 for (i = 0; i < SCI_MAX_PHYS; i++)
1702                         if (oem->ports[i].phy_mask != 0)
1703                                 return -EINVAL;
1704         } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1705                 u8 phy_mask = 0;
1706
1707                 for (i = 0; i < SCI_MAX_PHYS; i++)
1708                         phy_mask |= oem->ports[i].phy_mask;
1709
1710                 if (phy_mask == 0)
1711                         return -EINVAL;
1712         } else
1713                 return -EINVAL;
1714
1715         if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
1716             oem->controller.max_concurr_spin_up < 1)
1717                 return -EINVAL;
1718
1719         if (oem->controller.do_enable_ssc) {
1720                 if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
1721                         return -EINVAL;
1722
1723                 if (version >= ISCI_ROM_VER_1_1) {
1724                         u8 test = oem->controller.ssc_sata_tx_spread_level;
1725
1726                         switch (test) {
1727                         case 0:
1728                         case 2:
1729                         case 3:
1730                         case 6:
1731                         case 7:
1732                                 break;
1733                         default:
1734                                 return -EINVAL;
1735                         }
1736
1737                         test = oem->controller.ssc_sas_tx_spread_level;
1738                         if (oem->controller.ssc_sas_tx_type == 0) {
1739                                 switch (test) {
1740                                 case 0:
1741                                 case 2:
1742                                 case 3:
1743                                         break;
1744                                 default:
1745                                         return -EINVAL;
1746                                 }
1747                         } else if (oem->controller.ssc_sas_tx_type == 1) {
1748                                 switch (test) {
1749                                 case 0:
1750                                 case 3:
1751                                 case 6:
1752                                         break;
1753                                 default:
1754                                         return -EINVAL;
1755                                 }
1756                         }
1757                 }
1758         }
1759
1760         return 0;
1761 }
1762
1763 static u8 max_spin_up(struct isci_host *ihost)
1764 {
1765         if (ihost->user_parameters.max_concurr_spinup)
1766                 return min_t(u8, ihost->user_parameters.max_concurr_spinup,
1767                              MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1768         else
1769                 return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
1770                              MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1771 }
1772
1773 static void power_control_timeout(unsigned long data)
1774 {
1775         struct sci_timer *tmr = (struct sci_timer *)data;
1776         struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
1777         struct isci_phy *iphy;
1778         unsigned long flags;
1779         u8 i;
1780
1781         spin_lock_irqsave(&ihost->scic_lock, flags);
1782
1783         if (tmr->cancel)
1784                 goto done;
1785
1786         ihost->power_control.phys_granted_power = 0;
1787
1788         if (ihost->power_control.phys_waiting == 0) {
1789                 ihost->power_control.timer_started = false;
1790                 goto done;
1791         }
1792
1793         for (i = 0; i < SCI_MAX_PHYS; i++) {
1794
1795                 if (ihost->power_control.phys_waiting == 0)
1796                         break;
1797
1798                 iphy = ihost->power_control.requesters[i];
1799                 if (iphy == NULL)
1800                         continue;
1801
1802                 if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
1803                         break;
1804
1805                 ihost->power_control.requesters[i] = NULL;
1806                 ihost->power_control.phys_waiting--;
1807                 ihost->power_control.phys_granted_power++;
1808                 sci_phy_consume_power_handler(iphy);
1809
1810                 if (iphy->protocol == SAS_PROTOCOL_SSP) {
1811                         u8 j;
1812
1813                         for (j = 0; j < SCI_MAX_PHYS; j++) {
1814                                 struct isci_phy *requester = ihost->power_control.requesters[j];
1815
1816                                 /*
1817                                  * Search the power_control queue to see if there are other phys
1818                                  * attached to the same remote device. If found, take all of
1819                                  * them out of await_sas_power state.
1820                                  */
1821                                 if (requester != NULL && requester != iphy) {
1822                                         u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
1823                                                           iphy->frame_rcvd.iaf.sas_addr,
1824                                                           sizeof(requester->frame_rcvd.iaf.sas_addr));
1825
1826                                         if (other == 0) {
1827                                                 ihost->power_control.requesters[j] = NULL;
1828                                                 ihost->power_control.phys_waiting--;
1829                                                 sci_phy_consume_power_handler(requester);
1830                                         }
1831                                 }
1832                         }
1833                 }
1834         }
1835
1836         /*
1837          * It doesn't matter if the power list is empty, we need to start the
1838          * timer in case another phy becomes ready.
1839          */
1840         sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1841         ihost->power_control.timer_started = true;
1842
1843 done:
1844         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1845 }
1846
1847 void sci_controller_power_control_queue_insert(struct isci_host *ihost,
1848                                                struct isci_phy *iphy)
1849 {
1850         BUG_ON(iphy == NULL);
1851
1852         if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
1853                 ihost->power_control.phys_granted_power++;
1854                 sci_phy_consume_power_handler(iphy);
1855
1856                 /*
1857                  * stop and start the power_control timer. When the timer fires, the
1858                  * no_of_phys_granted_power will be set to 0
1859                  */
1860                 if (ihost->power_control.timer_started)
1861                         sci_del_timer(&ihost->power_control.timer);
1862
1863                 sci_mod_timer(&ihost->power_control.timer,
1864                                  SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1865                 ihost->power_control.timer_started = true;
1866
1867         } else {
1868                 /*
1869                  * There are phys, attached to the same sas address as this phy, are
1870                  * already in READY state, this phy don't need wait.
1871                  */
1872                 u8 i;
1873                 struct isci_phy *current_phy;
1874
1875                 for (i = 0; i < SCI_MAX_PHYS; i++) {
1876                         u8 other;
1877                         current_phy = &ihost->phys[i];
1878
1879                         other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
1880                                        iphy->frame_rcvd.iaf.sas_addr,
1881                                        sizeof(current_phy->frame_rcvd.iaf.sas_addr));
1882
1883                         if (current_phy->sm.current_state_id == SCI_PHY_READY &&
1884                             current_phy->protocol == SAS_PROTOCOL_SSP &&
1885                             other == 0) {
1886                                 sci_phy_consume_power_handler(iphy);
1887                                 break;
1888                         }
1889                 }
1890
1891                 if (i == SCI_MAX_PHYS) {
1892                         /* Add the phy in the waiting list */
1893                         ihost->power_control.requesters[iphy->phy_index] = iphy;
1894                         ihost->power_control.phys_waiting++;
1895                 }
1896         }
1897 }
1898
1899 void sci_controller_power_control_queue_remove(struct isci_host *ihost,
1900                                                struct isci_phy *iphy)
1901 {
1902         BUG_ON(iphy == NULL);
1903
1904         if (ihost->power_control.requesters[iphy->phy_index])
1905                 ihost->power_control.phys_waiting--;
1906
1907         ihost->power_control.requesters[iphy->phy_index] = NULL;
1908 }
1909
1910 static int is_long_cable(int phy, unsigned char selection_byte)
1911 {
1912         return !!(selection_byte & (1 << phy));
1913 }
1914
1915 static int is_medium_cable(int phy, unsigned char selection_byte)
1916 {
1917         return !!(selection_byte & (1 << (phy + 4)));
1918 }
1919
1920 static enum cable_selections decode_selection_byte(
1921         int phy,
1922         unsigned char selection_byte)
1923 {
1924         return ((selection_byte & (1 << phy)) ? 1 : 0)
1925                 + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
1926 }
1927
1928 static unsigned char *to_cable_select(struct isci_host *ihost)
1929 {
1930         if (is_cable_select_overridden())
1931                 return ((unsigned char *)&cable_selection_override)
1932                         + ihost->id;
1933         else
1934                 return &ihost->oem_parameters.controller.cable_selection_mask;
1935 }
1936
1937 enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
1938 {
1939         return decode_selection_byte(phy, *to_cable_select(ihost));
1940 }
1941
1942 char *lookup_cable_names(enum cable_selections selection)
1943 {
1944         static char *cable_names[] = {
1945                 [short_cable]     = "short",
1946                 [long_cable]      = "long",
1947                 [medium_cable]    = "medium",
1948                 [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
1949         };
1950         return (selection <= undefined_cable) ? cable_names[selection]
1951                                               : cable_names[undefined_cable];
1952 }
1953
1954 #define AFE_REGISTER_WRITE_DELAY 10
1955
1956 static void sci_controller_afe_initialization(struct isci_host *ihost)
1957 {
1958         struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
1959         const struct sci_oem_params *oem = &ihost->oem_parameters;
1960         struct pci_dev *pdev = ihost->pdev;
1961         u32 afe_status;
1962         u32 phy_id;
1963         unsigned char cable_selection_mask = *to_cable_select(ihost);
1964
1965         /* Clear DFX Status registers */
1966         writel(0x0081000f, &afe->afe_dfx_master_control0);
1967         udelay(AFE_REGISTER_WRITE_DELAY);
1968
1969         if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
1970                 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1971                  * Timer, PM Stagger Timer
1972                  */
1973                 writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
1974                 udelay(AFE_REGISTER_WRITE_DELAY);
1975         }
1976
1977         /* Configure bias currents to normal */
1978         if (is_a2(pdev))
1979                 writel(0x00005A00, &afe->afe_bias_control);
1980         else if (is_b0(pdev) || is_c0(pdev))
1981                 writel(0x00005F00, &afe->afe_bias_control);
1982         else if (is_c1(pdev))
1983                 writel(0x00005500, &afe->afe_bias_control);
1984
1985         udelay(AFE_REGISTER_WRITE_DELAY);
1986
1987         /* Enable PLL */
1988         if (is_a2(pdev))
1989                 writel(0x80040908, &afe->afe_pll_control0);
1990         else if (is_b0(pdev) || is_c0(pdev))
1991                 writel(0x80040A08, &afe->afe_pll_control0);
1992         else if (is_c1(pdev)) {
1993                 writel(0x80000B08, &afe->afe_pll_control0);
1994                 udelay(AFE_REGISTER_WRITE_DELAY);
1995                 writel(0x00000B08, &afe->afe_pll_control0);
1996                 udelay(AFE_REGISTER_WRITE_DELAY);
1997                 writel(0x80000B08, &afe->afe_pll_control0);
1998         }
1999
2000         udelay(AFE_REGISTER_WRITE_DELAY);
2001
2002         /* Wait for the PLL to lock */
2003         do {
2004                 afe_status = readl(&afe->afe_common_block_status);
2005                 udelay(AFE_REGISTER_WRITE_DELAY);
2006         } while ((afe_status & 0x00001000) == 0);
2007
2008         if (is_a2(pdev)) {
2009                 /* Shorten SAS SNW lock time (RxLock timer value from 76
2010                  * us to 50 us)
2011                  */
2012                 writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
2013                 udelay(AFE_REGISTER_WRITE_DELAY);
2014         }
2015
2016         for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
2017                 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id];
2018                 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
2019                 int cable_length_long =
2020                         is_long_cable(phy_id, cable_selection_mask);
2021                 int cable_length_medium =
2022                         is_medium_cable(phy_id, cable_selection_mask);
2023
2024                 if (is_a2(pdev)) {
2025                         /* All defaults, except the Receive Word
2026                          * Alignament/Comma Detect Enable....(0xe800)
2027                          */
2028                         writel(0x00004512, &xcvr->afe_xcvr_control0);
2029                         udelay(AFE_REGISTER_WRITE_DELAY);
2030
2031                         writel(0x0050100F, &xcvr->afe_xcvr_control1);
2032                         udelay(AFE_REGISTER_WRITE_DELAY);
2033                 } else if (is_b0(pdev)) {
2034                         /* Configure transmitter SSC parameters */
2035                         writel(0x00030000, &xcvr->afe_tx_ssc_control);
2036                         udelay(AFE_REGISTER_WRITE_DELAY);
2037                 } else if (is_c0(pdev)) {
2038                         /* Configure transmitter SSC parameters */
2039                         writel(0x00010202, &xcvr->afe_tx_ssc_control);
2040                         udelay(AFE_REGISTER_WRITE_DELAY);
2041
2042                         /* All defaults, except the Receive Word
2043                          * Alignament/Comma Detect Enable....(0xe800)
2044                          */
2045                         writel(0x00014500, &xcvr->afe_xcvr_control0);
2046                         udelay(AFE_REGISTER_WRITE_DELAY);
2047                 } else if (is_c1(pdev)) {
2048                         /* Configure transmitter SSC parameters */
2049                         writel(0x00010202, &xcvr->afe_tx_ssc_control);
2050                         udelay(AFE_REGISTER_WRITE_DELAY);
2051
2052                         /* All defaults, except the Receive Word
2053                          * Alignament/Comma Detect Enable....(0xe800)
2054                          */
2055                         writel(0x0001C500, &xcvr->afe_xcvr_control0);
2056                         udelay(AFE_REGISTER_WRITE_DELAY);
2057                 }
2058
2059                 /* Power up TX and RX out from power down (PWRDNTX and
2060                  * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
2061                  */
2062                 if (is_a2(pdev))
2063                         writel(0x000003F0, &xcvr->afe_channel_control);
2064                 else if (is_b0(pdev)) {
2065                         writel(0x000003D7, &xcvr->afe_channel_control);
2066                         udelay(AFE_REGISTER_WRITE_DELAY);
2067
2068                         writel(0x000003D4, &xcvr->afe_channel_control);
2069                 } else if (is_c0(pdev)) {
2070                         writel(0x000001E7, &xcvr->afe_channel_control);
2071                         udelay(AFE_REGISTER_WRITE_DELAY);
2072
2073                         writel(0x000001E4, &xcvr->afe_channel_control);
2074                 } else if (is_c1(pdev)) {
2075                         writel(cable_length_long ? 0x000002F7 : 0x000001F7,
2076                                &xcvr->afe_channel_control);
2077                         udelay(AFE_REGISTER_WRITE_DELAY);
2078
2079                         writel(cable_length_long ? 0x000002F4 : 0x000001F4,
2080                                &xcvr->afe_channel_control);
2081                 }
2082                 udelay(AFE_REGISTER_WRITE_DELAY);
2083
2084                 if (is_a2(pdev)) {
2085                         /* Enable TX equalization (0xe824) */
2086                         writel(0x00040000, &xcvr->afe_tx_control);
2087                         udelay(AFE_REGISTER_WRITE_DELAY);
2088                 }
2089
2090                 if (is_a2(pdev) || is_b0(pdev))
2091                         /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2092                          * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2093                          * Enabled) ....(0xe800)
2094                          */
2095                         writel(0x00004100, &xcvr->afe_xcvr_control0);
2096                 else if (is_c0(pdev))
2097                         writel(0x00014100, &xcvr->afe_xcvr_control0);
2098                 else if (is_c1(pdev))
2099                         writel(0x0001C100, &xcvr->afe_xcvr_control0);
2100                 udelay(AFE_REGISTER_WRITE_DELAY);
2101
2102                 /* Leave DFE/FFE on */
2103                 if (is_a2(pdev))
2104                         writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2105                 else if (is_b0(pdev)) {
2106                         writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2107                         udelay(AFE_REGISTER_WRITE_DELAY);
2108                         /* Enable TX equalization (0xe824) */
2109                         writel(0x00040000, &xcvr->afe_tx_control);
2110                 } else if (is_c0(pdev)) {
2111                         writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
2112                         udelay(AFE_REGISTER_WRITE_DELAY);
2113
2114                         writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
2115                         udelay(AFE_REGISTER_WRITE_DELAY);
2116
2117                         /* Enable TX equalization (0xe824) */
2118                         writel(0x00040000, &xcvr->afe_tx_control);
2119                 } else if (is_c1(pdev)) {
2120                         writel(cable_length_long ? 0x01500C0C :
2121                                cable_length_medium ? 0x01400C0D : 0x02400C0D,
2122                                &xcvr->afe_xcvr_control1);
2123                         udelay(AFE_REGISTER_WRITE_DELAY);
2124
2125                         writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
2126                         udelay(AFE_REGISTER_WRITE_DELAY);
2127
2128                         writel(cable_length_long ? 0x33091C1F :
2129                                cable_length_medium ? 0x3315181F : 0x2B17161F,
2130                                &xcvr->afe_rx_ssc_control0);
2131                         udelay(AFE_REGISTER_WRITE_DELAY);
2132
2133                         /* Enable TX equalization (0xe824) */
2134                         writel(0x00040000, &xcvr->afe_tx_control);
2135                 }
2136
2137                 udelay(AFE_REGISTER_WRITE_DELAY);
2138
2139                 writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
2140                 udelay(AFE_REGISTER_WRITE_DELAY);
2141
2142                 writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
2143                 udelay(AFE_REGISTER_WRITE_DELAY);
2144
2145                 writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
2146                 udelay(AFE_REGISTER_WRITE_DELAY);
2147
2148                 writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
2149                 udelay(AFE_REGISTER_WRITE_DELAY);
2150         }
2151
2152         /* Transfer control to the PEs */
2153         writel(0x00010f00, &afe->afe_dfx_master_control0);
2154         udelay(AFE_REGISTER_WRITE_DELAY);
2155 }
2156
2157 static void sci_controller_initialize_power_control(struct isci_host *ihost)
2158 {
2159         sci_init_timer(&ihost->power_control.timer, power_control_timeout);
2160
2161         memset(ihost->power_control.requesters, 0,
2162                sizeof(ihost->power_control.requesters));
2163
2164         ihost->power_control.phys_waiting = 0;
2165         ihost->power_control.phys_granted_power = 0;
2166 }
2167
2168 static enum sci_status sci_controller_initialize(struct isci_host *ihost)
2169 {
2170         struct sci_base_state_machine *sm = &ihost->sm;
2171         enum sci_status result = SCI_FAILURE;
2172         unsigned long i, state, val;
2173
2174         if (ihost->sm.current_state_id != SCIC_RESET) {
2175                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2176                          __func__, ihost->sm.current_state_id);
2177                 return SCI_FAILURE_INVALID_STATE;
2178         }
2179
2180         sci_change_state(sm, SCIC_INITIALIZING);
2181
2182         sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
2183
2184         ihost->next_phy_to_start = 0;
2185         ihost->phy_startup_timer_pending = false;
2186
2187         sci_controller_initialize_power_control(ihost);
2188
2189         /*
2190          * There is nothing to do here for B0 since we do not have to
2191          * program the AFE registers.
2192          * / @todo The AFE settings are supposed to be correct for the B0 but
2193          * /       presently they seem to be wrong. */
2194         sci_controller_afe_initialization(ihost);
2195
2196
2197         /* Take the hardware out of reset */
2198         writel(0, &ihost->smu_registers->soft_reset_control);
2199
2200         /*
2201          * / @todo Provide meaningfull error code for hardware failure
2202          * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2203         for (i = 100; i >= 1; i--) {
2204                 u32 status;
2205
2206                 /* Loop until the hardware reports success */
2207                 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2208                 status = readl(&ihost->smu_registers->control_status);
2209
2210                 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2211                         break;
2212         }
2213         if (i == 0)
2214                 goto out;
2215
2216         /*
2217          * Determine what are the actaul device capacities that the
2218          * hardware will support */
2219         val = readl(&ihost->smu_registers->device_context_capacity);
2220
2221         /* Record the smaller of the two capacity values */
2222         ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2223         ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2224         ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2225
2226         /*
2227          * Make all PEs that are unassigned match up with the
2228          * logical ports
2229          */
2230         for (i = 0; i < ihost->logical_port_entries; i++) {
2231                 struct scu_port_task_scheduler_group_registers __iomem
2232                         *ptsg = &ihost->scu_registers->peg0.ptsg;
2233
2234                 writel(i, &ptsg->protocol_engine[i]);
2235         }
2236
2237         /* Initialize hardware PCI Relaxed ordering in DMA engines */
2238         val = readl(&ihost->scu_registers->sdma.pdma_configuration);
2239         val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2240         writel(val, &ihost->scu_registers->sdma.pdma_configuration);
2241
2242         val = readl(&ihost->scu_registers->sdma.cdma_configuration);
2243         val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2244         writel(val, &ihost->scu_registers->sdma.cdma_configuration);
2245
2246         /*
2247          * Initialize the PHYs before the PORTs because the PHY registers
2248          * are accessed during the port initialization.
2249          */
2250         for (i = 0; i < SCI_MAX_PHYS; i++) {
2251                 result = sci_phy_initialize(&ihost->phys[i],
2252                                             &ihost->scu_registers->peg0.pe[i].tl,
2253                                             &ihost->scu_registers->peg0.pe[i].ll);
2254                 if (result != SCI_SUCCESS)
2255                         goto out;
2256         }
2257
2258         for (i = 0; i < ihost->logical_port_entries; i++) {
2259                 struct isci_port *iport = &ihost->ports[i];
2260
2261                 iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
2262                 iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
2263                 iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
2264         }
2265
2266         result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
2267
2268  out:
2269         /* Advance the controller state machine */
2270         if (result == SCI_SUCCESS)
2271                 state = SCIC_INITIALIZED;
2272         else
2273                 state = SCIC_FAILED;
2274         sci_change_state(sm, state);
2275
2276         return result;
2277 }
2278
2279 static int sci_controller_dma_alloc(struct isci_host *ihost)
2280 {
2281         struct device *dev = &ihost->pdev->dev;
2282         size_t size;
2283         int i;
2284
2285         /* detect re-initialization */
2286         if (ihost->completion_queue)
2287                 return 0;
2288
2289         size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2290         ihost->completion_queue = dmam_alloc_coherent(dev, size, &ihost->cq_dma,
2291                                                       GFP_KERNEL);
2292         if (!ihost->completion_queue)
2293                 return -ENOMEM;
2294
2295         size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
2296         ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &ihost->rnc_dma,
2297                                                                GFP_KERNEL);
2298
2299         if (!ihost->remote_node_context_table)
2300                 return -ENOMEM;
2301
2302         size = ihost->task_context_entries * sizeof(struct scu_task_context),
2303         ihost->task_context_table = dmam_alloc_coherent(dev, size, &ihost->tc_dma,
2304                                                         GFP_KERNEL);
2305         if (!ihost->task_context_table)
2306                 return -ENOMEM;
2307
2308         size = SCI_UFI_TOTAL_SIZE;
2309         ihost->ufi_buf = dmam_alloc_coherent(dev, size, &ihost->ufi_dma, GFP_KERNEL);
2310         if (!ihost->ufi_buf)
2311                 return -ENOMEM;
2312
2313         for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
2314                 struct isci_request *ireq;
2315                 dma_addr_t dma;
2316
2317                 ireq = dmam_alloc_coherent(dev, sizeof(*ireq), &dma, GFP_KERNEL);
2318                 if (!ireq)
2319                         return -ENOMEM;
2320
2321                 ireq->tc = &ihost->task_context_table[i];
2322                 ireq->owning_controller = ihost;
2323                 spin_lock_init(&ireq->state_lock);
2324                 ireq->request_daddr = dma;
2325                 ireq->isci_host = ihost;
2326                 ihost->reqs[i] = ireq;
2327         }
2328
2329         return 0;
2330 }
2331
2332 static int sci_controller_mem_init(struct isci_host *ihost)
2333 {
2334         int err = sci_controller_dma_alloc(ihost);
2335
2336         if (err)
2337                 return err;
2338
2339         writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower);
2340         writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper);
2341
2342         writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower);
2343         writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper);
2344
2345         writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower);
2346         writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper);
2347
2348         sci_unsolicited_frame_control_construct(ihost);
2349
2350         /*
2351          * Inform the silicon as to the location of the UF headers and
2352          * address table.
2353          */
2354         writel(lower_32_bits(ihost->uf_control.headers.physical_address),
2355                 &ihost->scu_registers->sdma.uf_header_base_address_lower);
2356         writel(upper_32_bits(ihost->uf_control.headers.physical_address),
2357                 &ihost->scu_registers->sdma.uf_header_base_address_upper);
2358
2359         writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
2360                 &ihost->scu_registers->sdma.uf_address_table_lower);
2361         writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
2362                 &ihost->scu_registers->sdma.uf_address_table_upper);
2363
2364         return 0;
2365 }
2366
2367 /**
2368  * isci_host_init - (re-)initialize hardware and internal (private) state
2369  * @ihost: host to init
2370  *
2371  * Any public facing objects (like asd_sas_port, and asd_sas_phys), or
2372  * one-time initialization objects like locks and waitqueues, are
2373  * not touched (they are initialized in isci_host_alloc)
2374  */
2375 int isci_host_init(struct isci_host *ihost)
2376 {
2377         int i, err;
2378         enum sci_status status;
2379
2380         status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));
2381         if (status != SCI_SUCCESS) {
2382                 dev_err(&ihost->pdev->dev,
2383                         "%s: sci_controller_construct failed - status = %x\n",
2384                         __func__,
2385                         status);
2386                 return -ENODEV;
2387         }
2388
2389         spin_lock_irq(&ihost->scic_lock);
2390         status = sci_controller_initialize(ihost);
2391         spin_unlock_irq(&ihost->scic_lock);
2392         if (status != SCI_SUCCESS) {
2393                 dev_warn(&ihost->pdev->dev,
2394                          "%s: sci_controller_initialize failed -"
2395                          " status = 0x%x\n",
2396                          __func__, status);
2397                 return -ENODEV;
2398         }
2399
2400         err = sci_controller_mem_init(ihost);
2401         if (err)
2402                 return err;
2403
2404         /* enable sgpio */
2405         writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
2406         for (i = 0; i < isci_gpio_count(ihost); i++)
2407                 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
2408         writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
2409
2410         return 0;
2411 }
2412
2413 void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
2414                             struct isci_phy *iphy)
2415 {
2416         switch (ihost->sm.current_state_id) {
2417         case SCIC_STARTING:
2418                 sci_del_timer(&ihost->phy_timer);
2419                 ihost->phy_startup_timer_pending = false;
2420                 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2421                                                   iport, iphy);
2422                 sci_controller_start_next_phy(ihost);
2423                 break;
2424         case SCIC_READY:
2425                 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2426                                                   iport, iphy);
2427                 break;
2428         default:
2429                 dev_dbg(&ihost->pdev->dev,
2430                         "%s: SCIC Controller linkup event from phy %d in "
2431                         "unexpected state %d\n", __func__, iphy->phy_index,
2432                         ihost->sm.current_state_id);
2433         }
2434 }
2435
2436 void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
2437                               struct isci_phy *iphy)
2438 {
2439         switch (ihost->sm.current_state_id) {
2440         case SCIC_STARTING:
2441         case SCIC_READY:
2442                 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
2443                                                    iport, iphy);
2444                 break;
2445         default:
2446                 dev_dbg(&ihost->pdev->dev,
2447                         "%s: SCIC Controller linkdown event from phy %d in "
2448                         "unexpected state %d\n",
2449                         __func__,
2450                         iphy->phy_index,
2451                         ihost->sm.current_state_id);
2452         }
2453 }
2454
2455 static bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
2456 {
2457         u32 index;
2458
2459         for (index = 0; index < ihost->remote_node_entries; index++) {
2460                 if ((ihost->device_table[index] != NULL) &&
2461                    (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2462                         return true;
2463         }
2464
2465         return false;
2466 }
2467
2468 void sci_controller_remote_device_stopped(struct isci_host *ihost,
2469                                           struct isci_remote_device *idev)
2470 {
2471         if (ihost->sm.current_state_id != SCIC_STOPPING) {
2472                 dev_dbg(&ihost->pdev->dev,
2473                         "SCIC Controller 0x%p remote device stopped event "
2474                         "from device 0x%p in unexpected state %d\n",
2475                         ihost, idev,
2476                         ihost->sm.current_state_id);
2477                 return;
2478         }
2479
2480         if (!sci_controller_has_remote_devices_stopping(ihost))
2481                 sci_change_state(&ihost->sm, SCIC_STOPPED);
2482 }
2483
2484 void sci_controller_post_request(struct isci_host *ihost, u32 request)
2485 {
2486         dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
2487                 __func__, ihost->id, request);
2488
2489         writel(request, &ihost->smu_registers->post_context_port);
2490 }
2491
2492 struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
2493 {
2494         u16 task_index;
2495         u16 task_sequence;
2496
2497         task_index = ISCI_TAG_TCI(io_tag);
2498
2499         if (task_index < ihost->task_context_entries) {
2500                 struct isci_request *ireq = ihost->reqs[task_index];
2501
2502                 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
2503                         task_sequence = ISCI_TAG_SEQ(io_tag);
2504
2505                         if (task_sequence == ihost->io_request_sequence[task_index])
2506                                 return ireq;
2507                 }
2508         }
2509
2510         return NULL;
2511 }
2512
2513 /**
2514  * This method allocates remote node index and the reserves the remote node
2515  *    context space for use. This method can fail if there are no more remote
2516  *    node index available.
2517  * @scic: This is the controller object which contains the set of
2518  *    free remote node ids
2519  * @sci_dev: This is the device object which is requesting the a remote node
2520  *    id
2521  * @node_id: This is the remote node id that is assinged to the device if one
2522  *    is available
2523  *
2524  * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2525  * node index available.
2526  */
2527 enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
2528                                                             struct isci_remote_device *idev,
2529                                                             u16 *node_id)
2530 {
2531         u16 node_index;
2532         u32 remote_node_count = sci_remote_device_node_count(idev);
2533
2534         node_index = sci_remote_node_table_allocate_remote_node(
2535                 &ihost->available_remote_nodes, remote_node_count
2536                 );
2537
2538         if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2539                 ihost->device_table[node_index] = idev;
2540
2541                 *node_id = node_index;
2542
2543                 return SCI_SUCCESS;
2544         }
2545
2546         return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2547 }
2548
2549 void sci_controller_free_remote_node_context(struct isci_host *ihost,
2550                                              struct isci_remote_device *idev,
2551                                              u16 node_id)
2552 {
2553         u32 remote_node_count = sci_remote_device_node_count(idev);
2554
2555         if (ihost->device_table[node_id] == idev) {
2556                 ihost->device_table[node_id] = NULL;
2557
2558                 sci_remote_node_table_release_remote_node_index(
2559                         &ihost->available_remote_nodes, remote_node_count, node_id
2560                         );
2561         }
2562 }
2563
2564 void sci_controller_copy_sata_response(void *response_buffer,
2565                                        void *frame_header,
2566                                        void *frame_buffer)
2567 {
2568         /* XXX type safety? */
2569         memcpy(response_buffer, frame_header, sizeof(u32));
2570
2571         memcpy(response_buffer + sizeof(u32),
2572                frame_buffer,
2573                sizeof(struct dev_to_host_fis) - sizeof(u32));
2574 }
2575
2576 void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
2577 {
2578         if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
2579                 writel(ihost->uf_control.get,
2580                         &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
2581 }
2582
2583 void isci_tci_free(struct isci_host *ihost, u16 tci)
2584 {
2585         u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2586
2587         ihost->tci_pool[tail] = tci;
2588         ihost->tci_tail = tail + 1;
2589 }
2590
2591 static u16 isci_tci_alloc(struct isci_host *ihost)
2592 {
2593         u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2594         u16 tci = ihost->tci_pool[head];
2595
2596         ihost->tci_head = head + 1;
2597         return tci;
2598 }
2599
2600 static u16 isci_tci_space(struct isci_host *ihost)
2601 {
2602         return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2603 }
2604
2605 u16 isci_alloc_tag(struct isci_host *ihost)
2606 {
2607         if (isci_tci_space(ihost)) {
2608                 u16 tci = isci_tci_alloc(ihost);
2609                 u8 seq = ihost->io_request_sequence[tci];
2610
2611                 return ISCI_TAG(seq, tci);
2612         }
2613
2614         return SCI_CONTROLLER_INVALID_IO_TAG;
2615 }
2616
2617 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2618 {
2619         u16 tci = ISCI_TAG_TCI(io_tag);
2620         u16 seq = ISCI_TAG_SEQ(io_tag);
2621
2622         /* prevent tail from passing head */
2623         if (isci_tci_active(ihost) == 0)
2624                 return SCI_FAILURE_INVALID_IO_TAG;
2625
2626         if (seq == ihost->io_request_sequence[tci]) {
2627                 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2628
2629                 isci_tci_free(ihost, tci);
2630
2631                 return SCI_SUCCESS;
2632         }
2633         return SCI_FAILURE_INVALID_IO_TAG;
2634 }
2635
2636 enum sci_status sci_controller_start_io(struct isci_host *ihost,
2637                                         struct isci_remote_device *idev,
2638                                         struct isci_request *ireq)
2639 {
2640         enum sci_status status;
2641
2642         if (ihost->sm.current_state_id != SCIC_READY) {
2643                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2644                          __func__, ihost->sm.current_state_id);
2645                 return SCI_FAILURE_INVALID_STATE;
2646         }
2647
2648         status = sci_remote_device_start_io(ihost, idev, ireq);
2649         if (status != SCI_SUCCESS)
2650                 return status;
2651
2652         set_bit(IREQ_ACTIVE, &ireq->flags);
2653         sci_controller_post_request(ihost, ireq->post_context);
2654         return SCI_SUCCESS;
2655 }
2656
2657 enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
2658                                                  struct isci_remote_device *idev,
2659                                                  struct isci_request *ireq)
2660 {
2661         /* terminate an ongoing (i.e. started) core IO request.  This does not
2662          * abort the IO request at the target, but rather removes the IO
2663          * request from the host controller.
2664          */
2665         enum sci_status status;
2666
2667         if (ihost->sm.current_state_id != SCIC_READY) {
2668                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2669                          __func__, ihost->sm.current_state_id);
2670                 return SCI_FAILURE_INVALID_STATE;
2671         }
2672
2673         status = sci_io_request_terminate(ireq);
2674         if (status != SCI_SUCCESS)
2675                 return status;
2676
2677         /*
2678          * Utilize the original post context command and or in the POST_TC_ABORT
2679          * request sub-type.
2680          */
2681         sci_controller_post_request(ihost,
2682                                     ireq->post_context | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2683         return SCI_SUCCESS;
2684 }
2685
2686 /**
2687  * sci_controller_complete_io() - This method will perform core specific
2688  *    completion operations for an IO request.  After this method is invoked,
2689  *    the user should consider the IO request as invalid until it is properly
2690  *    reused (i.e. re-constructed).
2691  * @ihost: The handle to the controller object for which to complete the
2692  *    IO request.
2693  * @idev: The handle to the remote device object for which to complete
2694  *    the IO request.
2695  * @ireq: the handle to the io request object to complete.
2696  */
2697 enum sci_status sci_controller_complete_io(struct isci_host *ihost,
2698                                            struct isci_remote_device *idev,
2699                                            struct isci_request *ireq)
2700 {
2701         enum sci_status status;
2702         u16 index;
2703
2704         switch (ihost->sm.current_state_id) {
2705         case SCIC_STOPPING:
2706                 /* XXX: Implement this function */
2707                 return SCI_FAILURE;
2708         case SCIC_READY:
2709                 status = sci_remote_device_complete_io(ihost, idev, ireq);
2710                 if (status != SCI_SUCCESS)
2711                         return status;
2712
2713                 index = ISCI_TAG_TCI(ireq->io_tag);
2714                 clear_bit(IREQ_ACTIVE, &ireq->flags);
2715                 return SCI_SUCCESS;
2716         default:
2717                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2718                          __func__, ihost->sm.current_state_id);
2719                 return SCI_FAILURE_INVALID_STATE;
2720         }
2721
2722 }
2723
2724 enum sci_status sci_controller_continue_io(struct isci_request *ireq)
2725 {
2726         struct isci_host *ihost = ireq->owning_controller;
2727
2728         if (ihost->sm.current_state_id != SCIC_READY) {
2729                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2730                          __func__, ihost->sm.current_state_id);
2731                 return SCI_FAILURE_INVALID_STATE;
2732         }
2733
2734         set_bit(IREQ_ACTIVE, &ireq->flags);
2735         sci_controller_post_request(ihost, ireq->post_context);
2736         return SCI_SUCCESS;
2737 }
2738
2739 /**
2740  * sci_controller_start_task() - This method is called by the SCIC user to
2741  *    send/start a framework task management request.
2742  * @controller: the handle to the controller object for which to start the task
2743  *    management request.
2744  * @remote_device: the handle to the remote device object for which to start
2745  *    the task management request.
2746  * @task_request: the handle to the task request object to start.
2747  */
2748 enum sci_task_status sci_controller_start_task(struct isci_host *ihost,
2749                                                struct isci_remote_device *idev,
2750                                                struct isci_request *ireq)
2751 {
2752         enum sci_status status;
2753
2754         if (ihost->sm.current_state_id != SCIC_READY) {
2755                 dev_warn(&ihost->pdev->dev,
2756                          "%s: SCIC Controller starting task from invalid "
2757                          "state\n",
2758                          __func__);
2759                 return SCI_TASK_FAILURE_INVALID_STATE;
2760         }
2761
2762         status = sci_remote_device_start_task(ihost, idev, ireq);
2763         switch (status) {
2764         case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2765                 set_bit(IREQ_ACTIVE, &ireq->flags);
2766
2767                 /*
2768                  * We will let framework know this task request started successfully,
2769                  * although core is still woring on starting the request (to post tc when
2770                  * RNC is resumed.)
2771                  */
2772                 return SCI_SUCCESS;
2773         case SCI_SUCCESS:
2774                 set_bit(IREQ_ACTIVE, &ireq->flags);
2775                 sci_controller_post_request(ihost, ireq->post_context);
2776                 break;
2777         default:
2778                 break;
2779         }
2780
2781         return status;
2782 }
2783
2784 static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
2785 {
2786         int d;
2787
2788         /* no support for TX_GP_CFG */
2789         if (reg_index == 0)
2790                 return -EINVAL;
2791
2792         for (d = 0; d < isci_gpio_count(ihost); d++) {
2793                 u32 val = 0x444; /* all ODx.n clear */
2794                 int i;
2795
2796                 for (i = 0; i < 3; i++) {
2797                         int bit = (i << 2) + 2;
2798
2799                         bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
2800                                                        write_data, reg_index,
2801                                                        reg_count);
2802                         if (bit < 0)
2803                                 break;
2804
2805                         /* if od is set, clear the 'invert' bit */
2806                         val &= ~(bit << ((i << 2) + 2));
2807                 }
2808
2809                 if (i < 3)
2810                         break;
2811                 writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
2812         }
2813
2814         /* unless reg_index is > 1, we should always be able to write at
2815          * least one register
2816          */
2817         return d > 0;
2818 }
2819
2820 int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
2821                     u8 reg_count, u8 *write_data)
2822 {
2823         struct isci_host *ihost = sas_ha->lldd_ha;
2824         int written;
2825
2826         switch (reg_type) {
2827         case SAS_GPIO_REG_TX_GP:
2828                 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);
2829                 break;
2830         default:
2831                 written = -EINVAL;
2832         }
2833
2834         return written;
2835 }